Merge branch 'HEAD' into dev
This commit is contained in:
commit
44f0cd871d
BIN
dataflow_neuro/.DS_Store
vendored
Normal file
BIN
dataflow_neuro/.DS_Store
vendored
Normal file
Binary file not shown.
@ -131,18 +131,18 @@ defproc register_rw (avMx1of2<1+lognw+wl> in; avMx1of2<lognw+wl> out; d1of<wl> d
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vtree<1+lognw+wl> val_input(.in = in.d,.out = _in_v_temp, .supply = supply);
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vtree<1+lognw+wl> val_input(.in = in.d,.out = _in_v_temp, .supply = supply);
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sigbuf_1output<12> val_input_X(.in = _in_v_temp,.out = in.v,.supply = supply);
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sigbuf_1output<12> val_input_X(.in = _in_v_temp,.out = in.v,.supply = supply);
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// Acknowledgment
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// Acknowledgment
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OR2_X1 ack_readwrite(.a = _in_a_write,.b = _in_a_read,.y = _in_a_temp,.vdd = supply.vdd,.vss = supply.vss);
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OR2_X1 ack_readwrite(.a = _in_a_write,.b = _in_a_read,.y = _in_a_temp,.vdd = supply.vdd,.vss = supply.vss);
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sigbuf_1output<12> ack_input_X(.in = _in_a_temp,.out = in.a,.supply = supply);
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sigbuf_1output<12> ack_input_X(.in = _in_a_temp,.out = in.a,.supply = supply);
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// WRITE
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// WRITE
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// Generation of the fake clock pulse if write is HIGH (inverted because the ff clocks are low_active)
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// Generation of the fake clock pulse if write is HIGH (inverted because the ff clocks are low_active)
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bool _in_v_temp_write;
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bool _in_v_temp_write;
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AND2_X1 clk_switch(.a = _in_v_temp,.b = in.d.d[lognw+wl].f, .y = _in_v_temp_write,.vdd = supply.vdd,.vss = supply.vss);
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AND2_X1 clk_switch(.a = _in_v_temp,.b = in.d.d[lognw+wl].f,.y = _in_v_temp_write,.vdd = supply.vdd,.vss = supply.vss);
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delayprog<N_dly_cfg> clk_dly(.in = _in_v_temp_write, .out = _clock_temp,.s = dly_cfg, .supply = supply);
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delayprog<N_dly_cfg> clk_dly(.in = _in_v_temp_write, .out = _clock_temp,.s = dly_cfg, .supply = supply);
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INV_X1 inv_clk(.a = _clock_temp,.y = _clock_temp_inv,.vdd = supply.vdd,.vss = supply.vss);
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INV_X1 inv_clk(.a = _clock_temp,.y = _clock_temp_inv,.vdd = supply.vdd,.vss = supply.vss);
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sigbuf<nw> clk_X(.in = _clock_temp_inv,.out = _clock,.supply = supply);
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sigbuf<nw> clk_X(.in = _clock_temp_inv, .out = _clock,.supply = supply);
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sigbuf<wl> clock_buffer[nw];
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sigbuf<wl> clock_buffer[nw];
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bool _clock_word_temp[nw],_clock_word[nw],_clock_buffer_out[nw*wl];
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bool _clock_word_temp[nw],_clock_word[nw],_clock_buffer_out[nw*wl];
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// Sending back to the ackowledge
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// Sending back to the acknowledge
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bool _in_a_write_temp;
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bool _in_a_write_temp;
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delayprog<N_dly_cfg> ack_dly(.in = _clock_temp, .out = _in_a_write_temp,.s = dly_cfg, .supply = supply);
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delayprog<N_dly_cfg> ack_dly(.in = _clock_temp, .out = _in_a_write_temp,.s = dly_cfg, .supply = supply);
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AND2_X1 ack_write_and(.a = in.d.d[lognw+wl].f,.b = _in_a_write_temp,.y = _in_a_write,.vdd = supply.vdd, .vss = supply.vss);
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AND2_X1 ack_write_and(.a = in.d.d[lognw+wl].f,.b = _in_a_write_temp,.y = _in_a_write,.vdd = supply.vdd, .vss = supply.vss);
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@ -154,7 +154,6 @@ defproc register_rw (avMx1of2<1+lognw+wl> in; avMx1of2<lognw+wl> out; d1of<wl> d
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ortree<nw> bitselector_f[wl];
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ortree<nw> bitselector_f[wl];
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AND2_X1 word_selector_t[nw*wl];
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AND2_X1 word_selector_t[nw*wl];
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AND2_X1 word_selector_f[nw*wl];
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AND2_X1 word_selector_f[nw*wl];
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bool _out_word_to_read[2*nw*wl];
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buffer_s<lognw+wl> output_buf(.out = out,.supply = supply, .reset_B = reset_B);
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buffer_s<lognw+wl> output_buf(.out = out,.supply = supply, .reset_B = reset_B);
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AND2_X1 address_propagator_f[lognw],address_propagator_t[lognw];
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AND2_X1 address_propagator_f[lognw],address_propagator_t[lognw];
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// Outputting the address if the read is true
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// Outputting the address if the read is true
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@ -186,6 +185,11 @@ defproc register_rw (avMx1of2<1+lognw+wl> in; avMx1of2<lognw+wl> out; d1of<wl> d
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// Creating the different flip flop arrays
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// Creating the different flip flop arrays
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bool _out_encoder[nw];
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bool _out_encoder[nw];
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DFFQ_R_X1 ff[nw*wl];
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DFFQ_R_X1 ff[nw*wl];
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AND2_X1 val_chck[nw*wl];
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bool _val_chck_out[nw*wl];
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bool _in_v_temp_buf[nw*wl];
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sigbuf<nw*wl> v_buf(.in = _in_v_temp,.out = _in_v_temp_buf,.supply = supply);
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// For loop for assigning the different components
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// For loop for assigning the different components
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pint bitval;
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pint bitval;
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(k:nw:atree[k].supply = supply;)
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(k:nw:atree[k].supply = supply;)
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@ -221,9 +225,13 @@ defproc register_rw (avMx1of2<1+lognw+wl> in; avMx1of2<lognw+wl> out; d1of<wl> d
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word_to_read_X[word_idx].supply = supply;
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word_to_read_X[word_idx].supply = supply;
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(bit_idx:wl:
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(bit_idx:wl:
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// Describing all the FF and their connection
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// Describing all the FF and their connection
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val_chck[bit_idx].a = _in_v_temp_buf[word_idx+bit_idx];
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val_chck[bit_idx].b = in.d.d[bit_idx].t;
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val_chck[bit_idx].y = _val_chck_out[bit_idx];
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val_chck[bit_idx].vdd = supply.vdd;
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val_chck[bit_idx].vss = supply.vss;
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ff[bit_idx+word_idx*(wl)].clk_B = clock_buffer[word_idx].out[bit_idx];
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ff[bit_idx+word_idx*(wl)].clk_B = clock_buffer[word_idx].out[bit_idx];
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ff[bit_idx+word_idx*(wl)].d = in.d.d[bit_idx].t;
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ff[bit_idx+word_idx*(wl)].d = in.d.d[bit_idx].t;
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ff[bit_idx+word_idx*(wl)].q = data[word_idx].d[bit_idx];
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ff[bit_idx+word_idx*(wl)].q = data[word_idx].d[bit_idx];
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@ -231,11 +239,11 @@ defproc register_rw (avMx1of2<1+lognw+wl> in; avMx1of2<lognw+wl> out; d1of<wl> d
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ff[bit_idx+word_idx*(wl)].vdd = supply.vdd;
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ff[bit_idx+word_idx*(wl)].vdd = supply.vdd;
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ff[bit_idx+word_idx*(wl)].vss = supply.vss;
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ff[bit_idx+word_idx*(wl)].vss = supply.vss;
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// READ: creating the selectors for propagating the right word
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// READ: creating the selectors for propagating the right word
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word_to_read_X[word_idx].out[bit_idx] = word_selector_t[bit_idx+word_idx*(wl)].a;
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word_to_read_X[word_idx].out[bit_idx] = word_selector_t[bit_idx+(word_idx*(wl))].a;
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word_to_read_X[word_idx].out[bit_idx+wl] = word_selector_f[bit_idx+word_idx*(wl)].a;
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word_to_read_X[word_idx].out[bit_idx+wl] = word_selector_f[bit_idx+(word_idx*(wl))].a;
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word_selector_t[bit_idx+word_idx*(wl)].b = ff[bit_idx+word_idx*(wl)].q;
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word_selector_t[bit_idx+word_idx*(wl)].b = ff[bit_idx+(word_idx*(wl))].q;
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word_selector_t[bit_idx+word_idx*(wl)].y = bitselector_t[bit_idx].in[word_idx];
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word_selector_t[bit_idx+word_idx*(wl)].y = bitselector_t[bit_idx].in[word_idx];
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word_selector_f[bit_idx+word_idx*(wl)].b = ff[bit_idx+word_idx*(wl)].q_B;
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word_selector_f[bit_idx+word_idx*(wl)].b = ff[bit_idx+(word_idx*(wl))].q_B;
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word_selector_f[bit_idx+word_idx*(wl)].y = bitselector_f[bit_idx].in[word_idx];
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word_selector_f[bit_idx+word_idx*(wl)].y = bitselector_f[bit_idx].in[word_idx];
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bitselector_t[bit_idx].out = output_buf.in.d.d[bit_idx].t;
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bitselector_t[bit_idx].out = output_buf.in.d.d[bit_idx].t;
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bitselector_f[bit_idx].out = output_buf.in.d.d[bit_idx].f;
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bitselector_f[bit_idx].out = output_buf.in.d.d[bit_idx].f;
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@ -246,7 +254,5 @@ defproc register_rw (avMx1of2<1+lognw+wl> in; avMx1of2<lognw+wl> out; d1of<wl> d
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}
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}
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}}
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}}
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BIN
test/unit_tests/.DS_Store
vendored
Normal file
BIN
test/unit_tests/.DS_Store
vendored
Normal file
Binary file not shown.
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test/unit_tests/arbtree_5/.DS_Store
vendored
Normal file
BIN
test/unit_tests/arbtree_5/.DS_Store
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@ -1,57 +1,49 @@
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t.ff._mqib t.clk t.d t.q t.ff._sqib t.ff._sqi t.ff.__clk t.ff._mqi t.ff._clk
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t.ff.__clk_B t.ff._clk_B t.d t.clk
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[0] start test
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[0] start test
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1 Reset : 0
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61021 Reset : 0
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1 t.clk : 0
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61021 t.clk : 1
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1 t.d : 0
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61021 t.d : 0
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3 t.ff._mqib : 1 [by t.d:=0]
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61022 t.ff._clk_B : 0 [by t.clk:=1]
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4756 t.ff._mqi : 0 [by t.ff._mqib:=1]
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61023 t.ff.__clk_B : 1 [by t.ff._clk_B:=0]
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5893 t.ff._sqib : 1 [by t.ff._mqi:=0]
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65875 t._reset_B : 1 [by Reset:=0]
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6007 t.ff._sqi : 0 [by t.ff._sqib:=1]
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7093 t._reset_B : 1 [by Reset:=0]
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10468 t.ff._clk : 1 [by t.clk:=0]
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12194 t.ff.__clk : 0 [by t.ff._clk:=1]
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71259 t.q : 0 [by t.ff._sqib:=1]
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[1] reset completed
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[1] reset completed
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71259 t.clk : 1
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71298 t.ff._clk : 0 [by t.clk:=1]
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71313 t.ff.__clk : 1 [by t.ff._clk:=0]
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[2] tested d = 0, clk rise
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[2] tested d = 0, clk rise
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71313 t.clk : 0
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65875 t.clk : 0
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71804 t.ff._clk : 1 [by t.clk:=0]
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65875 t.d : 1
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71817 t.ff.__clk : 0 [by t.ff._clk:=1]
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84773 t.ff._mqib : 0 [by t.d:=1]
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71817 t.d : 1
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85476 t.ff._mqi : 1 [by t.ff._mqib:=0]
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71817 t.clk : 1
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96922 t.ff._clk_B : 1 [by t.clk:=0]
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71857 t.ff._clk : 0 [by t.clk:=1]
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97123 t.ff.__clk_B : 0 [by t.ff._clk_B:=1]
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72272 t.ff.__clk : 1 [by t.ff._clk:=0]
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107244 t.ff._sqib : 0 [by t.ff._clk_B:=1]
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72292 t.ff._mqib : 0 [by t.ff.__clk:=1]
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107250 t.ff._sqi : 1 [by t.ff._sqib:=0]
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78353 t.ff._mqi : 1 [by t.ff._mqib:=0]
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110736 t.q : 1 [by t.ff._sqib:=0]
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78353 t.d : 0
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110738 t.ff.q_B : 0 [by t.q:=1]
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78353 t.clk : 0
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110738 t.clk : 1
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WARNING: unstable `t.ff._mqib'+
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113054 t.ff._clk_B : 0 [by t.clk:=1]
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>> cause: t.ff._clk (val: 1)
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113104 t.ff.__clk_B : 1 [by t.ff._clk_B:=0]
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78369 t.ff._clk : 1 [by t.clk:=0]
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113104 t.d : 0
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WARNING: weak-interference `t.ff._mqi'
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114289 t.ff._mqib : 1 [by t.d:=0]
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>> cause: t.ff._mqib (val: X)
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137967 t.ff._mqi : 0 [by t.ff._mqib:=1]
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>> time: 78400
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137967 t.clk : 0
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78400 t.ff._mqib : X [by t.ff._clk:=1]
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137992 t.ff._clk_B : 1 [by t.clk:=0]
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78404 t.ff._mqib : 0 [by t.ff._clk:=1]
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138009 t.ff.__clk_B : 0 [by t.ff._clk_B:=1]
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WARNING: weak-unstable `t.ff._sqib'-
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138073 t.ff._sqib : 1 [by t.ff.__clk_B:=0]
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>> cause: t.ff._mqi (val: X)
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138074 t.q : 0 [by t.ff._sqib:=1]
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>> time: 87529
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138478 t.ff._sqi : 0 [by t.ff._sqib:=1]
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87529 t.ff._mqi : X [by t.ff._mqib:=0]
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203221 t.ff.q_B : 1 [by t.q:=0]
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87544 t.ff._mqi : 1 [by t.ff._mqib:=0]
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203221 t.d : 1
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WARNING: weak-interference `t.ff._sqi'
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203221 t.clk : 1
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>> cause: t.ff._sqib (val: X)
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203222 t.ff._clk_B : 0 [by t.clk:=1]
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>> time: 92093
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214646 t.ff.__clk_B : 1 [by t.ff._clk_B:=0]
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WARNING: weak-interference `t.q'
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227406 t.ff._mqib : 0 [by t.ff.__clk_B:=1]
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>> cause: t.ff._sqib (val: X)
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227582 t.ff._mqi : 1 [by t.ff._mqib:=0]
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>> time: 92093
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92093 t.ff._sqib : X [by t.ff._mqi:=1]
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92148 t.q : X [by t.ff._sqib:=X]
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122467 t.ff.__clk : 0 [by t.ff._clk:=1]
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129024 t.ff._sqi : X [by t.ff._sqib:=X]
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135341 t.ff._sqib : 0 [by t.ff._mqi:=1]
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165121 t.q : 1 [by t.ff._sqib:=0]
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186994 t.ff._sqi : 1 [by t.ff._sqib:=0]
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[3] tested d = 1, clk rise and fall
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[3] tested d = 1, clk rise and fall
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227582 t.clk : 0
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227583 t.ff._clk_B : 1 [by t.clk:=0]
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227590 t.ff._sqib : 0 [by t.ff._clk_B:=1]
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227593 t.q : 1 [by t.ff._sqib:=0]
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234776 t.ff.q_B : 0 [by t.q:=1]
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241004 t.ff._sqi : 1 [by t.ff._sqib:=0]
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278221 t.ff.__clk_B : 0 [by t.ff._clk_B:=1]
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278221 t.d : 0
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@ -4,22 +4,24 @@
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"Reset"->"t._reset_B"-
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"Reset"->"t._reset_B"-
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~("Reset")->"t._reset_B"+
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~("Reset")->"t._reset_B"+
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= "t._reset_B" "t.ff.reset_B"
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= "t._reset_B" "t.ff.reset_B"
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"t.ff.clk"->"t.ff._clk"-
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"t.ff.clk_B"->"t.ff._clk_B"-
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~("t.ff.clk")->"t.ff._clk"+
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~("t.ff.clk_B")->"t.ff._clk_B"+
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"t.ff._clk"->"t.ff.__clk"-
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"t.ff._clk_B"->"t.ff.__clk_B"-
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~("t.ff._clk")->"t.ff.__clk"+
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~("t.ff._clk_B")->"t.ff.__clk_B"+
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~"t.ff.d"&~"t.ff._clk"|~"t.ff.reset_B"|~"t.ff.__clk"&~"t.ff._mqi"->"t.ff._mqib"+
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~"t.ff.d"&~"t.ff._clk_B"|~"t.ff.reset_B"|~"t.ff.__clk_B"&~"t.ff._mqi"->"t.ff._mqib"+
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"t.ff.d"&"t.ff.__clk"|"t.ff.reset_B"&"t.ff._mqi"&"t.ff._clk"->"t.ff._mqib"-
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("t.ff.d"&"t.ff.__clk_B"|"t.ff._mqi"&"t.ff._clk_B")&"t.ff.reset_B"->"t.ff._mqib"-
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"t.ff._mqib"->"t.ff._mqi"-
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"t.ff._mqib"->"t.ff._mqi"-
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~("t.ff._mqib")->"t.ff._mqi"+
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~("t.ff._mqib")->"t.ff._mqi"+
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~"t.ff._mqi"&~"t.ff.__clk"|~"t.ff.reset_B"|~"t.ff._sqi"&~"t.ff._clk"->"t.ff._sqib"+
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~"t.ff._mqi"&~"t.ff.__clk_B"|~"t.ff.reset_B"|~"t.ff._sqi"&~"t.ff._clk_B"->"t.ff._sqib"+
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"t.ff._mqi"&"t.ff._clk"|"t.ff._sqi"&"t.ff.__clk"&"t.ff.reset_B"->"t.ff._sqib"-
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("t.ff._mqi"&"t.ff._clk_B"|"t.ff._sqi"&"t.ff.__clk_B")&"t.ff.reset_B"->"t.ff._sqib"-
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"t.ff._sqib"->"t.ff._sqi"-
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"t.ff._sqib"->"t.ff._sqi"-
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~("t.ff._sqib")->"t.ff._sqi"+
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~("t.ff._sqib")->"t.ff._sqi"+
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"t.ff._sqib"->"t.ff.q"-
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"t.ff._sqib"->"t.ff.q"-
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~("t.ff._sqib")->"t.ff.q"+
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~("t.ff._sqib")->"t.ff.q"+
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"t.ff.q"->"t.ff.q_B"-
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~("t.ff.q")->"t.ff.q_B"+
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= "Vdd" "t.ff.vdd"
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= "Vdd" "t.ff.vdd"
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= "GND" "t.ff.vss"
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= "GND" "t.ff.vss"
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= "t.q" "t.ff.q"
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= "t.q" "t.ff.q"
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= "t.clk" "t.ff.clk"
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= "t.clk" "t.ff.clk_B"
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= "t.d" "t.ff.d"
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= "t.d" "t.ff.d"
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@ -33,7 +33,7 @@ open tmpl::dataflow_neuro;
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defproc flipflop_test (bool! q; bool? d,clk){
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defproc flipflop_test (bool! q; bool? d,clk){
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DFFQ_R_X1 ff(.d=d,.clk = clk, .q = q);
|
DFFQ_R_X1 ff(.d=d,.clk_B = clk, .q = q);
|
||||||
//Low active Reset
|
//Low active Reset
|
||||||
bool _reset_B;
|
bool _reset_B;
|
||||||
prs {
|
prs {
|
||||||
|
|||||||
@ -1,29 +1,51 @@
|
|||||||
watchall
|
watchall
|
||||||
system "echo '[0] start test'"
|
system "echo '[0] start test'"
|
||||||
|
|
||||||
set Reset 0
|
set Reset 0
|
||||||
set t.d 0
|
set t.d 0
|
||||||
set t.clk 0
|
set t.clk 1
|
||||||
cycle
|
cycle
|
||||||
status X
|
status X
|
||||||
mode run
|
mode run
|
||||||
assert t.q 0
|
assert t.q 0
|
||||||
|
|
||||||
cycle
|
|
||||||
assert t.q 0
|
|
||||||
system "echo '[1] reset completed'"
|
system "echo '[1] reset completed'"
|
||||||
set t.clk 1
|
|
||||||
cycle
|
|
||||||
assert t.q 0
|
|
||||||
system "echo '[2] tested d = 0, clk rise'"
|
system "echo '[2] tested d = 0, clk rise'"
|
||||||
set t.clk 0
|
set t.clk 0
|
||||||
|
set t.d 1
|
||||||
cycle
|
cycle
|
||||||
|
|
||||||
|
set t.clk 1
|
||||||
|
cycle
|
||||||
|
set t.d 0
|
||||||
|
cycle
|
||||||
|
|
||||||
|
assert t.q 1
|
||||||
|
|
||||||
|
set t.clk 0
|
||||||
|
cycle
|
||||||
|
assert t.q 0
|
||||||
|
|
||||||
|
set t.d 0
|
||||||
|
set t.clk 0
|
||||||
|
cycle
|
||||||
|
|
||||||
|
assert t.q 0
|
||||||
|
|
||||||
set t.d 1
|
set t.d 1
|
||||||
cycle
|
cycle
|
||||||
set t.clk 1
|
set t.clk 1
|
||||||
cycle
|
cycle
|
||||||
set t.d 0
|
|
||||||
assert t.q 0
|
assert t.q 0
|
||||||
|
|
||||||
|
system "echo '[3] tested d = 1, clk rise and fall'"
|
||||||
|
|
||||||
|
set t.d 1
|
||||||
|
cycle
|
||||||
set t.clk 0
|
set t.clk 0
|
||||||
cycle
|
cycle
|
||||||
|
set t.d 0
|
||||||
|
cycle
|
||||||
|
|
||||||
assert t.q 1
|
assert t.q 1
|
||||||
system "echo '[3] tested d = 1, clk rise and fall'"
|
|
||||||
@ -1,149 +1,2 @@
|
|||||||
t.registers.read_write_demux.vc.ct.in[0] t.registers.read_write_demux._en2_X_t[0] t.in.d.d[1].f t.registers.read_write_demux._c_f_buf[0] t.registers.read_write_demux.out2_a_B_buf_t.buf1._y t.registers.read_write_demux._out1_a_BX_f[0] t.in.d.d[3].t t.registers._in_read.v t.registers.read_write_demux._in_v t.in.d.d[1].t t.registers.read_write_demux._c_v t.in.d.d[0].t t.registers.read_write_demux._en1_X_f[0] t.in.d.d[4].f t.registers.read_write_demux.out1_en_buf_f.buf1._y t.in.d.d[0].f t.registers.read_write_demux.vc.ct.tmp[5] t.in.d.d[2].f t.registers.read_write_demux._out2_a_BX_t[0] t.in.d.d[3].f t.registers.read_write_demux._c_t_buf[0] t.registers.read_write_demux.vc.ct.C2Els[0]._y t.registers.read_write_demux._out1_a_BX_t[0] t.in.v t.registers.read_write_demux._en t.registers.read_write_demux._out1_a_B t.registers.read_write_demux._out2_a_BX_f[0] t.in.d.d[4].t t.registers.read_write_demux.c_buf_f.buf1._y t.registers.read_write_demux._en2_X_f[0] t.registers.read_write_demux._en1_X_t[0] t.registers.read_write_demux.out1_a_B_buf_t.buf1._y t.registers.read_write_demux.out2_en_buf_f.buf1._y t.registers.read_write_demux._out2_a_B t.registers.read_write_demux.vc.ct.tmp[4] t.registers.read_write_demux.vc.ct.in[2] t.registers.read_write_demux._in_c_v_ t.registers.read_write_demux.out2_en_buf_t.buf1._y t.registers._in_read.a t.in.d.d[2].t t.registers.read_write_demux.out2_a_B_buf_f.buf1._y t.registers.read_write_demux.vc.ct.in[1] t.registers.read_write_demux.c_buf_t.buf1._y t.registers.read_write_demux.c_f_c_t_or._y t.registers.read_write_demux._out_v t.registers._in_write.a t.registers._in_write.v t.registers.read_write_demux.in_v_buf._y t.registers.read_write_demux.out1_a_B_buf_f.buf1._y t.registers.read_write_demux.out1_en_buf_t.buf1._y t.registers.read_write_demux.vc.ct.in[3] t.registers.read_write_demux.vc.OR2_tf[1]._y t.registers.read_write_demux.c_el._y t.registers.read_write_demux.out_or._y t.registers.read_write_demux.vc.OR2_tf[2]._y t.registers.read_write_demux.vc.ct.C2Els[1]._y t.registers.read_write_demux.vc.OR2_tf[0]._y t.registers.read_write_demux.vc.ct.C2Els[2]._y t.registers.read_write_demux.vc.OR2_tf[3]._y
|
t.registers.ff[4].clk_B t.registers._clock_word_temp[0] t.in.d.d[1].f t.registers._clock_temp t.registers.ack_dly._a[1] t.registers.ff[0].clk_B t.registers._clock t.dly_cfg[1] t.registers.ff[0].d t.registers.ack_dly.dly[1].__y t.registers.clk_dly.and2[0]._y t.registers.val_input.ct.in[1] t.in.d.d[4].f t.registers._clock_word_temp[2] t.registers.ff[5].__clk_B t.registers.clk_dly.dly[2]._y t.registers.ack_dly.dly[1].___y t.registers.ff[4]._clk_B t.registers._out_encoder[3] t.registers.clock_buffer[1].buf1._y t.registers.ff[6].clk_B t.registers.atree[2].in[1] t.dly_cfg[0] t.registers._in_v_temp t.registers._out_encoder[2] t.registers._out_encoder[1] t.registers.clk_dly.and2[1]._y t.registers.atree[0].in[0] t.registers.ack_dly.dly[2]._y t.registers.val_input.ct.in[0] t.registers._in_a_temp t.in.d.d[0].f t.in.v t.registers.clk_dly.dly[1].y t.registers.ff[3]._clk_B t.in.d.d[4].t t.registers.clk_dly.dly[2].y t.registers.clk_dly.dly[1].a t.registers._clock_word_temp[3] t.registers.ack_dly.dly[0].___y t.registers.val_input.ct.in[3] t.registers.ff[1].d t.registers.clock_buffer[0].buf1._y t.registers._out_encoder[0] t.registers.atree[1].in[0] t.registers.ack_dly.dly[2].___y t.registers.ack_dly.mu2[0]._y t.registers.atree[1].and2s[0]._y t.registers.clk_dly._a[1] t.registers.atree[0].in[1] t.registers.ff[2].__clk_B t.registers.val_input.ct.in[4] t.registers.val_input.OR2_tf[3]._y t.registers.clk_X.buf1._y t.registers.ff[7].__clk_B t.registers._clock_word_temp[1] t.registers.and_encoder[2]._y t.registers.clk_dly.dly[0].___y t.registers._clock_temp_inv t.registers.ff[7]._clk_B t.registers.clk_dly.dly[1].___y t.in.a t.registers.clk_dly.mu2[1]._s t.registers.ff[1]._clk_B t.registers.clk_dly.dly[0]._y t.registers.val_input.ct.in[2] t.registers.val_input.OR2_tf[2]._y t.registers.val_input.ct.tmp[6] t.registers.clk_dly.dly[1]._y t.registers.ack_dly.dly[2].y t.registers.atree[0].and2s[0]._y t.registers.clk_dly.mu2[1]._y t.registers.clk_dly.mu2[0]._s t.registers.ack_dly.dly[0]._y t.registers.clk_dly.dly[0].a t.registers.ack_dly.dly[0].a t.registers.ff[0]._clk_B t.registers.clock_buffer[2].buf1._y t.registers.clk_dly.dly[1].__y t.registers.ff[2].clk_B t.registers.ff[6]._clk_B t.registers.clk_dly.dly[0].y t.registers.clk_dly.mu2[0]._y t.registers.clock_buffer[3].buf1._y t.registers.val_input.ct.tmp[5] t.registers.ack_dly.dly[1]._y t.registers.and_encoder[0]._y t.registers.val_input.ct.C2Els[1]._y t.registers.ack_dly.dly[1].y t.registers.ack_dly.and2[1]._y t.registers.val_input.OR2_tf[1]._y t.registers.clk_dly.dly[0].__y t.registers.ff[3].__clk_B t.registers.ack_dly.dly[0].y t.registers.clk_dly.dly[2].__y t.registers.atree[3].and2s[0]._y t.registers.ff[6].__clk_B t.registers.ack_dly.dly[1].a t.registers.ff[4].__clk_B t.registers.atree[2].and2s[0]._y t.registers.ff[1].__clk_B t.registers.val_input_X.buf1._y t.registers.ack_dly.dly[2].__y t.registers.val_input.OR2_tf[0]._y t.registers.ff[0].__clk_B t.registers.ff[5]._clk_B t.registers.and_encoder[1]._y t.registers.ack_dly.and2[0]._y t.registers.ack_dly.mu2[1]._s t.registers.clk_dly.dly[2].___y t.registers.val_input.OR2_tf[4]._y t.registers.ack_input_X.buf1._y t.registers.val_input.ct.C2Els[0]._y t.registers.ack_dly.mu2[1]._y t.registers.val_input.ct.C3Els[0]._y t.registers.ack_dly.dly[0].__y t.registers.and_encoder[3]._y t.registers.ff[2]._clk_B t.registers.ack_dly.mu2[0]._s
|
||||||
[0] start test
|
[0] start test
|
||||||
Node `t._in_write.d.d[0].f' not found
|
|
||||||
Node `t._in_read.d.d[0].f' not found
|
|
||||||
106506 t.in.d.d[0].f : 0
|
|
||||||
106506 Reset : 0
|
|
||||||
106506 t.registers._in_read.v : 0
|
|
||||||
106506 t.in.d.d[1].f : 0
|
|
||||||
106506 t.registers._in_write.v : 0
|
|
||||||
106506 t.registers._in_read.a : 0
|
|
||||||
106506 t.in.d.d[3].f : 0
|
|
||||||
106506 t.registers._in_write.a : 0
|
|
||||||
106506 t.data[1].d[1] : 0
|
|
||||||
106506 t.in.d.d[2].t : 0
|
|
||||||
106506 t.data[1].d[0] : 0
|
|
||||||
106506 t.data[0].d[1] : 0
|
|
||||||
106506 t.in.d.d[0].t : 0
|
|
||||||
106506 t.in.d.d[2].f : 0
|
|
||||||
106506 t.data[0].d[0] : 0
|
|
||||||
106506 t.in.d.d[4].t : 0
|
|
||||||
106506 t.in.d.d[1].t : 0
|
|
||||||
106506 t.in.d.d[4].f : 0
|
|
||||||
106506 t.in.d.d[3].t : 0
|
|
||||||
106524 t.registers.read_write_demux.c_buf_t.buf1._y : 1 [by t.in.d.d[4].t:=0]
|
|
||||||
107057 t._reset_B : 1 [by Reset:=0]
|
|
||||||
107460 t.registers.read_write_demux._out2_a_B : 1 [by t.registers._in_read.a:=0]
|
|
||||||
107488 t.registers.read_write_demux.vc.OR2_tf[2]._y : 1 [by t.in.d.d[2].f:=0]
|
|
||||||
107559 t.registers.read_write_demux.reset_buf._y : 0 [by t._reset_B:=1]
|
|
||||||
107577 t.registers.read_write_demux.out_or._y : 1 [by t.registers._in_write.v:=0]
|
|
||||||
107587 t.registers.read_write_demux._out1_a_B : 1 [by t.registers._in_write.a:=0]
|
|
||||||
107598 t.registers.read_write_demux.out1_a_B_buf_f.buf1._y : 0 [by t.registers.read_write_demux._out1_a_B:=1]
|
|
||||||
107627 t.registers.read_write_demux.vc.ct.in[2] : 0 [by t.registers.read_write_demux.vc.OR2_tf[2]._y:=1]
|
|
||||||
107646 t.registers.read_write_demux._out_v : 0 [by t.registers.read_write_demux.out_or._y:=1]
|
|
||||||
107661 t.registers.read_write_demux._en : 1 [by t.registers.read_write_demux._out_v:=0]
|
|
||||||
107662 t.registers.read_write_demux.out2_en_buf_f.buf1._y : 0 [by t.registers.read_write_demux._en:=1]
|
|
||||||
107663 t.registers.read_write_demux.out2_a_B_buf_t.buf1._y : 0 [by t.registers.read_write_demux._out2_a_B:=1]
|
|
||||||
107698 t.registers.read_write_demux.out1_en_buf_t.buf1._y : 0 [by t.registers.read_write_demux._en:=1]
|
|
||||||
107703 t.registers.read_write_demux._out2_a_BX_f[0] : 1 [by t.registers.read_write_demux.out2_a_B_buf_t.buf1._y:=0]
|
|
||||||
107773 t.registers.read_write_demux.out1_en_buf_f.buf1._y : 0 [by t.registers.read_write_demux._en:=1]
|
|
||||||
107802 t.registers.read_write_demux._out1_a_BX_t[0] : 1 [by t.registers.read_write_demux.out1_a_B_buf_f.buf1._y:=0]
|
|
||||||
107860 t.registers.read_write_demux._en1_X_f[0] : 1 [by t.registers.read_write_demux.out1_en_buf_f.buf1._y:=0]
|
|
||||||
107955 t.registers.read_write_demux._en1_X_t[0] : 1 [by t.registers.read_write_demux.out1_en_buf_t.buf1._y:=0]
|
|
||||||
108400 t.registers.read_write_demux.out2_en_buf_t.buf1._y : 0 [by t.registers.read_write_demux._en:=1]
|
|
||||||
108694 t.registers.read_write_demux._en2_X_t[0] : 1 [by t.registers.read_write_demux.out2_en_buf_t.buf1._y:=0]
|
|
||||||
109314 t.registers.read_write_demux.out2_a_B_buf_f.buf1._y : 0 [by t.registers.read_write_demux._out2_a_B:=1]
|
|
||||||
109315 t.registers.read_write_demux._out2_a_BX_t[0] : 1 [by t.registers.read_write_demux.out2_a_B_buf_f.buf1._y:=0]
|
|
||||||
110509 t.registers.read_write_demux.c_f_c_t_or._y : 1 [by t.in.d.d[4].f:=0]
|
|
||||||
110519 t.registers.read_write_demux.vc.OR2_tf[1]._y : 1 [by t.in.d.d[1].t:=0]
|
|
||||||
111284 t.registers.read_write_demux._c_t_buf[0] : 0 [by t.registers.read_write_demux.c_buf_t.buf1._y:=1]
|
|
||||||
112315 t.registers.read_write_demux._c_v : 0 [by t.registers.read_write_demux.c_f_c_t_or._y:=1]
|
|
||||||
112526 t.registers.read_write_demux.vc.ct.in[1] : 0 [by t.registers.read_write_demux.vc.OR2_tf[1]._y:=1]
|
|
||||||
128090 t.registers.read_write_demux.vc.OR2_tf[3]._y : 1 [by t.in.d.d[3].t:=0]
|
|
||||||
129299 t.registers.read_write_demux.vc.ct.in[3] : 0 [by t.registers.read_write_demux.vc.OR2_tf[3]._y:=1]
|
|
||||||
129889 t.registers.read_write_demux.vc.ct.C2Els[1]._y : 1 [by t.registers.read_write_demux.vc.ct.in[3]:=0]
|
|
||||||
130067 t.registers.read_write_demux.vc.ct.tmp[5] : 0 [by t.registers.read_write_demux.vc.ct.C2Els[1]._y:=1]
|
|
||||||
143905 t.registers.read_write_demux._reset_BX : 1 [by t.registers.read_write_demux.reset_buf._y:=0]
|
|
||||||
144708 t.registers.read_write_demux.reset_bufarray.buf3._y : 0 [by t.registers.read_write_demux._reset_BX:=1]
|
|
||||||
144872 t.registers.read_write_demux._reset_BXX[0] : 1 [by t.registers.read_write_demux.reset_bufarray.buf3._y:=0]
|
|
||||||
151407 t.registers.read_write_demux.c_buf_f.buf1._y : 1 [by t.in.d.d[4].f:=0]
|
|
||||||
153602 t.registers.read_write_demux._c_f_buf[0] : 0 [by t.registers.read_write_demux.c_buf_f.buf1._y:=1]
|
|
||||||
155174 t.registers.read_write_demux._en2_X_f[0] : 1 [by t.registers.read_write_demux.out2_en_buf_f.buf1._y:=0]
|
|
||||||
159373 t.registers.read_write_demux.out1_a_B_buf_t.buf1._y : 0 [by t.registers.read_write_demux._out1_a_B:=1]
|
|
||||||
159395 t.registers.read_write_demux._out1_a_BX_f[0] : 1 [by t.registers.read_write_demux.out1_a_B_buf_t.buf1._y:=0]
|
|
||||||
160976 t.registers.read_write_demux.vc.OR2_tf[0]._y : 1 [by t.in.d.d[0].t:=0]
|
|
||||||
161823 t.registers.read_write_demux.vc.ct.in[0] : 0 [by t.registers.read_write_demux.vc.OR2_tf[0]._y:=1]
|
|
||||||
191951 t.registers.read_write_demux.vc.ct.C2Els[0]._y : 1 [by t.registers.read_write_demux.vc.ct.in[0]:=0]
|
|
||||||
192084 t.registers.read_write_demux.vc.ct.tmp[4] : 0 [by t.registers.read_write_demux.vc.ct.C2Els[0]._y:=1]
|
|
||||||
207746 t.registers.read_write_demux.vc.ct.C2Els[2]._y : 1 [by t.registers.read_write_demux.vc.ct.tmp[4]:=0]
|
|
||||||
208105 t.registers.read_write_demux._in_v : 0 [by t.registers.read_write_demux.vc.ct.C2Els[2]._y:=1]
|
|
||||||
208326 t.registers.read_write_demux.c_el._y : 1 [by t.registers.read_write_demux._in_v:=0]
|
|
||||||
208333 t.registers.read_write_demux._in_c_v_ : 0 [by t.registers.read_write_demux.c_el._y:=1]
|
|
||||||
222221 t.registers.read_write_demux.in_v_buf._y : 1 [by t.registers.read_write_demux._in_v:=0]
|
|
||||||
222251 t.in.v : 0 [by t.registers.read_write_demux.in_v_buf._y:=1]
|
|
||||||
|
|
||||||
[1] reset completed
|
|
||||||
222251 t.dly_cfg[0] : 1
|
|
||||||
222251 t.dly_cfg[1] : 1
|
|
||||||
[2] delay line set
|
|
||||||
222251 t.in.d.d[0].t : 1
|
|
||||||
222251 t.in.d.d[4].t : 1
|
|
||||||
222251 t.in.d.d[2].f : 1
|
|
||||||
222251 t.in.d.d[1].t : 1
|
|
||||||
222251 t.in.d.d[3].f : 1
|
|
||||||
222258 t.registers.read_write_demux.vc.OR2_tf[1]._y : 0 [by t.in.d.d[1].t:=1]
|
|
||||||
222342 t.registers.read_write_demux.c_f_c_t_or._y : 0 [by t.in.d.d[4].t:=1]
|
|
||||||
222364 t.registers.read_write_demux.vc.ct.in[1] : 1 [by t.registers.read_write_demux.vc.OR2_tf[1]._y:=0]
|
|
||||||
222420 t.registers.read_write_demux._c_v : 1 [by t.registers.read_write_demux.c_f_c_t_or._y:=0]
|
|
||||||
224440 t.registers.read_write_demux.vc.OR2_tf[2]._y : 0 [by t.in.d.d[2].f:=1]
|
|
||||||
224715 t.registers.read_write_demux.vc.ct.in[2] : 1 [by t.registers.read_write_demux.vc.OR2_tf[2]._y:=0]
|
|
||||||
225038 t.registers.read_write_demux.vc.OR2_tf[3]._y : 0 [by t.in.d.d[3].f:=1]
|
|
||||||
228964 t.registers.read_write_demux.vc.OR2_tf[0]._y : 0 [by t.in.d.d[0].t:=1]
|
|
||||||
229419 t.registers.read_write_demux.vc.ct.in[0] : 1 [by t.registers.read_write_demux.vc.OR2_tf[0]._y:=0]
|
|
||||||
229431 t.registers.read_write_demux.vc.ct.C2Els[0]._y : 0 [by t.registers.read_write_demux.vc.ct.in[0]:=1]
|
|
||||||
229835 t.registers.read_write_demux.vc.ct.tmp[4] : 1 [by t.registers.read_write_demux.vc.ct.C2Els[0]._y:=0]
|
|
||||||
244034 t.registers.read_write_demux.vc.ct.in[3] : 1 [by t.registers.read_write_demux.vc.OR2_tf[3]._y:=0]
|
|
||||||
244046 t.registers.read_write_demux.vc.ct.C2Els[1]._y : 0 [by t.registers.read_write_demux.vc.ct.in[3]:=1]
|
|
||||||
249962 t.registers.read_write_demux.vc.ct.tmp[5] : 1 [by t.registers.read_write_demux.vc.ct.C2Els[1]._y:=0]
|
|
||||||
254238 t.registers.read_write_demux.vc.ct.C2Els[2]._y : 0 [by t.registers.read_write_demux.vc.ct.tmp[5]:=1]
|
|
||||||
257137 t.registers.read_write_demux._in_v : 1 [by t.registers.read_write_demux.vc.ct.C2Els[2]._y:=0]
|
|
||||||
257139 t.registers.read_write_demux.c_el._y : 0 [by t.registers.read_write_demux._in_v:=1]
|
|
||||||
261432 t.registers.read_write_demux.in_v_buf._y : 0 [by t.registers.read_write_demux._in_v:=1]
|
|
||||||
261674 t.registers.read_write_demux._in_c_v_ : 1 [by t.registers.read_write_demux.c_el._y:=0]
|
|
||||||
262681 t.in.v : 1 [by t.registers.read_write_demux.in_v_buf._y:=0]
|
|
||||||
279712 t.registers.read_write_demux.c_buf_t.buf1._y : 0 [by t.in.d.d[4].t:=1]
|
|
||||||
283211 t.registers.read_write_demux._c_t_buf[0] : 1 [by t.registers.read_write_demux.c_buf_t.buf1._y:=0]
|
|
||||||
283286 t.registers.read_write_demux.out1_f_buf_func[3]._y : 0 [by t.registers.read_write_demux._c_t_buf[0]:=1]
|
|
||||||
283349 t.registers.read_write_demux.out1_t_buf_func[1]._y : 0 [by t.registers.read_write_demux._c_t_buf[0]:=1]
|
|
||||||
283351 t.registers.read_write_demux.out1_t_buf_func[1].y : 1 [by t.registers.read_write_demux.out1_t_buf_func[1]._y:=0]
|
|
||||||
283377 t.registers.read_write_demux.out1_f_buf_func[2]._y : 0 [by t.registers.read_write_demux._c_t_buf[0]:=1]
|
|
||||||
283556 t.registers.read_write_demux.out1_t_buf_func[0]._y : 0 [by t.registers.read_write_demux._c_t_buf[0]:=1]
|
|
||||||
283557 t.registers.read_write_demux.out1_t_buf_func[0].y : 1 [by t.registers.read_write_demux.out1_t_buf_func[0]._y:=0]
|
|
||||||
288549 t.registers.read_write_demux.out1_f_buf_func[3].y : 1 [by t.registers.read_write_demux.out1_f_buf_func[3]._y:=0]
|
|
||||||
327294 t.registers.read_write_demux.out1_f_buf_func[2].y : 1 [by t.registers.read_write_demux.out1_f_buf_func[2]._y:=0]
|
|
||||||
Node `t.registers._clock' not found
|
|
||||||
Node `t.registers._out_encoder[0]' not found
|
|
||||||
Node `t.registers._out_encoder[1]' not found
|
|
||||||
Node `t.registers._out_encoder[2]' not found
|
|
||||||
Node `t.registers._out_encoder[3]' not found
|
|
||||||
327294 t.in.d.d[0].t : 0
|
|
||||||
327294 t.in.d.d[4].t : 0
|
|
||||||
327294 t.in.d.d[2].f : 0
|
|
||||||
327294 t.in.d.d[1].t : 0
|
|
||||||
327294 t.in.d.d[3].f : 0
|
|
||||||
327305 t.registers.read_write_demux.c_buf_t.buf1._y : 1 [by t.in.d.d[4].t:=0]
|
|
||||||
327310 t.registers.read_write_demux.vc.OR2_tf[3]._y : 1 [by t.in.d.d[3].f:=0]
|
|
||||||
327361 t.registers.read_write_demux.vc.OR2_tf[2]._y : 1 [by t.in.d.d[2].f:=0]
|
|
||||||
327664 t.registers.read_write_demux.c_f_c_t_or._y : 1 [by t.in.d.d[4].t:=0]
|
|
||||||
327838 t.registers.read_write_demux.vc.ct.in[3] : 0 [by t.registers.read_write_demux.vc.OR2_tf[3]._y:=1]
|
|
||||||
327842 t.registers.read_write_demux.vc.OR2_tf[0]._y : 1 [by t.in.d.d[0].t:=0]
|
|
||||||
329796 t.registers.read_write_demux.vc.ct.in[2] : 0 [by t.registers.read_write_demux.vc.OR2_tf[2]._y:=1]
|
|
||||||
329935 t.registers.read_write_demux.vc.OR2_tf[1]._y : 1 [by t.in.d.d[1].t:=0]
|
|
||||||
329937 t.registers.read_write_demux.vc.ct.in[1] : 0 [by t.registers.read_write_demux.vc.OR2_tf[1]._y:=1]
|
|
||||||
331867 t.registers.read_write_demux._c_t_buf[0] : 0 [by t.registers.read_write_demux.c_buf_t.buf1._y:=1]
|
|
||||||
342837 t.registers.read_write_demux.vc.ct.C2Els[1]._y : 1 [by t.registers.read_write_demux.vc.ct.in[2]:=0]
|
|
||||||
351767 t.registers.read_write_demux.vc.ct.in[0] : 0 [by t.registers.read_write_demux.vc.OR2_tf[0]._y:=1]
|
|
||||||
351770 t.registers.read_write_demux.vc.ct.C2Els[0]._y : 1 [by t.registers.read_write_demux.vc.ct.in[0]:=0]
|
|
||||||
351799 t.registers.read_write_demux.vc.ct.tmp[4] : 0 [by t.registers.read_write_demux.vc.ct.C2Els[0]._y:=1]
|
|
||||||
354544 t.registers.read_write_demux._c_v : 0 [by t.registers.read_write_demux.c_f_c_t_or._y:=1]
|
|
||||||
403795 t.registers.read_write_demux.vc.ct.tmp[5] : 0 [by t.registers.read_write_demux.vc.ct.C2Els[1]._y:=1]
|
|
||||||
404112 t.registers.read_write_demux.vc.ct.C2Els[2]._y : 1 [by t.registers.read_write_demux.vc.ct.tmp[5]:=0]
|
|
||||||
405713 t.registers.read_write_demux._in_v : 0 [by t.registers.read_write_demux.vc.ct.C2Els[2]._y:=1]
|
|
||||||
405757 t.registers.read_write_demux.c_el._y : 1 [by t.registers.read_write_demux._in_v:=0]
|
|
||||||
405866 t.registers.read_write_demux.in_v_buf._y : 1 [by t.registers.read_write_demux._in_v:=0]
|
|
||||||
408518 t.registers.read_write_demux._in_c_v_ : 0 [by t.registers.read_write_demux.c_el._y:=1]
|
|
||||||
419549 t.in.v : 0 [by t.registers.read_write_demux.in_v_buf._y:=1]
|
|
||||||
[3] clock checked
|
|
||||||
Node `t.registers._clock' not found
|
|
||||||
Node `t.registers.ff[0].q' not found
|
|
||||||
Node `t.registers.ff[1].q' not found
|
|
||||||
|
|||||||
File diff suppressed because it is too large
Load Diff
@ -33,7 +33,7 @@ open tmpl::dataflow_neuro;
|
|||||||
// 2 bits encoder, 2 bits long words, 2 delays????
|
// 2 bits encoder, 2 bits long words, 2 delays????
|
||||||
defproc register_test (avMx1of2<1+2+2> in; d1of<2> data[1<<2]; bool? dly_cfg[2]){
|
defproc register_test (avMx1of2<1+2+2> in; d1of<2> data[1<<2]; bool? dly_cfg[2]){
|
||||||
|
|
||||||
register_rw_v2<2,2,2> registers(.in=in,.data = data);
|
register_w<2,2,2> registers(.in=in,.data = data);
|
||||||
//Low active Reset
|
//Low active Reset
|
||||||
bool _reset_B;
|
bool _reset_B;
|
||||||
power _supply;
|
power _supply;
|
||||||
|
|||||||
@ -2,12 +2,12 @@ watchall
|
|||||||
system "echo '[0] start test'"
|
system "echo '[0] start test'"
|
||||||
|
|
||||||
set-qdi-channel-neutral "t.in" 5
|
set-qdi-channel-neutral "t.in" 5
|
||||||
set-qdi-channel-neutral "t._in_write" 5
|
|
||||||
set-qdi-channel-neutral "t._in_read" 5
|
|
||||||
set t.data[0].d[0] 0
|
set t.data[0].d[0] 0
|
||||||
set t.data[0].d[1] 0
|
set t.data[0].d[1] 0
|
||||||
set t.data[1].d[0] 0
|
set t.data[1].d[0] 0
|
||||||
set t.data[1].d[1] 0
|
set t.data[1].d[1] 0
|
||||||
|
|
||||||
set t.registers._in_write.a 0
|
set t.registers._in_write.a 0
|
||||||
set t.registers._in_read.a 0
|
set t.registers._in_read.a 0
|
||||||
set t.registers._in_write.v 0
|
set t.registers._in_write.v 0
|
||||||
|
|||||||
File diff suppressed because one or more lines are too long
Binary file not shown.
File diff suppressed because it is too large
Load Diff
@ -31,9 +31,9 @@ import globals;
|
|||||||
|
|
||||||
open tmpl::dataflow_neuro;
|
open tmpl::dataflow_neuro;
|
||||||
// 2 bits encoder, 2 bits long words, 2 delays????
|
// 2 bits encoder, 2 bits long words, 2 delays????
|
||||||
defproc register_test (avMx1of2<1+2+2> in; avMx1of2<2+2> out;d1of<2> data[1<<2]; bool? dly_cfg[2]){
|
defproc register_test (avMx1of2<1+2+2> in; avMx1of2<2+2> out;d1of<2> data[1<<2]; bool? dly_cfg[3]){
|
||||||
|
|
||||||
register_rw<2,2,2> registers(.in=in,.data = data,.out = out);
|
register_rw<2,2,3> registers(.in=in,.data = data,.out = out);
|
||||||
//Low active Reset
|
//Low active Reset
|
||||||
bool _reset_B;
|
bool _reset_B;
|
||||||
power _supply;
|
power _supply;
|
||||||
|
|||||||
@ -1,4 +1,9 @@
|
|||||||
watchall
|
watch t.registers.clock_buffer[0].out[0]
|
||||||
|
watch t.registers.clock_buffer[1].out[0]
|
||||||
|
watch t.registers.clock_buffer[2].out[0]
|
||||||
|
watch t.registers.clock_buffer[3].out[0]
|
||||||
|
|
||||||
|
|
||||||
system "echo '[0] start test'"
|
system "echo '[0] start test'"
|
||||||
system "echo '----------------------------------------------------------'"
|
system "echo '----------------------------------------------------------'"
|
||||||
|
|
||||||
@ -10,21 +15,32 @@ set t.data[1].d[0] 0
|
|||||||
set t.data[1].d[1] 0
|
set t.data[1].d[1] 0
|
||||||
set t.dly_cfg[0] 1
|
set t.dly_cfg[0] 1
|
||||||
set t.dly_cfg[1] 1
|
set t.dly_cfg[1] 1
|
||||||
|
set t.dly_cfg[2] 1
|
||||||
|
|
||||||
set t.out.a 0
|
set t.out.a 0
|
||||||
set t.out.v 0
|
set t.out.v 0
|
||||||
cycle
|
cycle
|
||||||
#set t.registers._in_write.a 0
|
set t.in.a 0
|
||||||
set Reset 0
|
set Reset 0
|
||||||
set t.dly_cfg[0] 1
|
|
||||||
set t.dly_cfg[1] 1
|
|
||||||
cycle
|
cycle
|
||||||
assert-qdi-channel-neutral "t.in" 5
|
assert-qdi-channel-neutral "t.in" 5
|
||||||
assert-qdi-channel-neutral "t.out" 4
|
assert-qdi-channel-neutral "t.out" 4
|
||||||
# There shouldnt be any status X
|
mode run
|
||||||
status X
|
|
||||||
#mode run
|
|
||||||
cycle
|
cycle
|
||||||
|
|
||||||
|
# check delay config programming
|
||||||
|
assert t.registers.clk_dly.s[0] 1
|
||||||
|
assert t.registers.clk_dly.s[1] 1
|
||||||
|
|
||||||
|
assert t.registers.ff[0].q 0
|
||||||
|
assert t.registers.ff[1].q 0
|
||||||
|
assert t.registers.ff[2].q 0
|
||||||
|
assert t.registers.ff[3].q 0
|
||||||
|
assert t.registers.ff[4].q 0
|
||||||
|
assert t.registers.ff[5].q 0
|
||||||
|
assert t.registers.ff[6].q 0
|
||||||
|
assert t.registers.ff[7].q 0
|
||||||
|
|
||||||
assert-qdi-channel-neutral "t.out" 4
|
assert-qdi-channel-neutral "t.out" 4
|
||||||
assert t.data[0].d[0] 0
|
assert t.data[0].d[0] 0
|
||||||
assert t.data[0].d[1] 0
|
assert t.data[0].d[1] 0
|
||||||
@ -34,20 +50,17 @@ cycle
|
|||||||
system "echo '[1] reset completed'"
|
system "echo '[1] reset completed'"
|
||||||
system "echo '----------------------------------------------------------'"
|
system "echo '----------------------------------------------------------'"
|
||||||
|
|
||||||
# Set delay config lines
|
|
||||||
|
|
||||||
cycle
|
|
||||||
system "echo '[2] delay line set'"
|
|
||||||
system "echo '----------------------------------------------------------'"
|
|
||||||
|
|
||||||
|
|
||||||
set-qdi-channel-valid "t.in" 5 3
|
set-qdi-channel-valid "t.in" 5 3
|
||||||
# 3 -> 00011 -> writing mode, address 00, word 11
|
# 3 -> 00011 -> writing mode, address 00, word 11
|
||||||
cycle
|
cycle
|
||||||
|
|
||||||
assert t.in.a 1
|
assert t.in.a 1
|
||||||
assert-qdi-channel-neutral "t.out" 4
|
assert-qdi-channel-neutral "t.out" 4
|
||||||
|
assert t.registers._in_v_temp 1
|
||||||
set-qdi-channel-neutral "t.in" 5
|
set-qdi-channel-neutral "t.in" 5
|
||||||
cycle
|
cycle
|
||||||
|
assert t.registers._in_v_temp 0
|
||||||
|
|
||||||
assert t.registers.ff[0].q 1
|
assert t.registers.ff[0].q 1
|
||||||
assert t.registers.ff[1].q 1
|
assert t.registers.ff[1].q 1
|
||||||
assert t.registers.ff[2].q 0
|
assert t.registers.ff[2].q 0
|
||||||
@ -56,31 +69,397 @@ assert t.registers.ff[4].q 0
|
|||||||
assert t.registers.ff[5].q 0
|
assert t.registers.ff[5].q 0
|
||||||
assert t.registers.ff[6].q 0
|
assert t.registers.ff[6].q 0
|
||||||
assert t.registers.ff[7].q 0
|
assert t.registers.ff[7].q 0
|
||||||
|
assert t.in.v 0
|
||||||
|
|
||||||
|
set t.out.a 0
|
||||||
|
set t.out.v 0
|
||||||
|
assert t.in.a 0
|
||||||
|
cycle
|
||||||
|
assert t.registers._clock_temp_inv 1
|
||||||
|
|
||||||
system "echo '[3] first writing done'"
|
system "echo '[3] first writing done'"
|
||||||
system "echo '----------------------------------------------------------'"
|
system "echo '----------------------------------------------------------'"
|
||||||
|
|
||||||
set-qdi-channel-valid "t.in" 5 16
|
# set-qdi-channel-valid "t.in" 5 16
|
||||||
# 16 -> 10000 -> reading mode, address 00, word 00 (word doesnt needed here)
|
# # 16 -> 10000 -> reading mode, address 00, word 00 (word doesnt needed here)
|
||||||
cycle
|
# cycle
|
||||||
assert t.registers._clock_temp_inv 1
|
# assert t.registers._clock_temp_inv 1
|
||||||
assert-qdi-channel-valid "t.out" 4 3
|
|
||||||
set t.out.v 1
|
# assert t.registers.word_to_read_X[0].out[0] 1
|
||||||
cycle
|
# assert t.registers.word_to_read_X[0].out[1] 1
|
||||||
set t.out.a 1
|
# assert t.registers.word_to_read_X[0].out[2] 1
|
||||||
assert t.registers._clock_temp_inv 1
|
# assert t.registers.word_to_read_X[0].out[3] 1
|
||||||
cycle
|
|
||||||
assert t.in.a 1
|
# assert-qdi-channel-valid "t.out" 4 3
|
||||||
set-qdi-channel-neutral "t.in" 5
|
# set t.out.v 1
|
||||||
assert t.registers._clock_temp_inv 1
|
# cycle
|
||||||
cycle
|
# set t.out.a 1
|
||||||
assert t.registers._clock_temp_inv 1
|
# assert t.registers._clock_temp_inv 1
|
||||||
assert t.registers.ff[0].q 1
|
# cycle
|
||||||
assert t.registers.ff[1].q 1
|
# assert t.in.a 1
|
||||||
assert t.registers.ff[2].q 0
|
# set-qdi-channel-neutral "t.in" 5
|
||||||
assert t.registers.ff[3].q 0
|
# assert t.registers._clock_temp_inv 1
|
||||||
assert-qdi-channel-neutral "t.out" 4
|
# cycle
|
||||||
system "echo '[4] reading done'"
|
# assert t.registers.ff[0].q 1
|
||||||
system "echo '----------------------------------------------------------'"
|
# assert t.registers.ff[1].q 1
|
||||||
|
# assert t.registers.ff[2].q 0
|
||||||
|
# assert t.registers.ff[3].q 0
|
||||||
|
# assert-qdi-channel-neutral "t.out" 4
|
||||||
|
# assert t.registers._in_v_temp 0
|
||||||
|
|
||||||
|
# set t.out.a 0
|
||||||
|
# set t.out.v 0
|
||||||
|
# assert t.in.a 0
|
||||||
|
# cycle
|
||||||
|
|
||||||
|
# system "echo '[4] reading done'"
|
||||||
|
# system "echo '----------------------------------------------------------'"
|
||||||
|
|
||||||
|
|
||||||
|
# set-qdi-channel-valid "t.in" 5 7
|
||||||
|
# # 7 -> 00111 -> writing mode, address 01, word 11
|
||||||
|
# cycle
|
||||||
|
|
||||||
|
# assert t.in.a 1
|
||||||
|
# assert-qdi-channel-neutral "t.out" 4
|
||||||
|
# assert t.registers._in_v_temp 1
|
||||||
|
|
||||||
|
# set-qdi-channel-neutral "t.in" 5
|
||||||
|
# cycle
|
||||||
|
# assert t.registers._in_v_temp 0
|
||||||
|
|
||||||
|
# assert t.registers.ff[0].q 1
|
||||||
|
# assert t.registers.ff[1].q 1
|
||||||
|
# assert t.registers.ff[2].q 1
|
||||||
|
# assert t.registers.ff[3].q 1
|
||||||
|
# assert t.registers.ff[4].q 0
|
||||||
|
# assert t.registers.ff[5].q 0
|
||||||
|
# assert t.registers.ff[6].q 0
|
||||||
|
# assert t.registers.ff[7].q 0
|
||||||
|
# assert t.in.v 0
|
||||||
|
|
||||||
|
# set t.out.a 0
|
||||||
|
# set t.out.v 0
|
||||||
|
# cycle
|
||||||
|
# assert t.registers._clock_temp_inv 1
|
||||||
|
|
||||||
|
# system "echo '[5] second writing done'"
|
||||||
|
# system "echo '----------------------------------------------------------'"
|
||||||
|
|
||||||
|
# set-qdi-channel-valid "t.in" 5 11
|
||||||
|
# # 11 -> 01011 -> writing mode, address 10, word 11
|
||||||
|
# cycle
|
||||||
|
|
||||||
|
# assert t.in.a 1
|
||||||
|
# assert-qdi-channel-neutral "t.out" 4
|
||||||
|
# assert t.registers._in_v_temp 1
|
||||||
|
# set-qdi-channel-neutral "t.in" 5
|
||||||
|
# cycle
|
||||||
|
# assert t.registers._in_v_temp 0
|
||||||
|
|
||||||
|
# assert t.registers.ff[0].q 1
|
||||||
|
# assert t.registers.ff[1].q 1
|
||||||
|
# assert t.registers.ff[2].q 1
|
||||||
|
# assert t.registers.ff[3].q 1
|
||||||
|
# assert t.registers.ff[4].q 1
|
||||||
|
# assert t.registers.ff[5].q 1
|
||||||
|
# assert t.registers.ff[6].q 0
|
||||||
|
# assert t.registers.ff[7].q 0
|
||||||
|
# assert t.in.v 0
|
||||||
|
|
||||||
|
# set t.out.a 0
|
||||||
|
# set t.out.v 0
|
||||||
|
# assert t.in.a 0
|
||||||
|
# cycle
|
||||||
|
|
||||||
|
# system "echo '[6] third writing done'"
|
||||||
|
# system "echo '----------------------------------------------------------'"
|
||||||
|
|
||||||
|
# set-qdi-channel-valid "t.in" 5 15
|
||||||
|
# # 15 -> 01111 -> writing mode, address 11, word 11
|
||||||
|
# cycle
|
||||||
|
|
||||||
|
# assert t.in.a 1
|
||||||
|
# assert-qdi-channel-neutral "t.out" 4
|
||||||
|
# assert t.registers._in_v_temp 1
|
||||||
|
# set-qdi-channel-neutral "t.in" 5
|
||||||
|
# cycle
|
||||||
|
# assert t.registers._in_v_temp 0
|
||||||
|
|
||||||
|
# assert t.registers.ff[0].q 1
|
||||||
|
# assert t.registers.ff[1].q 1
|
||||||
|
# assert t.registers.ff[2].q 1
|
||||||
|
# assert t.registers.ff[3].q 1
|
||||||
|
# assert t.registers.ff[4].q 1
|
||||||
|
# assert t.registers.ff[5].q 1
|
||||||
|
# assert t.registers.ff[6].q 1
|
||||||
|
# assert t.registers.ff[7].q 1
|
||||||
|
# assert t.in.v 0
|
||||||
|
|
||||||
|
# set t.out.a 0
|
||||||
|
# set t.out.v 0
|
||||||
|
# assert t.in.a 0
|
||||||
|
# cycle
|
||||||
|
|
||||||
|
# system "echo '[7] fourth writing done'"
|
||||||
|
# system "echo '----------------------------------------------------------'"
|
||||||
|
|
||||||
|
# set-qdi-channel-valid "t.in" 5 28
|
||||||
|
# # 28 -> 11100 -> reading mode, address 11, word 00 (word doesnt needed here)
|
||||||
|
# cycle
|
||||||
|
# assert t.registers._clock_temp_inv 1
|
||||||
|
|
||||||
|
# assert-qdi-channel-valid "t.out" 4 15
|
||||||
|
# set t.out.v 1
|
||||||
|
# cycle
|
||||||
|
# set t.out.a 1
|
||||||
|
# assert t.registers._clock_temp_inv 1
|
||||||
|
# cycle
|
||||||
|
# assert t.in.a 1
|
||||||
|
# set-qdi-channel-neutral "t.in" 5
|
||||||
|
# assert t.registers._clock_temp_inv 1
|
||||||
|
# cycle
|
||||||
|
# assert-qdi-channel-neutral "t.out" 4
|
||||||
|
# assert t.registers._in_v_temp 0
|
||||||
|
|
||||||
|
# set t.out.a 0
|
||||||
|
# set t.out.v 0
|
||||||
|
# assert t.in.a 0
|
||||||
|
# cycle
|
||||||
|
|
||||||
|
# system "echo '[8] 11 reading done'"
|
||||||
|
# system "echo '----------------------------------------------------------'"
|
||||||
|
|
||||||
|
# set-qdi-channel-valid "t.in" 5 20
|
||||||
|
# # 20 -> 10100 -> reading mode, address 01, word 00 (word doesnt needed here)
|
||||||
|
# cycle
|
||||||
|
# assert t.registers._clock_temp_inv 1
|
||||||
|
|
||||||
|
# assert-qdi-channel-valid "t.out" 4 7
|
||||||
|
# set t.out.v 1
|
||||||
|
# cycle
|
||||||
|
# set t.out.a 1
|
||||||
|
# assert t.registers._clock_temp_inv 1
|
||||||
|
# cycle
|
||||||
|
# assert t.in.a 1
|
||||||
|
# set-qdi-channel-neutral "t.in" 5
|
||||||
|
# assert t.registers._clock_temp_inv 1
|
||||||
|
# cycle
|
||||||
|
# assert-qdi-channel-neutral "t.out" 4
|
||||||
|
# assert t.registers._in_v_temp 0
|
||||||
|
|
||||||
|
# set t.out.a 0
|
||||||
|
# set t.out.v 0
|
||||||
|
# assert t.in.a 0
|
||||||
|
# cycle
|
||||||
|
|
||||||
|
# system "echo '[9] 01 reading done'"
|
||||||
|
# system "echo '----------------------------------------------------------'"
|
||||||
|
|
||||||
|
# set-qdi-channel-valid "t.in" 5 24
|
||||||
|
# # 24 -> 11000 -> reading mode, address 10, word 00 (word doesnt needed here)
|
||||||
|
# cycle
|
||||||
|
# assert t.registers._clock_temp_inv 1
|
||||||
|
|
||||||
|
# assert-qdi-channel-valid "t.out" 4 11
|
||||||
|
# set t.out.v 1
|
||||||
|
# cycle
|
||||||
|
# set t.out.a 1
|
||||||
|
# assert t.registers._clock_temp_inv 1
|
||||||
|
# cycle
|
||||||
|
# assert t.in.a 1
|
||||||
|
# set-qdi-channel-neutral "t.in" 5
|
||||||
|
# assert t.registers._clock_temp_inv 1
|
||||||
|
# cycle
|
||||||
|
# assert-qdi-channel-neutral "t.out" 4
|
||||||
|
# assert t.registers._in_v_temp 0
|
||||||
|
|
||||||
|
# set t.out.a 0
|
||||||
|
# set t.out.v 0
|
||||||
|
# assert t.in.a 0
|
||||||
|
# cycle
|
||||||
|
|
||||||
|
# system "echo '[8] 10 reading done'"
|
||||||
|
# system "echo '----------------------------------------------------------'"
|
||||||
|
|
||||||
|
# set-qdi-channel-valid "t.in" 5 13
|
||||||
|
# # 13 -> 01101 -> writing mode, address 11, word 01
|
||||||
|
# cycle
|
||||||
|
|
||||||
|
# assert t.in.a 1
|
||||||
|
# assert-qdi-channel-neutral "t.out" 4
|
||||||
|
# assert t.registers._in_v_temp 1
|
||||||
|
# set-qdi-channel-neutral "t.in" 5
|
||||||
|
# cycle
|
||||||
|
# assert t.registers._in_v_temp 0
|
||||||
|
|
||||||
|
# assert t.registers.ff[0].q 1
|
||||||
|
# assert t.registers.ff[1].q 1
|
||||||
|
# assert t.registers.ff[2].q 1
|
||||||
|
# assert t.registers.ff[3].q 1
|
||||||
|
# assert t.registers.ff[4].q 1
|
||||||
|
# assert t.registers.ff[5].q 1
|
||||||
|
# assert t.registers.ff[6].q 1
|
||||||
|
# assert t.registers.ff[7].q 1
|
||||||
|
# assert t.in.v 0
|
||||||
|
|
||||||
|
# set t.out.a 0
|
||||||
|
# set t.out.v 0
|
||||||
|
# assert t.in.a 0
|
||||||
|
# cycle
|
||||||
|
|
||||||
|
# system "echo '[9] Rewrite 11 to 01'"
|
||||||
|
# system "echo '----------------------------------------------------------'"
|
||||||
|
|
||||||
|
|
||||||
|
# set-qdi-channel-valid "t.in" 5 0
|
||||||
|
# # 13 -> 00000 -> writing mode, address 00, word 00
|
||||||
|
# cycle
|
||||||
|
|
||||||
|
# assert t.in.a 1
|
||||||
|
# assert-qdi-channel-neutral "t.out" 4
|
||||||
|
# assert t.registers._in_v_temp 1
|
||||||
|
# set-qdi-channel-neutral "t.in" 5
|
||||||
|
# cycle
|
||||||
|
# assert t.registers._in_v_temp 0
|
||||||
|
|
||||||
|
# assert t.registers.ff[0].q 0
|
||||||
|
# assert t.registers.ff[1].q 0
|
||||||
|
# assert t.registers.ff[2].q 1
|
||||||
|
# assert t.registers.ff[3].q 1
|
||||||
|
# assert t.registers.ff[4].q 1
|
||||||
|
# assert t.registers.ff[5].q 1
|
||||||
|
# assert t.registers.ff[6].q 1
|
||||||
|
# assert t.registers.ff[7].q 1
|
||||||
|
# assert t.in.v 0
|
||||||
|
|
||||||
|
# set t.out.a 0
|
||||||
|
# set t.out.v 0
|
||||||
|
# assert t.in.a 0
|
||||||
|
# cycle
|
||||||
|
|
||||||
|
# system "echo '[9] Rewrite 11 to 01'"
|
||||||
|
# system "echo '----------------------------------------------------------'"
|
||||||
|
|
||||||
|
|
||||||
|
# set-qdi-channel-valid "t.in" 5 0
|
||||||
|
# # 0 -> 00000 -> writing mode, address 00, word 00
|
||||||
|
# cycle
|
||||||
|
|
||||||
|
# assert t.in.a 1
|
||||||
|
# assert-qdi-channel-neutral "t.out" 4
|
||||||
|
# assert t.registers._in_v_temp 1
|
||||||
|
# set-qdi-channel-neutral "t.in" 5
|
||||||
|
# cycle
|
||||||
|
# assert t.registers._in_v_temp 0
|
||||||
|
|
||||||
|
# assert t.registers.ff[0].q 0
|
||||||
|
# assert t.registers.ff[1].q 0
|
||||||
|
# assert t.registers.ff[2].q 1
|
||||||
|
# assert t.registers.ff[3].q 1
|
||||||
|
# assert t.registers.ff[4].q 1
|
||||||
|
# assert t.registers.ff[5].q 1
|
||||||
|
# assert t.registers.ff[6].q 1
|
||||||
|
# assert t.registers.ff[7].q 0
|
||||||
|
# assert t.in.v 0
|
||||||
|
|
||||||
|
# set t.out.a 0
|
||||||
|
# set t.out.v 0
|
||||||
|
# assert t.in.a 0
|
||||||
|
# cycle
|
||||||
|
|
||||||
|
# system "echo '[9] Rewrite 11 to 01'"
|
||||||
|
# system "echo '----------------------------------------------------------'"
|
||||||
|
|
||||||
|
|
||||||
|
# set-qdi-channel-valid "t.in" 5 0
|
||||||
|
# # 0 -> 00000 -> writing mode, address 00, word 00
|
||||||
|
# cycle
|
||||||
|
|
||||||
|
# assert t.in.a 1
|
||||||
|
# assert-qdi-channel-neutral "t.out" 4
|
||||||
|
# assert t.registers._in_v_temp 1
|
||||||
|
# set-qdi-channel-neutral "t.in" 5
|
||||||
|
# cycle
|
||||||
|
# assert t.registers._in_v_temp 0
|
||||||
|
|
||||||
|
# assert t.registers.ff[0].q 0
|
||||||
|
# assert t.registers.ff[1].q 0
|
||||||
|
# assert t.registers.ff[2].q 1
|
||||||
|
# assert t.registers.ff[3].q 1
|
||||||
|
# assert t.registers.ff[4].q 1
|
||||||
|
# assert t.registers.ff[5].q 1
|
||||||
|
# assert t.registers.ff[6].q 1
|
||||||
|
# assert t.registers.ff[7].q 0
|
||||||
|
# assert t.in.v 0
|
||||||
|
|
||||||
|
# set t.out.a 0
|
||||||
|
# set t.out.v 0
|
||||||
|
# assert t.in.a 0
|
||||||
|
# cycle
|
||||||
|
|
||||||
|
# system "echo '[9] Rewrite 11 to 01'"
|
||||||
|
# system "echo '----------------------------------------------------------'"
|
||||||
|
|
||||||
|
|
||||||
|
# set-qdi-channel-valid "t.in" 5 0
|
||||||
|
# # 13 -> 00000 -> writing mode, address 00, word 00
|
||||||
|
# cycle
|
||||||
|
|
||||||
|
# assert t.in.a 1
|
||||||
|
# assert-qdi-channel-neutral "t.out" 4
|
||||||
|
# assert t.registers._in_v_temp 1
|
||||||
|
# set-qdi-channel-neutral "t.in" 5
|
||||||
|
# cycle
|
||||||
|
# assert t.registers._in_v_temp 0
|
||||||
|
|
||||||
|
# assert t.registers.ff[0].q 0
|
||||||
|
# assert t.registers.ff[1].q 0
|
||||||
|
# assert t.registers.ff[2].q 1
|
||||||
|
# assert t.registers.ff[3].q 1
|
||||||
|
# assert t.registers.ff[4].q 1
|
||||||
|
# assert t.registers.ff[5].q 1
|
||||||
|
# assert t.registers.ff[6].q 1
|
||||||
|
# assert t.registers.ff[7].q 0
|
||||||
|
# assert t.in.v 0
|
||||||
|
|
||||||
|
# set t.out.a 0
|
||||||
|
# set t.out.v 0
|
||||||
|
# assert t.in.a 0
|
||||||
|
# cycle
|
||||||
|
|
||||||
|
# system "echo '[9] Rewrite 11 to 01'"
|
||||||
|
# system "echo '----------------------------------------------------------'"
|
||||||
|
|
||||||
|
|
||||||
|
# set-qdi-channel-valid "t.in" 5 3
|
||||||
|
# # 13 -> 00011 -> writing mode, address 00, word 11
|
||||||
|
# cycle
|
||||||
|
|
||||||
|
# assert t.in.a 1
|
||||||
|
# assert-qdi-channel-neutral "t.out" 4
|
||||||
|
# assert t.registers._in_v_temp 1
|
||||||
|
# set-qdi-channel-neutral "t.in" 5
|
||||||
|
# cycle
|
||||||
|
# assert t.registers._in_v_temp 0
|
||||||
|
|
||||||
|
# assert t.registers.ff[0].q 1
|
||||||
|
# assert t.registers.ff[1].q 1
|
||||||
|
# assert t.registers.ff[2].q 1
|
||||||
|
# assert t.registers.ff[3].q 1
|
||||||
|
# assert t.registers.ff[4].q 1
|
||||||
|
# assert t.registers.ff[5].q 1
|
||||||
|
# assert t.registers.ff[6].q 1
|
||||||
|
# assert t.registers.ff[7].q 0
|
||||||
|
# assert t.in.v 0
|
||||||
|
|
||||||
|
# set t.out.a 0
|
||||||
|
# set t.out.v 0
|
||||||
|
# assert t.in.a 0
|
||||||
|
# cycle
|
||||||
|
|
||||||
|
# system "echo '[9] Rewrite 11 to 01'"
|
||||||
|
# system "echo '----------------------------------------------------------'"
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user