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merged encoder

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This commit is contained in:
alexmadison
2022-03-04 14:27:38 +01:00
parent f55322bc7c 18cf090b45
commit 4a4c4eeb14
15 changed files with 1255 additions and 33 deletions
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13
dataflow_neuro/cell_lib_async.act
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@ -524,6 +524,19 @@ namespace tmpl {
mk_excllo(_y1, _y2)
}
}
defproc PULLDOWN_X4(bool? a; bool! y; bool? vdd, vss)
{
prs{
[keeper=0] a -> y-
}
}
defproc PULLUP_X4(bool? a; bool! y; bool? vdd, vss)
{
prs{
[keeper=0] ~a -> y+
}
}
}}

43
dataflow_neuro/cell_lib_std.act
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@ -373,6 +373,49 @@ namespace tmpl {
}
sizing { _en{-2}; y{-2,2} }
}
export defproc DFFQ_R_X1 (bool? clk, reset, S, d, vdd, vss; bool! q)
{
bool _clk, __clk, _q_B, _dl;
bool _Ro, _So;
bool _So2;
bool _qb;
prs {
_q_B<10> -> q-
~_q_B<20> -> q+
clk<10> -> _clk-
~clk<20> -> _clk+
_clk<10> -> __clk-
~_clk<20> -> __clk+
reset<20> -> _Ro-
~reset<20> -> _Ro+
// S<20> & _dl -> _So-
// ~S<20> | ~_dl -> _So+
[keeper=0] d<10> & _clk -> _dl-
~d<20> & ~__clk<10> -> _dl+
reset<20> & _qb -> _q_B-
~reset<20> | ~_qb -> _q_B+
// _q_B<20> & S -> _So2-
// ~_q_B<20> | ~S -> _So2+
// input stage feedback
transgate<10> (__clk,_clk,_Ro,_dl)
// input to output
transgate<10> (__clk,_clk,reset,_qb)
// output feedback
transgate<10> (_clk,__clk,reset,_qb)
}
sizing { q{-1} }
}
}
}

156
dataflow_neuro/coders.act
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@ -234,7 +234,6 @@ namespace tmpl {
}
// Generates the OR-trees required to go from
// N one-hot inputs to Nc dual rail binary encoding.
export template<pint Nc, N>
@ -282,46 +281,137 @@ namespace tmpl {
)
}
template<pint N, pint M,pint address_size, pint ACK_STRENGTH>
defproc encoder2D(a1of1 x[N]; a1of1 y[M] ;avMx1of2<address_size> addr; power supply; bool reset_B) {
// Reset buffers
bool _reset_BX,_reset_BXX[H];
BUF_X1 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
sigbuf<2*address_size+3> reset_bufarray(.in=_reset_BX, .out=_reset_BXX,.vdd=supply.vdd,.vss=supply.vss);
// template<pint N, pint M, ACK_STRENGTH>
// defproc encoder2D(a1of1 x[N]; a1of1 y[M] ;avMx1of2<X> addr; bool! out_a; power supply)
// {
// // Arbiters
// a1of1 _out_arb_x,_out_arb_y;
// a1of1 _x_temp[N];
// (i:N:
// _x_temp[i].r = x[i].r;
// )
// (i:M:
// _y_temp[i].r = y[i].r;
// )
// arbtree<N> Xarb(.in = _x_temp,.out = _out_arb_X,.supply = supply);
// arbtree<M> Yarb(.in = _y_temp,.out = _out_arb_Y,.supply = supply);
// Arbiters
a1of1 _out_arb_x,_out_arb_y;
a1of1 _x_temp[N];
(i:N:
_x_temp[i].r = x[i].r;
)
(i:M:
_y_temp[i].r = y[i].r;
)
arbtree<N> Xarb(.in = _x_temp,.out = _out_arb_X,.supply = supply);
arbtree<M> Yarb(.in = _y_temp,.out = _out_arb_Y,.supply = supply);
// sigbuf<ACK_STRENGTH> x_ack_arb[N];
// sigbuf<ACK_STRENGTH> y_ack_arb[M];
// (i:N:
// x_ack_arb[i].in = _x_temp[i].a;
// x_ack_arb[i].out[0] = x[i].a;
// x_ack_arb[i].supply = supply;
// )
// (i:M:
// y_ack_arb[i].in = _y_temp[i].a;
// y_ack_arb[i].out[0] = y[i].a;
// y_ack_arb[i].supply = supply;
// )
// Sigbufs for strong ackowledge signals
sigbuf_1output<ACK_STRENGTH> x_ack_arb[N];
sigbuf_1output<ACK_STRENGTH> y_ack_arb[M];
(i:N:
x_ack_arb[i].in = _x_temp[i].a;
x_ack_arb[i].out[0] = x[i].a;
x_ack_arb[i].supply = supply;
)
(i:M:
y_ack_arb[i].in = _y_temp[i].a;
y_ack_arb[i].out[0] = y[i].a;
y_ack_arb[i].supply = supply;
)
// This block checks that the input is valid and that the arbiter made a choice
// Then activates the ack of the arbiter
bool _x_v,_in_x_v;
A_2C2P_RB_X1 Y_ack_confirm();
Y_ack_confirm.p1 = _x_v;
Y_ack_confirm.p2 =_in_x_v;
Y_ack_confirm.c1 = _out_arb_Y.r;
Y_ack_confirm.c2 = _x_a_B;
Y_ack_confirm.y = _out_arb_Y.a;
Y_ack_confirm.vdd = supply.vdd;
Y_ack_confirm.vss = supply.vss;
Y_ack_confirm.reset_B = _reset_BXX[0];
// This block checks that the input is valid and that the arbiter made a choice
// Then activates the ack of the arbiter
A_2C_RB X_ack_confirm();
X_ack_confirm.c1 = _out_arb_X.r;
X_ack_confirm.c2 = _x_a_B;
X_ack_confirm.vdd = supply.vdd;
X_ack_confirm.vss = supply.vss;
X_ack_confirm.reset_B = _reset_BXX[1];
//X_REQ validation
bool _x_req_array[N],_x_v,_x_v_B;
(i:N:_x_req_array[i] = x[i].r;)
ortree x_req_ortree(.in = _x_req_array,.out = _x_v,.supply = supply);
INV_X1 not_x_req_ortree(.in = _x_v,.out = _x_v_B);
//
A_2P3P1C2N_RB_X4 x_ack();
//branch1
x_ack.p1 = _in_x_v;
x_ack.p2 = _x_v_B;
//branch2
x_ack.p3 = _in_x_v;
x_ack.p4 = _in_y_v;
x_ack.p5 = _x_v;
//
x_ack.c1 = _en
x_ack.n1 = addr.v
x_ack.n2 = _in_x_v;
//
x_ack.y = _x_a;
//
x_ack.vdd = supply.vdd;
x_ack.vss = supply.vss;
x_ack.reset_B = _reset_BXX[2];
INV_X1 not_x_ack(.in = _x_a,.out = _x_a_B);
A_1C2P enabling(.p1 = addr.a, .p2 = addr.v, .c1 = _x_a, .y = _en, .vdd = supply.vdd, .vss = supply.vss)
avMx1of2<N> _in_x;
dualrail<N> _in;
_in_x.d = _in.d;
_in_x.v = _in_x_v;
//buffer_func_s
A_2C2N_RB buffer_func_s_f[address_size];
A_2C2N_RB buffer_func_s_t[address_size];
sigbuf<address_size> en_buf_t(.in=_en, .out=_en_X_t, .supply=supply);
sigbuf<address_size> en_buf_f(.in=_en, .out=_en_X_f, .supply=supply);
INV_X1 out_a_inv(.a=addr.a,.y=_out_a_B);
sigbuf<address_size> out_a_B_buf_f(.in=_out_a_B,.out=_out_a_BX_t, .supply=supply);
sigbuf<address_size> out_a_B_buf_t(.in=_out_a_B,.out=_out_a_BX_f, .supply=supply);
(i:address_size:
buffer_func_s_f[i].c1 = _en_X_f[i];
buffer_func_s_f[i].c2 = _out_a_BX_f[i];
buffer_func_s_f[i].n1 = _in_x.d.d[i].f;
buffer_func_s_f[i].n1 = _in_x.v;
buffer_func_s_f[i].vdd=supply.vdd;
buffer_func_s_f[i].vss=supply.vss;
buffer_func_s_f[i].pr_B = _reset_BXX[i+3];
buffer_func_s_f[i].sr_B = _reset_BXX[i+3];
buffer_func_s_f[i].y = addr.d.d[i].f;
buffer_func_s_t[i].c1 = _en_X_r[i];
buffer_func_s_t[i].c2 = _out_a_BX_t[i];
buffer_func_s_t[i].n1 = _in_x.d.d[i].r;
buffer_func_s_t[i].n1 = _in_x.v;
buffer_func_s_t[i].vdd=supply.vdd;
buffer_func_s_t[i].vss=supply.vss;
buffer_func_s_t[i].pr_B = _reset_BXX[i+3+address_size];
buffer_func_s_t[i].sr_B = _reset_BXX[i+3+address_size];
buffer_func_s_t[i].y = addr.d.d[i].t;
)
bool _addr_v
vtree addr_validity(.in = addr,.out = _addr_v);
sigbuf_1output<4> addr_validity_x(.in = _addr_v,.out = addr.v);
addr_validity.supply = supply;
addr_validity_x.supply = supply;
}
// }
}

23
dataflow_neuro/primitives.act
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@ -673,4 +673,27 @@ namespace tmpl {
(i:N:mu2[i].vss = supply.vss;)
(i:((1<<N)-1):dly[i].vss = supply.vss;)
}
export
defproc line_end_pull_up (a1of1 in; bool? reset_B; power supply; bool! out)
{
bool _out, __out, nor_out;
BUF_X4 buf1(.a=in.a, .y=_out, .vdd=supply.vdd,.vss=supply.vss);
BUF_X4 buf2(.a=_out, .y=__out, .vdd=supply.vdd,.vss=supply.vss);
NOR2_X1 aenor(.a=_out, .b=reset_B, .y = nor_out, .vdd=supply.vdd,.vss=supply.vss);
PULLUP_X4 pull_up(.a=nor_out, .y=out);
}
defproc line_end_pull_down (a1of1 in; bool? reset_B; power supply; bool! out)
{
bool _out, __out, nor_out;
BUF_X4 buf1(.a=in.a, .y=_out, .vdd=supply.vdd,.vss=supply.vss);
BUF_X4 buf2(.a=_out, .y=__out, .vdd=supply.vdd,.vss=supply.vss);
NOR2_X1 aenor(.a=_out, .b=reset_B, .y = nor_out, .vdd=supply.vdd,.vss=supply.vss);
PULLUP_X4 pull_down(.a=nor_out, .y=out);
}
}}

113
dataflow_neuro/registers.act Normal file
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@ -0,0 +1,113 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
*
import "../../dataflow_neuro/cell_lib_async.act";
import "../../dataflow_neuro/cell_lib_std.act";
import "../../dataflow_neuro/treegates.act";
import "../../dataflow_neuro/primitives.act";
import "../../dataflow_neuro/coders.act";
// import tmpl::dataflow_neuro;
// import tmpl::dataflow_neuro;
import std::channel;
open std::channel;
namespace tmpl {
namespace dataflow_neuro {
// Circuit for storing, reading and writing registers using AER
// The block has the parameters:
// log_nw -> log2(number of words), parameters you can store
// wl -> word length, length of each word
// N_dly_cfg -> the number of config bits in the ACK delay line
// The block has the pins:
// in -> input data,
// - the first bit is write/read_B
// - the next log_nw bits describe the location,
// - the last wl the word to write
// data -> the data saved in the flip flop, sized wl x nw
export template<pint log_nw,wl,N_dly_cfg>
defproc register_rw (avMx1of2<1+log_nw+wl> in, d1of<wl> data[2<<log_nw] ){
bool _in_v_temp,_in_a_temp,_clock_temp,_clock;
//Validation of the input
vtree val_input(.in = in,.out = _in_v_temp, .supply = supply);
sigbuf_1output<4> val_input_X(.in = _in_v_temp,.out = in.v,.supply = supply);
in.v = _in_v_temp;
// Generation of the clock pulse
delayprog<N_dly_cfg> dly(.in = _in_v_temp, .s = _clock_temp, .supply = supply);
sigbuf_1output<4> val_input_X(.in = _clock_temp,.out = _clock,.supply = supply);
// Sending back to the ackowledge
delayprog<N_dly_cfg> dly(.in = _clock, .s = _in_a_temp, .supply = supply);
sigbuf_1output<4> val_input_X(.in = _in_a_temp,.out = in.a,.supply = supply);
//Reset Buffers
bool _reset_BX,_reset_BXX[_nw*w];
BUF_X1 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
sigbuf<_nw*wl> reset_bufarray(.in=_reset_BX, .out=_reset_BXX,.vdd=supply.vdd,.vss=supply.vss);
// Creating the different flip flop arrays
bool _nw = 2<<log_nw;
bool _word_idx = 0;
bool _out_encoder[_nw],_clock_word_temp[_nw],_clock_word[_nw];
andtree<log_nw> atree[_nw];
AND2_X1 and_encoder[_nw]
sigbuf<wl> clock_buffer;
DFQ_R_X1 ff[_nw*wl];
(k:_nw:atree_x[k].supply = supply;)
(_word_idx:_nw:
// Decoding the bit pattern to understand which word we are looking at
(pin_idx:log_nw:
bitval = (_word_idx & ( 1 << pin_idx )) >> pin_idx; // Get binary digit of integer i, column j
[bitval = 1 ->
atree[_word_idx].in[pin_idx] = in.d.d[pin_idx+1].t;
[] bitval = 0 ->
atree[_word_idx].in[pin_idx] = in.d.d[pin_idx+1].f;
[]bitval >= 2 -> {false : "fuck"};
]
)
// Activating the fake clock for the right word
atree_x[_word_idx].out = _out_encoder[_word_idx];
and_encoder[_word_idx].a = _out_encoder[_word_idx];
and_encoder[_word_idx].b = _clock
and_encoder[_word_idx].y = _clock_word_temp[_word_idx];
and_encoder[_word_idx].vdd = supply.vdd;
and_encoder[_word_idx].vss = supply.vss;
clock_buffer[_word_idx].in = _clock_word_temp[_word_idx];
clock_buffer[_word_idx].out = _clock_word[_word_idx];
clock_buffer[_word_idx].vdd = supply.vdd;
clock_buffer[_word_idx].vss = supply.vss;
// Describing all the FF and their connection
(_bit_idx:wl:
ff[_bit_idx*(1+_word_idx)].clk = _clock_word[_word_idx];
ff[_bit_idx*(1+_word_idx)].d = in.d.d[_bit_idx+1+log_nw];
ff[_bit_idx*(1+_word_idx)].q = data[_word_idx].d[_bit_idx];
ff[_bit_idx*(1+_word_idx)].reset_B = reset_BXX[_bit_idx*(1+_word_idx)];
ff[_bit_idx*(1+_word_idx)].vdd = supply.vdd;
ff[_bit_idx*(1+_word_idx)].vss = supply.vss;
)
)
}
}}

26
dataflow_neuro/treegates.act
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@ -439,6 +439,32 @@ defproc sigbuf (bool? in; bool! out[N]; power supply)
(i:1..N-1:out[i]=out[0];)
}
//Sigbuf in which there is only 1 output. Made for outputs that cannot have multiple wires.
export template<pint N>
defproc sigbuf_1output (bool? in; bool! out; power supply)
{
{ N >= 0 : "sigbuf: parameter error" };
{ N <= 43 : "sigbuf: parameter error, N too big" };
/* -- just use in sized driver here -- */
[ N <= 4 ->
BUF_X1 buf1 (.a = in, .y = out, .vdd = supply.vdd, .vss = supply.vss);
[] N >= 5 & N <= 7 ->
BUF_X2 buf2 (.a = in, .y = out, .vdd = supply.vdd, .vss = supply.vss);
[] N >= 8 & N <= 10 ->
BUF_X3 buf3 (.a = in, .y = out, .vdd = supply.vdd, .vss = supply.vss);
[] N >= 11 & N <= 14 ->
BUF_X4 buf4 (.a = in, .y = out, .vdd = supply.vdd, .vss = supply.vss);
[] N >= 15 & N <= 18 ->
BUF_X6 buf6 (.a = in, .y = out, .vdd = supply.vdd, .vss = supply.vss);
[] N >= 19 & N <= 29 ->
BUF_X8 buf8 (.a = in, .y = out, .vdd = supply.vdd, .vss = supply.vss);
[] N >= 30 & N <= 42 ->
BUF_X12 buf12 (.a = in, .y = out, .vdd = supply.vdd, .vss = supply.vss);
]
}
}}