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packets to sram rw working

This commit is contained in:
alexmadison 2022-05-10 14:07:51 +02:00
parent 9ceaa10eeb
commit 4c208bc18a
3 changed files with 469 additions and 415 deletions
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52
dataflow_neuro/chips.act
View File

@ -604,7 +604,7 @@ defproc texel_dualcore_mapper (bd<N_IN> in, out;
bool? mapper_en;
avMx1of2<30> out_sram_wr; // Input packets to go to SRAM (rw word addr)
avMx1of2<8> out_sram_spk; // Spike packets from enc to go to SRAM (core-nrn addr)
avMx1of2<15> in_sram_r; // Readout packets from SRAM (data only)
avMx1of2<29> in_sram_r; // Readout packets from SRAM
avMx1of2<14> in_sram_spk // Spike packets from SRAM (core-syn addr)
){
@ -629,7 +629,8 @@ defproc texel_dualcore_mapper (bd<N_IN> in, out;
// dmx to SRAM
bool is_to_sram, is_to_cores;
demux<32> sram_dmx(.in = _fork.out2, .supply = supply, .reset_B = _reset_BX);
fifo<32, N_BUFFERS> fifo_fork2sramdmx(.in = _fork.out2, .supply = supply, .reset_B = _reset_BX);
demux<32> sram_dmx(.in = fifo_fork2sramdmx.out, .supply = supply, .reset_B = _reset_BX);
sram_dmx.cond.d.d[0].t = is_to_sram;
sram_dmx.cond.d.d[0].f = is_to_cores;
AND2_X1 sram_dmx_and(.a = sram_dmx.in.d.d[30].f, .b = sram_dmx.in.d.d[29].t,
@ -638,15 +639,26 @@ defproc texel_dualcore_mapper (bd<N_IN> in, out;
OR3_X1 sram_dmx_or(.a = sram_dmx.in.d.d[30].t, .b = sram_dmx.in.d.d[30].t, .c = sram_dmx.in.d.d[29].f,
.y = is_to_cores,
.vdd = supply.vdd, .vss = supply.vss);
slice_data<32, 0, 29> pre_sram_slice(.in = sram_dmx.out2, .supply = supply);
out_sram_wr.a = pre_sram_slice.out.a;
out_sram_wr.v = pre_sram_slice.out.v;
(i:29:out_sram_wr.d.d[i] = pre_sram_slice.out.d.d[i];)
out_sram_wr.d.d[29] = pre_sram_slice.in.d.d[31];
slice_data<32, 0, 30> pre_sram_slice(.supply = supply);
pre_sram_slice.in.a = sram_dmx.out2.a;
pre_sram_slice.in.v = sram_dmx.out2.v;
(i:29:pre_sram_slice.in.d.d[i] = sram_dmx.out2.d.d[i];)
pre_sram_slice.in.d.d[29] = sram_dmx.out2.d.d[31];
pre_sram_slice.in.d.d[30] = sram_dmx.out2.d.d[30];
pre_sram_slice.in.d.d[31] = sram_dmx.out2.d.d[29];
fifo<30, N_BUFFERS> fifo_out_sram_wr(.in = pre_sram_slice.out, .out = out_sram_wr,
.reset_B = _reset_BX, .supply = supply);
// fifo_out_sram_wr.in.a = pre_sram_slice.out.a;
// fifo_out_sram_wr.in.v = pre_sram_slice.out.v;
// (i:29:fifo_out_sram_wr.in.d.d[i] = pre_sram_slice.out.d.d[i];)
// fifo_out_sram_wr.in.d.d[29] = pre_sram_slice.in.d.d[31];
// spikes from sram
// requires weird merging because [core, syny, synx] needs to go to [core, ZEROES, syny, synx]
append<14,32,0> sram_spk_in_append(.in = in_sram_spk, .supply = supply);
fifo<14, N_BUFFERS> fifo_in_sram_spk(.in = in_sram_spk, .reset_B = _reset_BX, .supply = supply);
append<14,32,0> sram_spk_in_append(.in = fifo_in_sram_spk.out, .supply = supply);
merge<32> merge_dmx8spk(.in1 = sram_dmx.out1, .reset_B = _reset_BX, .supply = supply);
merge_dmx8spk.in2.a = sram_spk_in_append.out.a;
merge_dmx8spk.in2.v = sram_spk_in_append.out.v;
@ -726,21 +738,33 @@ defproc texel_dualcore_mapper (bd<N_IN> in, out;
.supply = supply, .reset_B = _reset_BX);
// fork after core merge then go to mapper if its a spike
fork<32> postcore_fork(.in = merge_core1x2.out, .reset_B = _reset_BX, .supply = supply);
fifo<32, N_BUFFERS> fifo_core2fork(.in = merge_core1x2.out, .reset_B = _reset_BX, .supply = supply);
fork<32> postcore_fork(.in = fifo_core2fork.out, .reset_B = _reset_BX, .supply = supply);
dropper_static<32, false> sram_dropper(.in = postcore_fork.out1, .cond = mapper_en, .supply = supply);
// Need to have it then drop the spike if its from a register.
// to do: go into a self-acknowledging dmx_td, with the cond being on the register bit.
demux_td<32, false> drop_if_reg(.in = sram_dropper.out, .reset_B = _reset_BX, .supply = supply); // if cond true, go out on data
drop_if_reg.cond.d.d[0] = sram_dropper.out.d.d[30];
drop_if_reg.token.r = drop_if_reg.token.a;
slice_data<32,0,8> slice_to_sram(.in = drop_if_reg.out, .out = out_sram_spk, .supply = supply);
fifo<8,N_BUFFERS> fifo_out_sram_spk(.out = out_sram_spk, .reset_B = _reset_BX, .supply = supply);
slice_data<32,0,8> slice_to_sram(.in = drop_if_reg.out, .out = fifo_out_sram_spk.in, .supply = supply);
// And move the msb (core bit) to just after the neuron address...
slice_to_sram.in.a = drop_if_reg.out.a;
slice_to_sram.in.v = drop_if_reg.out.v;
(i:7:slice_to_sram.in.d.d[i] = drop_if_reg.out.d.d[i];)
slice_to_sram.in.d.d[7] = drop_if_reg.out.d.d[31];
(i:7..30: slice_to_sram.in.d.d[i+1] = drop_if_reg.out.d.d[i];)
// merge from cores and sram read in
fifo<29, N_BUFFERS> fifo_in_sram_r(.in = in_sram_r, .reset_B = _reset_BX, .supply = supply);
fifo<32, N_BUFFERS> fifo_fork2mrg(.in = postcore_fork.out2, .reset_B = _reset_BX, .supply = supply);
append<29,3,2> sram_read_in_append(.in = fifo_in_sram_r.out, .supply = supply);
merge<32> merge_sram8core(.in1 = fifo_fork2mrg.out, .in2 = sram_read_in_append.out,
.reset_B = _reset_BX, .supply = supply);
// Merge cores and loopback
merge<N_IN> merge_drop8core(.in1 = postcore_fork.out2, .in2 = fifo_drop2mrg.out,
fifo<32, N_BUFFERS> fifo_mrg2mrg(.in = merge_sram8core.out, .reset_B = _reset_BX, .supply = supply);
merge<N_IN> merge_drop8core(.in1 = fifo_mrg2mrg.out, .in2 = fifo_drop2mrg.out,
.reset_B = _reset_BX, .supply = supply);
// qdi2bd

4
test/unit_tests/texel_dualcore_glue_mapper/test.act
View File

@ -127,9 +127,10 @@ defproc chip_texel_dualcore (bd<N_IN> in, out;
bool? bd_dly_cfg[N_BD_DLY_CFG], bd_dly_cfg2[N_BD_DLY_CFG2];
bool? loopback_en;
bool? mapper_en;
avMx1of2<30> out_sram_wr; // Input packets to go to SRAM (rw word addr)
avMx1of2<8> out_sram_spk; // Spike packets from enc to go to SRAM (core-nrn addr)
avMx1of2<15> in_sram_r; // Readout packets from SRAM (data only)
avMx1of2<29> in_sram_r; // Readout packets from SRAM (data only)
avMx1of2<14> in_sram_spk // Spike packets from SRAM (core-syn addr)
@ -157,6 +158,7 @@ defproc chip_texel_dualcore (bd<N_IN> in, out;
.c1_reg_data = c1_reg_data, .c1_dec_req_x = c1_dec_req_x, .c1_dec_req_y = c1_dec_req_y, .c1_dec_ackB = c1_dec_ackB, .c1_syn_pu = c1_syn_pu, .c1_enc_inx = c1_enc_inx, .c1_enc_iny = c1_enc_iny, .c1_nrn_pd_x = c1_nrn_pd_x, .c1_nrn_pd_y = c1_nrn_pd_y, .c1_nrn_mon_x = c1_nrn_mon_x, .c1_nrn_mon_y = c1_nrn_mon_y, .c1_syn_mon_x = c1_syn_mon_x, .c1_syn_mon_y = c1_syn_mon_y, .c1_syn_mon_AMZI = c1_syn_mon_AMZI, .c1_nrn_mon_AMZI = c1_nrn_mon_AMZI, .c1_syn_mon_AMZO = c1_syn_mon_AMZO, .c1_nrn_mon_AMZO = c1_nrn_mon_AMZO, .c1_syn_flags_EFO = c1_syn_flags_EFO, .c1_nrn_flags_EFO = c1_nrn_flags_EFO, .c1_reset_nrn_hs_BO = c1_reset_nrn_hs_BO, .c1_reset_syn_hs_BO = c1_reset_syn_hs_BO, .c1_reset_nrn_stge_BO = c1_reset_nrn_stge_BO, .c1_reset_syn_stge_BO = c1_reset_syn_stge_BO, .c2_reg_data = c2_reg_data, .c2_dec_req_x = c2_dec_req_x, .c2_dec_req_y = c2_dec_req_y, .c2_dec_ackB = c2_dec_ackB, .c2_syn_pu = c2_syn_pu, .c2_enc_inx = c2_enc_inx, .c2_enc_iny = c2_enc_iny, .c2_nrn_pd_x = c2_nrn_pd_x, .c2_nrn_pd_y = c2_nrn_pd_y, .c2_nrn_mon_x = c2_nrn_mon_x, .c2_nrn_mon_y = c2_nrn_mon_y, .c2_syn_mon_x = c2_syn_mon_x, .c2_syn_mon_y = c2_syn_mon_y, .c2_syn_mon_AMZI = c2_syn_mon_AMZI, .c2_nrn_mon_AMZI = c2_nrn_mon_AMZI, .c2_syn_mon_AMZO = c2_syn_mon_AMZO, .c2_nrn_mon_AMZO = c2_nrn_mon_AMZO, .c2_syn_flags_EFO = c2_syn_flags_EFO, .c2_nrn_flags_EFO = c2_nrn_flags_EFO, .c2_reset_nrn_hs_BO = c2_reset_nrn_hs_BO, .c2_reset_syn_hs_BO = c2_reset_syn_hs_BO, .c2_reset_nrn_stge_BO = c2_reset_nrn_stge_BO, .c2_reset_syn_stge_BO = c2_reset_syn_stge_BO,
.bd_dly_cfg = bd_dly_cfg, .bd_dly_cfg2 = bd_dly_cfg2,
.loopback_en = loopback_en,
.mapper_en = mapper_en,
.out_sram_wr = out_sram_wr, .out_sram_spk = out_sram_spk,
.in_sram_r = in_sram_r, .in_sram_spk = in_sram_spk,
.reset_B = reset_B, .reset_reg_B = reset_reg_B, .reset_syn_stge_BI = reset_syn_stge_BI,

828
test/unit_tests/texel_dualcore_glue_mapper/test.prsim
View File

@ -4,10 +4,15 @@ watch c.c1_synapses[0].a
watch c.c1_neurons[0].r
watch c.c1_neurons[0].a
set-qdi-channel-neutral "c.out_sram_wr" 30
set-qdi-channel-neutral "c.out_sram_spk" 8
set-qdi-channel-neutral "c.in_sram_r" 15
# set-qdi-channel-neutral "c.out_sram_wr" 30
# set-qdi-channel-neutral "c.out_sram_spk" 8
set c.out_sram_wr.a 0
set c.out_sram_wr.v 0
set c.out_sram_spk.a 0
set c.out_sram_spk.v 0
set-qdi-channel-neutral "c.in_sram_r" 29
set-qdi-channel-neutral "c.in_sram_spk" 14
set c.mapper_en 0
set c.bd_dly_cfg[0] 1
@ -6750,30 +6755,14 @@ set c.out.a 0
cycle
# extra tests
# check that resetB does not wipe the registers
system "echo '[] Writing 69420 to core 0 address 2'"
set-bd-data-valid "c.in" 32 1615055618
cycle
set c.in.r 1
cycle
assert c.in.a 1
system "echo '[] Removing input'"
set-bd-channel-neutral "c.in" 32
cycle
assert c.in.a 0
set c.reset_B 0
cycle
set c.reset_B 1
# sram mapper io tests
set c.mapper_en 1
cycle
# Send rw packets to SRAM
system "echo '[] Reading core 0 address 2'"
set-bd-data-valid "c.in" 32 1073741826
system "echo '[] Sending packet 2147483647 to SRAM, input = 0b10111111111111111111111111111111'"
set-bd-data-valid "c.in" 32 3221225471
cycle
set c.in.r 1
cycle
@ -6785,25 +6774,20 @@ cycle
assert c.in.a 0
system "echo '[] Receiving output 69420 from core 0 register 2'"
assert-bd-channel-valid "c.out" 32 1078184706
set c.out.a 1
system "echo '[] Checking sram rw packet received'"
assert-qdi-channel-valid "c.out_sram_wr" 30 2147483647
set c.out_sram_wr.a 1
set c.out_sram_wr.v 1
cycle
assert-bd-channel-neutral "c.out" 32
set c.out.a 0
assert-qdi-channel-neutral "c.out_sram_wr" 30
set c.out_sram_wr.a 0
set c.out_sram_wr.v 0
cycle
# check that reset_reg_B does wipe the registers
mode unstab # required since resetting the regs necessarily makes instabs in going val -> inval -> val
set c.reset_reg_B 0
cycle
set c.reset_reg_B 1
cycle
mode run
system "echo '[] Reading core 0 address 2'"
set-bd-data-valid "c.in" 32 1073741826
system "echo '[] Sending packet 992380055 to SRAM, input = 0b10111011001001101000010010010111'"
set-bd-data-valid "c.in" 32 3139863703
cycle
set c.in.r 1
cycle
@ -6815,303 +6799,18 @@ cycle
assert c.in.a 0
system "echo '[] Receiving output 0 from core 0 register 2'"
assert-bd-channel-valid "c.out" 32 1073741826
set c.out.a 1
system "echo '[] Checking sram rw packet received'"
assert-qdi-channel-valid "c.out_sram_wr" 30 992380055
set c.out_sram_wr.a 1
set c.out_sram_wr.v 1
cycle
assert-bd-channel-neutral "c.out" 32
set c.out.a 0
assert-qdi-channel-neutral "c.out_sram_wr" 30
set c.out_sram_wr.a 0
set c.out_sram_wr.v 0
cycle
# reset tests: check that resetB propagates to all hs resets.
mode unstab
set c.reset_B 0
cycle
assert c.c1_reset_nrn_hs_BO[0] 0
assert c.c1_reset_syn_hs_BO[0] 0
assert c.c2_reset_nrn_hs_BO[0] 0
assert c.c2_reset_syn_hs_BO[0] 0
assert c.c1_reset_nrn_hs_BO[1] 0
assert c.c1_reset_syn_hs_BO[1] 0
assert c.c2_reset_nrn_hs_BO[1] 0
assert c.c2_reset_syn_hs_BO[1] 0
assert c.c1_reset_nrn_hs_BO[2] 0
assert c.c1_reset_syn_hs_BO[2] 0
assert c.c2_reset_nrn_hs_BO[2] 0
assert c.c2_reset_syn_hs_BO[2] 0
assert c.c1_reset_nrn_hs_BO[3] 0
assert c.c1_reset_syn_hs_BO[3] 0
assert c.c2_reset_nrn_hs_BO[3] 0
assert c.c2_reset_syn_hs_BO[3] 0
assert c.c1_reset_nrn_hs_BO[4] 0
assert c.c1_reset_syn_hs_BO[4] 0
assert c.c2_reset_nrn_hs_BO[4] 0
assert c.c2_reset_syn_hs_BO[4] 0
assert c.c1_reset_nrn_hs_BO[5] 0
assert c.c1_reset_syn_hs_BO[5] 0
assert c.c2_reset_nrn_hs_BO[5] 0
assert c.c2_reset_syn_hs_BO[5] 0
assert c.c1_reset_nrn_hs_BO[6] 0
assert c.c1_reset_syn_hs_BO[6] 0
assert c.c2_reset_nrn_hs_BO[6] 0
assert c.c2_reset_syn_hs_BO[6] 0
assert c.c1_reset_nrn_hs_BO[7] 0
assert c.c1_reset_syn_hs_BO[7] 0
assert c.c2_reset_nrn_hs_BO[7] 0
assert c.c2_reset_syn_hs_BO[7] 0
assert c.c1_reset_nrn_hs_BO[8] 0
assert c.c1_reset_syn_hs_BO[8] 0
assert c.c2_reset_nrn_hs_BO[8] 0
assert c.c2_reset_syn_hs_BO[8] 0
assert c.c1_reset_nrn_hs_BO[9] 0
assert c.c1_reset_syn_hs_BO[9] 0
assert c.c2_reset_nrn_hs_BO[9] 0
assert c.c2_reset_syn_hs_BO[9] 0
assert c.c1_reset_nrn_hs_BO[10] 0
assert c.c1_reset_syn_hs_BO[10] 0
assert c.c2_reset_nrn_hs_BO[10] 0
assert c.c2_reset_syn_hs_BO[10] 0
assert c.c1_reset_nrn_hs_BO[11] 0
assert c.c1_reset_syn_hs_BO[11] 0
assert c.c2_reset_nrn_hs_BO[11] 0
assert c.c2_reset_syn_hs_BO[11] 0
assert c.c1_reset_nrn_hs_BO[12] 0
assert c.c1_reset_syn_hs_BO[12] 0
assert c.c2_reset_nrn_hs_BO[12] 0
assert c.c2_reset_syn_hs_BO[12] 0
assert c.c1_reset_nrn_hs_BO[13] 0
assert c.c1_reset_syn_hs_BO[13] 0
assert c.c2_reset_nrn_hs_BO[13] 0
assert c.c2_reset_syn_hs_BO[13] 0
assert c.c1_reset_nrn_hs_BO[14] 0
assert c.c1_reset_syn_hs_BO[14] 0
assert c.c2_reset_nrn_hs_BO[14] 0
assert c.c2_reset_syn_hs_BO[14] 0
set c.reset_B 1
cycle
assert c.c1_reset_nrn_hs_BO[0] 1
assert c.c1_reset_syn_hs_BO[0] 1
assert c.c2_reset_nrn_hs_BO[0] 1
assert c.c2_reset_syn_hs_BO[0] 1
assert c.c1_reset_nrn_hs_BO[1] 1
assert c.c1_reset_syn_hs_BO[1] 1
assert c.c2_reset_nrn_hs_BO[1] 1
assert c.c2_reset_syn_hs_BO[1] 1
assert c.c1_reset_nrn_hs_BO[2] 1
assert c.c1_reset_syn_hs_BO[2] 1
assert c.c2_reset_nrn_hs_BO[2] 1
assert c.c2_reset_syn_hs_BO[2] 1
assert c.c1_reset_nrn_hs_BO[3] 1
assert c.c1_reset_syn_hs_BO[3] 1
assert c.c2_reset_nrn_hs_BO[3] 1
assert c.c2_reset_syn_hs_BO[3] 1
assert c.c1_reset_nrn_hs_BO[4] 1
assert c.c1_reset_syn_hs_BO[4] 1
assert c.c2_reset_nrn_hs_BO[4] 1
assert c.c2_reset_syn_hs_BO[4] 1
assert c.c1_reset_nrn_hs_BO[5] 1
assert c.c1_reset_syn_hs_BO[5] 1
assert c.c2_reset_nrn_hs_BO[5] 1
assert c.c2_reset_syn_hs_BO[5] 1
assert c.c1_reset_nrn_hs_BO[6] 1
assert c.c1_reset_syn_hs_BO[6] 1
assert c.c2_reset_nrn_hs_BO[6] 1
assert c.c2_reset_syn_hs_BO[6] 1
assert c.c1_reset_nrn_hs_BO[7] 1
assert c.c1_reset_syn_hs_BO[7] 1
assert c.c2_reset_nrn_hs_BO[7] 1
assert c.c2_reset_syn_hs_BO[7] 1
assert c.c1_reset_nrn_hs_BO[8] 1
assert c.c1_reset_syn_hs_BO[8] 1
assert c.c2_reset_nrn_hs_BO[8] 1
assert c.c2_reset_syn_hs_BO[8] 1
assert c.c1_reset_nrn_hs_BO[9] 1
assert c.c1_reset_syn_hs_BO[9] 1
assert c.c2_reset_nrn_hs_BO[9] 1
assert c.c2_reset_syn_hs_BO[9] 1
assert c.c1_reset_nrn_hs_BO[10] 1
assert c.c1_reset_syn_hs_BO[10] 1
assert c.c2_reset_nrn_hs_BO[10] 1
assert c.c2_reset_syn_hs_BO[10] 1
assert c.c1_reset_nrn_hs_BO[11] 1
assert c.c1_reset_syn_hs_BO[11] 1
assert c.c2_reset_nrn_hs_BO[11] 1
assert c.c2_reset_syn_hs_BO[11] 1
assert c.c1_reset_nrn_hs_BO[12] 1
assert c.c1_reset_syn_hs_BO[12] 1
assert c.c2_reset_nrn_hs_BO[12] 1
assert c.c2_reset_syn_hs_BO[12] 1
assert c.c1_reset_nrn_hs_BO[13] 1
assert c.c1_reset_syn_hs_BO[13] 1
assert c.c2_reset_nrn_hs_BO[13] 1
assert c.c2_reset_syn_hs_BO[13] 1
assert c.c1_reset_nrn_hs_BO[14] 1
assert c.c1_reset_syn_hs_BO[14] 1
assert c.c2_reset_nrn_hs_BO[14] 1
assert c.c2_reset_syn_hs_BO[14] 1
# mode run
# reset tests: check that reset_syn_stge propagates to synapse reg outputs
set c.reset_syn_stge_BI 0
cycle
assert c.c1_reset_syn_stge_BO[0] 0
assert c.c2_reset_syn_stge_BO[0] 0
assert c.c1_reset_syn_stge_BO[1] 0
assert c.c2_reset_syn_stge_BO[1] 0
assert c.c1_reset_syn_stge_BO[2] 0
assert c.c2_reset_syn_stge_BO[2] 0
assert c.c1_reset_syn_stge_BO[3] 0
assert c.c2_reset_syn_stge_BO[3] 0
assert c.c1_reset_syn_stge_BO[4] 0
assert c.c2_reset_syn_stge_BO[4] 0
assert c.c1_reset_syn_stge_BO[5] 0
assert c.c2_reset_syn_stge_BO[5] 0
assert c.c1_reset_syn_stge_BO[6] 0
assert c.c2_reset_syn_stge_BO[6] 0
assert c.c1_reset_syn_stge_BO[7] 0
assert c.c2_reset_syn_stge_BO[7] 0
assert c.c1_reset_syn_stge_BO[8] 0
assert c.c2_reset_syn_stge_BO[8] 0
assert c.c1_reset_syn_stge_BO[9] 0
assert c.c2_reset_syn_stge_BO[9] 0
assert c.c1_reset_syn_stge_BO[10] 0
assert c.c2_reset_syn_stge_BO[10] 0
assert c.c1_reset_syn_stge_BO[11] 0
assert c.c2_reset_syn_stge_BO[11] 0
assert c.c1_reset_syn_stge_BO[12] 0
assert c.c2_reset_syn_stge_BO[12] 0
assert c.c1_reset_syn_stge_BO[13] 0
assert c.c2_reset_syn_stge_BO[13] 0
assert c.c1_reset_syn_stge_BO[14] 0
assert c.c2_reset_syn_stge_BO[14] 0
set c.reset_syn_stge_BI 1
cycle
assert c.c1_reset_syn_stge_BO[0] 1
assert c.c2_reset_syn_stge_BO[0] 1
assert c.c1_reset_syn_stge_BO[1] 1
assert c.c2_reset_syn_stge_BO[1] 1
assert c.c1_reset_syn_stge_BO[2] 1
assert c.c2_reset_syn_stge_BO[2] 1
assert c.c1_reset_syn_stge_BO[3] 1
assert c.c2_reset_syn_stge_BO[3] 1
assert c.c1_reset_syn_stge_BO[4] 1
assert c.c2_reset_syn_stge_BO[4] 1
assert c.c1_reset_syn_stge_BO[5] 1
assert c.c2_reset_syn_stge_BO[5] 1
assert c.c1_reset_syn_stge_BO[6] 1
assert c.c2_reset_syn_stge_BO[6] 1
assert c.c1_reset_syn_stge_BO[7] 1
assert c.c2_reset_syn_stge_BO[7] 1
assert c.c1_reset_syn_stge_BO[8] 1
assert c.c2_reset_syn_stge_BO[8] 1
assert c.c1_reset_syn_stge_BO[9] 1
assert c.c2_reset_syn_stge_BO[9] 1
assert c.c1_reset_syn_stge_BO[10] 1
assert c.c2_reset_syn_stge_BO[10] 1
assert c.c1_reset_syn_stge_BO[11] 1
assert c.c2_reset_syn_stge_BO[11] 1
assert c.c1_reset_syn_stge_BO[12] 1
assert c.c2_reset_syn_stge_BO[12] 1
assert c.c1_reset_syn_stge_BO[13] 1
assert c.c2_reset_syn_stge_BO[13] 1
assert c.c1_reset_syn_stge_BO[14] 1
assert c.c2_reset_syn_stge_BO[14] 1
mode run
# reset tests: check that setting the register bit propagates to nrn stge reset
assert c.c1_reset_nrn_stge_BO[0] 1
assert c.c2_reset_nrn_stge_BO[0] 1
assert c.c1_reset_nrn_stge_BO[1] 1
assert c.c2_reset_nrn_stge_BO[1] 1
assert c.c1_reset_nrn_stge_BO[2] 1
assert c.c2_reset_nrn_stge_BO[2] 1
assert c.c1_reset_nrn_stge_BO[3] 1
assert c.c2_reset_nrn_stge_BO[3] 1
assert c.c1_reset_nrn_stge_BO[4] 1
assert c.c2_reset_nrn_stge_BO[4] 1
assert c.c1_reset_nrn_stge_BO[5] 1
assert c.c2_reset_nrn_stge_BO[5] 1
assert c.c1_reset_nrn_stge_BO[6] 1
assert c.c2_reset_nrn_stge_BO[6] 1
assert c.c1_reset_nrn_stge_BO[7] 1
assert c.c2_reset_nrn_stge_BO[7] 1
assert c.c1_reset_nrn_stge_BO[8] 1
assert c.c2_reset_nrn_stge_BO[8] 1
assert c.c1_reset_nrn_stge_BO[9] 1
assert c.c2_reset_nrn_stge_BO[9] 1
assert c.c1_reset_nrn_stge_BO[10] 1
assert c.c2_reset_nrn_stge_BO[10] 1
assert c.c1_reset_nrn_stge_BO[11] 1
assert c.c2_reset_nrn_stge_BO[11] 1
assert c.c1_reset_nrn_stge_BO[12] 1
assert c.c2_reset_nrn_stge_BO[12] 1
assert c.c1_reset_nrn_stge_BO[13] 1
assert c.c2_reset_nrn_stge_BO[13] 1
assert c.c1_reset_nrn_stge_BO[14] 1
assert c.c2_reset_nrn_stge_BO[14] 1
system "echo '[] Writing 64 to core 0 address 0'"
set-bd-data-valid "c.in" 32 1610616832
cycle
set c.in.r 1
cycle
assert c.in.a 1
system "echo '[] Removing input'"
set-bd-channel-neutral "c.in" 32
cycle
assert c.in.a 0
assert c.c1_reset_nrn_stge_BO[0] 0
assert c.c2_reset_nrn_stge_BO[0] 1
assert c.c1_reset_nrn_stge_BO[1] 0
assert c.c2_reset_nrn_stge_BO[1] 1
assert c.c1_reset_nrn_stge_BO[2] 0
assert c.c2_reset_nrn_stge_BO[2] 1
assert c.c1_reset_nrn_stge_BO[3] 0
assert c.c2_reset_nrn_stge_BO[3] 1
assert c.c1_reset_nrn_stge_BO[4] 0
assert c.c2_reset_nrn_stge_BO[4] 1
assert c.c1_reset_nrn_stge_BO[5] 0
assert c.c2_reset_nrn_stge_BO[5] 1
assert c.c1_reset_nrn_stge_BO[6] 0
assert c.c2_reset_nrn_stge_BO[6] 1
assert c.c1_reset_nrn_stge_BO[7] 0
assert c.c2_reset_nrn_stge_BO[7] 1
assert c.c1_reset_nrn_stge_BO[8] 0
assert c.c2_reset_nrn_stge_BO[8] 1
assert c.c1_reset_nrn_stge_BO[9] 0
assert c.c2_reset_nrn_stge_BO[9] 1
assert c.c1_reset_nrn_stge_BO[10] 0
assert c.c2_reset_nrn_stge_BO[10] 1
assert c.c1_reset_nrn_stge_BO[11] 0
assert c.c2_reset_nrn_stge_BO[11] 1
assert c.c1_reset_nrn_stge_BO[12] 0
assert c.c2_reset_nrn_stge_BO[12] 1
assert c.c1_reset_nrn_stge_BO[13] 0
assert c.c2_reset_nrn_stge_BO[13] 1
assert c.c1_reset_nrn_stge_BO[14] 0
assert c.c2_reset_nrn_stge_BO[14] 1
system "echo '[] Writing 64 to core 1 address 0'"
set-bd-data-valid "c.in" 32 3758100480
system "echo '[] Sending packet 2089788400 to SRAM, input = 0b10111100100011111010001111110000'"
set-bd-data-valid "c.in" 32 3163530224
cycle
set c.in.r 1
cycle
@ -7123,40 +6822,18 @@ cycle
assert c.in.a 0
assert c.c1_reset_nrn_stge_BO[0] 0
assert c.c2_reset_nrn_stge_BO[0] 0
assert c.c1_reset_nrn_stge_BO[1] 0
assert c.c2_reset_nrn_stge_BO[1] 0
assert c.c1_reset_nrn_stge_BO[2] 0
assert c.c2_reset_nrn_stge_BO[2] 0
assert c.c1_reset_nrn_stge_BO[3] 0
assert c.c2_reset_nrn_stge_BO[3] 0
assert c.c1_reset_nrn_stge_BO[4] 0
assert c.c2_reset_nrn_stge_BO[4] 0
assert c.c1_reset_nrn_stge_BO[5] 0
assert c.c2_reset_nrn_stge_BO[5] 0
assert c.c1_reset_nrn_stge_BO[6] 0
assert c.c2_reset_nrn_stge_BO[6] 0
assert c.c1_reset_nrn_stge_BO[7] 0
assert c.c2_reset_nrn_stge_BO[7] 0
assert c.c1_reset_nrn_stge_BO[8] 0
assert c.c2_reset_nrn_stge_BO[8] 0
assert c.c1_reset_nrn_stge_BO[9] 0
assert c.c2_reset_nrn_stge_BO[9] 0
assert c.c1_reset_nrn_stge_BO[10] 0
assert c.c2_reset_nrn_stge_BO[10] 0
assert c.c1_reset_nrn_stge_BO[11] 0
assert c.c2_reset_nrn_stge_BO[11] 0
assert c.c1_reset_nrn_stge_BO[12] 0
assert c.c2_reset_nrn_stge_BO[12] 0
assert c.c1_reset_nrn_stge_BO[13] 0
assert c.c2_reset_nrn_stge_BO[13] 0
assert c.c1_reset_nrn_stge_BO[14] 0
assert c.c2_reset_nrn_stge_BO[14] 0
system "echo '[] Checking sram rw packet received'"
assert-qdi-channel-valid "c.out_sram_wr" 30 2089788400
set c.out_sram_wr.a 1
set c.out_sram_wr.v 1
cycle
assert-qdi-channel-neutral "c.out_sram_wr" 30
set c.out_sram_wr.a 0
set c.out_sram_wr.v 0
cycle
system "echo '[] Writing 0 to core 0 address 0'"
set-bd-data-valid "c.in" 32 1610612736
system "echo '[] Sending packet 98194987 to SRAM, input = 0b100101110110100101011000101011'"
set-bd-data-valid "c.in" 32 635065899
cycle
set c.in.r 1
cycle
@ -7168,8 +6845,18 @@ cycle
assert c.in.a 0
system "echo '[] Writing 0 to core 1 address 0'"
set-bd-data-valid "c.in" 32 3758096384
system "echo '[] Checking sram rw packet received'"
assert-qdi-channel-valid "c.out_sram_wr" 30 98194987
set c.out_sram_wr.a 1
set c.out_sram_wr.v 1
cycle
assert-qdi-channel-neutral "c.out_sram_wr" 30
set c.out_sram_wr.a 0
set c.out_sram_wr.v 0
cycle
system "echo '[] Sending packet 661175428 to SRAM, input = 0b10100111011010001011110010000100'"
set-bd-data-valid "c.in" 32 2808659076
cycle
set c.in.r 1
cycle
@ -7180,40 +6867,381 @@ set-bd-channel-neutral "c.in" 32
cycle
assert c.in.a 0
system "echo '[] Checking sram rw packet received'"
assert-qdi-channel-valid "c.out_sram_wr" 30 661175428
set c.out_sram_wr.a 1
set c.out_sram_wr.v 1
cycle
assert-qdi-channel-neutral "c.out_sram_wr" 30
set c.out_sram_wr.a 0
set c.out_sram_wr.v 0
cycle
assert c.c1_reset_nrn_stge_BO[0] 1
assert c.c2_reset_nrn_stge_BO[0] 1
assert c.c1_reset_nrn_stge_BO[1] 1
assert c.c2_reset_nrn_stge_BO[1] 1
assert c.c1_reset_nrn_stge_BO[2] 1
assert c.c2_reset_nrn_stge_BO[2] 1
assert c.c1_reset_nrn_stge_BO[3] 1
assert c.c2_reset_nrn_stge_BO[3] 1
assert c.c1_reset_nrn_stge_BO[4] 1
assert c.c2_reset_nrn_stge_BO[4] 1
assert c.c1_reset_nrn_stge_BO[5] 1
assert c.c2_reset_nrn_stge_BO[5] 1
assert c.c1_reset_nrn_stge_BO[6] 1
assert c.c2_reset_nrn_stge_BO[6] 1
assert c.c1_reset_nrn_stge_BO[7] 1
assert c.c2_reset_nrn_stge_BO[7] 1
assert c.c1_reset_nrn_stge_BO[8] 1
assert c.c2_reset_nrn_stge_BO[8] 1
assert c.c1_reset_nrn_stge_BO[9] 1
assert c.c2_reset_nrn_stge_BO[9] 1
assert c.c1_reset_nrn_stge_BO[10] 1
assert c.c2_reset_nrn_stge_BO[10] 1
assert c.c1_reset_nrn_stge_BO[11] 1
assert c.c2_reset_nrn_stge_BO[11] 1
assert c.c1_reset_nrn_stge_BO[12] 1
assert c.c2_reset_nrn_stge_BO[12] 1
assert c.c1_reset_nrn_stge_BO[13] 1
assert c.c2_reset_nrn_stge_BO[13] 1
assert c.c1_reset_nrn_stge_BO[14] 1
assert c.c2_reset_nrn_stge_BO[14] 1
system "echo '[] Sending packet 678670619 to SRAM, input = 0b10101000011100111011000100011011'"
set-bd-data-valid "c.in" 32 2826154267
cycle
set c.in.r 1
cycle
assert c.in.a 1
system "echo '[] Removing input'"
set-bd-channel-neutral "c.in" 32
cycle
assert c.in.a 0
system "echo '[] Checking sram rw packet received'"
assert-qdi-channel-valid "c.out_sram_wr" 30 678670619
set c.out_sram_wr.a 1
set c.out_sram_wr.v 1
cycle
assert-qdi-channel-neutral "c.out_sram_wr" 30
set c.out_sram_wr.a 0
set c.out_sram_wr.v 0
cycle
# set three different nrn AMZI lines to different vals
# target one with mon, look at output
# target another with mon, look at output
system "echo '[] Sending packet 1094726289 to SRAM, input = 0b100001010000000011001010010001'"
set-bd-data-valid "c.in" 32 557855377
cycle
set c.in.r 1
cycle
assert c.in.a 1
system "echo '[] Removing input'"
set-bd-channel-neutral "c.in" 32
cycle
assert c.in.a 0
system "echo '[] Checking sram rw packet received'"
assert-qdi-channel-valid "c.out_sram_wr" 30 1094726289
set c.out_sram_wr.a 1
set c.out_sram_wr.v 1
cycle
assert-qdi-channel-neutral "c.out_sram_wr" 30
set c.out_sram_wr.a 0
set c.out_sram_wr.v 0
cycle
system "echo '[] Sending packet 79757788 to SRAM, input = 0b100100110000010000000111011100'"
set-bd-data-valid "c.in" 32 616628700
cycle
set c.in.r 1
cycle
assert c.in.a 1
system "echo '[] Removing input'"
set-bd-channel-neutral "c.in" 32
cycle
assert c.in.a 0
system "echo '[] Checking sram rw packet received'"
assert-qdi-channel-valid "c.out_sram_wr" 30 79757788
set c.out_sram_wr.a 1
set c.out_sram_wr.v 1
cycle
assert-qdi-channel-neutral "c.out_sram_wr" 30
set c.out_sram_wr.a 0
set c.out_sram_wr.v 0
cycle
system "echo '[] Sending packet 217278680 to SRAM, input = 0b101100111100110110100011011000'"
set-bd-data-valid "c.in" 32 754149592
cycle
set c.in.r 1
cycle
assert c.in.a 1
system "echo '[] Removing input'"
set-bd-channel-neutral "c.in" 32
cycle
assert c.in.a 0
system "echo '[] Checking sram rw packet received'"
assert-qdi-channel-valid "c.out_sram_wr" 30 217278680
set c.out_sram_wr.a 1
set c.out_sram_wr.v 1
cycle
assert-qdi-channel-neutral "c.out_sram_wr" 30
set c.out_sram_wr.a 0
set c.out_sram_wr.v 0
cycle
system "echo '[] Sending packet 1060621136 to SRAM, input = 0b10111111001101111100101101010000'"
set-bd-data-valid "c.in" 32 3208104784
cycle
set c.in.r 1
cycle
assert c.in.a 1
system "echo '[] Removing input'"
set-bd-channel-neutral "c.in" 32
cycle
assert c.in.a 0
system "echo '[] Checking sram rw packet received'"
assert-qdi-channel-valid "c.out_sram_wr" 30 1060621136
set c.out_sram_wr.a 1
set c.out_sram_wr.v 1
cycle
assert-qdi-channel-neutral "c.out_sram_wr" 30
set c.out_sram_wr.a 0
set c.out_sram_wr.v 0
cycle
system "echo '[] Sending packet 786253442 to SRAM, input = 0b10101110110111010100011010000010'"
set-bd-data-valid "c.in" 32 2933737090
cycle
set c.in.r 1
cycle
assert c.in.a 1
system "echo '[] Removing input'"
set-bd-channel-neutral "c.in" 32
cycle
assert c.in.a 0
system "echo '[] Checking sram rw packet received'"
assert-qdi-channel-valid "c.out_sram_wr" 30 786253442
set c.out_sram_wr.a 1
set c.out_sram_wr.v 1
cycle
assert-qdi-channel-neutral "c.out_sram_wr" 30
set c.out_sram_wr.a 0
set c.out_sram_wr.v 0
cycle
system "echo '[] Sending packet 973441044 to SRAM, input = 0b10111010000001011000100000010100'"
set-bd-data-valid "c.in" 32 3120924692
cycle
set c.in.r 1
cycle
assert c.in.a 1
system "echo '[] Removing input'"
set-bd-channel-neutral "c.in" 32
cycle
assert c.in.a 0
system "echo '[] Checking sram rw packet received'"
assert-qdi-channel-valid "c.out_sram_wr" 30 973441044
set c.out_sram_wr.a 1
set c.out_sram_wr.v 1
cycle
assert-qdi-channel-neutral "c.out_sram_wr" 30
set c.out_sram_wr.a 0
set c.out_sram_wr.v 0
cycle
system "echo '[] Sending packet 2056336981 to SRAM, input = 0b10111010100100010011011001010101'"
set-bd-data-valid "c.in" 32 3130078805
cycle
set c.in.r 1
cycle
assert c.in.a 1
system "echo '[] Removing input'"
set-bd-channel-neutral "c.in" 32
cycle
assert c.in.a 0
system "echo '[] Checking sram rw packet received'"
assert-qdi-channel-valid "c.out_sram_wr" 30 2056336981
set c.out_sram_wr.a 1
set c.out_sram_wr.v 1
cycle
assert-qdi-channel-neutral "c.out_sram_wr" 30
set c.out_sram_wr.a 0
set c.out_sram_wr.v 0
cycle
system "echo '[] Sending packet 354576334 to SRAM, input = 0b110101001000100110011111001110'"
set-bd-data-valid "c.in" 32 891447246
cycle
set c.in.r 1
cycle
assert c.in.a 1
system "echo '[] Removing input'"
set-bd-channel-neutral "c.in" 32
cycle
assert c.in.a 0
system "echo '[] Checking sram rw packet received'"
assert-qdi-channel-valid "c.out_sram_wr" 30 354576334
set c.out_sram_wr.a 1
set c.out_sram_wr.v 1
cycle
assert-qdi-channel-neutral "c.out_sram_wr" 30
set c.out_sram_wr.a 0
set c.out_sram_wr.v 0
cycle
system "echo '[] Sending packet 900729561 to SRAM, input = 0b10110101101100000000101011011001'"
set-bd-data-valid "c.in" 32 3048213209
cycle
set c.in.r 1
cycle
assert c.in.a 1
system "echo '[] Removing input'"
set-bd-channel-neutral "c.in" 32
cycle
assert c.in.a 0
system "echo '[] Checking sram rw packet received'"
assert-qdi-channel-valid "c.out_sram_wr" 30 900729561
set c.out_sram_wr.a 1
set c.out_sram_wr.v 1
cycle
assert-qdi-channel-neutral "c.out_sram_wr" 30
set c.out_sram_wr.a 0
set c.out_sram_wr.v 0
cycle
system "echo '[] Sending packet 1758190681 to SRAM, input = 0b10101000110010111101110001011001'"
set-bd-data-valid "c.in" 32 2831932505
cycle
set c.in.r 1
cycle
assert c.in.a 1
system "echo '[] Removing input'"
set-bd-channel-neutral "c.in" 32
cycle
assert c.in.a 0
system "echo '[] Checking sram rw packet received'"
assert-qdi-channel-valid "c.out_sram_wr" 30 1758190681
set c.out_sram_wr.a 1
set c.out_sram_wr.v 1
cycle
assert-qdi-channel-neutral "c.out_sram_wr" 30
set c.out_sram_wr.a 0
set c.out_sram_wr.v 0
cycle
system "echo '[] Sending packet 2053675008 to SRAM, input = 0b10111010011010001001100000000000'"
set-bd-data-valid "c.in" 32 3127416832
cycle
set c.in.r 1
cycle
assert c.in.a 1
system "echo '[] Removing input'"
set-bd-channel-neutral "c.in" 32
cycle
assert c.in.a 0
system "echo '[] Checking sram rw packet received'"
assert-qdi-channel-valid "c.out_sram_wr" 30 2053675008
set c.out_sram_wr.a 1
set c.out_sram_wr.v 1
cycle
assert-qdi-channel-neutral "c.out_sram_wr" 30
set c.out_sram_wr.a 0
set c.out_sram_wr.v 0
cycle
system "echo '[] Sending packet 597269325 to SRAM, input = 0b10100011100110011001101101001101'"
set-bd-data-valid "c.in" 32 2744752973
cycle
set c.in.r 1
cycle
assert c.in.a 1
system "echo '[] Removing input'"
set-bd-channel-neutral "c.in" 32
cycle
assert c.in.a 0
system "echo '[] Checking sram rw packet received'"
assert-qdi-channel-valid "c.out_sram_wr" 30 597269325
set c.out_sram_wr.a 1
set c.out_sram_wr.v 1
cycle
assert-qdi-channel-neutral "c.out_sram_wr" 30
set c.out_sram_wr.a 0
set c.out_sram_wr.v 0
cycle
system "echo '[] Sending packet 63281016 to SRAM, input = 0b100011110001011001011101111000'"
set-bd-data-valid "c.in" 32 600151928
cycle
set c.in.r 1
cycle
assert c.in.a 1
system "echo '[] Removing input'"
set-bd-channel-neutral "c.in" 32
cycle
assert c.in.a 0
system "echo '[] Checking sram rw packet received'"
assert-qdi-channel-valid "c.out_sram_wr" 30 63281016
set c.out_sram_wr.a 1
set c.out_sram_wr.v 1
cycle
assert-qdi-channel-neutral "c.out_sram_wr" 30
set c.out_sram_wr.a 0
set c.out_sram_wr.v 0
cycle
system "echo '[] Sending packet 1439738843 to SRAM, input = 0b110101110100001010101111011011'"
set-bd-data-valid "c.in" 32 902867931
cycle
set c.in.r 1
cycle
assert c.in.a 1
system "echo '[] Removing input'"
set-bd-channel-neutral "c.in" 32
cycle
assert c.in.a 0
system "echo '[] Checking sram rw packet received'"
assert-qdi-channel-valid "c.out_sram_wr" 30 1439738843
set c.out_sram_wr.a 1
set c.out_sram_wr.v 1
cycle
assert-qdi-channel-neutral "c.out_sram_wr" 30
set c.out_sram_wr.a 0
set c.out_sram_wr.v 0
cycle
system "echo '[] Sending packet 763598892 to SRAM, input = 0b10101101100000111001100000101100'"
set-bd-data-valid "c.in" 32 2911082540
cycle
set c.in.r 1
cycle
assert c.in.a 1
system "echo '[] Removing input'"
set-bd-channel-neutral "c.in" 32
cycle
assert c.in.a 0
system "echo '[] Checking sram rw packet received'"
assert-qdi-channel-valid "c.out_sram_wr" 30 763598892
set c.out_sram_wr.a 1
set c.out_sram_wr.v 1
cycle
assert-qdi-channel-neutral "c.out_sram_wr" 30
set c.out_sram_wr.a 0
set c.out_sram_wr.v 0
cycle