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packets to sram rw working

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alexmadison
2022-05-10 14:07:51 +02:00
parent 9ceaa10eeb
commit 4c208bc18a
3 changed files with 469 additions and 415 deletions
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52
dataflow_neuro/chips.act
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@ -604,7 +604,7 @@ defproc texel_dualcore_mapper (bd<N_IN> in, out;
bool? mapper_en;
avMx1of2<30> out_sram_wr; // Input packets to go to SRAM (rw word addr)
avMx1of2<8> out_sram_spk; // Spike packets from enc to go to SRAM (core-nrn addr)
avMx1of2<15> in_sram_r; // Readout packets from SRAM (data only)
avMx1of2<29> in_sram_r; // Readout packets from SRAM
avMx1of2<14> in_sram_spk // Spike packets from SRAM (core-syn addr)
){
@ -629,7 +629,8 @@ defproc texel_dualcore_mapper (bd<N_IN> in, out;
// dmx to SRAM
bool is_to_sram, is_to_cores;
demux<32> sram_dmx(.in = _fork.out2, .supply = supply, .reset_B = _reset_BX);
fifo<32, N_BUFFERS> fifo_fork2sramdmx(.in = _fork.out2, .supply = supply, .reset_B = _reset_BX);
demux<32> sram_dmx(.in = fifo_fork2sramdmx.out, .supply = supply, .reset_B = _reset_BX);
sram_dmx.cond.d.d[0].t = is_to_sram;
sram_dmx.cond.d.d[0].f = is_to_cores;
AND2_X1 sram_dmx_and(.a = sram_dmx.in.d.d[30].f, .b = sram_dmx.in.d.d[29].t,
@ -638,15 +639,26 @@ defproc texel_dualcore_mapper (bd<N_IN> in, out;
OR3_X1 sram_dmx_or(.a = sram_dmx.in.d.d[30].t, .b = sram_dmx.in.d.d[30].t, .c = sram_dmx.in.d.d[29].f,
.y = is_to_cores,
.vdd = supply.vdd, .vss = supply.vss);
slice_data<32, 0, 29> pre_sram_slice(.in = sram_dmx.out2, .supply = supply);
out_sram_wr.a = pre_sram_slice.out.a;
out_sram_wr.v = pre_sram_slice.out.v;
(i:29:out_sram_wr.d.d[i] = pre_sram_slice.out.d.d[i];)
out_sram_wr.d.d[29] = pre_sram_slice.in.d.d[31];
slice_data<32, 0, 30> pre_sram_slice(.supply = supply);
pre_sram_slice.in.a = sram_dmx.out2.a;
pre_sram_slice.in.v = sram_dmx.out2.v;
(i:29:pre_sram_slice.in.d.d[i] = sram_dmx.out2.d.d[i];)
pre_sram_slice.in.d.d[29] = sram_dmx.out2.d.d[31];
pre_sram_slice.in.d.d[30] = sram_dmx.out2.d.d[30];
pre_sram_slice.in.d.d[31] = sram_dmx.out2.d.d[29];
fifo<30, N_BUFFERS> fifo_out_sram_wr(.in = pre_sram_slice.out, .out = out_sram_wr,
.reset_B = _reset_BX, .supply = supply);
// fifo_out_sram_wr.in.a = pre_sram_slice.out.a;
// fifo_out_sram_wr.in.v = pre_sram_slice.out.v;
// (i:29:fifo_out_sram_wr.in.d.d[i] = pre_sram_slice.out.d.d[i];)
// fifo_out_sram_wr.in.d.d[29] = pre_sram_slice.in.d.d[31];
// spikes from sram
// requires weird merging because [core, syny, synx] needs to go to [core, ZEROES, syny, synx]
append<14,32,0> sram_spk_in_append(.in = in_sram_spk, .supply = supply);
fifo<14, N_BUFFERS> fifo_in_sram_spk(.in = in_sram_spk, .reset_B = _reset_BX, .supply = supply);
append<14,32,0> sram_spk_in_append(.in = fifo_in_sram_spk.out, .supply = supply);
merge<32> merge_dmx8spk(.in1 = sram_dmx.out1, .reset_B = _reset_BX, .supply = supply);
merge_dmx8spk.in2.a = sram_spk_in_append.out.a;
merge_dmx8spk.in2.v = sram_spk_in_append.out.v;
@ -726,21 +738,33 @@ defproc texel_dualcore_mapper (bd<N_IN> in, out;
.supply = supply, .reset_B = _reset_BX);
// fork after core merge then go to mapper if its a spike
fork<32> postcore_fork(.in = merge_core1x2.out, .reset_B = _reset_BX, .supply = supply);
fifo<32, N_BUFFERS> fifo_core2fork(.in = merge_core1x2.out, .reset_B = _reset_BX, .supply = supply);
fork<32> postcore_fork(.in = fifo_core2fork.out, .reset_B = _reset_BX, .supply = supply);
dropper_static<32, false> sram_dropper(.in = postcore_fork.out1, .cond = mapper_en, .supply = supply);
// Need to have it then drop the spike if its from a register.
// to do: go into a self-acknowledging dmx_td, with the cond being on the register bit.
demux_td<32, false> drop_if_reg(.in = sram_dropper.out, .reset_B = _reset_BX, .supply = supply); // if cond true, go out on data
drop_if_reg.cond.d.d[0] = sram_dropper.out.d.d[30];
drop_if_reg.token.r = drop_if_reg.token.a;
slice_data<32,0,8> slice_to_sram(.in = drop_if_reg.out, .out = out_sram_spk, .supply = supply);
fifo<8,N_BUFFERS> fifo_out_sram_spk(.out = out_sram_spk, .reset_B = _reset_BX, .supply = supply);
slice_data<32,0,8> slice_to_sram(.in = drop_if_reg.out, .out = fifo_out_sram_spk.in, .supply = supply);
// And move the msb (core bit) to just after the neuron address...
slice_to_sram.in.a = drop_if_reg.out.a;
slice_to_sram.in.v = drop_if_reg.out.v;
(i:7:slice_to_sram.in.d.d[i] = drop_if_reg.out.d.d[i];)
slice_to_sram.in.d.d[7] = drop_if_reg.out.d.d[31];
(i:7..30: slice_to_sram.in.d.d[i+1] = drop_if_reg.out.d.d[i];)
// merge from cores and sram read in
fifo<29, N_BUFFERS> fifo_in_sram_r(.in = in_sram_r, .reset_B = _reset_BX, .supply = supply);
fifo<32, N_BUFFERS> fifo_fork2mrg(.in = postcore_fork.out2, .reset_B = _reset_BX, .supply = supply);
append<29,3,2> sram_read_in_append(.in = fifo_in_sram_r.out, .supply = supply);
merge<32> merge_sram8core(.in1 = fifo_fork2mrg.out, .in2 = sram_read_in_append.out,
.reset_B = _reset_BX, .supply = supply);
// Merge cores and loopback
merge<N_IN> merge_drop8core(.in1 = postcore_fork.out2, .in2 = fifo_drop2mrg.out,
fifo<32, N_BUFFERS> fifo_mrg2mrg(.in = merge_sram8core.out, .reset_B = _reset_BX, .supply = supply);
merge<N_IN> merge_drop8core(.in1 = fifo_mrg2mrg.out, .in2 = fifo_drop2mrg.out,
.reset_B = _reset_BX, .supply = supply);
// qdi2bd