texel dualcore testing wip
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alexmadison committed
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@@ -120,7 +120,7 @@ defproc texel_core (avMx1of2<N_IN> in, out;
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// Output
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fifo<N_IN, N_BUFFERS> fifo_mrg2bd(.in = merge_enc8reg.out, .out = out,
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fifo<N_IN, N_BUFFERS> fifo_out(.in = merge_enc8reg.out, .out = out,
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.reset_B = _reset_BX, .supply = supply);
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@@ -420,10 +420,13 @@ defproc texel_dualcore (bd<N_IN> in, out;
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.supply = supply
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);
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fifo<N_IN-1,N_BUFFERS> fifo_core1out(.in = core1.out, .reset_B = _reset_BX, .supply = supply);
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fifo<N_IN-1,N_BUFFERS> fifo_core2out(.in = core2.out, .reset_B = _reset_BX, .supply = supply);
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// Merge cores
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append<N_IN-1, 1, 0> append_core1(.in = core1.out, .supply = supply);
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append<N_IN-1, 1, 1> append_core2(.in = core2.out, .supply = supply);
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append<N_IN-1, 1, 0> append_core1(.in = fifo_core1out.out, .supply = supply);
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append<N_IN-1, 1, 1> append_core2(.in = fifo_core2out.out, .supply = supply);
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merge<N_IN> merge_core1x2(.in1 = append_core1.out, .in2 = append_core2.out,
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.supply = supply, .reset_B = _reset_BX);
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File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,649 @@
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c.c.core2.syn_x_AMZI_tbuf[4].y c.c._qdi2bd.dly.dly[4].y c.c._bd2qdi.dly.dly[6].bufchain[12].y c.c2_nrn_r[56] c.c1_nrn_r[82] c.c1_nrn_r[40] c.c2_nrn_r[10] c.c2_syn_mon_AMZI[29] c.c._bd2qdi._reqXX[0] c.c1_syn_mon_AMZI[27] c.c1_syn_a[42] c.c._bd2qdi.dly.dly[11].bufchain[13]._y c.c2_nrn_mon_AMZI[30] c.c._bd2qdi.dly.dly[1].bufchain[1].y c.c1_nrn_r[55] c.c1_nrn_mon_AMZO[3] c.c._bd2qdi.dly.dly[0].bufchain[7]._y c.c1_syn_a[87] c.c1_syn_a[44] c.c2_nrn_mon_AMZO[4] c.c1_syn_mon_AMZI[10] c.c._bd2qdi.dly.dly[7].bufchain[0]._y c.c._bd2qdi.dly.dly[11].bufchain[4]._y c.c._bd2qdi.dly.mu2[3]._s c.c1_syn_a[69] c.in.d[27] c.c._bd2qdi.dly.dly[13].bufchain[1].y c.c2_nrn_mon_AMZO[3] c.c2_nrn_r[17] c.c2_syn_mon_AMZO[2] c.c.core1.nrn_x_AMZI_tbuf[0].y c.c1_nrn_mon_AMZO[6] c.c1_syn_mon_AMZO[1] c.c1_nrn_r[38] c.c2_syn_mon_AMZO[4] c.c1_syn_mon_AMZI[68] c.c._qdi2bd.dly.dly[7].a c.c1_syn_a[33] c.c._bd2qdi.dly2.out c.c._qdi2bd.dly.dly[2].bufchain[10]._y c.c2_nrn_r[25] c.bd_dly_cfg[2] c.c._bd2qdi.dly.dly[10].bufchain[5].y c.c1_nrn_mon_AMZI[3] c.c1_nrn_r[85] c.c2_syn_mon_AMZO[3] c.c2_syn_mon_AMZI[56] c.c._bd2qdi.dly2.dly[0].bufchain[10].y c.c1_nrn_mon_AMZI[22] c.c1_nrn_r[44] c.c2_syn_a[81] c.c2_syn_a[35] c.c._bd2qdi.dly.dly[11].bufchain[8].y c.c2_nrn_r[49] c.c._bd2qdi.dly.dly[14].bufchain[5].y c.c1_syn_a[53] c.c2_nrn_r[58] c.c1_nrn_r[23] c.c._qdi2bd.dly.dly[7].bufchain[4].y c.c._loopback_dropper.and_f[0].b c.c2_syn_a[79] c.c._qdi2bd.dly.dly[4].bufchain[7]._y c.c1_nrn_mon_AMZO[5] c.c2_syn_mon_AMZI[7] c.c._qdi2bd.dly.dly[14].bufchain[11]._y c.c1_nrn_mon_AMZI[99] c.c._qdi2bd.dly.dly[5].bufchain[13]._y c.c1_nrn_r[74] c.c.core1.nrn_x_AMZI_tbuf[2].y c.c2_nrn_mon_AMZI[64] c.c._qdi2bd.dly.dly[4].bufchain[14].y c.c._qdi2bd.buf._out_a_BX[0] c.c2_nrn_mon_AMZO[1] c.c1_nrn_r[75] c.c._bd2qdi.dly.dly[6].bufchain[11].y c.c1_nrn_mon_AMZI[96] c.c2_nrn_mon_AMZO[0] c.c._bd2qdi.dly2.dly[2].bufchain[14].y c.c2_nrn_r[32] c.c1_nrn_mon_AMZO[2] c.c2_nrn_r[80] c.c2_nrn_r[0] c.c2_syn_mon_AMZI[8] c.c1_syn_a[64] c.c._bd2qdi.dly.dly[0].bufchain[0].y c.c._bd2qdi.dly.dly[11].bufchain[1].y c.c2_syn_a[63] c.c1_nrn_r[78] c.c._qdi2bd.dly.dly[12].bufchain[3].y c.c1_nrn_r[16] c.c2_syn_mon_AMZI[39] c.c2_syn_mon_AMZI[61] c.c2_nrn_r[84] c.c1_syn_a[4] c.c2_nrn_mon_AMZI[91] c.c.core2.syn_x_AMZI_tbuf[0].y c.c2_nrn_r[60] c.c._qdi2bd.dly.dly[11].bufchain[11].y c.c.core2.nrn_x_AMZI_tbuf[1].y c.c._bd2qdi.dly.dly[11].bufchain[11].y c.c._bd2qdi.dly.dly[10].bufchain[0].y c.c._bd2qdi._req_slowfall c.c.core1.syn_x_AMZI_tbuf[2].y c.c2_syn_a[57] c.c1_nrn_r[72] c.c._bd2qdi.dly.dly[7].y c.c.core2.syn_x_AMZI_tbuf[2].y c.c._bd2qdi._inB[30] c.c._bd2qdi.dly.dly[3].bufchain[10].y c.c1_syn_a[74] c.c.core1.nrn_x_AMZI_tbuf[4].y c.c1_nrn_mon_AMZI[32] c.c._bd2qdi.dly._a[2] c.c1_nrn_r[51] c.c1_nrn_r[14] c.c2_nrn_mon_AMZI[100] c.c2_nrn_mon_AMZI[70] c.c._qdi2bd.dly.dly[13].bufchain[11]._y c.c2_nrn_mon_AMZI[25] c.c._qdi2bd.dly.dly[3].y c.c._qdi2bd.dly.dly[13].bufchain[6].y c.c1_nrn_mon_AMZO[1] c.c._qdi2bd.dly.dly[8].bufchain[2].y c.c2_syn_a[7] c.c._qdi2bd.dly.dly[10].bufchain[10].y c.c1_syn_a[88] c.c1_nrn_r[19] c.c._bd2qdi.dly.dly[0].bufchain[12]._y c.c2_syn_a[13] c.c2_nrn_mon_AMZI[85] c.c1_syn_a[10] c.c1_nrn_mon_AMZI[15] c.c.core2.nrn_x_AMZI_tbuf[0].y c.c2_syn_a[8] c.c2_nrn_mon_AMZO[2] c.c1_syn_a[29] c.c1_nrn_mon_AMZI[91] c.in.d[18] c.c.core1.nrn_x_AMZI_tbuf[3].y c.c1_nrn_r[35] c.c2_syn_mon_AMZI[69] c.c2_nrn_mon_AMZI[92] c.c2_syn_mon_AMZI[48] c.c._bd2qdi.dly.dly[14].bufchain[1]._y c.c1_syn_mon_AMZI[63] c.c1_syn_mon_AMZI[32] c.c1_nrn_r[70] c.c1_syn_mon_AMZO[4] c.c1_nrn_r[9] c.c2_nrn_mon_AMZO[5] c.c2_nrn_r[88] c.c._qdi2bd.dly.dly[10].bufchain[0].y c.c1_nrn_r[17] c.c2_nrn_mon_AMZI[84] c.c1_nrn_r[20] c.c._bd2qdi.dly2.mu2[1]._y c.c1_nrn_r[65] c.c1_syn_a[31] c.c2_nrn_r[7] c.c2_nrn_r[40] c.c2_nrn_r[67] c.c1_nrn_r[29] c.c2_nrn_r[76] c.c2_syn_mon_AMZI[49] c.c1_nrn_r[8] c.c._bd2qdi.dly2.dly[1].bufchain[14]._y c.c._qdi2bd.dly.dly[4].bufchain[3].y c.c1_nrn_mon_AMZO[4] c.c2_nrn_r[48] c.c2_nrn_r[44] c.c._qdi2bd.dly.dly[8].bufchain[12].y c.c2_syn_mon_AMZI[63] c.c1_syn_a[3] c.c2_nrn_r[15] c.c2_nrn_r[51] c.c._bd2qdi.dly.dly[4].bufchain[8].y c.c._qdi2bd.dly.dly[6].bufchain[1]._y c.c2_nrn_r[18] c.c1_syn_mon_AMZI[14] c.c._qdi2bd.dly.dly[6].bufchain[10].y c.c._qdi2bd.dly.dly[13].bufchain[9].y c.c1_syn_mon_AMZO[0] c.c1_syn_a[41] c.c2_nrn_r[59] c.c._qdi2bd.dly._a[2] c.c1_syn_mon_AMZI[65] c.c1_syn_a[75] c.c1_syn_mon_AMZI[0] c.c._qdi2bd.dly.dly[9].bufchain[2].y c.c1_nrn_mon_AMZI[101] c.c2_nrn_r[13] c.c._bd2qdi.dly.dly[0].y c.c1_syn_mon_AMZI[67] c.c2_syn_a[49] c.c1_syn_a[50] c.c2_syn_a[59] c.in.d[12] c.c1_syn_a[78] c.c2_nrn_r[63] c.c._bd2qdi.dly.dly[10].bufchain[0]._y c.c1_nrn_mon_AMZI[52] c.c._bd2qdi.dly.dly[7].bufchain[8].y c.in.d[17] c.c._qdi2bd.dly.dly[9].bufchain[12].y c.c.core2.nrn_x_AMZI_tbuf[5].y c.in.d[4] c.c._bd2qdi._inB[20] c.c2_nrn_r[19] c.c1_nrn_r[43] c.c2_nrn_r[72] c.c1_nrn_r[3] c.in.d[5] c.c2_nrn_r[70] c.c1_syn_mon_AMZI[73] c.c2_nrn_r[3] c.c1_nrn_r[22] c.c1_nrn_r[67] c.c._qdi2bd.dly.dly[2].bufchain[7].y c.c2_nrn_r[5] c.Line truncated
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c.c.core2.syn_x_AMZI_tbuf[4].y c.c2_syn_mon_AMZI[29] c.c1_syn_mon_AMZI[27] c.c2_nrn_mon_AMZI[30] c.c1_nrn_mon_AMZO[3] c.c2_nrn_mon_AMZO[4] c.c1_syn_mon_AMZI[10] c.c2_nrn_mon_AMZO[3] c.c2_syn_mon_AMZO[2] c.c.core1.nrn_x_AMZI_tbuf[0].y c.c1_nrn_mon_AMZO[6] c.c1_syn_mon_AMZO[1] c.c2_syn_mon_AMZO[4] c.c1_syn_mon_AMZI[68] c.c1_nrn_mon_AMZI[3] c.c2_syn_mon_AMZO[3] c.c2_syn_mon_AMZI[56] c.c1_nrn_mon_AMZI[22] c.c1_nrn_mon_AMZO[5] c.c2_syn_mon_AMZI[7] c.c1_nrn_mon_AMZI[99] c.c.core1.nrn_x_AMZI_tbuf[2].y c.c2_nrn_mon_AMZI[64] c.c2_nrn_mon_AMZO[1] c.c1_nrn_mon_AMZI[96] c.c2_nrn_mon_AMZO[0] c.c1_nrn_mon_AMZO[2] c.c2_syn_mon_AMZI[8] c.c2_syn_mon_AMZI[39] c.c2_syn_mon_AMZI[61] c.c2_nrn_mon_AMZI[91] c.c.core2.syn_x_AMZI_tbuf[0].y c.c.core2.nrn_x_AMZI_tbuf[1].y c.c.core1.syn_x_AMZI_tbuf[2].y c.c.core2.syn_x_AMZI_tbuf[2].y c.c.core1.nrn_x_AMZI_tbuf[4].y c.c1_nrn_mon_AMZI[32] c.c2_nrn_mon_AMZI[100] c.c2_nrn_mon_AMZI[70] c.c2_nrn_mon_AMZI[25] c.c1_nrn_mon_AMZO[1] c.c2_nrn_mon_AMZI[85] c.c1_nrn_mon_AMZI[15] c.c.core2.nrn_x_AMZI_tbuf[0].y c.c2_nrn_mon_AMZO[2] c.c1_nrn_mon_AMZI[91] c.c.core1.nrn_x_AMZI_tbuf[3].y c.c2_syn_mon_AMZI[69] c.c2_nrn_mon_AMZI[92] c.c2_syn_mon_AMZI[48] c.c1_syn_mon_AMZI[63] c.c1_syn_mon_AMZI[32] c.c1_syn_mon_AMZO[4] c.c2_nrn_mon_AMZO[5] c.c2_nrn_mon_AMZI[84] c.c2_syn_mon_AMZI[49] c.c1_nrn_mon_AMZO[4] c.c2_syn_mon_AMZI[63] c.c1_syn_mon_AMZI[14] c.c1_syn_mon_AMZO[0] c.c1_syn_mon_AMZI[65] c.c1_syn_mon_AMZI[0] c.c1_nrn_mon_AMZI[101] c.c1_syn_mon_AMZI[67] c.c1_nrn_mon_AMZI[52] c.c.core2.nrn_x_AMZI_tbuf[5].y c.c1_syn_mon_AMZI[73] c.c2_syn_mon_AMZI[30] c.c2_syn_mon_AMZI[28] c.c2_nrn_mon_AMZI[31] c.c.core1.syn_x_AMZI_tbuf[1].y c.c1_syn_mon_AMZI[58] c.c1_syn_mon_AMZI[2] c.c1_syn_mon_AMZI[45] c.c2_nrn_mon_AMZI[41] c.c.core2.nrn_x_AMZI_tbuf[6].y c.c1_nrn_mon_AMZI[7] c.c2_nrn_mon_AMZI[82] c.c1_syn_mon_AMZI[51] c.c.core2.syn_x_AMZI_tbuf[1].y c.c1_syn_mon_AMZO[2] c.c1_syn_mon_AMZI[56] c.c1_nrn_mon_AMZI[43] c.c1_syn_mon_AMZI[7] c.c2_syn_mon_AMZI[12] c.c2_syn_mon_AMZI[40] c.c1_nrn_mon_AMZI[71] c.c1_nrn_mon_AMZI[9] c.c1_nrn_mon_AMZI[57] c.c.core1.nrn_x_AMZI_tbuf[1].y c.c2_nrn_mon_AMZI[6] c.c1_syn_mon_AMZI[59] c.c1_nrn_mon_AMZI[61] c.c1_nrn_mon_AMZI[48] c.c1_syn_mon_AMZI[16] c.c1_syn_mon_AMZI[4] c.c1_syn_mon_AMZI[61] c.c2_nrn_mon_AMZI[90] c.c1_syn_mon_AMZI[37] c.c.core1.syn_x_AMZI_tbuf[3].y c.c.core2.nrn_x_AMZI_tbuf[2].y c.c2_syn_mon_AMZI[1] c.c2_syn_mon_AMZI[72] c.c1_syn_mon_AMZI[25] c.c1_syn_mon_AMZI[39] c.c1_syn_mon_AMZO[3] c.c2_nrn_mon_AMZI[24] c.c1_nrn_mon_AMZI[68] c.c1_nrn_mon_AMZI[62] c.c2_syn_mon_AMZO[0] c.c.core1.syn_x_AMZI_tbuf[0].y c.c2_nrn_mon_AMZI[1] c.c2_nrn_mon_AMZI[89] c.c2_syn_mon_AMZI[67] c.c2_nrn_mon_AMZI[33] c.c1_syn_mon_AMZI[38] c.c2_nrn_mon_AMZI[37] c.c.core2.syn_x_AMZI_tbuf[3].y c.c1_syn_mon_AMZI[72] c.c1_syn_mon_AMZI[54] c.c2_nrn_mon_AMZI[72] c.c2_syn_mon_AMZI[35] c.c2_nrn_mon_AMZI[102] c.c1_syn_mon_AMZI[6] c.c2_nrn_mon_AMZI[74] c.c2_syn_mon_AMZI[11] c.c2_nrn_mon_AMZO[6] c.c2_nrn_mon_AMZI[79] c.c1_syn_mon_AMZI[50] c.c1_nrn_mon_AMZI[75] c.c.core2.nrn_x_AMZI_tbuf[4].y c.c1_syn_mon_AMZI[55] c.c1_nrn_mon_AMZI[60] c.c2_nrn_mon_AMZI[19] c.c2_syn_mon_AMZI[33] c.c1_syn_mon_AMZI[23] c.c.core1.nrn_x_AMZI_tbuf[6].y c.c2_syn_mon_AMZI[71] c.c.core1.nrn_x_AMZI_tbuf[5].y c.c1_syn_mon_AMZI[8] c.c1_nrn_mon_AMZI[92] c.c2_syn_mon_AMZI[41] c.c2_syn_mon_AMZI[60] c.c2_syn_mon_AMZI[24] c.c1_syn_mon_AMZI[46] c.c1_nrn_mon_AMZI[39] c.c2_syn_mon_AMZI[66] c.c2_nrn_mon_AMZI[58] c.c1_nrn_mon_AMZI[69] c.c1_nrn_mon_AMZI[10] c.c2_syn_mon_AMZI[45] c.c1_nrn_mon_AMZI[73] c.c2_nrn_mon_AMZI[3] c.c2_nrn_mon_AMZI[23] c.c1_nrn_mon_AMZI[5] c.c1_nrn_mon_AMZO[0] c.c1_nrn_mon_AMZI[51] c.c1_syn_mon_AMZI[36] c.c1_nrn_mon_AMZI[104] c.c2_syn_mon_AMZI[4] c.c2_nrn_mon_AMZI[22] c.c.core1.nrn_mon_AMZO_sb.sb[6].buf12._y c.c1_syn_mon_AMZI[48] c.c1_nrn_mon_AMZI[78] c.c1_nrn_mon_AMZI[98] c.c2_nrn_mon_AMZI[20] c.c2_nrn_mon_AMZI[12] c.c2_nrn_mon_AMZI[77] c.c2_syn_mon_AMZI[58] c.c2_nrn_mon_AMZI[48] c.c2_nrn_mon_AMZI[104] c.c1_syn_mon_AMZI[17] c.c1_syn_mon_AMZI[15] c.c2_syn_mon_AMZI[54] c.c1_nrn_mon_AMZI[1] c.c1_syn_mon_AMZI[64] c.c2_nrn_mon_AMZI[11] c.c2_syn_mon_AMZI[32] c.c.core2.nrn_x_AMZI_tbuf[3].y c.c2_nrn_mon_AMZI[101] c.c2_nrn_mon_AMZI[29] c.c.core1.syn_x_AMZI_tbuf[4].y c.c2_syn_mon_AMZI[19] c.c2_syn_mon_AMZI[65] c.c2_nrn_mon_AMZI[8] c.c1_syn_mon_AMZI[21] c.c2_nrn_mon_AMZI[93] c.c2_nrn_mon_AMZI[39] c.c.core1.nrn_mon_AMZO_sb.sb[4].buf12._y c.c2_nrn_mon_AMZI[97] c.c2_syn_mon_AMZI[70] c.c1_nrn_mon_AMZI[41] c.c2_nrn_mon_AMZI[68] c.c1_nrn_mon_AMZI[40] c.c1_nrn_mon_AMZI[11] c.c2_nrn_mon_AMZI[50] c.c1_nrn_mon_AMZI[44] c.c1_nrn_mon_AMZI[13] c.c1_nrn_mon_AMZI[38] c.c2_nrn_mon_AMZI[69] c.c1_syn_mon_AMZI[31] c.c.core2.syn_mon_AMZO_sb.sb[1].buf12._y c.c1_nrn_mon_AMZI[54] c.c2_nrn_mon_AMZI[16] c.c1_nrn_mon_AMZI[6] c.c1_nrn_mon_AMZI[84] c.c2_syn_mon_AMZI[43] c.c2_syn_mon_AMZI[52] c.c2_syn_mon_AMZI[2] c.c1_nrn_mon_AMZI[37] c.c2_syn_mon_AMZO[1] c.c1_syn_mon_AMZI[49] c.c1_syn_mon_AMZI[47] c.c1_nrn_mon_AMZI[65] c.c1_nrn_mon_AMZI[35] c.c1_nrn_mon_AMZI[95] c.c2_syn_mon_Line truncated
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[] Set reset 0
|
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c.c.core2.syn_x_AMZI_tbuf[4].y c.c2_syn_mon_AMZI[29] c.c1_syn_mon_AMZI[27] c.c2_nrn_mon_AMZI[30] c.c1_nrn_mon_AMZO[3] c.c2_nrn_mon_AMZO[4] c.c1_syn_mon_AMZI[10] c.c2_nrn_mon_AMZO[3] c.c2_syn_mon_AMZO[2] c.c.core1.nrn_x_AMZI_tbuf[0].y c.c1_nrn_mon_AMZO[6] c.c1_syn_mon_AMZO[1] c.c2_syn_mon_AMZO[4] c.c1_syn_mon_AMZI[68] c.c1_nrn_mon_AMZI[3] c.c2_syn_mon_AMZO[3] c.c2_syn_mon_AMZI[56] c.c1_nrn_mon_AMZI[22] c.c1_nrn_mon_AMZO[5] c.c2_syn_mon_AMZI[7] c.c1_nrn_mon_AMZI[99] c.c.core1.nrn_x_AMZI_tbuf[2].y c.c2_nrn_mon_AMZI[64] c.c2_nrn_mon_AMZO[1] c.c1_nrn_mon_AMZI[96] c.c2_nrn_mon_AMZO[0] c.c1_nrn_mon_AMZO[2] c.c2_syn_mon_AMZI[8] c.c2_syn_mon_AMZI[39] c.c2_syn_mon_AMZI[61] c.c2_nrn_mon_AMZI[91] c.c.core2.syn_x_AMZI_tbuf[0].y c.c.core2.nrn_x_AMZI_tbuf[1].y c.c.core1.syn_x_AMZI_tbuf[2].y c.c.core2.syn_x_AMZI_tbuf[2].y c.c.core1.nrn_x_AMZI_tbuf[4].y c.c1_nrn_mon_AMZI[32] c.c2_nrn_mon_AMZI[100] c.c2_nrn_mon_AMZI[70] c.c2_nrn_mon_AMZI[25] c.c1_nrn_mon_AMZO[1] c.c2_nrn_mon_AMZI[85] c.c1_nrn_mon_AMZI[15] c.c.core2.nrn_x_AMZI_tbuf[0].y c.c2_nrn_mon_AMZO[2] c.c1_nrn_mon_AMZI[91] c.c.core1.nrn_x_AMZI_tbuf[3].y c.c2_syn_mon_AMZI[69] c.c2_nrn_mon_AMZI[92] c.c2_syn_mon_AMZI[48] c.c1_syn_mon_AMZI[63] c.c1_syn_mon_AMZI[32] c.c1_syn_mon_AMZO[4] c.c2_nrn_mon_AMZO[5] c.c2_nrn_mon_AMZI[84] c.c2_syn_mon_AMZI[49] c.c1_nrn_mon_AMZO[4] c.c2_syn_mon_AMZI[63] c.c1_syn_mon_AMZI[14] c.c1_syn_mon_AMZO[0] c.c1_syn_mon_AMZI[65] c.c1_syn_mon_AMZI[0] c.c1_nrn_mon_AMZI[101] c.c1_syn_mon_AMZI[67] c.c1_nrn_mon_AMZI[52] c.c.core2.nrn_x_AMZI_tbuf[5].y c.c1_syn_mon_AMZI[73] c.c2_syn_mon_AMZI[30] c.c2_syn_mon_AMZI[28] c.c2_nrn_mon_AMZI[31] c.c.core1.syn_x_AMZI_tbuf[1].y c.c1_syn_mon_AMZI[58] c.c1_syn_mon_AMZI[2] c.c1_syn_mon_AMZI[45] c.c2_nrn_mon_AMZI[41] c.c.core2.nrn_x_AMZI_tbuf[6].y c.c1_nrn_mon_AMZI[7] c.c2_nrn_mon_AMZI[82] c.c1_syn_mon_AMZI[51] c.c.core2.syn_x_AMZI_tbuf[1].y c.c1_syn_mon_AMZO[2] c.c1_syn_mon_AMZI[56] c.c1_nrn_mon_AMZI[43] c.c1_syn_mon_AMZI[7] c.c2_syn_mon_AMZI[12] c.c2_syn_mon_AMZI[40] c.c1_nrn_mon_AMZI[71] c.c1_nrn_mon_AMZI[9] c.c1_nrn_mon_AMZI[57] c.c.core1.nrn_x_AMZI_tbuf[1].y c.c2_nrn_mon_AMZI[6] c.c1_syn_mon_AMZI[59] c.c1_nrn_mon_AMZI[61] c.c1_nrn_mon_AMZI[48] c.c1_syn_mon_AMZI[16] c.c1_syn_mon_AMZI[4] c.c1_syn_mon_AMZI[61] c.c2_nrn_mon_AMZI[90] c.c1_syn_mon_AMZI[37] c.c.core1.syn_x_AMZI_tbuf[3].y c.c.core2.nrn_x_AMZI_tbuf[2].y c.c2_syn_mon_AMZI[1] c.c2_syn_mon_AMZI[72] c.c1_syn_mon_AMZI[25] c.c1_syn_mon_AMZI[39] c.c1_syn_mon_AMZO[3] c.c2_nrn_mon_AMZI[24] c.c1_nrn_mon_AMZI[68] c.c1_nrn_mon_AMZI[62] c.c2_syn_mon_AMZO[0] c.c.core1.syn_x_AMZI_tbuf[0].y c.c2_nrn_mon_AMZI[1] c.c2_nrn_mon_AMZI[89] c.c2_syn_mon_AMZI[67] c.c2_nrn_mon_AMZI[33] c.c1_syn_mon_AMZI[38] c.c2_nrn_mon_AMZI[37] c.c.core2.syn_x_AMZI_tbuf[3].y c.c1_syn_mon_AMZI[72] c.c1_syn_mon_AMZI[54] c.c2_nrn_mon_AMZI[72] c.c2_syn_mon_AMZI[35] c.c2_nrn_mon_AMZI[102] c.c1_syn_mon_AMZI[6] c.c2_nrn_mon_AMZI[74] c.c2_syn_mon_AMZI[11] c.c2_nrn_mon_AMZO[6] c.c2_nrn_mon_AMZI[79] c.c1_syn_mon_AMZI[50] c.c1_nrn_mon_AMZI[75] c.c.core2.nrn_x_AMZI_tbuf[4].y c.c1_syn_mon_AMZI[55] c.c1_nrn_mon_AMZI[60] c.c2_nrn_mon_AMZI[19] c.c2_syn_mon_AMZI[33] c.c1_syn_mon_AMZI[23] c.c.core1.nrn_x_AMZI_tbuf[6].y c.c2_syn_mon_AMZI[71] c.c.core1.nrn_x_AMZI_tbuf[5].y c.c1_syn_mon_AMZI[8] c.c1_nrn_mon_AMZI[92] c.c2_syn_mon_AMZI[41] c.c2_syn_mon_AMZI[60] c.c2_syn_mon_AMZI[24] c.c1_syn_mon_AMZI[46] c.c1_nrn_mon_AMZI[39] c.c2_syn_mon_AMZI[66] c.c2_nrn_mon_AMZI[58] c.c1_nrn_mon_AMZI[69] c.c1_nrn_mon_AMZI[10] c.c2_syn_mon_AMZI[45] c.c1_nrn_mon_AMZI[73] c.c2_nrn_mon_AMZI[3] c.c2_nrn_mon_AMZI[23] c.c1_nrn_mon_AMZI[5] c.c1_nrn_mon_AMZO[0] c.c1_nrn_mon_AMZI[51] c.c1_syn_mon_AMZI[36] c.c1_nrn_mon_AMZI[104] c.c2_syn_mon_AMZI[4] c.c2_nrn_mon_AMZI[22] c.c.core1.nrn_mon_AMZO_sb.sb[6].buf12._y c.c1_syn_mon_AMZI[48] c.c1_nrn_mon_AMZI[78] c.c1_nrn_mon_AMZI[98] c.c2_nrn_mon_AMZI[20] c.c2_nrn_mon_AMZI[12] c.c2_nrn_mon_AMZI[77] c.c2_syn_mon_AMZI[58] c.c2_nrn_mon_AMZI[48] c.c2_nrn_mon_AMZI[104] c.c1_syn_mon_AMZI[17] c.c1_syn_mon_AMZI[15] c.c2_syn_mon_AMZI[54] c.c1_nrn_mon_AMZI[1] c.c1_syn_mon_AMZI[64] c.c2_nrn_mon_AMZI[11] c.c2_syn_mon_AMZI[32] c.c.core2.nrn_x_AMZI_tbuf[3].y c.c2_nrn_mon_AMZI[101] c.c2_nrn_mon_AMZI[29] c.c.core1.syn_x_AMZI_tbuf[4].y c.c2_syn_mon_AMZI[19] c.c2_syn_mon_AMZI[65] c.c2_nrn_mon_AMZI[8] c.c1_syn_mon_AMZI[21] c.c2_nrn_mon_AMZI[93] c.c2_nrn_mon_AMZI[39] c.c.core1.nrn_mon_AMZO_sb.sb[4].buf12._y c.c2_nrn_mon_AMZI[97] c.c2_syn_mon_AMZI[70] c.c1_nrn_mon_AMZI[41] c.c2_nrn_mon_AMZI[68] c.c1_nrn_mon_AMZI[40] c.c1_nrn_mon_AMZI[11] c.c2_nrn_mon_AMZI[50] c.c1_nrn_mon_AMZI[44] c.c1_nrn_mon_AMZI[13] c.c1_nrn_mon_AMZI[38] c.c2_nrn_mon_AMZI[69] c.c1_syn_mon_AMZI[31] c.c.core2.syn_mon_AMZO_sb.sb[1].buf12._y c.c1_nrn_mon_AMZI[54] c.c2_nrn_mon_AMZI[16] c.c1_nrn_mon_AMZI[6] c.c1_nrn_mon_AMZI[84] c.c2_syn_mon_AMZI[43] c.c2_syn_mon_AMZI[52] c.c2_syn_mon_AMZI[2] c.c1_nrn_mon_AMZI[37] c.c2_syn_mon_AMZO[1] c.c1_syn_mon_AMZI[49] c.c1_syn_mon_AMZI[47] c.c1_nrn_mon_AMZI[65] c.c1_nrn_mon_AMZI[35] c.c1_nrn_mon_AMZI[95] c.c2_syn_mon_Line truncated
|
||||
[] Writing 30 to core 1 address 2
|
||||
[] Removing input
|
||||
[] Reading core 1 address 2
|
||||
[] Removing input
|
||||
[] Receiving output 30 from core 1 register 2
|
||||
[] Writing 6408920 to core 0 address 0
|
||||
[] Removing input
|
||||
[] Writing 3765103 to core 0 address 1
|
||||
[] Removing input
|
||||
[] Writing 1599066 to core 0 address 2
|
||||
[] Removing input
|
||||
[] Writing 6209994 to core 0 address 3
|
||||
[] Removing input
|
||||
[] Writing 3869017 to core 0 address 4
|
||||
[] Removing input
|
||||
[] Writing 4194016 to core 0 address 5
|
||||
[] Removing input
|
||||
[] Writing 4328621 to core 0 address 6
|
||||
[] Removing input
|
||||
[] Writing 1261935 to core 0 address 7
|
||||
[] Removing input
|
||||
[] Writing 2000611 to core 0 address 8
|
||||
[] Removing input
|
||||
[] Writing 3302177 to core 0 address 9
|
||||
[] Removing input
|
||||
[] Writing 1844302 to core 0 address 10
|
||||
[] Removing input
|
||||
[] Writing 1045614 to core 0 address 11
|
||||
[] Removing input
|
||||
[] Writing 2086984 to core 0 address 12
|
||||
[] Removing input
|
||||
[] Writing 6215204 to core 0 address 13
|
||||
[] Removing input
|
||||
[] Writing 299518 to core 0 address 14
|
||||
[] Removing input
|
||||
[] Writing 6307472 to core 0 address 15
|
||||
[] Removing input
|
||||
[] Writing 4523524 to core 0 address 16
|
||||
[] Removing input
|
||||
[] Writing 7832943 to core 0 address 17
|
||||
[] Removing input
|
||||
[] Writing 6747353 to core 0 address 18
|
||||
[] Removing input
|
||||
[] Writing 524742 to core 0 address 19
|
||||
[] Removing input
|
||||
[] Writing 3424695 to core 0 address 20
|
||||
[] Removing input
|
||||
[] Writing 4441827 to core 0 address 21
|
||||
[] Removing input
|
||||
[] Writing 94091 to core 0 address 22
|
||||
[] Removing input
|
||||
[] Writing 5799164 to core 0 address 23
|
||||
[] Removing input
|
||||
[] Writing 3352912 to core 0 address 24
|
||||
[] Removing input
|
||||
[] Writing 6181841 to core 0 address 25
|
||||
[] Removing input
|
||||
[] Writing 5915273 to core 0 address 26
|
||||
[] Removing input
|
||||
[] Writing 7910415 to core 0 address 27
|
||||
[] Removing input
|
||||
[] Writing 5461476 to core 0 address 28
|
||||
[] Removing input
|
||||
[] Writing 6198901 to core 0 address 29
|
||||
[] Removing input
|
||||
[] Writing 2681558 to core 0 address 30
|
||||
[] Removing input
|
||||
[] Writing 2011100 to core 0 address 31
|
||||
[] Removing input
|
||||
[] Writing 1766022 to core 0 address 32
|
||||
[] Removing input
|
||||
[] Writing 4777116 to core 0 address 33
|
||||
[] Removing input
|
||||
[] Writing 7332919 to core 0 address 34
|
||||
[] Removing input
|
||||
[] Writing 7881362 to core 0 address 35
|
||||
[] Removing input
|
||||
[] Writing 3352305 to core 0 address 36
|
||||
[] Removing input
|
||||
[] Writing 708607 to core 0 address 37
|
||||
[] Removing input
|
||||
[] Writing 7852776 to core 0 address 38
|
||||
[] Removing input
|
||||
[] Writing 4654042 to core 0 address 39
|
||||
[] Removing input
|
||||
[] Writing 8047941 to core 0 address 40
|
||||
[] Removing input
|
||||
[] Writing 2356710 to core 0 address 41
|
||||
[] Removing input
|
||||
[] Writing 1490805 to core 0 address 42
|
||||
[] Removing input
|
||||
[] Writing 5840107 to core 0 address 43
|
||||
[] Removing input
|
||||
[] Writing 4612067 to core 0 address 44
|
||||
[] Removing input
|
||||
[] Writing 2356890 to core 0 address 45
|
||||
[] Removing input
|
||||
[] Writing 4150607 to core 0 address 46
|
||||
[] Removing input
|
||||
[] Writing 3677767 to core 0 address 47
|
||||
[] Removing input
|
||||
[] Writing 5610065 to core 0 address 48
|
||||
[] Removing input
|
||||
[] Writing 2716239 to core 0 address 49
|
||||
[] Removing input
|
||||
[] Writing 5394492 to core 0 address 50
|
||||
[] Removing input
|
||||
[] Writing 4937489 to core 0 address 51
|
||||
[] Removing input
|
||||
[] Writing 4304831 to core 0 address 52
|
||||
[] Removing input
|
||||
[] Writing 8092217 to core 0 address 53
|
||||
[] Removing input
|
||||
[] Writing 1796782 to core 0 address 54
|
||||
[] Removing input
|
||||
[] Writing 3704126 to core 0 address 55
|
||||
[] Removing input
|
||||
[] Writing 7019592 to core 0 address 56
|
||||
[] Removing input
|
||||
[] Writing 7008470 to core 0 address 57
|
||||
[] Removing input
|
||||
[] Writing 2845373 to core 0 address 58
|
||||
[] Removing input
|
||||
[] Writing 356722 to core 0 address 59
|
||||
[] Removing input
|
||||
[] Writing 276406 to core 0 address 60
|
||||
[] Removing input
|
||||
[] Writing 1238748 to core 0 address 61
|
||||
[] Removing input
|
||||
[] Writing 4618950 to core 0 address 62
|
||||
[] Removing input
|
||||
[] Writing 7728738 to core 0 address 63
|
||||
[] Removing input
|
||||
[] Writing 1504173 to core 1 address 0
|
||||
[] Removing input
|
||||
[] Writing 1021893 to core 1 address 1
|
||||
[] Removing input
|
||||
[] Writing 7109610 to core 1 address 2
|
||||
[] Removing input
|
||||
[] Writing 6937942 to core 1 address 3
|
||||
[] Removing input
|
||||
[] Writing 1852966 to core 1 address 4
|
||||
[] Removing input
|
||||
[] Writing 8349090 to core 1 address 5
|
||||
[] Removing input
|
||||
[] Writing 1472410 to core 1 address 6
|
||||
[] Removing input
|
||||
[] Writing 1733791 to core 1 address 7
|
||||
[] Removing input
|
||||
[] Writing 279622 to core 1 address 8
|
||||
[] Removing input
|
||||
[] Writing 4203827 to core 1 address 9
|
||||
[] Removing input
|
||||
[] Writing 7147640 to core 1 address 10
|
||||
[] Removing input
|
||||
[] Writing 2315900 to core 1 address 11
|
||||
[] Removing input
|
||||
[] Writing 5885805 to core 1 address 12
|
||||
[] Removing input
|
||||
[] Writing 5676797 to core 1 address 13
|
||||
[] Removing input
|
||||
[] Writing 3693747 to core 1 address 14
|
||||
[] Removing input
|
||||
[] Writing 1619171 to core 1 address 15
|
||||
[] Removing input
|
||||
[] Writing 3919645 to core 1 address 16
|
||||
[] Removing input
|
||||
[] Writing 1708825 to core 1 address 17
|
||||
[] Removing input
|
||||
[] Writing 2975396 to core 1 address 18
|
||||
[] Removing input
|
||||
[] Writing 753463 to core 1 address 19
|
||||
[] Removing input
|
||||
[] Writing 6866223 to core 1 address 20
|
||||
[] Removing input
|
||||
[] Writing 1508957 to core 1 address 21
|
||||
[] Removing input
|
||||
[] Writing 6659664 to core 1 address 22
|
||||
[] Removing input
|
||||
[] Writing 6874607 to core 1 address 23
|
||||
[] Removing input
|
||||
[] Writing 5711803 to core 1 address 24
|
||||
[] Removing input
|
||||
[] Writing 5145132 to core 1 address 25
|
||||
[] Removing input
|
||||
[] Writing 190818 to core 1 address 26
|
||||
[] Removing input
|
||||
[] Writing 7760922 to core 1 address 27
|
||||
[] Removing input
|
||||
[] Writing 5670224 to core 1 address 28
|
||||
[] Removing input
|
||||
[] Writing 1313371 to core 1 address 29
|
||||
[] Removing input
|
||||
[] Writing 1161556 to core 1 address 30
|
||||
[] Removing input
|
||||
[] Writing 8366148 to core 1 address 31
|
||||
[] Removing input
|
||||
[] Writing 6860350 to core 1 address 32
|
||||
[] Removing input
|
||||
[] Writing 88361 to core 1 address 33
|
||||
[] Removing input
|
||||
[] Writing 5554412 to core 1 address 34
|
||||
[] Removing input
|
||||
[] Writing 3327330 to core 1 address 35
|
||||
[] Removing input
|
||||
[] Writing 2792301 to core 1 address 36
|
||||
[] Removing input
|
||||
[] Writing 7291409 to core 1 address 37
|
||||
[] Removing input
|
||||
[] Writing 5442962 to core 1 address 38
|
||||
[] Removing input
|
||||
[] Writing 3090484 to core 1 address 39
|
||||
[] Removing input
|
||||
[] Writing 3677305 to core 1 address 40
|
||||
[] Removing input
|
||||
[] Writing 1931800 to core 1 address 41
|
||||
[] Removing input
|
||||
[] Writing 4647837 to core 1 address 42
|
||||
[] Removing input
|
||||
[] Writing 2748771 to core 1 address 43
|
||||
[] Removing input
|
||||
[] Writing 1853701 to core 1 address 44
|
||||
[] Removing input
|
||||
[] Writing 7542420 to core 1 address 45
|
||||
[] Removing input
|
||||
[] Writing 4701564 to core 1 address 46
|
||||
[] Removing input
|
||||
[] Writing 7150520 to core 1 address 47
|
||||
[] Removing input
|
||||
[] Writing 2436447 to core 1 address 48
|
||||
[] Removing input
|
||||
[] Writing 2974030 to core 1 address 49
|
||||
[] Removing input
|
||||
[] Writing 2999015 to core 1 address 50
|
||||
[] Removing input
|
||||
[] Writing 6741461 to core 1 address 51
|
||||
[] Removing input
|
||||
[] Writing 6473162 to core 1 address 52
|
||||
[] Removing input
|
||||
[] Writing 1045613 to core 1 address 53
|
||||
[] Removing input
|
||||
[] Writing 3002225 to core 1 address 54
|
||||
[] Removing input
|
||||
[] Writing 5399719 to core 1 address 55
|
||||
[] Removing input
|
||||
[] Writing 559188 to core 1 address 56
|
||||
[] Removing input
|
||||
[] Writing 3622321 to core 1 address 57
|
||||
[] Removing input
|
||||
[] Writing 2330967 to core 1 address 58
|
||||
[] Removing input
|
||||
[] Writing 1861155 to core 1 address 59
|
||||
[] Removing input
|
||||
[] Writing 5442382 to core 1 address 60
|
||||
[] Removing input
|
||||
[] Writing 8112402 to core 1 address 61
|
||||
[] Removing input
|
||||
[] Writing 3261765 to core 1 address 62
|
||||
[] Removing input
|
||||
[] Writing 7896780 to core 1 address 63
|
||||
[] Removing input
|
||||
[] Reading core 0 address 0
|
||||
[] Removing input
|
||||
[] Receiving output 6408920 from core 0 register 0
|
||||
[] Reading core 0 address 1
|
||||
[] Removing input
|
||||
[] Receiving output 3765103 from core 0 register 1
|
||||
[] Reading core 0 address 2
|
||||
[] Removing input
|
||||
[] Receiving output 1599066 from core 0 register 2
|
||||
[] Reading core 0 address 3
|
||||
[] Removing input
|
||||
[] Receiving output 6209994 from core 0 register 3
|
||||
[] Reading core 0 address 4
|
||||
[] Removing input
|
||||
[] Receiving output 3869017 from core 0 register 4
|
||||
[] Reading core 0 address 5
|
||||
[] Removing input
|
||||
[] Receiving output 4194016 from core 0 register 5
|
||||
[] Reading core 0 address 6
|
||||
[] Removing input
|
||||
[] Receiving output 4328621 from core 0 register 6
|
||||
[] Reading core 0 address 7
|
||||
[] Removing input
|
||||
[] Receiving output 1261935 from core 0 register 7
|
||||
[] Reading core 0 address 8
|
||||
[] Removing input
|
||||
[] Receiving output 2000611 from core 0 register 8
|
||||
[] Reading core 0 address 9
|
||||
[] Removing input
|
||||
[] Receiving output 3302177 from core 0 register 9
|
||||
[] Reading core 0 address 10
|
||||
[] Removing input
|
||||
[] Receiving output 1844302 from core 0 register 10
|
||||
[] Reading core 0 address 11
|
||||
[] Removing input
|
||||
[] Receiving output 1045614 from core 0 register 11
|
||||
[] Reading core 0 address 12
|
||||
[] Removing input
|
||||
[] Receiving output 2086984 from core 0 register 12
|
||||
[] Reading core 0 address 13
|
||||
[] Removing input
|
||||
[] Receiving output 6215204 from core 0 register 13
|
||||
[] Reading core 0 address 14
|
||||
[] Removing input
|
||||
[] Receiving output 299518 from core 0 register 14
|
||||
[] Reading core 0 address 15
|
||||
[] Removing input
|
||||
[] Receiving output 6307472 from core 0 register 15
|
||||
[] Reading core 0 address 16
|
||||
[] Removing input
|
||||
[] Receiving output 4523524 from core 0 register 16
|
||||
[] Reading core 0 address 17
|
||||
[] Removing input
|
||||
[] Receiving output 7832943 from core 0 register 17
|
||||
[] Reading core 0 address 18
|
||||
[] Removing input
|
||||
[] Receiving output 6747353 from core 0 register 18
|
||||
[] Reading core 0 address 19
|
||||
[] Removing input
|
||||
[] Receiving output 524742 from core 0 register 19
|
||||
[] Reading core 0 address 20
|
||||
[] Removing input
|
||||
[] Receiving output 3424695 from core 0 register 20
|
||||
[] Reading core 0 address 21
|
||||
[] Removing input
|
||||
[] Receiving output 4441827 from core 0 register 21
|
||||
[] Reading core 0 address 22
|
||||
[] Removing input
|
||||
[] Receiving output 94091 from core 0 register 22
|
||||
[] Reading core 0 address 23
|
||||
[] Removing input
|
||||
[] Receiving output 5799164 from core 0 register 23
|
||||
[] Reading core 0 address 24
|
||||
[] Removing input
|
||||
[] Receiving output 3352912 from core 0 register 24
|
||||
[] Reading core 0 address 25
|
||||
[] Removing input
|
||||
[] Receiving output 6181841 from core 0 register 25
|
||||
[] Reading core 0 address 26
|
||||
[] Removing input
|
||||
[] Receiving output 5915273 from core 0 register 26
|
||||
[] Reading core 0 address 27
|
||||
[] Removing input
|
||||
[] Receiving output 7910415 from core 0 register 27
|
||||
[] Reading core 0 address 28
|
||||
[] Removing input
|
||||
[] Receiving output 5461476 from core 0 register 28
|
||||
[] Reading core 0 address 29
|
||||
[] Removing input
|
||||
[] Receiving output 6198901 from core 0 register 29
|
||||
[] Reading core 0 address 30
|
||||
[] Removing input
|
||||
[] Receiving output 2681558 from core 0 register 30
|
||||
[] Reading core 0 address 31
|
||||
[] Removing input
|
||||
[] Receiving output 2011100 from core 0 register 31
|
||||
[] Reading core 0 address 32
|
||||
[] Removing input
|
||||
[] Receiving output 1766022 from core 0 register 32
|
||||
[] Reading core 0 address 33
|
||||
[] Removing input
|
||||
[] Receiving output 4777116 from core 0 register 33
|
||||
[] Reading core 0 address 34
|
||||
[] Removing input
|
||||
[] Receiving output 7332919 from core 0 register 34
|
||||
[] Reading core 0 address 35
|
||||
[] Removing input
|
||||
[] Receiving output 7881362 from core 0 register 35
|
||||
[] Reading core 0 address 36
|
||||
[] Removing input
|
||||
[] Receiving output 3352305 from core 0 register 36
|
||||
[] Reading core 0 address 37
|
||||
[] Removing input
|
||||
[] Receiving output 708607 from core 0 register 37
|
||||
[] Reading core 0 address 38
|
||||
[] Removing input
|
||||
[] Receiving output 7852776 from core 0 register 38
|
||||
[] Reading core 0 address 39
|
||||
[] Removing input
|
||||
[] Receiving output 4654042 from core 0 register 39
|
||||
[] Reading core 0 address 40
|
||||
[] Removing input
|
||||
[] Receiving output 8047941 from core 0 register 40
|
||||
[] Reading core 0 address 41
|
||||
[] Removing input
|
||||
[] Receiving output 2356710 from core 0 register 41
|
||||
[] Reading core 0 address 42
|
||||
[] Removing input
|
||||
[] Receiving output 1490805 from core 0 register 42
|
||||
[] Reading core 0 address 43
|
||||
[] Removing input
|
||||
[] Receiving output 5840107 from core 0 register 43
|
||||
[] Reading core 0 address 44
|
||||
[] Removing input
|
||||
[] Receiving output 4612067 from core 0 register 44
|
||||
[] Reading core 0 address 45
|
||||
[] Removing input
|
||||
[] Receiving output 2356890 from core 0 register 45
|
||||
[] Reading core 0 address 46
|
||||
[] Removing input
|
||||
[] Receiving output 4150607 from core 0 register 46
|
||||
[] Reading core 0 address 47
|
||||
[] Removing input
|
||||
[] Receiving output 3677767 from core 0 register 47
|
||||
[] Reading core 0 address 48
|
||||
[] Removing input
|
||||
[] Receiving output 5610065 from core 0 register 48
|
||||
[] Reading core 0 address 49
|
||||
[] Removing input
|
||||
[] Receiving output 2716239 from core 0 register 49
|
||||
[] Reading core 0 address 50
|
||||
[] Removing input
|
||||
[] Receiving output 5394492 from core 0 register 50
|
||||
[] Reading core 0 address 51
|
||||
[] Removing input
|
||||
[] Receiving output 4937489 from core 0 register 51
|
||||
[] Reading core 0 address 52
|
||||
[] Removing input
|
||||
[] Receiving output 4304831 from core 0 register 52
|
||||
[] Reading core 0 address 53
|
||||
[] Removing input
|
||||
[] Receiving output 8092217 from core 0 register 53
|
||||
[] Reading core 0 address 54
|
||||
[] Removing input
|
||||
[] Receiving output 1796782 from core 0 register 54
|
||||
[] Reading core 0 address 55
|
||||
[] Removing input
|
||||
[] Receiving output 3704126 from core 0 register 55
|
||||
[] Reading core 0 address 56
|
||||
[] Removing input
|
||||
[] Receiving output 7019592 from core 0 register 56
|
||||
[] Reading core 0 address 57
|
||||
[] Removing input
|
||||
[] Receiving output 7008470 from core 0 register 57
|
||||
[] Reading core 0 address 58
|
||||
[] Removing input
|
||||
[] Receiving output 2845373 from core 0 register 58
|
||||
[] Reading core 0 address 59
|
||||
[] Removing input
|
||||
[] Receiving output 356722 from core 0 register 59
|
||||
[] Reading core 0 address 60
|
||||
[] Removing input
|
||||
[] Receiving output 276406 from core 0 register 60
|
||||
[] Reading core 0 address 61
|
||||
[] Removing input
|
||||
[] Receiving output 1238748 from core 0 register 61
|
||||
[] Reading core 0 address 62
|
||||
[] Removing input
|
||||
[] Receiving output 4618950 from core 0 register 62
|
||||
[] Reading core 0 address 63
|
||||
[] Removing input
|
||||
[] Receiving output 7728738 from core 0 register 63
|
||||
[] Reading core 1 address 0
|
||||
[] Removing input
|
||||
[] Receiving output 1504173 from core 1 register 0
|
||||
[] Reading core 1 address 1
|
||||
[] Removing input
|
||||
[] Receiving output 1021893 from core 1 register 1
|
||||
[] Reading core 1 address 2
|
||||
[] Removing input
|
||||
[] Receiving output 7109610 from core 1 register 2
|
||||
[] Reading core 1 address 3
|
||||
[] Removing input
|
||||
[] Receiving output 6937942 from core 1 register 3
|
||||
[] Reading core 1 address 4
|
||||
[] Removing input
|
||||
[] Receiving output 1852966 from core 1 register 4
|
||||
[] Reading core 1 address 5
|
||||
[] Removing input
|
||||
[] Receiving output 8349090 from core 1 register 5
|
||||
[] Reading core 1 address 6
|
||||
[] Removing input
|
||||
[] Receiving output 1472410 from core 1 register 6
|
||||
[] Reading core 1 address 7
|
||||
[] Removing input
|
||||
[] Receiving output 1733791 from core 1 register 7
|
||||
[] Reading core 1 address 8
|
||||
[] Removing input
|
||||
[] Receiving output 279622 from core 1 register 8
|
||||
[] Reading core 1 address 9
|
||||
[] Removing input
|
||||
[] Receiving output 4203827 from core 1 register 9
|
||||
[] Reading core 1 address 10
|
||||
[] Removing input
|
||||
[] Receiving output 7147640 from core 1 register 10
|
||||
[] Reading core 1 address 11
|
||||
[] Removing input
|
||||
[] Receiving output 2315900 from core 1 register 11
|
||||
[] Reading core 1 address 12
|
||||
[] Removing input
|
||||
[] Receiving output 5885805 from core 1 register 12
|
||||
[] Reading core 1 address 13
|
||||
[] Removing input
|
||||
[] Receiving output 5676797 from core 1 register 13
|
||||
[] Reading core 1 address 14
|
||||
[] Removing input
|
||||
[] Receiving output 3693747 from core 1 register 14
|
||||
[] Reading core 1 address 15
|
||||
[] Removing input
|
||||
[] Receiving output 1619171 from core 1 register 15
|
||||
[] Reading core 1 address 16
|
||||
[] Removing input
|
||||
[] Receiving output 3919645 from core 1 register 16
|
||||
[] Reading core 1 address 17
|
||||
[] Removing input
|
||||
[] Receiving output 1708825 from core 1 register 17
|
||||
[] Reading core 1 address 18
|
||||
[] Removing input
|
||||
[] Receiving output 2975396 from core 1 register 18
|
||||
[] Reading core 1 address 19
|
||||
[] Removing input
|
||||
[] Receiving output 753463 from core 1 register 19
|
||||
[] Reading core 1 address 20
|
||||
[] Removing input
|
||||
[] Receiving output 6866223 from core 1 register 20
|
||||
[] Reading core 1 address 21
|
||||
[] Removing input
|
||||
[] Receiving output 1508957 from core 1 register 21
|
||||
[] Reading core 1 address 22
|
||||
[] Removing input
|
||||
[] Receiving output 6659664 from core 1 register 22
|
||||
[] Reading core 1 address 23
|
||||
[] Removing input
|
||||
[] Receiving output 6874607 from core 1 register 23
|
||||
[] Reading core 1 address 24
|
||||
[] Removing input
|
||||
[] Receiving output 5711803 from core 1 register 24
|
||||
[] Reading core 1 address 25
|
||||
[] Removing input
|
||||
[] Receiving output 5145132 from core 1 register 25
|
||||
[] Reading core 1 address 26
|
||||
[] Removing input
|
||||
[] Receiving output 190818 from core 1 register 26
|
||||
[] Reading core 1 address 27
|
||||
[] Removing input
|
||||
[] Receiving output 7760922 from core 1 register 27
|
||||
[] Reading core 1 address 28
|
||||
[] Removing input
|
||||
[] Receiving output 5670224 from core 1 register 28
|
||||
[] Reading core 1 address 29
|
||||
[] Removing input
|
||||
[] Receiving output 1313371 from core 1 register 29
|
||||
[] Reading core 1 address 30
|
||||
[] Removing input
|
||||
[] Receiving output 1161556 from core 1 register 30
|
||||
[] Reading core 1 address 31
|
||||
[] Removing input
|
||||
[] Receiving output 8366148 from core 1 register 31
|
||||
[] Reading core 1 address 32
|
||||
[] Removing input
|
||||
[] Receiving output 6860350 from core 1 register 32
|
||||
[] Reading core 1 address 33
|
||||
[] Removing input
|
||||
[] Receiving output 88361 from core 1 register 33
|
||||
[] Reading core 1 address 34
|
||||
[] Removing input
|
||||
[] Receiving output 5554412 from core 1 register 34
|
||||
[] Reading core 1 address 35
|
||||
[] Removing input
|
||||
[] Receiving output 3327330 from core 1 register 35
|
||||
[] Reading core 1 address 36
|
||||
[] Removing input
|
||||
[] Receiving output 2792301 from core 1 register 36
|
||||
[] Reading core 1 address 37
|
||||
[] Removing input
|
||||
[] Receiving output 7291409 from core 1 register 37
|
||||
[] Reading core 1 address 38
|
||||
[] Removing input
|
||||
[] Receiving output 5442962 from core 1 register 38
|
||||
[] Reading core 1 address 39
|
||||
[] Removing input
|
||||
[] Receiving output 3090484 from core 1 register 39
|
||||
[] Reading core 1 address 40
|
||||
[] Removing input
|
||||
[] Receiving output 3677305 from core 1 register 40
|
||||
[] Reading core 1 address 41
|
||||
[] Removing input
|
||||
[] Receiving output 1931800 from core 1 register 41
|
||||
[] Reading core 1 address 42
|
||||
[] Removing input
|
||||
[] Receiving output 4647837 from core 1 register 42
|
||||
[] Reading core 1 address 43
|
||||
[] Removing input
|
||||
[] Receiving output 2748771 from core 1 register 43
|
||||
[] Reading core 1 address 44
|
||||
[] Removing input
|
||||
[] Receiving output 1853701 from core 1 register 44
|
||||
[] Reading core 1 address 45
|
||||
[] Removing input
|
||||
[] Receiving output 7542420 from core 1 register 45
|
||||
[] Reading core 1 address 46
|
||||
[] Removing input
|
||||
[] Receiving output 4701564 from core 1 register 46
|
||||
[] Reading core 1 address 47
|
||||
[] Removing input
|
||||
[] Receiving output 7150520 from core 1 register 47
|
||||
[] Reading core 1 address 48
|
||||
[] Removing input
|
||||
[] Receiving output 2436447 from core 1 register 48
|
||||
[] Reading core 1 address 49
|
||||
[] Removing input
|
||||
[] Receiving output 2974030 from core 1 register 49
|
||||
[] Reading core 1 address 50
|
||||
[] Removing input
|
||||
[] Receiving output 2999015 from core 1 register 50
|
||||
[] Reading core 1 address 51
|
||||
[] Removing input
|
||||
[] Receiving output 6741461 from core 1 register 51
|
||||
[] Reading core 1 address 52
|
||||
[] Removing input
|
||||
[] Receiving output 6473162 from core 1 register 52
|
||||
[] Reading core 1 address 53
|
||||
[] Removing input
|
||||
[] Receiving output 1045613 from core 1 register 53
|
||||
[] Reading core 1 address 54
|
||||
[] Removing input
|
||||
[] Receiving output 3002225 from core 1 register 54
|
||||
[] Reading core 1 address 55
|
||||
[] Removing input
|
||||
[] Receiving output 5399719 from core 1 register 55
|
||||
[] Reading core 1 address 56
|
||||
[] Removing input
|
||||
[] Receiving output 559188 from core 1 register 56
|
||||
[] Reading core 1 address 57
|
||||
[] Removing input
|
||||
[] Receiving output 3622321 from core 1 register 57
|
||||
[] Reading core 1 address 58
|
||||
[] Removing input
|
||||
[] Receiving output 2330967 from core 1 register 58
|
||||
[] Reading core 1 address 59
|
||||
[] Removing input
|
||||
[] Receiving output 1861155 from core 1 register 59
|
||||
[] Reading core 1 address 60
|
||||
[] Removing input
|
||||
[] Receiving output 5442382 from core 1 register 60
|
||||
[] Reading core 1 address 61
|
||||
[] Removing input
|
||||
[] Receiving output 8112402 from core 1 register 61
|
||||
[] Reading core 1 address 62
|
||||
[] Removing input
|
||||
[] Receiving output 3261765 from core 1 register 62
|
||||
[] Reading core 1 address 63
|
||||
[] Removing input
|
||||
[] Receiving output 7896780 from core 1 register 63
|
||||
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,164 @@
|
||||
/*************************************************************************
|
||||
*
|
||||
* This file is part of ACT dataflow neuro library.
|
||||
* It's the testing facility for cell_lib_std.act
|
||||
*
|
||||
* Copyright (c) 2022 University of Groningen - Ole Richter
|
||||
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
|
||||
* Copyright (c) 2022 University of Groningen - Michele Mastella
|
||||
* Copyright (c) 2022 University of Groningen - Madison Cotteret
|
||||
*
|
||||
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
|
||||
*
|
||||
* You may redistribute and modify this documentation and make products
|
||||
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
|
||||
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
|
||||
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
|
||||
* for applicable conditions.
|
||||
*
|
||||
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
|
||||
*
|
||||
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
|
||||
* these sources, You must maintain the Source Location visible in its
|
||||
* documentation.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
import "../../dataflow_neuro/coders.act";
|
||||
import "../../dataflow_neuro/primitives.act";
|
||||
import "../../dataflow_neuro/chips.act";
|
||||
|
||||
import globals;
|
||||
import std::data;
|
||||
|
||||
open std::data;
|
||||
|
||||
|
||||
open tmpl::dataflow_neuro;
|
||||
|
||||
|
||||
|
||||
pint N_IN = 32;
|
||||
|
||||
pint N_NRN_X = 15;
|
||||
pint N_NRN_Y = 6;
|
||||
pint NC_NRN_X = 4;
|
||||
pint NC_NRN_Y = 3;
|
||||
|
||||
// pint N_SYN_X = 15;
|
||||
// pint N_SYN_Y = 348;
|
||||
// pint NC_SYN_X = 6;
|
||||
// pint NC_SYN_Y = 9;
|
||||
pint N_SYN_X = 15;
|
||||
pint N_SYN_Y = 6;
|
||||
pint NC_SYN_X = 4;
|
||||
pint NC_SYN_Y = 3;
|
||||
|
||||
pint N_SYN_DLY_CFG = 4;
|
||||
pint N_BD_DLY_CFG = 4;
|
||||
pint N_BD_DLY_CFG2 = 2;
|
||||
|
||||
pint N_NRN_MON_X = N_NRN_X*2; // [mon,kill]*N
|
||||
pint N_NRN_MON_Y = N_NRN_Y; // [mon]*N
|
||||
|
||||
pint N_SYN_MON_X = N_SYN_X*4; // [mon, dev_mon, set, reset]*N
|
||||
pint N_SYN_MON_Y = N_SYN_Y; // [mon]*N
|
||||
|
||||
pint N_MON_AMZO_PER_SYN = 5;
|
||||
pint N_MON_AMZO_PER_NRN = 7;
|
||||
|
||||
pint N_FLAGS_PER_SYN = 3; // Syn: Must be at least 3 (since those ones have special safety)
|
||||
pint N_FLAGS_PER_NRN = 9; // and leq than the number of bits in a reg, since have presumed only needs one.
|
||||
|
||||
pint N_BUFFERS = 3;
|
||||
|
||||
pint N_LINE_PD_DLY = 3;
|
||||
|
||||
pint REG_NCA = 6;
|
||||
pint REG_M = 1<<REG_NCA;
|
||||
pint REG_NCW = 23;
|
||||
|
||||
|
||||
defproc chip_texel_dualcore (bd<N_IN> in, out;
|
||||
|
||||
Mx1of2<REG_NCW> c1_reg_data[REG_M];
|
||||
// a1of1 c1_synapses[N_SYN_X * N_SYN_Y];
|
||||
// a1of1 c1_neurons[N_NRN_X * N_NRN_Y];
|
||||
bool! c1_syn_r[N_SYN_X * N_SYN_Y];
|
||||
bool? c1_syn_a[N_SYN_X * N_SYN_Y];
|
||||
bool? c1_nrn_r[N_NRN_X * N_NRN_Y];
|
||||
bool! c1_nrn_a[N_NRN_X * N_NRN_Y];
|
||||
|
||||
bool! c1_nrn_mon_x[N_NRN_MON_X], c1_nrn_mon_y[N_NRN_MON_Y];
|
||||
bool! c1_syn_mon_x[N_SYN_MON_X], c1_syn_mon_y[N_SYN_MON_Y];
|
||||
bool? c1_syn_mon_AMZI[N_SYN_X * N_MON_AMZO_PER_SYN], c1_nrn_mon_AMZI[N_NRN_X * N_MON_AMZO_PER_NRN];
|
||||
bool! c1_syn_mon_AMZO[N_MON_AMZO_PER_SYN], c1_nrn_mon_AMZO[N_MON_AMZO_PER_NRN];
|
||||
bool! c1_syn_flags_EFO[N_FLAGS_PER_SYN], c1_nrn_flags_EFO[N_FLAGS_PER_NRN];
|
||||
|
||||
Mx1of2<REG_NCW> c2_reg_data[REG_M];
|
||||
// a1of1 c2_synapses[N_SYN_X * N_SYN_Y];
|
||||
// a1of1 c2_neurons[N_NRN_X * N_NRN_Y];
|
||||
bool! c2_syn_r[N_SYN_X * N_SYN_Y];
|
||||
bool? c2_syn_a[N_SYN_X * N_SYN_Y];
|
||||
bool? c2_nrn_r[N_NRN_X * N_NRN_Y];
|
||||
bool! c2_nrn_a[N_NRN_X * N_NRN_Y];
|
||||
|
||||
bool! c2_nrn_mon_x[N_NRN_MON_X], c2_nrn_mon_y[N_NRN_MON_Y];
|
||||
bool! c2_syn_mon_x[N_SYN_MON_X], c2_syn_mon_y[N_SYN_MON_Y];
|
||||
bool? c2_syn_mon_AMZI[N_SYN_X * N_MON_AMZO_PER_SYN], c2_nrn_mon_AMZI[N_NRN_X * N_MON_AMZO_PER_NRN];
|
||||
bool! c2_syn_mon_AMZO[N_MON_AMZO_PER_SYN], c2_nrn_mon_AMZO[N_MON_AMZO_PER_NRN];
|
||||
bool! c2_syn_flags_EFO[N_FLAGS_PER_SYN], c2_nrn_flags_EFO[N_FLAGS_PER_NRN];
|
||||
|
||||
bool? bd_dly_cfg[N_BD_DLY_CFG], bd_dly_cfg2[N_BD_DLY_CFG2];
|
||||
bool? loopback_en){
|
||||
|
||||
bool _reset_B;
|
||||
prs {
|
||||
Reset => _reset_B-
|
||||
}
|
||||
power supply;
|
||||
supply.vdd = Vdd;
|
||||
supply.vss = GND;
|
||||
|
||||
|
||||
a1of1 c1_synapses[N_SYN_X * N_SYN_Y];
|
||||
a1of1 c1_neurons[N_NRN_X * N_NRN_Y];
|
||||
a1of1 c2_synapses[N_SYN_X * N_SYN_Y];
|
||||
a1of1 c2_neurons[N_NRN_X * N_NRN_Y];
|
||||
(i:N_SYN_X * N_SYN_Y:
|
||||
c1_synapses[i].r = c1_syn_r[i];
|
||||
c2_synapses[i].r = c2_syn_r[i];
|
||||
c1_synapses[i].a = c1_syn_a[i];
|
||||
c2_synapses[i].a = c2_syn_a[i];
|
||||
)
|
||||
(i:N_NRN_X * N_NRN_Y:
|
||||
c1_neurons[i].r = c1_nrn_r[i];
|
||||
c2_neurons[i].r = c2_nrn_r[i];
|
||||
c1_neurons[i].a = c1_nrn_a[i];
|
||||
c2_neurons[i].a = c2_nrn_a[i];
|
||||
)
|
||||
|
||||
|
||||
texel_dualcore<N_IN,
|
||||
N_NRN_X, N_NRN_Y, N_SYN_X, N_SYN_Y,
|
||||
NC_NRN_X, NC_NRN_Y, NC_SYN_X, NC_SYN_Y,
|
||||
N_SYN_DLY_CFG,
|
||||
N_NRN_MON_X, N_NRN_MON_Y, N_SYN_MON_X, N_SYN_MON_Y,
|
||||
N_MON_AMZO_PER_SYN, N_MON_AMZO_PER_NRN,
|
||||
N_FLAGS_PER_SYN, N_FLAGS_PER_NRN,
|
||||
N_BUFFERS,
|
||||
N_LINE_PD_DLY,
|
||||
N_BD_DLY_CFG, N_BD_DLY_CFG2,
|
||||
REG_NCA, REG_NCW, REG_M> c(.in = in, .out = out,
|
||||
.c1_reg_data = c1_reg_data, .c1_synapses = c1_synapses, .c1_neurons = c1_neurons, .c1_nrn_mon_x = c1_nrn_mon_x, .c1_nrn_mon_y = c1_nrn_mon_y, .c1_syn_mon_x = c1_syn_mon_x, .c1_syn_mon_y = c1_syn_mon_y, .c1_syn_mon_AMZI = c1_syn_mon_AMZI, .c1_nrn_mon_AMZI = c1_nrn_mon_AMZI, .c1_syn_mon_AMZO = c1_syn_mon_AMZO, .c1_nrn_mon_AMZO = c1_nrn_mon_AMZO, .c1_syn_flags_EFO = c1_syn_flags_EFO, .c1_nrn_flags_EFO = c1_nrn_flags_EFO, .c2_reg_data = c2_reg_data, .c2_synapses = c2_synapses, .c2_neurons = c2_neurons, .c2_nrn_mon_x = c2_nrn_mon_x, .c2_nrn_mon_y = c2_nrn_mon_y, .c2_syn_mon_x = c2_syn_mon_x, .c2_syn_mon_y = c2_syn_mon_y, .c2_syn_mon_AMZI = c2_syn_mon_AMZI, .c2_nrn_mon_AMZI = c2_nrn_mon_AMZI, .c2_syn_mon_AMZO = c2_syn_mon_AMZO, .c2_nrn_mon_AMZO = c2_nrn_mon_AMZO, .c2_syn_flags_EFO = c2_syn_flags_EFO, .c2_nrn_flags_EFO = c2_nrn_flags_EFO, .bd_dly_cfg = bd_dly_cfg, .bd_dly_cfg2 = bd_dly_cfg2,
|
||||
.loopback_en = loopback_en, .supply = supply, .reset_B = _reset_B);
|
||||
|
||||
|
||||
|
||||
}
|
||||
|
||||
|
||||
// fifo_decoder_neurons_encoder_fifo e;
|
||||
chip_texel_dualcore c;
|
||||
File diff suppressed because it is too large.
Load diff
Reference in new issue
Block a user