texel dualcore testing wip

dataflow_neuro/chips.act

@@ -120,7 +120,7 @@ defproc texel_core (avMx1of2<N_IN> in, out;
 
 
     // Output
-    fifo<N_IN, N_BUFFERS> fifo_mrg2bd(.in = merge_enc8reg.out, .out = out,
+    fifo<N_IN, N_BUFFERS> fifo_out(.in = merge_enc8reg.out, .out = out,
         .reset_B = _reset_BX, .supply = supply);
 
 
@@ -420,10 +420,13 @@ defproc texel_dualcore (bd<N_IN> in, out;
             .supply = supply
             );
 
+    fifo<N_IN-1,N_BUFFERS> fifo_core1out(.in = core1.out, .reset_B = _reset_BX, .supply = supply);
+    fifo<N_IN-1,N_BUFFERS> fifo_core2out(.in = core2.out, .reset_B = _reset_BX, .supply = supply);
+
    
     // Merge cores
-    append<N_IN-1, 1, 0> append_core1(.in = core1.out, .supply = supply);
+    append<N_IN-1, 1, 0> append_core1(.in = fifo_core1out.out, .supply = supply);
-    append<N_IN-1, 1, 1> append_core2(.in = core2.out, .supply = supply);
+    append<N_IN-1, 1, 1> append_core2(.in = fifo_core2out.out, .supply = supply);
     merge<N_IN> merge_core1x2(.in1 = append_core1.out, .in2 = append_core2.out,
         .supply = supply, .reset_B = _reset_BX);
 

test/unit_tests/texel_dualcore/test.act

@@ -0,0 +1,164 @@
+/*************************************************************************
+ *
+ *  This file is part of ACT dataflow neuro library.
+ * It's the testing facility for cell_lib_std.act
+ *
+ *  Copyright (c) 2022 University of Groningen - Ole Richter  
+ *  Copyright (c) 2022 University of Groningen - Hugh Greatorex
+ *  Copyright (c) 2022 University of Groningen - Michele Mastella
+ *  Copyright (c) 2022 University of Groningen - Madison Cotteret
+ *
+ *  This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
+ *
+ *  You may redistribute and modify this documentation and make products
+ *  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
+ *  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
+ *  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
+ *  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
+ *  for applicable conditions.
+ *
+ *  Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
+ *
+ *  As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
+ *  these sources, You must maintain the Source Location visible in its
+ *  documentation.
+ *
+ **************************************************************************
+ */
+
+import "../../dataflow_neuro/coders.act";
+import "../../dataflow_neuro/primitives.act";
+import "../../dataflow_neuro/chips.act";
+
+import globals;
+import std::data;
+
+open std::data;
+
+
+open tmpl::dataflow_neuro;
+
+
+
+pint N_IN = 32;
+
+pint N_NRN_X = 15;
+pint N_NRN_Y = 6;
+pint NC_NRN_X = 4;
+pint NC_NRN_Y = 3;
+
+// pint N_SYN_X = 15;
+// pint N_SYN_Y = 348;
+// pint NC_SYN_X = 6;
+// pint NC_SYN_Y = 9;
+pint N_SYN_X = 15;
+pint N_SYN_Y = 6;
+pint NC_SYN_X = 4;
+pint NC_SYN_Y = 3;
+
+pint N_SYN_DLY_CFG = 4;
+pint N_BD_DLY_CFG = 4;
+pint N_BD_DLY_CFG2 = 2;
+
+pint N_NRN_MON_X = N_NRN_X*2; // [mon,kill]*N
+pint N_NRN_MON_Y = N_NRN_Y; // [mon]*N
+
+pint N_SYN_MON_X = N_SYN_X*4; // [mon, dev_mon, set, reset]*N
+pint N_SYN_MON_Y = N_SYN_Y; //  [mon]*N
+
+pint N_MON_AMZO_PER_SYN = 5;
+pint N_MON_AMZO_PER_NRN = 7;
+
+pint N_FLAGS_PER_SYN = 3; // Syn: Must be at least 3 (since those ones have special safety)
+pint N_FLAGS_PER_NRN = 9; // and leq than the number of bits in a reg, since have presumed only needs one.
+
+pint N_BUFFERS = 3;
+
+pint N_LINE_PD_DLY = 3;
+
+pint REG_NCA = 6;
+pint REG_M = 1<<REG_NCA;
+pint REG_NCW = 23;
+
+
+defproc chip_texel_dualcore (bd<N_IN> in, out;
+
+    Mx1of2<REG_NCW> c1_reg_data[REG_M];
+    // a1of1 c1_synapses[N_SYN_X * N_SYN_Y];
+    // a1of1 c1_neurons[N_NRN_X * N_NRN_Y];
+    bool! c1_syn_r[N_SYN_X * N_SYN_Y];
+    bool? c1_syn_a[N_SYN_X * N_SYN_Y];
+    bool? c1_nrn_r[N_NRN_X * N_NRN_Y];
+    bool! c1_nrn_a[N_NRN_X * N_NRN_Y];
+    
+    bool! c1_nrn_mon_x[N_NRN_MON_X], c1_nrn_mon_y[N_NRN_MON_Y];
+    bool! c1_syn_mon_x[N_SYN_MON_X], c1_syn_mon_y[N_SYN_MON_Y];
+    bool? c1_syn_mon_AMZI[N_SYN_X * N_MON_AMZO_PER_SYN], c1_nrn_mon_AMZI[N_NRN_X * N_MON_AMZO_PER_NRN];
+    bool! c1_syn_mon_AMZO[N_MON_AMZO_PER_SYN], c1_nrn_mon_AMZO[N_MON_AMZO_PER_NRN];
+    bool! c1_syn_flags_EFO[N_FLAGS_PER_SYN], c1_nrn_flags_EFO[N_FLAGS_PER_NRN];
+
+    Mx1of2<REG_NCW> c2_reg_data[REG_M];
+    // a1of1 c2_synapses[N_SYN_X * N_SYN_Y];
+    // a1of1 c2_neurons[N_NRN_X * N_NRN_Y];
+    bool! c2_syn_r[N_SYN_X * N_SYN_Y];
+    bool? c2_syn_a[N_SYN_X * N_SYN_Y];
+    bool? c2_nrn_r[N_NRN_X * N_NRN_Y];
+    bool! c2_nrn_a[N_NRN_X * N_NRN_Y];
+    
+    bool! c2_nrn_mon_x[N_NRN_MON_X], c2_nrn_mon_y[N_NRN_MON_Y];
+    bool! c2_syn_mon_x[N_SYN_MON_X], c2_syn_mon_y[N_SYN_MON_Y];
+    bool? c2_syn_mon_AMZI[N_SYN_X * N_MON_AMZO_PER_SYN], c2_nrn_mon_AMZI[N_NRN_X * N_MON_AMZO_PER_NRN];
+    bool! c2_syn_mon_AMZO[N_MON_AMZO_PER_SYN], c2_nrn_mon_AMZO[N_MON_AMZO_PER_NRN];
+    bool! c2_syn_flags_EFO[N_FLAGS_PER_SYN], c2_nrn_flags_EFO[N_FLAGS_PER_NRN];
+
+    bool? bd_dly_cfg[N_BD_DLY_CFG], bd_dly_cfg2[N_BD_DLY_CFG2];
+    bool? loopback_en){
+
+    bool _reset_B; 
+    prs {
+        Reset => _reset_B-
+    }
+    power supply;
+    supply.vdd = Vdd;
+    supply.vss = GND;
+
+
+    a1of1 c1_synapses[N_SYN_X * N_SYN_Y];
+    a1of1 c1_neurons[N_NRN_X * N_NRN_Y];
+    a1of1 c2_synapses[N_SYN_X * N_SYN_Y];
+    a1of1 c2_neurons[N_NRN_X * N_NRN_Y];
+    (i:N_SYN_X * N_SYN_Y:
+        c1_synapses[i].r = c1_syn_r[i];
+        c2_synapses[i].r = c2_syn_r[i];
+        c1_synapses[i].a = c1_syn_a[i];
+        c2_synapses[i].a = c2_syn_a[i];
+    )
+    (i:N_NRN_X * N_NRN_Y:
+        c1_neurons[i].r = c1_nrn_r[i];
+        c2_neurons[i].r = c2_nrn_r[i];
+        c1_neurons[i].a = c1_nrn_a[i];
+        c2_neurons[i].a = c2_nrn_a[i];
+    )
+
+
+    texel_dualcore<N_IN,
+    N_NRN_X, N_NRN_Y, N_SYN_X, N_SYN_Y,
+    NC_NRN_X, NC_NRN_Y, NC_SYN_X, NC_SYN_Y,
+    N_SYN_DLY_CFG,
+    N_NRN_MON_X, N_NRN_MON_Y, N_SYN_MON_X, N_SYN_MON_Y,
+    N_MON_AMZO_PER_SYN, N_MON_AMZO_PER_NRN,
+    N_FLAGS_PER_SYN, N_FLAGS_PER_NRN,
+    N_BUFFERS,
+    N_LINE_PD_DLY,
+    N_BD_DLY_CFG, N_BD_DLY_CFG2,
+    REG_NCA, REG_NCW, REG_M> c(.in = in, .out = out,
+        .c1_reg_data = c1_reg_data, .c1_synapses = c1_synapses, .c1_neurons = c1_neurons, .c1_nrn_mon_x = c1_nrn_mon_x, .c1_nrn_mon_y = c1_nrn_mon_y, .c1_syn_mon_x = c1_syn_mon_x, .c1_syn_mon_y = c1_syn_mon_y, .c1_syn_mon_AMZI = c1_syn_mon_AMZI, .c1_nrn_mon_AMZI = c1_nrn_mon_AMZI, .c1_syn_mon_AMZO = c1_syn_mon_AMZO, .c1_nrn_mon_AMZO = c1_nrn_mon_AMZO, .c1_syn_flags_EFO = c1_syn_flags_EFO, .c1_nrn_flags_EFO = c1_nrn_flags_EFO, .c2_reg_data = c2_reg_data, .c2_synapses = c2_synapses, .c2_neurons = c2_neurons, .c2_nrn_mon_x = c2_nrn_mon_x, .c2_nrn_mon_y = c2_nrn_mon_y, .c2_syn_mon_x = c2_syn_mon_x, .c2_syn_mon_y = c2_syn_mon_y, .c2_syn_mon_AMZI = c2_syn_mon_AMZI, .c2_nrn_mon_AMZI = c2_nrn_mon_AMZI, .c2_syn_mon_AMZO = c2_syn_mon_AMZO, .c2_nrn_mon_AMZO = c2_nrn_mon_AMZO, .c2_syn_flags_EFO = c2_syn_flags_EFO, .c2_nrn_flags_EFO = c2_nrn_flags_EFO, .bd_dly_cfg = bd_dly_cfg, .bd_dly_cfg2 = bd_dly_cfg2,
+        .loopback_en = loopback_en, .supply = supply, .reset_B = _reset_B);
+
+    
+
+}
+
+
+// fifo_decoder_neurons_encoder_fifo e;
+chip_texel_dualcore c;