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register_rw continued

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This commit is contained in:
Michele
2022-03-09 20:02:41 +01:00
parent 6f1a970cfd
commit 4dcd975554
4 changed files with 380 additions and 414 deletions
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16
dataflow_neuro/registers.act
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@ -133,12 +133,8 @@ defproc register_rw (avMx1of2<1+lognw+wl> in; avMx1of2<lognw+wl> out; d1of<wl> d
//Validation of the input
avMx1of2<lognw+wl> _in_temp2,_in_read,_in_write;
avMx1of2<1>_in_flag;
// bool _in_stable;
// (i:1+lognw+wl:_in_temp.d[i] = in.d.d[i];)
// vtree<1+lognw+wl> val_input(.in = _in_temp,.out = _in_v_temp, .supply = supply);
// sigbuf_1output<4> val_input_X(.in = _in_v_temp,.out = in.v,.supply = supply);
// Read or write?
AND3_X1 ack_and(.a = _in_temp2.a,.b = _in_flag.a,.c = _ff_v,.y = in.a,.vdd = supply.vdd,.vss = supply.vss);
AND2_X1 ack_and(.a = _in_temp2.a,.b = _ff_v,.y = in.a,.vdd = supply.vdd,.vss = supply.vss);
in.v = _in_temp2.v;
_in_flag.d.d[0] = in.d.d[lognw+wl];
(i:lognw+wl:_in_temp2.d.d[i] = in.d.d[i];)
@ -148,8 +144,9 @@ defproc register_rw (avMx1of2<1+lognw+wl> in; avMx1of2<lognw+wl> out; d1of<wl> d
// Validation
Mx1of2<lognw+wl> _in_write_temp;
(i:lognw+wl:_in_write_temp.d[i] = _in_write.d.d[i];)
vtree<lognw+wl> val_input(.in = _in_write_temp,.out = _in_write.v, .supply = supply);
vtree<lognw+wl> val_input_write(.in = _in_write_temp,.out = _in_write.v, .supply = supply);
// Acknowledgment
//delayprog<N_dly_cfg> ack_dly(.in = _clock, .out = _in_write.a,.s = dly_cfg, .supply = supply);
// Generation of the fake clock pulse (inverted because the ff clocks are low_active)
delayprog<N_dly_cfg> clk_dly(.in = _in_write.v, .out = _clock_temp,.s = dly_cfg, .supply = supply);
INV_X1 inv_clk(.a = _clock_temp,.y = _clock_temp_inv,.vdd = supply.vdd,.vss = supply.vss);
@ -162,11 +159,12 @@ defproc register_rw (avMx1of2<1+lognw+wl> in; avMx1of2<lognw+wl> out; d1of<wl> d
vtree<wl> ff_validator;
Mx1of2<wl> _out_temp;
(i:wl:_out_temp.d[i] = out.d.d[i];)
ff_validator.in = _out_temp;
ff_validator.out = _ff_v;
ff_validator.supply = supply;
// Acknowledgment
_in_read.a = _ff_v; //The circuit is ack when flip flop data are valid
//Reset Buffers
bool _reset_BX,_reset_mem_BX,_reset_mem_BXX[nw*wl*2];
BUF_X1 reset_buf_BX(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);