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register_rw continued

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Michele
2022-03-09 20:02:41 +01:00
parent 6f1a970cfd
commit 4dcd975554
4 changed files with 380 additions and 414 deletions
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26
test/unit_tests/register_wrw/test.prsim
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@@ -1,18 +1,13 @@
watchall
#watchall
system "echo '[0] start test'"
system "echo '----------------------------------------------------------'"
set-qdi-channel-neutral "t.in" 5
set-qdi-channel-neutral "t._in_write" 5
set-qdi-channel-neutral "t._in_read" 5
set t.data[0].d[0] 0
set t.data[0].d[1] 0
set t.data[1].d[0] 0
set t.data[1].d[1] 0
set t.registers._in_write.a 0
set t.registers._in_read.a 0
set t.registers._in_write.v 0
set t.registers._in_read.v 0
set t.out.a 0
set Reset 0
cycle
status X
@@ -24,13 +19,16 @@ assert t.data[1].d[0] 0
assert t.data[1].d[1] 0
cycle
system "echo '[1] reset completed'"
system "echo '----------------------------------------------------------'"
# Set delay config lines
set t.dly_cfg[0] 1
set t.dly_cfg[1] 1
cycle
assert-qdi-channel-neutral "t.in" 5
system "echo '[2] delay line set'"
set-qdi-channel-valid "t.in" 5 19
system "echo '----------------------------------------------------------'"
set-qdi-channel-valid "t.in" 5 3
cycle
assert-qdi-channel-valid "t.registers._in_write" 4 3
assert t.registers._clock 0
@@ -42,8 +40,10 @@ cycle
set-qdi-channel-neutral "t.in" 5
cycle
assert t.registers._clock 1
assert t.registers.ff[0].q 1
assert t.registers.ff[1].q 1
system "echo '[3] clock checked'"
assert t.registers.ff_t[0].q 1
assert t.registers.ff_t[1].q 1
system "echo '[3] first writing done'"
system "echo '----------------------------------------------------------'"