bics/actlib_dataflow_neuro
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added slice before registers, so register sizes can be reduced

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This commit is contained in:
alexmadison 2022-07-06 17:26:26 +02:00
parent 27a0d34153
commit 502d35b000
4 changed files with 15 additions and 11 deletions
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3
dataflow_neuro/chips_noread.act
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@ -94,7 +94,8 @@ defproc texel_core (avMx1of2<N_IN> in, out;
demux_bit_msb<N_IN-1> _demux(.in = fifo_in.out, .reset_B = _reset_BX, .supply = supply);
// Register
fifo<N_IN-1,N_BUFFERS> fifo_dmx2reg(.in = _demux.out2, .reset_B = _reset_BX, .supply = supply);
slice_data<N_IN-1, 0,REG_NCW+REG_NCA> slice_pre_reg(.in = _demux.out2, .supply = supply);
fifo<REG_NCW+REG_NCA,N_BUFFERS> fifo_dmx2reg(.in = slice_pre_reg.out, .reset_B = _reset_BX, .supply = supply);
register_w_array<REG_NCA, REG_NCW, REG_M> register(.in = fifo_dmx2reg.out, .data = reg_data,
.supply = supply, .reset_B = reset_reg_B);

19
dataflow_neuro/primitives.act
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@ -841,17 +841,22 @@ defproc slice_data(avMx1of2<N> in; avMx1of2<std::min(N1,N)-std::max(N0,0)> out;
_N1 = std::min(N1,N);
_N0 = std::max(N0,0);
[_N0 = 0 & _N1 = N ->
in = out;
[] _N0 != 0 | _N1 != N ->
// BUF_X1 ack_buf(.a = out.a, .y = in.a, .vss = supply.vss, .vdd = supply.vdd);
vtree<N> in_vt(.in = in.d, .out = in.v, .supply = supply);
(i:_N1-_N0:
in.d.d[i + _N0] = out.d.d[i];
)
vtree<N> in_vt(.in = in.d, .out = in.v, .supply = supply);
(i:_N1-_N0:
in.d.d[i + _N0] = out.d.d[i];
)
// in.a = out.a;
A_2C_B_X1 Cel(.c1 = out.a, .c2 =in.v, .y = in.a, .vss = supply.vss, .vdd = supply.vdd);
]
// in.a = out.a;
A_2C_B_X1 Cel(.c1 = out.a, .c2 =in.v, .y = in.a, .vss = supply.vss, .vdd = supply.vdd);
}

2
test/unit_tests/texel_dualcore_glue_noread/test.act
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@ -75,7 +75,7 @@ pint N_LINE_PD_DLY = 2;
pint REG_NCA = 6;
pint REG_M = 1<<REG_NCA;
pint REG_NCW = 24;
pint REG_NCW = 23;
defproc texel_dualcore_glue_noread (bd<N_IN> in, out;

2
test/unit_tests/texel_dualcore_glue_noread/test.prsim
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@ -50,8 +50,6 @@ watch c.c1_reg_data[0].d[21].t
watch c.c1_reg_data[0].d[21].f
watch c.c1_reg_data[0].d[22].t
watch c.c1_reg_data[0].d[22].f
watch c.c1_reg_data[0].d[23].t
watch c.c1_reg_data[0].d[23].f
set c.bd_dly_cfg[0] 1