removed tests of non-A-cell registers
This commit is contained in:
alexmadison
parent
5eb77108ab
commit
51010a6095
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@ -1,52 +0,0 @@
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/*************************************************************************
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*
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* This file is part of ACT dataflow neuro library.
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* It's the testing facility for cell_lib_std.act
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*
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* Copyright (c) 2022 University of Groningen - Ole Richter
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* Copyright (c) 2022 University of Groningen - Hugh Greatorex
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* Copyright (c) 2022 University of Groningen - Michele Mastella
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* Copyright (c) 2022 University of Groningen - Madison Cotteret
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*
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* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
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*
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* You may redistribute and modify this documentation and make products
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* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
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* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
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* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
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* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
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* for applicable conditions.
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*
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* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
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*
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* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
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* these sources, You must maintain the Source Location visible in its
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* documentation.
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*
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**************************************************************************
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*/
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import "../../dataflow_neuro/registers.act";
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import globals;
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open tmpl::dataflow_neuro;
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// 2 bits encoder, 2 bits long words, 2 delays????
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defproc register_test (avMx1of2<1+2+2> in; d1of<2> data[1<<2]; bool? dly_cfg[2]){
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register_w<2,2,2> registers(.in=in,.data = data);
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//Low active Reset
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bool _reset_B;
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power _supply;
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prs {
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Reset => _reset_B-
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}
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registers.supply = _supply;
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_supply.vss = GND;
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_supply.vdd = Vdd;
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registers.reset_B = _reset_B;
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registers.reset_mem_B = _reset_B;
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registers.dly_cfg = dly_cfg;
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}
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register_test t;
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@ -1,49 +0,0 @@
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watchall
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system "echo '[0] start test'"
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set-qdi-channel-neutral "t.in" 5
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set t.data[0].d[0] 0
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set t.data[0].d[1] 0
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set t.data[1].d[0] 0
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set t.data[1].d[1] 0
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set t.registers._in_write.a 0
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set t.registers._in_read.a 0
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set t.registers._in_write.v 0
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set t.registers._in_read.v 0
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set Reset 0
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cycle
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status X
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mode run
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assert-qdi-channel-neutral "t.in" 5
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assert t.data[0].d[0] 0
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assert t.data[0].d[1] 0
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assert t.data[1].d[0] 0
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assert t.data[1].d[1] 0
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cycle
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system "echo '[1] reset completed'"
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# Set delay config lines
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set t.dly_cfg[0] 1
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set t.dly_cfg[1] 1
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cycle
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assert-qdi-channel-neutral "t.in" 5
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system "echo '[2] delay line set'"
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set-qdi-channel-valid "t.in" 5 19
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cycle
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assert-qdi-channel-valid "t.registers._in_write" 4 3
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assert t.registers._clock 0
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assert t.registers._out_encoder[0] 1
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assert t.registers._out_encoder[1] 0
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assert t.registers._out_encoder[2] 0
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assert t.registers._out_encoder[3] 0
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cycle
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set-qdi-channel-neutral "t.in" 5
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cycle
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assert t.registers._clock 1
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assert t.registers.ff[0].q 1
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assert t.registers.ff[1].q 1
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system "echo '[3] clock checked'"
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@ -1,52 +0,0 @@
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/*************************************************************************
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*
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* This file is part of ACT dataflow neuro library.
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* It's the testing facility for cell_lib_std.act
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*
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* Copyright (c) 2022 University of Groningen - Ole Richter
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* Copyright (c) 2022 University of Groningen - Hugh Greatorex
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* Copyright (c) 2022 University of Groningen - Michele Mastella
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* Copyright (c) 2022 University of Groningen - Madison Cotteret
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*
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* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
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*
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* You may redistribute and modify this documentation and make products
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* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
|
||||
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
|
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* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
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* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
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* for applicable conditions.
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*
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* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
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*
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* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
|
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* these sources, You must maintain the Source Location visible in its
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* documentation.
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*
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**************************************************************************
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*/
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import "../../dataflow_neuro/registers.act";
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import globals;
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open tmpl::dataflow_neuro;
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// 2 bits encoder, 2 bits long words, 2 delays????
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defproc register_test (avMx1of2<1+2+2> in; avMx1of2<2+2> out;d1of<2> data[1<<2]; bool? dly_cfg[3]){
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register_rw<2,2,3> registers(.in=in,.data = data,.out = out);
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//Low active Reset
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bool _reset_B;
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power _supply;
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prs {
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Reset => _reset_B-
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}
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registers.supply = _supply;
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_supply.vss = GND;
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_supply.vdd = Vdd;
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registers.reset_B = _reset_B;
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registers.reset_mem_B = _reset_B;
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registers.dly_cfg = dly_cfg;
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}
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register_test t;
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@ -1,465 +0,0 @@
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watch t.registers.clock_buffer[0].out[0]
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watch t.registers.clock_buffer[1].out[0]
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watch t.registers.clock_buffer[2].out[0]
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watch t.registers.clock_buffer[3].out[0]
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system "echo '[0] start test'"
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system "echo '----------------------------------------------------------'"
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set-qdi-channel-neutral "t.in" 5
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set-qdi-channel-neutral "t.out" 4
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set t.data[0].d[0] 0
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set t.data[0].d[1] 0
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set t.data[1].d[0] 0
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set t.data[1].d[1] 0
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set t.dly_cfg[0] 1
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set t.dly_cfg[1] 1
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set t.dly_cfg[2] 1
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set t.out.a 0
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set t.out.v 0
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cycle
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set t.in.a 0
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set Reset 0
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cycle
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assert-qdi-channel-neutral "t.in" 5
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assert-qdi-channel-neutral "t.out" 4
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mode run
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cycle
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# check delay config programming
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assert t.registers.clk_dly.s[0] 1
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assert t.registers.clk_dly.s[1] 1
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assert t.registers.ff[0].q 0
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assert t.registers.ff[1].q 0
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assert t.registers.ff[2].q 0
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assert t.registers.ff[3].q 0
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assert t.registers.ff[4].q 0
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assert t.registers.ff[5].q 0
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assert t.registers.ff[6].q 0
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assert t.registers.ff[7].q 0
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assert-qdi-channel-neutral "t.out" 4
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assert t.data[0].d[0] 0
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assert t.data[0].d[1] 0
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assert t.data[1].d[0] 0
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assert t.data[1].d[1] 0
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cycle
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system "echo '[1] reset completed'"
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system "echo '----------------------------------------------------------'"
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set-qdi-channel-valid "t.in" 5 3
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# 3 -> 00011 -> writing mode, address 00, word 11
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cycle
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assert t.in.a 1
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assert-qdi-channel-neutral "t.out" 4
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assert t.registers._in_v_temp 1
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set-qdi-channel-neutral "t.in" 5
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cycle
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assert t.registers._in_v_temp 0
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assert t.registers.ff[0].q 1
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assert t.registers.ff[1].q 1
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assert t.registers.ff[2].q 0
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assert t.registers.ff[3].q 0
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assert t.registers.ff[4].q 0
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assert t.registers.ff[5].q 0
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assert t.registers.ff[6].q 0
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assert t.registers.ff[7].q 0
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assert t.in.v 0
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set t.out.a 0
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set t.out.v 0
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assert t.in.a 0
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cycle
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assert t.registers._clock_temp_inv 1
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system "echo '[3] first writing done'"
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system "echo '----------------------------------------------------------'"
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# set-qdi-channel-valid "t.in" 5 16
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# # 16 -> 10000 -> reading mode, address 00, word 00 (word doesnt needed here)
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# cycle
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# assert t.registers._clock_temp_inv 1
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# assert t.registers.word_to_read_X[0].out[0] 1
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# assert t.registers.word_to_read_X[0].out[1] 1
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# assert t.registers.word_to_read_X[0].out[2] 1
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# assert t.registers.word_to_read_X[0].out[3] 1
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# assert-qdi-channel-valid "t.out" 4 3
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# set t.out.v 1
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# cycle
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# set t.out.a 1
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# assert t.registers._clock_temp_inv 1
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# cycle
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# assert t.in.a 1
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# set-qdi-channel-neutral "t.in" 5
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# assert t.registers._clock_temp_inv 1
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# cycle
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# assert t.registers.ff[0].q 1
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# assert t.registers.ff[1].q 1
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# assert t.registers.ff[2].q 0
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# assert t.registers.ff[3].q 0
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# assert-qdi-channel-neutral "t.out" 4
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# assert t.registers._in_v_temp 0
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# set t.out.a 0
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# set t.out.v 0
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# assert t.in.a 0
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# cycle
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# system "echo '[4] reading done'"
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# system "echo '----------------------------------------------------------'"
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# set-qdi-channel-valid "t.in" 5 7
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# # 7 -> 00111 -> writing mode, address 01, word 11
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# cycle
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# assert t.in.a 1
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# assert-qdi-channel-neutral "t.out" 4
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# assert t.registers._in_v_temp 1
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# set-qdi-channel-neutral "t.in" 5
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# cycle
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# assert t.registers._in_v_temp 0
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# assert t.registers.ff[0].q 1
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# assert t.registers.ff[1].q 1
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# assert t.registers.ff[2].q 1
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# assert t.registers.ff[3].q 1
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# assert t.registers.ff[4].q 0
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# assert t.registers.ff[5].q 0
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# assert t.registers.ff[6].q 0
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# assert t.registers.ff[7].q 0
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# assert t.in.v 0
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# set t.out.a 0
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# set t.out.v 0
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# cycle
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# assert t.registers._clock_temp_inv 1
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# system "echo '[5] second writing done'"
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# system "echo '----------------------------------------------------------'"
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# set-qdi-channel-valid "t.in" 5 11
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# # 11 -> 01011 -> writing mode, address 10, word 11
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# cycle
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# assert t.in.a 1
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# assert-qdi-channel-neutral "t.out" 4
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# assert t.registers._in_v_temp 1
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# set-qdi-channel-neutral "t.in" 5
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# cycle
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# assert t.registers._in_v_temp 0
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# assert t.registers.ff[0].q 1
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# assert t.registers.ff[1].q 1
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# assert t.registers.ff[2].q 1
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# assert t.registers.ff[3].q 1
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# assert t.registers.ff[4].q 1
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# assert t.registers.ff[5].q 1
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# assert t.registers.ff[6].q 0
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# assert t.registers.ff[7].q 0
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# assert t.in.v 0
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# set t.out.a 0
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# set t.out.v 0
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# assert t.in.a 0
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# cycle
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# system "echo '[6] third writing done'"
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# system "echo '----------------------------------------------------------'"
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# set-qdi-channel-valid "t.in" 5 15
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# # 15 -> 01111 -> writing mode, address 11, word 11
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# cycle
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# assert t.in.a 1
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# assert-qdi-channel-neutral "t.out" 4
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# assert t.registers._in_v_temp 1
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# set-qdi-channel-neutral "t.in" 5
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# cycle
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# assert t.registers._in_v_temp 0
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# assert t.registers.ff[0].q 1
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# assert t.registers.ff[1].q 1
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# assert t.registers.ff[2].q 1
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# assert t.registers.ff[3].q 1
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# assert t.registers.ff[4].q 1
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# assert t.registers.ff[5].q 1
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# assert t.registers.ff[6].q 1
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# assert t.registers.ff[7].q 1
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# assert t.in.v 0
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# set t.out.a 0
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# set t.out.v 0
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# assert t.in.a 0
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# cycle
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# system "echo '[7] fourth writing done'"
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# system "echo '----------------------------------------------------------'"
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# set-qdi-channel-valid "t.in" 5 28
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# # 28 -> 11100 -> reading mode, address 11, word 00 (word doesnt needed here)
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# cycle
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# assert t.registers._clock_temp_inv 1
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# assert-qdi-channel-valid "t.out" 4 15
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# set t.out.v 1
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# cycle
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# set t.out.a 1
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# assert t.registers._clock_temp_inv 1
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# cycle
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# assert t.in.a 1
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# set-qdi-channel-neutral "t.in" 5
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# assert t.registers._clock_temp_inv 1
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# cycle
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# assert-qdi-channel-neutral "t.out" 4
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# assert t.registers._in_v_temp 0
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# set t.out.a 0
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# set t.out.v 0
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# assert t.in.a 0
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# cycle
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# system "echo '[8] 11 reading done'"
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# system "echo '----------------------------------------------------------'"
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# set-qdi-channel-valid "t.in" 5 20
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# # 20 -> 10100 -> reading mode, address 01, word 00 (word doesnt needed here)
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# cycle
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# assert t.registers._clock_temp_inv 1
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# assert-qdi-channel-valid "t.out" 4 7
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# set t.out.v 1
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# cycle
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# set t.out.a 1
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# assert t.registers._clock_temp_inv 1
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# cycle
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# assert t.in.a 1
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# set-qdi-channel-neutral "t.in" 5
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# assert t.registers._clock_temp_inv 1
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# cycle
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# assert-qdi-channel-neutral "t.out" 4
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# assert t.registers._in_v_temp 0
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# set t.out.a 0
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# set t.out.v 0
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# assert t.in.a 0
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# cycle
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# system "echo '[9] 01 reading done'"
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# system "echo '----------------------------------------------------------'"
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# set-qdi-channel-valid "t.in" 5 24
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# # 24 -> 11000 -> reading mode, address 10, word 00 (word doesnt needed here)
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# cycle
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# assert t.registers._clock_temp_inv 1
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# assert-qdi-channel-valid "t.out" 4 11
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# set t.out.v 1
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# cycle
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# set t.out.a 1
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# assert t.registers._clock_temp_inv 1
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# cycle
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# assert t.in.a 1
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# set-qdi-channel-neutral "t.in" 5
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# assert t.registers._clock_temp_inv 1
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# cycle
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# assert-qdi-channel-neutral "t.out" 4
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# assert t.registers._in_v_temp 0
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# set t.out.a 0
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# set t.out.v 0
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# assert t.in.a 0
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# cycle
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# system "echo '[8] 10 reading done'"
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# system "echo '----------------------------------------------------------'"
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# set-qdi-channel-valid "t.in" 5 13
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# # 13 -> 01101 -> writing mode, address 11, word 01
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# cycle
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# assert t.in.a 1
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# assert-qdi-channel-neutral "t.out" 4
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# assert t.registers._in_v_temp 1
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# set-qdi-channel-neutral "t.in" 5
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# cycle
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# assert t.registers._in_v_temp 0
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# assert t.registers.ff[0].q 1
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# assert t.registers.ff[1].q 1
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# assert t.registers.ff[2].q 1
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# assert t.registers.ff[3].q 1
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# assert t.registers.ff[4].q 1
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# assert t.registers.ff[5].q 1
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# assert t.registers.ff[6].q 1
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# assert t.registers.ff[7].q 1
|
||||
# assert t.in.v 0
|
||||
|
||||
# set t.out.a 0
|
||||
# set t.out.v 0
|
||||
# assert t.in.a 0
|
||||
# cycle
|
||||
|
||||
# system "echo '[9] Rewrite 11 to 01'"
|
||||
# system "echo '----------------------------------------------------------'"
|
||||
|
||||
|
||||
# set-qdi-channel-valid "t.in" 5 0
|
||||
# # 13 -> 00000 -> writing mode, address 00, word 00
|
||||
# cycle
|
||||
|
||||
# assert t.in.a 1
|
||||
# assert-qdi-channel-neutral "t.out" 4
|
||||
# assert t.registers._in_v_temp 1
|
||||
# set-qdi-channel-neutral "t.in" 5
|
||||
# cycle
|
||||
# assert t.registers._in_v_temp 0
|
||||
|
||||
# assert t.registers.ff[0].q 0
|
||||
# assert t.registers.ff[1].q 0
|
||||
# assert t.registers.ff[2].q 1
|
||||
# assert t.registers.ff[3].q 1
|
||||
# assert t.registers.ff[4].q 1
|
||||
# assert t.registers.ff[5].q 1
|
||||
# assert t.registers.ff[6].q 1
|
||||
# assert t.registers.ff[7].q 1
|
||||
# assert t.in.v 0
|
||||
|
||||
# set t.out.a 0
|
||||
# set t.out.v 0
|
||||
# assert t.in.a 0
|
||||
# cycle
|
||||
|
||||
# system "echo '[9] Rewrite 11 to 01'"
|
||||
# system "echo '----------------------------------------------------------'"
|
||||
|
||||
|
||||
# set-qdi-channel-valid "t.in" 5 0
|
||||
# # 0 -> 00000 -> writing mode, address 00, word 00
|
||||
# cycle
|
||||
|
||||
# assert t.in.a 1
|
||||
# assert-qdi-channel-neutral "t.out" 4
|
||||
# assert t.registers._in_v_temp 1
|
||||
# set-qdi-channel-neutral "t.in" 5
|
||||
# cycle
|
||||
# assert t.registers._in_v_temp 0
|
||||
|
||||
# assert t.registers.ff[0].q 0
|
||||
# assert t.registers.ff[1].q 0
|
||||
# assert t.registers.ff[2].q 1
|
||||
# assert t.registers.ff[3].q 1
|
||||
# assert t.registers.ff[4].q 1
|
||||
# assert t.registers.ff[5].q 1
|
||||
# assert t.registers.ff[6].q 1
|
||||
# assert t.registers.ff[7].q 0
|
||||
# assert t.in.v 0
|
||||
|
||||
# set t.out.a 0
|
||||
# set t.out.v 0
|
||||
# assert t.in.a 0
|
||||
# cycle
|
||||
|
||||
# system "echo '[9] Rewrite 11 to 01'"
|
||||
# system "echo '----------------------------------------------------------'"
|
||||
|
||||
|
||||
# set-qdi-channel-valid "t.in" 5 0
|
||||
# # 0 -> 00000 -> writing mode, address 00, word 00
|
||||
# cycle
|
||||
|
||||
# assert t.in.a 1
|
||||
# assert-qdi-channel-neutral "t.out" 4
|
||||
# assert t.registers._in_v_temp 1
|
||||
# set-qdi-channel-neutral "t.in" 5
|
||||
# cycle
|
||||
# assert t.registers._in_v_temp 0
|
||||
|
||||
# assert t.registers.ff[0].q 0
|
||||
# assert t.registers.ff[1].q 0
|
||||
# assert t.registers.ff[2].q 1
|
||||
# assert t.registers.ff[3].q 1
|
||||
# assert t.registers.ff[4].q 1
|
||||
# assert t.registers.ff[5].q 1
|
||||
# assert t.registers.ff[6].q 1
|
||||
# assert t.registers.ff[7].q 0
|
||||
# assert t.in.v 0
|
||||
|
||||
# set t.out.a 0
|
||||
# set t.out.v 0
|
||||
# assert t.in.a 0
|
||||
# cycle
|
||||
|
||||
# system "echo '[9] Rewrite 11 to 01'"
|
||||
# system "echo '----------------------------------------------------------'"
|
||||
|
||||
|
||||
# set-qdi-channel-valid "t.in" 5 0
|
||||
# # 13 -> 00000 -> writing mode, address 00, word 00
|
||||
# cycle
|
||||
|
||||
# assert t.in.a 1
|
||||
# assert-qdi-channel-neutral "t.out" 4
|
||||
# assert t.registers._in_v_temp 1
|
||||
# set-qdi-channel-neutral "t.in" 5
|
||||
# cycle
|
||||
# assert t.registers._in_v_temp 0
|
||||
|
||||
# assert t.registers.ff[0].q 0
|
||||
# assert t.registers.ff[1].q 0
|
||||
# assert t.registers.ff[2].q 1
|
||||
# assert t.registers.ff[3].q 1
|
||||
# assert t.registers.ff[4].q 1
|
||||
# assert t.registers.ff[5].q 1
|
||||
# assert t.registers.ff[6].q 1
|
||||
# assert t.registers.ff[7].q 0
|
||||
# assert t.in.v 0
|
||||
|
||||
# set t.out.a 0
|
||||
# set t.out.v 0
|
||||
# assert t.in.a 0
|
||||
# cycle
|
||||
|
||||
# system "echo '[9] Rewrite 11 to 01'"
|
||||
# system "echo '----------------------------------------------------------'"
|
||||
|
||||
|
||||
# set-qdi-channel-valid "t.in" 5 3
|
||||
# # 13 -> 00011 -> writing mode, address 00, word 11
|
||||
# cycle
|
||||
|
||||
# assert t.in.a 1
|
||||
# assert-qdi-channel-neutral "t.out" 4
|
||||
# assert t.registers._in_v_temp 1
|
||||
# set-qdi-channel-neutral "t.in" 5
|
||||
# cycle
|
||||
# assert t.registers._in_v_temp 0
|
||||
|
||||
# assert t.registers.ff[0].q 1
|
||||
# assert t.registers.ff[1].q 1
|
||||
# assert t.registers.ff[2].q 1
|
||||
# assert t.registers.ff[3].q 1
|
||||
# assert t.registers.ff[4].q 1
|
||||
# assert t.registers.ff[5].q 1
|
||||
# assert t.registers.ff[6].q 1
|
||||
# assert t.registers.ff[7].q 0
|
||||
# assert t.in.v 0
|
||||
|
||||
# set t.out.a 0
|
||||
# set t.out.v 0
|
||||
# assert t.in.a 0
|
||||
# cycle
|
||||
|
||||
# system "echo '[9] Rewrite 11 to 01'"
|
||||
# system "echo '----------------------------------------------------------'"
|
||||
|
||||
|
||||
|
||||
Loading…
Reference in New Issue