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removed tests of non-A-cell registers

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alexmadison 2023-11-21 15:54:11 +01:00
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commit 51010a6095
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52
test/unit_tests/register_write/test.act
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@ -1,52 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/registers.act";
import globals;
open tmpl::dataflow_neuro;
// 2 bits encoder, 2 bits long words, 2 delays????
defproc register_test (avMx1of2<1+2+2> in; d1of<2> data[1<<2]; bool? dly_cfg[2]){
register_w<2,2,2> registers(.in=in,.data = data);
//Low active Reset
bool _reset_B;
power _supply;
prs {
Reset => _reset_B-
}
registers.supply = _supply;
_supply.vss = GND;
_supply.vdd = Vdd;
registers.reset_B = _reset_B;
registers.reset_mem_B = _reset_B;
registers.dly_cfg = dly_cfg;
}
register_test t;

49
test/unit_tests/register_write/test.prsim
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watchall
system "echo '[0] start test'"
set-qdi-channel-neutral "t.in" 5
set t.data[0].d[0] 0
set t.data[0].d[1] 0
set t.data[1].d[0] 0
set t.data[1].d[1] 0
set t.registers._in_write.a 0
set t.registers._in_read.a 0
set t.registers._in_write.v 0
set t.registers._in_read.v 0
set Reset 0
cycle
status X
mode run
assert-qdi-channel-neutral "t.in" 5
assert t.data[0].d[0] 0
assert t.data[0].d[1] 0
assert t.data[1].d[0] 0
assert t.data[1].d[1] 0
cycle
system "echo '[1] reset completed'"
# Set delay config lines
set t.dly_cfg[0] 1
set t.dly_cfg[1] 1
cycle
assert-qdi-channel-neutral "t.in" 5
system "echo '[2] delay line set'"
set-qdi-channel-valid "t.in" 5 19
cycle
assert-qdi-channel-valid "t.registers._in_write" 4 3
assert t.registers._clock 0
assert t.registers._out_encoder[0] 1
assert t.registers._out_encoder[1] 0
assert t.registers._out_encoder[2] 0
assert t.registers._out_encoder[3] 0
cycle
set-qdi-channel-neutral "t.in" 5
cycle
assert t.registers._clock 1
assert t.registers.ff[0].q 1
assert t.registers.ff[1].q 1
system "echo '[3] clock checked'"

52
test/unit_tests/register_wrw/test.act
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/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/registers.act";
import globals;
open tmpl::dataflow_neuro;
// 2 bits encoder, 2 bits long words, 2 delays????
defproc register_test (avMx1of2<1+2+2> in; avMx1of2<2+2> out;d1of<2> data[1<<2]; bool? dly_cfg[3]){
register_rw<2,2,3> registers(.in=in,.data = data,.out = out);
//Low active Reset
bool _reset_B;
power _supply;
prs {
Reset => _reset_B-
}
registers.supply = _supply;
_supply.vss = GND;
_supply.vdd = Vdd;
registers.reset_B = _reset_B;
registers.reset_mem_B = _reset_B;
registers.dly_cfg = dly_cfg;
}
register_test t;

465
test/unit_tests/register_wrw/test.prsim
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@ -1,465 +0,0 @@
watch t.registers.clock_buffer[0].out[0]
watch t.registers.clock_buffer[1].out[0]
watch t.registers.clock_buffer[2].out[0]
watch t.registers.clock_buffer[3].out[0]
system "echo '[0] start test'"
system "echo '----------------------------------------------------------'"
set-qdi-channel-neutral "t.in" 5
set-qdi-channel-neutral "t.out" 4
set t.data[0].d[0] 0
set t.data[0].d[1] 0
set t.data[1].d[0] 0
set t.data[1].d[1] 0
set t.dly_cfg[0] 1
set t.dly_cfg[1] 1
set t.dly_cfg[2] 1
set t.out.a 0
set t.out.v 0
cycle
set t.in.a 0
set Reset 0
cycle
assert-qdi-channel-neutral "t.in" 5
assert-qdi-channel-neutral "t.out" 4
mode run
cycle
# check delay config programming
assert t.registers.clk_dly.s[0] 1
assert t.registers.clk_dly.s[1] 1
assert t.registers.ff[0].q 0
assert t.registers.ff[1].q 0
assert t.registers.ff[2].q 0
assert t.registers.ff[3].q 0
assert t.registers.ff[4].q 0
assert t.registers.ff[5].q 0
assert t.registers.ff[6].q 0
assert t.registers.ff[7].q 0
assert-qdi-channel-neutral "t.out" 4
assert t.data[0].d[0] 0
assert t.data[0].d[1] 0
assert t.data[1].d[0] 0
assert t.data[1].d[1] 0
cycle
system "echo '[1] reset completed'"
system "echo '----------------------------------------------------------'"
set-qdi-channel-valid "t.in" 5 3
# 3 -> 00011 -> writing mode, address 00, word 11
cycle
assert t.in.a 1
assert-qdi-channel-neutral "t.out" 4
assert t.registers._in_v_temp 1
set-qdi-channel-neutral "t.in" 5
cycle
assert t.registers._in_v_temp 0
assert t.registers.ff[0].q 1
assert t.registers.ff[1].q 1
assert t.registers.ff[2].q 0
assert t.registers.ff[3].q 0
assert t.registers.ff[4].q 0
assert t.registers.ff[5].q 0
assert t.registers.ff[6].q 0
assert t.registers.ff[7].q 0
assert t.in.v 0
set t.out.a 0
set t.out.v 0
assert t.in.a 0
cycle
assert t.registers._clock_temp_inv 1
system "echo '[3] first writing done'"
system "echo '----------------------------------------------------------'"
# set-qdi-channel-valid "t.in" 5 16
# # 16 -> 10000 -> reading mode, address 00, word 00 (word doesnt needed here)
# cycle
# assert t.registers._clock_temp_inv 1
# assert t.registers.word_to_read_X[0].out[0] 1
# assert t.registers.word_to_read_X[0].out[1] 1
# assert t.registers.word_to_read_X[0].out[2] 1
# assert t.registers.word_to_read_X[0].out[3] 1
# assert-qdi-channel-valid "t.out" 4 3
# set t.out.v 1
# cycle
# set t.out.a 1
# assert t.registers._clock_temp_inv 1
# cycle
# assert t.in.a 1
# set-qdi-channel-neutral "t.in" 5
# assert t.registers._clock_temp_inv 1
# cycle
# assert t.registers.ff[0].q 1
# assert t.registers.ff[1].q 1
# assert t.registers.ff[2].q 0
# assert t.registers.ff[3].q 0
# assert-qdi-channel-neutral "t.out" 4
# assert t.registers._in_v_temp 0
# set t.out.a 0
# set t.out.v 0
# assert t.in.a 0
# cycle
# system "echo '[4] reading done'"
# system "echo '----------------------------------------------------------'"
# set-qdi-channel-valid "t.in" 5 7
# # 7 -> 00111 -> writing mode, address 01, word 11
# cycle
# assert t.in.a 1
# assert-qdi-channel-neutral "t.out" 4
# assert t.registers._in_v_temp 1
# set-qdi-channel-neutral "t.in" 5
# cycle
# assert t.registers._in_v_temp 0
# assert t.registers.ff[0].q 1
# assert t.registers.ff[1].q 1
# assert t.registers.ff[2].q 1
# assert t.registers.ff[3].q 1
# assert t.registers.ff[4].q 0
# assert t.registers.ff[5].q 0
# assert t.registers.ff[6].q 0
# assert t.registers.ff[7].q 0
# assert t.in.v 0
# set t.out.a 0
# set t.out.v 0
# cycle
# assert t.registers._clock_temp_inv 1
# system "echo '[5] second writing done'"
# system "echo '----------------------------------------------------------'"
# set-qdi-channel-valid "t.in" 5 11
# # 11 -> 01011 -> writing mode, address 10, word 11
# cycle
# assert t.in.a 1
# assert-qdi-channel-neutral "t.out" 4
# assert t.registers._in_v_temp 1
# set-qdi-channel-neutral "t.in" 5
# cycle
# assert t.registers._in_v_temp 0
# assert t.registers.ff[0].q 1
# assert t.registers.ff[1].q 1
# assert t.registers.ff[2].q 1
# assert t.registers.ff[3].q 1
# assert t.registers.ff[4].q 1
# assert t.registers.ff[5].q 1
# assert t.registers.ff[6].q 0
# assert t.registers.ff[7].q 0
# assert t.in.v 0
# set t.out.a 0
# set t.out.v 0
# assert t.in.a 0
# cycle
# system "echo '[6] third writing done'"
# system "echo '----------------------------------------------------------'"
# set-qdi-channel-valid "t.in" 5 15
# # 15 -> 01111 -> writing mode, address 11, word 11
# cycle
# assert t.in.a 1
# assert-qdi-channel-neutral "t.out" 4
# assert t.registers._in_v_temp 1
# set-qdi-channel-neutral "t.in" 5
# cycle
# assert t.registers._in_v_temp 0
# assert t.registers.ff[0].q 1
# assert t.registers.ff[1].q 1
# assert t.registers.ff[2].q 1
# assert t.registers.ff[3].q 1
# assert t.registers.ff[4].q 1
# assert t.registers.ff[5].q 1
# assert t.registers.ff[6].q 1
# assert t.registers.ff[7].q 1
# assert t.in.v 0
# set t.out.a 0
# set t.out.v 0
# assert t.in.a 0
# cycle
# system "echo '[7] fourth writing done'"
# system "echo '----------------------------------------------------------'"
# set-qdi-channel-valid "t.in" 5 28
# # 28 -> 11100 -> reading mode, address 11, word 00 (word doesnt needed here)
# cycle
# assert t.registers._clock_temp_inv 1
# assert-qdi-channel-valid "t.out" 4 15
# set t.out.v 1
# cycle
# set t.out.a 1
# assert t.registers._clock_temp_inv 1
# cycle
# assert t.in.a 1
# set-qdi-channel-neutral "t.in" 5
# assert t.registers._clock_temp_inv 1
# cycle
# assert-qdi-channel-neutral "t.out" 4
# assert t.registers._in_v_temp 0
# set t.out.a 0
# set t.out.v 0
# assert t.in.a 0
# cycle
# system "echo '[8] 11 reading done'"
# system "echo '----------------------------------------------------------'"
# set-qdi-channel-valid "t.in" 5 20
# # 20 -> 10100 -> reading mode, address 01, word 00 (word doesnt needed here)
# cycle
# assert t.registers._clock_temp_inv 1
# assert-qdi-channel-valid "t.out" 4 7
# set t.out.v 1
# cycle
# set t.out.a 1
# assert t.registers._clock_temp_inv 1
# cycle
# assert t.in.a 1
# set-qdi-channel-neutral "t.in" 5
# assert t.registers._clock_temp_inv 1
# cycle
# assert-qdi-channel-neutral "t.out" 4
# assert t.registers._in_v_temp 0
# set t.out.a 0
# set t.out.v 0
# assert t.in.a 0
# cycle
# system "echo '[9] 01 reading done'"
# system "echo '----------------------------------------------------------'"
# set-qdi-channel-valid "t.in" 5 24
# # 24 -> 11000 -> reading mode, address 10, word 00 (word doesnt needed here)
# cycle
# assert t.registers._clock_temp_inv 1
# assert-qdi-channel-valid "t.out" 4 11
# set t.out.v 1
# cycle
# set t.out.a 1
# assert t.registers._clock_temp_inv 1
# cycle
# assert t.in.a 1
# set-qdi-channel-neutral "t.in" 5
# assert t.registers._clock_temp_inv 1
# cycle
# assert-qdi-channel-neutral "t.out" 4
# assert t.registers._in_v_temp 0
# set t.out.a 0
# set t.out.v 0
# assert t.in.a 0
# cycle
# system "echo '[8] 10 reading done'"
# system "echo '----------------------------------------------------------'"
# set-qdi-channel-valid "t.in" 5 13
# # 13 -> 01101 -> writing mode, address 11, word 01
# cycle
# assert t.in.a 1
# assert-qdi-channel-neutral "t.out" 4
# assert t.registers._in_v_temp 1
# set-qdi-channel-neutral "t.in" 5
# cycle
# assert t.registers._in_v_temp 0
# assert t.registers.ff[0].q 1
# assert t.registers.ff[1].q 1
# assert t.registers.ff[2].q 1
# assert t.registers.ff[3].q 1
# assert t.registers.ff[4].q 1
# assert t.registers.ff[5].q 1
# assert t.registers.ff[6].q 1
# assert t.registers.ff[7].q 1
# assert t.in.v 0
# set t.out.a 0
# set t.out.v 0
# assert t.in.a 0
# cycle
# system "echo '[9] Rewrite 11 to 01'"
# system "echo '----------------------------------------------------------'"
# set-qdi-channel-valid "t.in" 5 0
# # 13 -> 00000 -> writing mode, address 00, word 00
# cycle
# assert t.in.a 1
# assert-qdi-channel-neutral "t.out" 4
# assert t.registers._in_v_temp 1
# set-qdi-channel-neutral "t.in" 5
# cycle
# assert t.registers._in_v_temp 0
# assert t.registers.ff[0].q 0
# assert t.registers.ff[1].q 0
# assert t.registers.ff[2].q 1
# assert t.registers.ff[3].q 1
# assert t.registers.ff[4].q 1
# assert t.registers.ff[5].q 1
# assert t.registers.ff[6].q 1
# assert t.registers.ff[7].q 1
# assert t.in.v 0
# set t.out.a 0
# set t.out.v 0
# assert t.in.a 0
# cycle
# system "echo '[9] Rewrite 11 to 01'"
# system "echo '----------------------------------------------------------'"
# set-qdi-channel-valid "t.in" 5 0
# # 0 -> 00000 -> writing mode, address 00, word 00
# cycle
# assert t.in.a 1
# assert-qdi-channel-neutral "t.out" 4
# assert t.registers._in_v_temp 1
# set-qdi-channel-neutral "t.in" 5
# cycle
# assert t.registers._in_v_temp 0
# assert t.registers.ff[0].q 0
# assert t.registers.ff[1].q 0
# assert t.registers.ff[2].q 1
# assert t.registers.ff[3].q 1
# assert t.registers.ff[4].q 1
# assert t.registers.ff[5].q 1
# assert t.registers.ff[6].q 1
# assert t.registers.ff[7].q 0
# assert t.in.v 0
# set t.out.a 0
# set t.out.v 0
# assert t.in.a 0
# cycle
# system "echo '[9] Rewrite 11 to 01'"
# system "echo '----------------------------------------------------------'"
# set-qdi-channel-valid "t.in" 5 0
# # 0 -> 00000 -> writing mode, address 00, word 00
# cycle
# assert t.in.a 1
# assert-qdi-channel-neutral "t.out" 4
# assert t.registers._in_v_temp 1
# set-qdi-channel-neutral "t.in" 5
# cycle
# assert t.registers._in_v_temp 0
# assert t.registers.ff[0].q 0
# assert t.registers.ff[1].q 0
# assert t.registers.ff[2].q 1
# assert t.registers.ff[3].q 1
# assert t.registers.ff[4].q 1
# assert t.registers.ff[5].q 1
# assert t.registers.ff[6].q 1
# assert t.registers.ff[7].q 0
# assert t.in.v 0
# set t.out.a 0
# set t.out.v 0
# assert t.in.a 0
# cycle
# system "echo '[9] Rewrite 11 to 01'"
# system "echo '----------------------------------------------------------'"
# set-qdi-channel-valid "t.in" 5 0
# # 13 -> 00000 -> writing mode, address 00, word 00
# cycle
# assert t.in.a 1
# assert-qdi-channel-neutral "t.out" 4
# assert t.registers._in_v_temp 1
# set-qdi-channel-neutral "t.in" 5
# cycle
# assert t.registers._in_v_temp 0
# assert t.registers.ff[0].q 0
# assert t.registers.ff[1].q 0
# assert t.registers.ff[2].q 1
# assert t.registers.ff[3].q 1
# assert t.registers.ff[4].q 1
# assert t.registers.ff[5].q 1
# assert t.registers.ff[6].q 1
# assert t.registers.ff[7].q 0
# assert t.in.v 0
# set t.out.a 0
# set t.out.v 0
# assert t.in.a 0
# cycle
# system "echo '[9] Rewrite 11 to 01'"
# system "echo '----------------------------------------------------------'"
# set-qdi-channel-valid "t.in" 5 3
# # 13 -> 00011 -> writing mode, address 00, word 11
# cycle
# assert t.in.a 1
# assert-qdi-channel-neutral "t.out" 4
# assert t.registers._in_v_temp 1
# set-qdi-channel-neutral "t.in" 5
# cycle
# assert t.registers._in_v_temp 0
# assert t.registers.ff[0].q 1
# assert t.registers.ff[1].q 1
# assert t.registers.ff[2].q 1
# assert t.registers.ff[3].q 1
# assert t.registers.ff[4].q 1
# assert t.registers.ff[5].q 1
# assert t.registers.ff[6].q 1
# assert t.registers.ff[7].q 0
# assert t.in.v 0
# set t.out.a 0
# set t.out.v 0
# assert t.in.a 0
# cycle
# system "echo '[9] Rewrite 11 to 01'"
# system "echo '----------------------------------------------------------'"