bics
/
actlib_dataflow_neuro
12
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

Added std test

This commit is contained in:
Greatorex 2022-02-21 13:07:14 +01:00
parent 1b4fd2921d
commit 5fc6eaab9e
3 changed files with 93 additions and 36 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
dataflow_neuro/cell_lib_std.act
View File

@ -27,12 +27,12 @@
namespace std_cell_template {
namespace dataflow_neuro {
export defproc TIELO_X1(bool! y; bool? vdd, vss)
export defproc TIELO_X1(bool! y; bool vdd, vss)
{
y = vss;
}
export defproc TIEHI_X1(bool! y; bool? vdd, vss)
export defproc TIEHI_X1(bool! y; bool vdd, vss)
{
y = vdd;
}

58
dataflow_neuro/cell_lib_std_test.act Normal file
View File

@ -0,0 +1,58 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Alex Madison
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "cell_lib_std.act";
open std_cell_template::dataflow_neuro;
TIELO_X1 cell1;
TIEHI_X1 cell2;
INV_X1 cell4;
INV_X2 cell5;
INV_X4 cell6;
INV_X8 cell7;
CLKBUF1 cell8;
CLKBUF2 cell9;
CLKBUF3 cell10;
NOR2_X1 cell11;
NOR3_X1 cell12;
OR2_X1 cell13;
OR2_X2 cell14;
NAND2_X1 cell15;
NAND3_X1 cell16;
AND2_X1 cell17;
AND2_X2 cell18;
XOR2_X1 cell19;
XNOR2_X1 cell20;
MUX2_X1 cell25;
OAI21_X1 cell26;
AOI21_X1 cell27;
OAI22_X1 cell28;
AOI22_X1 cell29;
TBUF1_X1 cell30;
TBUF_X2 cell31;

67
test/unit_tests/std_instantiate/test.act
View File

@ -1,11 +1,12 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_async.act
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
@ -25,36 +26,34 @@
**************************************************************************
*/
import "../../dataflow_neuro/cell_lib_async.act";
open tmpl::dataflow_neuro;
A_1C1P2N_RB_X1 cell1;
A_1C1P2N_R_X1 cell2;
A_1C1P_1N_X1 cell3;
A_1C1P_B cell4;
A_1C1P cell5;
A_1C2P1N_X1 cell6;
A_1C2P_B_X1 cell7;
A_1C2P cell8;
A_1C3P2P2N_R_X1 cell9;
A_2C2N2N_RB_X1 cell10;
A_2C2N2N_RB_X2 cell11;
A_2C2N2N_RB_X4 cell12;
A_2C2N2N_R_X1 cell13;
A_2C2N_R_B_X2 cell14;
A_2C2N_R_B_X4 cell15;
A_2C2N_R_X1 cell16;
A_2C_B_X1 cell17;
A_2C_RB_X1 cell18;
A_2C_R_X1 cell19;
A_2C_X1 cell20;
A_3C_RB_X1 cell21;
A_3C_RB_X2 cell22;
A_3C_RB_X4 cell23;
A_3C_R_X1 cell24;
A_3C_X1 cell25;
A_4C_RB_X1 cell26;
A_4C_RB_X2 cell27;
A_4C_RB_X4 cell28;
A_4C_R_X1 cell29;
A_4P1N1N_B_X1 cell30;
A_4P1N1N_X1 cell31;
import "../../dataflow_neuro/cell_lib_std.act";
open std_cell_template::dataflow_neuro;
TIELO_X1 cell1;
TIEHI_X1 cell2;
INV_X1 cell4;
INV_X2 cell5;
INV_X4 cell6;
INV_X8 cell7;
CLKBUF1 cell8;
CLKBUF2 cell9;
CLKBUF3 cell10;
NOR2_X1 cell11;
NOR3_X1 cell12;
OR2_X1 cell13;
OR2_X2 cell14;
NAND2_X1 cell15;
NAND3_X1 cell16;
AND2_X1 cell17;
AND2_X2 cell18;
XOR2_X1 cell19;
XNOR2_X1 cell20;
MUX2_X1 cell25;
OAI21_X1 cell26;
AOI21_X1 cell27;
OAI22_X1 cell28;
AOI22_X1 cell29;
TBUF1_X1 cell30;
TBUF_X2 cell31;