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texel small prs

This commit is contained in:
alexmadison 2022-04-10 15:17:38 +02:00
parent feb28f27bf
commit 6eb6766bef
3 changed files with 151093 additions and 64954 deletions
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142014
test/unit_tests/texel_small/run/prsim.out
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73696
test/unit_tests/texel_small/run/test.prs
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337
test/unit_tests/texel_small/test.prsim
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@ -24,20 +24,7 @@ set Reset 0
cycle
# Reading address 0
set c.in.d[0] 0
set c.in.d[1] 0
set c.in.d[2] 0
set c.in.d[3] 0
set c.in.d[4] 0
set c.in.d[5] 0
set c.in.d[6] 0
set c.in.d[7] 0
set c.in.d[8] 0
set c.in.d[9] 0
set c.in.d[10] 0
set c.in.d[11] 0
set c.in.d[12] 0
set c.in.d[13] 1
set-bd-data-valid "c.in" 14 8192
cycle
set c.in.r 1
cycle
@ -49,6 +36,7 @@ cycle
assert c.in.a 0
# Should first get loopback
# Receiving output 0 from register 0
assert-bd-channel-valid "c.out" 14 8192
set c.out.a 1
cycle
@ -56,8 +44,10 @@ assert-bd-channel-neutral "c.out" 14
set c.out.a 0
cycle
# Expect register read packet to arrive
assert-bd-channel-valid "c.out" 14 4080
# Receiving output 0 from register 0
assert-bd-channel-valid "c.out" 14 0
set c.out.a 1
cycle
assert-bd-channel-neutral "c.out" 14
@ -68,60 +58,214 @@ cycle
set c.loopback_en 0
cycle
# Writing 68 to address 1
set c.in.d[0] 1
set c.in.d[1] 0
set c.in.d[2] 0
set c.in.d[3] 0
set c.in.d[4] 0
set c.in.d[5] 0
set c.in.d[6] 1
set c.in.d[7] 0
set c.in.d[8] 0
set c.in.d[9] 0
set c.in.d[10] 1
set c.in.d[11] 0
set c.in.d[12] 1
set c.in.d[13] 1
# Writing 17 to address 1
set-bd-data-valid "c.in" 14 12561
cycle
set c.in.r 1
cycle
assert c.in.a 1
# Remove input
set-bd-channel-neutral "c.in" 14
cycle
assert c.in.a 0
# Reading address 1
set c.in.d[0] 1
set c.in.d[1] 0
set c.in.d[2] 0
set c.in.d[3] 0
set c.in.d[4] 0
set c.in.d[5] 0
set c.in.d[6] 0
set c.in.d[7] 0
set c.in.d[8] 0
set c.in.d[9] 0
set c.in.d[10] 0
set c.in.d[11] 0
set c.in.d[12] 0
set c.in.d[13] 1
# Writing 255 to address 5
set-bd-data-valid "c.in" 14 16373
cycle
set c.in.r 1
cycle
assert c.in.a 1
# Remove input
# Remove input
set-bd-channel-neutral "c.in" 14
cycle
assert c.in.a 0
# Reading address 1
set-bd-data-valid "c.in" 14 8193
cycle
set c.in.r 1
cycle
assert c.in.a 1
# Remove input
set-bd-channel-neutral "c.in" 14
cycle
assert c.in.a 0
# Reading address 5
set-bd-data-valid "c.in" 14 8197
cycle
set c.in.r 1
cycle
assert c.in.a 1
# Remove input
set-bd-channel-neutral "c.in" 14
cycle
assert c.in.a 0
# Receiving output 68 from register 1
assert-bd-channel-valid "c.out" 14 1089
# Receiving output 17 from register 1
assert-bd-channel-valid "c.out" 14 273
set c.out.a 1
cycle
assert-bd-channel-neutral "c.out" 14
set c.out.a 0
cycle
# Receiving output 255 from register 5
assert-bd-channel-valid "c.out" 14 4085
set c.out.a 1
cycle
assert-bd-channel-neutral "c.out" 14
set c.out.a 0
cycle
# SPIKES
# Sending spike to synapse [0,1]
set-bd-data-valid "c.in" 14 2
cycle
set c.in.r 1
cycle
assert c.in.a 1
# Remove input
set-bd-channel-neutral "c.in" 14
cycle
assert c.in.a 0
# Receiving output spike [0,1]
assert-bd-channel-valid "c.out" 14 2
set c.out.a 1
cycle
assert-bd-channel-neutral "c.out" 14
set c.out.a 0
cycle
# Sending spike to synapse [1,3]
set-bd-data-valid "c.in" 14 7
cycle
set c.in.r 1
cycle
assert c.in.a 1
# Remove input
set-bd-channel-neutral "c.in" 14
cycle
assert c.in.a 0
# Receiving output spike [1,3]
assert-bd-channel-valid "c.out" 14 7
set c.out.a 1
cycle
assert-bd-channel-neutral "c.out" 14
set c.out.a 0
cycle
# Sending spike to synapse [1,2]
set-bd-data-valid "c.in" 14 5
cycle
set c.in.r 1
cycle
assert c.in.a 1
# Remove input
set-bd-channel-neutral "c.in" 14
cycle
assert c.in.a 0
# Receiving output spike [1,2]
assert-bd-channel-valid "c.out" 14 5
set c.out.a 1
cycle
assert-bd-channel-neutral "c.out" 14
set c.out.a 0
cycle
# Sending spike to synapse [1,3]
set-bd-data-valid "c.in" 14 7
cycle
set c.in.r 1
cycle
assert c.in.a 1
# Remove input
set-bd-channel-neutral "c.in" 14
cycle
assert c.in.a 0
# Receiving output spike [1,3]
assert-bd-channel-valid "c.out" 14 7
set c.out.a 1
cycle
assert-bd-channel-neutral "c.out" 14
set c.out.a 0
cycle
# Sending spike to synapse [0,2]
set-bd-data-valid "c.in" 14 4
cycle
set c.in.r 1
cycle
assert c.in.a 1
# Remove input
set-bd-channel-neutral "c.in" 14
cycle
assert c.in.a 0
# Receiving output spike [0,2]
assert-bd-channel-valid "c.out" 14 4
set c.out.a 1
cycle
assert-bd-channel-neutral "c.out" 14
set c.out.a 0
cycle
# Sending spike to synapse [0,3]
set-bd-data-valid "c.in" 14 6
cycle
set c.in.r 1
cycle
assert c.in.a 1
# Remove input
set-bd-channel-neutral "c.in" 14
cycle
assert c.in.a 0
# Receiving output spike [0,3]
assert-bd-channel-valid "c.out" 14 6
set c.out.a 1
cycle
assert-bd-channel-neutral "c.out" 14
@ -129,21 +273,90 @@ set c.out.a 0
cycle
# Sending spike to synapse [0,1]
set c.in.d[0] 0
set c.in.d[1] 1
set c.in.d[2] 0
set c.in.d[3] 0
set c.in.d[4] 0
set c.in.d[5] 0
set c.in.d[6] 0
set c.in.d[7] 0
set c.in.d[8] 0
set c.in.d[9] 0
set c.in.d[10] 0
set c.in.d[11] 0
set c.in.d[12] 0
set c.in.d[13] 0
set-bd-data-valid "c.in" 14 2
cycle
set c.in.r 1
cycle
assert c.in.a 1
# Remove input
set-bd-channel-neutral "c.in" 14
cycle
assert c.in.a 0
# Receiving output spike [0,1]
assert-bd-channel-valid "c.out" 14 2
set c.out.a 1
cycle
assert-bd-channel-neutral "c.out" 14
set c.out.a 0
cycle
# Sending spike to synapse [0,0]
set-bd-data-valid "c.in" 14 0
cycle
set c.in.r 1
cycle
assert c.in.a 1
# Remove input
set-bd-channel-neutral "c.in" 14
cycle
assert c.in.a 0
# Receiving output spike [0,0]
assert-bd-channel-valid "c.out" 14 0
set c.out.a 1
cycle
assert-bd-channel-neutral "c.out" 14
set c.out.a 0
cycle
# Sending spike to synapse [0,0]
set-bd-data-valid "c.in" 14 0
cycle
set c.in.r 1
cycle
assert c.in.a 1
# Remove input
set-bd-channel-neutral "c.in" 14
cycle
assert c.in.a 0
# Receiving output spike [0,0]
assert-bd-channel-valid "c.out" 14 0
set c.out.a 1
cycle
assert-bd-channel-neutral "c.out" 14
set c.out.a 0
cycle
# Sending spike to synapse [0,3]
set-bd-data-valid "c.in" 14 6
cycle
set c.in.r 1
cycle
assert c.in.a 1
# Remove input
set-bd-channel-neutral "c.in" 14
cycle
assert c.in.a 0
# Receiving output spike [0,3]
assert-bd-channel-valid "c.out" 14 6
set c.out.a 1
cycle
assert-bd-channel-neutral "c.out" 14
set c.out.a 0
cycle