bics
/
actlib_dataflow_neuro
12
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

Added arbiter_handshake

This commit is contained in:
M. Mastella 2022-02-23 19:01:54 +01:00
parent 97b0be5af0
commit 6f53a76dbc
9 changed files with 268 additions and 86 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

34
dataflow_neuro/cell_lib_async.act
View File

@ -478,24 +478,38 @@ namespace tmpl {
p_n_mode <- 1;
y {-1}}
}
export defcell arbiter_handshake(bool in1_r, in1_a,in2_r, in2_a out_r, out_a)
//Rajit example
defproc arbiter_Rajit (bool a, b, u, v)
{
bool _u, _v;
A_2C_B_X1 cel1(.c1 = out_a,.c2 = v,.y = in1_a);
A_2C_B_X1 cel2(.c1 = out_a,.c2 = u,.y = in2_a);
prs {
[keeper=0] in1_v & _v -> _u-
[keeper=0] ~in1_v | ~_v -> _u+
[keeper=0] in2_v & _u -> _v-
[keeper=0] ~in2_v | ~_u -> _v+
[keeper=0] ~_u | ~in2_a => u+
[keeper=0] ~_v | ~in1_a => v+
[keeper=0] u | v => out_r
[keeper=0] a & _v -> _u-
[keeper=0] ~a | ~_v -> _u+
[keeper=0] b & _u -> _v-
[keeper=0] ~b | ~_u -> _v+
[keeper=0] _u => u-
[keeper=0] _v => v-
}
spec {
mk_excllo(_u, _v)
}
}
defproc ARBITER (bool? a, b, c, d; bool! y1,y2; bool? vdd, vss)
{
bool _y1, _y2;
prs {
[keeper=0] a & _y2 -> _y1-
[keeper=0] ~a | ~_y2 -> _y1+
[keeper=0] b & _y1 -> _y2-
[keeper=0] ~b | ~_y1 -> _y2+
[keeper=0] ~_y1 | ~c => y1+
[keeper=0] ~_y2 | ~d => y2+
}
spec {
mk_excllo(_y1, _y2)
}
}
}}

127
dataflow_neuro/primitives.act
View File

@ -150,65 +150,65 @@ namespace tmpl {
)
}
export template<pint N>
defproc demux (avMx1of2<N> in; avMx1of2<N> out; bool? reset_B; power supply) {
//control
bool _en, _reset_BX,_reset_BXX[N];
OR2_X1 out_or(.a=out.v1, .b=out.v2,.vdd=supply.vdd,.vss=supply.vss)
A_3C_RB_X4 inack_ctl(.c1=_en,.c2=in.v,.c3=out.v,.y=in.a,.pr_B=_reset_BXX,.sr_B=_reset_BXX,.vdd=supply.vdd,.vss=supply.vss);
// export template<pint N>
// defproc demux (avMx1of2<N> in; avMx1of2<N> out; bool? reset_B; power supply) {
// //control
// bool _en, _reset_BX,_reset_BXX[N];
// OR2_X1 out_or(.a=out.v1, .b=out.v2,.vdd=supply.vdd,.vss=supply.vss);
// A_3C_RB_X4 inack_ctl(.c1=_en,.c2=in.v,.c3=out.v,.y=in.a,.pr_B=_reset_BXX,.sr_B=_reset_BXX,.vdd=supply.vdd,.vss=supply.vss);
//validity
BUF_X1 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
sigbuf<N> reset_bufarray(.in=_reset_BX, .out=_reset_BXX);
// //validity
// BUF_X1 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
// sigbuf<N> reset_bufarray(.in=_reset_BX, .out=_reset_BXX);
A_1C1P_X1 en_ctl(.c1=in.a,.p1=out.v,.y=_en,.vdd=supply.vdd,.vss=supply.vss);
// A_1C1P_X1 en_ctl(.c1=in.a,.p1=out.v,.y=_en,.vdd=supply.vdd,.vss=supply.vss);
//validity
bool _in_v, _c_f_buf, _c_t_buf, _c_v;
sigbuf<N> c_buf_t(.in=c_t, .out=_c_t_buf)
sigbuf<N> c_buf_f(.in=c_f, .out=_c_f_buf)
// //validity
// bool _in_v, _c_f_buf, _c_t_buf, _c_v;
// sigbuf<N> c_buf_t(.in=c_t, .out=_c_t_buf)
// sigbuf<N> c_buf_f(.in=c_f, .out=_c_f_buf)
OR2_X1 c_f_c_t_or(.a=_c_t_buf, .b=_c_f_buf, out._c_v)
ctree<N> vc(.in=in.d,.out=_in_v,.supply=supply);
// OR2_X1 c_f_c_t_or(.a=_c_t_buf, .b=_c_f_buf, out._c_v)
// ctree<N> vc(.in=in.d,.out=_in_v,.supply=supply);
BUF_X4 in_v_buf(.a=_in_v, .y=in.v,.vdd=supply.vdd,.vss=supply.vss);
// BUF_X4 in_v_buf(.a=_in_v, .y=in.v,.vdd=supply.vdd,.vss=supply.vss);
//function
bool _out_a_BX_t[N],_out_a_BX_f[N],_out_a_B,_en_X_t[N],_en_X_f[N];
A_2C1N_RB_X4 f_buf_func[N];
A_2C1N_RB_X4 t_buf_func[N];
sigbuf<N> en_buf_t(.in=_en, .out=_en_X_t, .supply=supply);
sigbuf<N> en_buf_f(.in=_en, .out=_en_X_f, .supply=supply);
INV_X1 out_a_inv(.a=out.a,.y=_out_a_B);
sigbuf<N> out_a_B_buf_f(.in=_out_a_B,.out=_out_a_BX_t);
sigbuf<N> out_a_B_buf_t(.in=_out_a_B,.out=_out_a_BX_f);
// check if you can also do single var to array connect a=b[N]
// and remove them from the loop
(i:N:
f_buf_func[i].y=out.d.d[i].f;
t_buf_func[i].y=out.d.d[i].t;
f_buf_func[i].c1=_en_X_f[i];
t_buf_func[i].c1=_en_X_t[i];
f_buf_func[i].c2=_out_a_BX_f[i];
t_buf_func[i].c2=_out_a_BX_t[i];
f_buf_func[i].n1=in.d.d[i].f;
t_buf_func[i].n1=in.d.d[i].t;
f_buf_func[i].vdd=supply.vdd;
t_buf_func[i].vdd=supply.vdd;
f_buf_func[i].vss=supply.vss;
t_buf_func[i].vss=supply.vss;
t_buf_func[i].pr_B = _reset_BXX[i];
t_buf_func[i].sr_B = _reset_BXX[i];
f_buf_func[i].pr_B = _reset_BXX[i];
f_buf_func[i].sr_B = _reset_BXX[i];
)
}
// //function
// bool _out_a_BX_t[N],_out_a_BX_f[N],_out_a_B,_en_X_t[N],_en_X_f[N];
// A_2C1N_RB_X4 f_buf_func[N];
// A_2C1N_RB_X4 t_buf_func[N];
// sigbuf<N> en_buf_t(.in=_en, .out=_en_X_t, .supply=supply);
// sigbuf<N> en_buf_f(.in=_en, .out=_en_X_f, .supply=supply);
// INV_X1 out_a_inv(.a=out.a,.y=_out_a_B);
// sigbuf<N> out_a_B_buf_f(.in=_out_a_B,.out=_out_a_BX_t);
// sigbuf<N> out_a_B_buf_t(.in=_out_a_B,.out=_out_a_BX_f);
// // check if you can also do single var to array connect a=b[N]
// // and remove them from the loop
// (i:N:
// f_buf_func[i].y=out.d.d[i].f;
// t_buf_func[i].y=out.d.d[i].t;
// f_buf_func[i].c1=_en_X_f[i];
// t_buf_func[i].c1=_en_X_t[i];
// f_buf_func[i].c2=_out_a_BX_f[i];
// t_buf_func[i].c2=_out_a_BX_t[i];
// f_buf_func[i].n1=in.d.d[i].f;
// t_buf_func[i].n1=in.d.d[i].t;
// f_buf_func[i].vdd=supply.vdd;
// t_buf_func[i].vdd=supply.vdd;
// f_buf_func[i].vss=supply.vss;
// t_buf_func[i].vss=supply.vss;
// t_buf_func[i].pr_B = _reset_BXX[i];
// t_buf_func[i].sr_B = _reset_BXX[i];
// f_buf_func[i].pr_B = _reset_BXX[i];
// f_buf_func[i].sr_B = _reset_BXX[i];
// )
// }
@ -287,16 +287,31 @@ namespace tmpl {
out2_f_buf_func[i].sr_B = _reset_BXX[i+N-1];
)
}
export template<pint N>
defproc merge (avMx1of2<N> in1; avMx1of2<N> in2; avMx1of2<N> out ; bool? reset_B; power supply) {
// export template<pint N>
// defproc merge (avMx1of2<N> in1; avMx1of2<N> in2; avMx1of2<N> out ; bool? reset_B; power supply) {
//control
// //control
// bool _en, _reset_BX,_reset_BXX[N];
// A_4C_RB_X4 in1ack_ctl(.c1=in1arb,.c2=_en,.c3=in1.v,.c4=out.v,.y=in1.a,.pr_B=_reset_BX,.sr_B=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
// A_4C_RB_X4 in2ack_ctl(.c1=in2arb,.c2=_en,.c3=in2.v,.c4=out.v,.y=in2.a,.pr_B=_reset_BX,.sr_B=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
// A_4P_1N1N en_ctl(.p1 = in1.a,.p2=in2.a,.p3=out_a_X,.p4 = out.v, .n1 = in1.a,.y = _en,.vdd=supply.vdd,.vss=supply.vss);
//reset_buffers
// //reset_buffers
// BUF_X1 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
// sigbuf<N> reset_bufarray(.in=_reset_BX, .out=_reset_BXX);
//validity
// //validity
//function
}
}
// //function
// }
// defproc arbiter_handshake(a1of1 in1; a1of1 in2; a1of1 out; power supply)
// {
// bool _y1_arb,_y2_arb;
// A_2C_B_X1 cel1(.c1 = out.a,.c2 = _y1_arb,.y = in2.a,.vdd = supply.vdd, .vss = supply.vss);
// A_2C_B_X1 cel2(.c1 = out.a,.c2 = _y2_arb,.y = in1.a,.vdd = supply.vdd, .vss = supply.vss);
// OR2_X1 or_cell(.a = _y1_arb, .b = _y2_arb, .y = out.r,.vdd = supply.vdd, .vss = supply.vss);
// ARBITER arbiter(.a = in1.r, .b = in2.r, .c = in2.a, .d = in1.a, .y1 = _y1_arb, .y2 = _y2_arb, .vdd = supply.vdd, .vss = supply.vss);
// }
}}

39
test/unit_tests/arbiter_2/run/prsim.out Normal file
View File

@ -0,0 +1,39 @@
a._v a.a a.u a.v a._u a.b
reset done
0 a.a : 0
0 a.b : 0
1 a._u : 1 [by a.a:=0]
7092 a._v : 1 [by a.b:=0]
7094 a.v : 0 [by a._v:=1]
10468 a.u : 0 [by a._u:=1]
step 1.1 finished
10468 a.a : 1
10468 a.b : 1
15221 a._u : 0 [by a.a:=1]
15335 a.u : 1 [by a._u:=0]
step 1.2 finished
15335 a.a : 0
15335 a.b : 0
80701 a._u : 1 [by a.a:=0]
82427 a.u : 0 [by a._u:=1]
step 2.1 finished
82427 a.a : 1
82427 a.b : 1
82466 a._u : 0 [by a.a:=1]
82957 a.u : 1 [by a._u:=0]
step 2.2 finished
82957 a.a : 0
82957 a.b : 0
82970 a._u : 1 [by a.a:=0]
83010 a.u : 0 [by a._u:=1]
step 3.1 finished
83010 a.b : 1
83425 a._v : 0 [by a.b:=1]
83445 a.v : 1 [by a._v:=0]
step 3.2 finished

12
test/unit_tests/arbiter_2/run/test.prs Normal file
View File

@ -0,0 +1,12 @@
= "GND" "GND"
= "Vdd" "Vdd"
= "Reset" "Reset"
"a.a"&"a._v"->"a._u"-
~"a.a"|~"a._v"->"a._u"+
"a.b"&"a._u"->"a._v"-
~"a.b"|~"a._u"->"a._v"+
"a._u"->"a.u"-
~("a._u")->"a.u"+
"a._v"->"a.v"-
~("a._v")->"a.v"+
mk_excllo("a._u","a._v")

17
test/unit_tests/arbiter_2/test.act
View File

@ -14,20 +14,5 @@ defproc arbiter (bool a, b, u, v)
}
}
bool Reset;
defproc driver(bool r, a)
{
prs {
Reset | a => r-
}
}
defproc test()
{
driver d1, d2;
arbiter a(d1.r, d2.r, d1.a, d2.a);
}
test t;
arbiter a;

39
test/unit_tests/arbiter_2/test.prsim
View File

@ -1,8 +1,39 @@
watchall
cycle
set Reset 0
cycle
system "echo 'reset done'"
set a.a 0
set a.b 0
advance 1000000
status X
mode run
system "echo 'finished'"
system "echo 'step 1.1 finished'"
set a.a 1
set a.b 1
advance 1000000
status X
mode run
system "echo 'step 1.2 finished'"
set a.a 0
set a.b 0
advance 1000000
status X
mode run
system "echo 'step 2.1 finished'"
set a.a 1
set a.b 1
advance 1000000
status X
mode run
system "echo 'step 2.2 finished'"
set a.a 0
set a.b 0
advance 1000000
status X
mode run
system "echo 'step 3.1 finished'"
set a.a 0
set a.b 1
advance 1000000
status X
mode run
system "echo 'step 3.2 finished'"

3
test/unit_tests/arbiter_handshake/run/test.prs Normal file
View File

@ -0,0 +1,3 @@
= "GND" "GND"
= "Vdd" "Vdd"
= "Reset" "Reset"

41
test/unit_tests/arbiter_handshake/test.act Normal file
View File

@ -0,0 +1,41 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/primitives.act";
import globals;
open tmpl::dataflow_neuro;
defproc arbiter_test(a1of1 in1; a1of1 in2; a1of1 out)
{
arbiter_handshake a(.in1 = in1, .in2 = in, .out = out);
a.supply.vdd = Vdd;
a.supply.vss = Gnd;
}
arbiter_test t;

42
test/unit_tests/arbiter_handshake/test.prsim Normal file
View File

@ -0,0 +1,42 @@
watchall
cycle
system "echo 'reset done'"
t.in1.d 0
t.in2.d 0
t.in1.v 0
t.in2.v 0
t.out.a 0
cycle
status X
mode run
system "echo 'step 1.1 finished'"
set a.a 1
set a.b 1
advance 1000000
status X
mode run
system "echo 'step 1.2 finished'"
set a.a 0
set a.b 0
advance 1000000
status X
mode run
system "echo 'step 2.1 finished'"
set a.a 1
set a.b 1
advance 1000000
status X
mode run
system "echo 'step 2.2 finished'"
set a.a 0
set a.b 0
advance 1000000
status X
mode run
system "echo 'step 3.1 finished'"
set a.a 0
set a.b 1
advance 1000000
status X
mode run
system "echo 'step 3.2 finished'"