added flip flop from XFAB
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@ -373,49 +373,29 @@ namespace tmpl {
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}
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}
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sizing { _en{-2}; y{-2,2} }
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sizing { _en{-2}; y{-2,2} }
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}
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}
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export defproc DFFQ_R_X1 (bool? clk, reset, S, d, vdd, vss; bool! q)
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export defproc DFFQ_R_X1 (bool? clk, reset_B, d; bool! q; bool? vdd,vss)
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{
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{
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bool _clk, __clk, _q_B, _dl;
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bool _clk, __clk, _mqi,_mqib,_sqi,_sqib;
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bool _Ro, _So;
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bool _So2;
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bool _qb;
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prs {
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prs {
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_q_B<10> -> q-
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~_q_B<20> -> q+
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clk<10> -> _clk-
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// Creating delayed versions of the clock
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~clk<20> -> _clk+
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clk => _clk-
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_clk => __clk-
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_clk<10> -> __clk-
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(~d & ~_clk)|(~reset_B)|(~__clk&~_mqi) -> _mqib+
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~_clk<20> -> __clk+
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(d & __clk)|(reset_B & _mqi & _clk) -> _mqib-
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reset<20> -> _Ro-
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_mqib => _mqi-
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~reset<20> -> _Ro+
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// S<20> & _dl -> _So-
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(~_mqi &~__clk)|(~reset_B)|(~_sqi&~_clk) -> _sqib+
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// ~S<20> | ~_dl -> _So+
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(_mqi &_clk)|(_sqi&__clk&reset_B) -> _sqib-
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[keeper=0] d<10> & _clk -> _dl-
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_sqib => _sqi-
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~d<20> & ~__clk<10> -> _dl+
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_sqib => q-
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reset<20> & _qb -> _q_B-
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~reset<20> | ~_qb -> _q_B+
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// _q_B<20> & S -> _So2-
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// ~_q_B<20> | ~S -> _So2+
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// input stage feedback
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transgate<10> (__clk,_clk,_Ro,_dl)
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// input to output
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transgate<10> (__clk,_clk,reset,_qb)
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// output feedback
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transgate<10> (_clk,__clk,reset,_qb)
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}
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}
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sizing { q{-1} }
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}
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}
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}
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}
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}
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}
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