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added tests for dynapse sadc hs

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alexmadison
2022-07-05 10:53:17 +02:00
parent 8753540b33
commit 7896e0de24
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/*************************************************************************
*
* This file is part of ACT dataflow neuro library
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/cell_lib_async.act";
import "../../dataflow_neuro/cell_lib_std.act";
import "../../dataflow_neuro/treegates.act";
import "../../dataflow_neuro/primitives.act";
import "../../dataflow_neuro/registers.act";
import "../../dataflow_neuro/coders.act";
import "../../dataflow_neuro/interfaces.act";
// import tmpl::dataflow_neuro;
// import tmpl::dataflow_neuro;
import std::channel;
open std::channel;
namespace tmpl {
namespace dataflow_neuro {
export
defproc sadc_hs (a1of1 in, out; bool? reset_B; power supply) {
bool _en;
bool _out_a_B;
INV_X1 ack_inv(.a = out.a, .y = _out_a_B, .vdd = supply.vdd, .vss = supply.vss);
A_2C1N_RB_X1 A_ack(.c1 = _en, .c2 = in.r, .n1 = out.r, .y = in.a,
.pr_B = reset_B, .sr_B = reset_B, .vss = supply.vss, .vdd = supply.vdd);
A_2C1N_RB_X1 A_req(.c1 = _en, .c2 = _out_a_B, .n1 = in.r, .y = out.r,
.pr_B = reset_B, .sr_B = reset_B, .vss = supply.vss, .vdd = supply.vdd);
A_1C1P_X1 A_en(.c1 = in.a, .p1 = out.r, .y = _en,
.vdd = supply.vdd, .vss = supply.vss);
}
}
}