added DLY4 cell

2022-03-01 15:28:22 +01:00 · 2022-03-01 15:28:22 +01:00 · 79a96ed511
parent 233c9a7d10
commit 79a96ed511
1 changed files with 12 additions and 0 deletions
--- a/dataflow_neuro/cell_lib_std.act
+++ b/dataflow_neuro/cell_lib_std.act
@ -99,6 +99,18 @@ namespace tmpl {
      sizing { _y {-6,2}; y {-12,4} }
    }

+    /*-- delay cells --*/
+    // TODO properly
+
+    export defcell DLY4_X1(bool! y; bool? a, vdd, vss)
+    {
+      bool _y;
+      prs {
+        a => _y-
+        _y => y-
+      }
+    }
+
      
    /*-- simple gates --*/