tdc glue small for testing
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test/unit_tests/texel_dualcore_glue_small/test.act
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test/unit_tests/texel_dualcore_glue_small/test.act
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/*************************************************************************
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*
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* This file is part of ACT dataflow neuro library.
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* It's the testing facility for cell_lib_std.act
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*
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* Copyright (c) 2022 University of Groningen - Ole Richter
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* Copyright (c) 2022 University of Groningen - Hugh Greatorex
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* Copyright (c) 2022 University of Groningen - Michele Mastella
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* Copyright (c) 2022 University of Groningen - Madison Cotteret
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*
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* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
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*
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* You may redistribute and modify this documentation and make products
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* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
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* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
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* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
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* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
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* for applicable conditions.
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*
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* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
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*
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* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
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* these sources, You must maintain the Source Location visible in its
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* documentation.
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*
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**************************************************************************
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*/
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import "../../dataflow_neuro/coders.act";
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import "../../dataflow_neuro/primitives.act";
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import "../../dataflow_neuro/chips.act";
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import "../../dataflow_neuro/dummy.act";
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import globals;
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import std::data;
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open std::data;
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open tmpl::dataflow_neuro;
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pint N_IN = 32;
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pint N_NRN_X = 2;
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pint N_NRN_Y = 3;
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pint NC_NRN_X = 1;
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pint NC_NRN_Y = 2;
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pint N_SYN_X = 2;
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pint N_SYN_Y = 6;
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pint NC_SYN_X = 1;
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pint NC_SYN_Y = 3;
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pint N_SYN_DLY_CFG = 4;
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pint N_BD_DLY_CFG = 4;
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pint N_BD_DLY_CFG2 = 2;
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pint N_NRN_MON_X = N_NRN_X*2; // [mon,kill]*N
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pint N_NRN_MON_Y = N_NRN_Y; // [mon]*N
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pint N_SYN_MON_X = N_SYN_X*4; // [mon, dev_mon, set, resetB]*N
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pint N_SYN_MON_Y = N_SYN_Y; // [mon]*N
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pint N_MON_AMZO_PER_SYN = 5;
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pint N_MON_AMZO_PER_NRN = 3;
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pint N_FLAGS_PER_SYN = 5; // Syn: Must be at least 3 (since those ones have special safety)
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pint N_FLAGS_PER_NRN = 3; // and leq than the number of bits in a reg, since have presumed only needs one.
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pint N_BUFFERS = 3;
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pint N_LINE_PD_DLY = 2;
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pint REG_NCA = 6;
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pint REG_M = 6;
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pint REG_NCW = 23;
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defproc texel_dualcore_glue_small (bd<N_IN> in, out;
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Mx1of2<REG_NCW> c1_reg_data[REG_M];
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// a1of1 c1_synapses[N_SYN_X * N_SYN_Y];
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// a1of1 c1_neurons[N_NRN_X * N_NRN_Y];
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bool! c1_dec_req_x[N_SYN_X], c1_dec_req_y[N_SYN_Y];
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bool? c1_dec_ackB[N_SYN_X];
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a1of1 c1_syn_pu[N_SYN_X];
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a1of1 c1_enc_inx[N_NRN_X], c1_enc_iny[N_NRN_Y];
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a1of1 c1_nrn_pd_x[N_NRN_X], c1_nrn_pd_y[N_NRN_Y];
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bool! c1_nrn_mon_x[N_NRN_MON_X], c1_nrn_mon_y[N_NRN_MON_Y];
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bool! c1_syn_mon_x[N_SYN_MON_X], c1_syn_mon_y[N_SYN_MON_Y];
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bool? c1_syn_mon_AMZI[N_SYN_X * N_MON_AMZO_PER_SYN], c1_nrn_mon_AMZI[N_NRN_X * N_MON_AMZO_PER_NRN];
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bool! c1_syn_mon_AMZO[N_MON_AMZO_PER_SYN], c1_nrn_mon_AMZO[N_MON_AMZO_PER_NRN];
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bool! c1_syn_flags_EFO[N_FLAGS_PER_SYN], c1_nrn_flags_EFO[N_FLAGS_PER_NRN];
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bool! c1_reset_nrn_hs_BO[N_NRN_X], c1_reset_syn_hs_BO[N_SYN_X],
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c1_reset_nrn_stge_BO[N_NRN_X], c1_reset_syn_stge_BO[N_SYN_X];
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Mx1of2<REG_NCW> c2_reg_data[REG_M];
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// a1of1 c2_synapses[N_SYN_X * N_SYN_Y];
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// a1of1 c2_neurons[N_NRN_X * N_NRN_Y];
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bool! c2_dec_req_x[N_SYN_X], c2_dec_req_y[N_SYN_Y];
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bool? c2_dec_ackB[N_SYN_X];
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a1of1 c2_syn_pu[N_SYN_X];
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a1of1 c2_enc_inx[N_NRN_X], c2_enc_iny[N_NRN_Y];
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a1of1 c2_nrn_pd_x[N_NRN_X], c2_nrn_pd_y[N_NRN_Y];
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bool! c2_nrn_mon_x[N_NRN_MON_X], c2_nrn_mon_y[N_NRN_MON_Y];
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bool! c2_syn_mon_x[N_SYN_MON_X], c2_syn_mon_y[N_SYN_MON_Y];
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bool? c2_syn_mon_AMZI[N_SYN_X * N_MON_AMZO_PER_SYN], c2_nrn_mon_AMZI[N_NRN_X * N_MON_AMZO_PER_NRN];
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bool! c2_syn_mon_AMZO[N_MON_AMZO_PER_SYN], c2_nrn_mon_AMZO[N_MON_AMZO_PER_NRN];
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bool! c2_syn_flags_EFO[N_FLAGS_PER_SYN], c2_nrn_flags_EFO[N_FLAGS_PER_NRN];
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bool! c2_reset_nrn_hs_BO[N_NRN_X], c2_reset_syn_hs_BO[N_SYN_X],
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c2_reset_nrn_stge_BO[N_NRN_X], c2_reset_syn_stge_BO[N_SYN_X];
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bool! reset_B, reset_reg_B, reset_syn_stge_BI;
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bool? bd_dly_cfg[N_BD_DLY_CFG], bd_dly_cfg2[N_BD_DLY_CFG2];
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bool? loopback_en){
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bool _reset_B;
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prs {
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Reset => _reset_B-
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}
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power supply;
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supply.vdd = Vdd;
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supply.vss = GND;
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texel_dualcore<N_IN,
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N_NRN_X, N_NRN_Y, N_SYN_X, N_SYN_Y,
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NC_NRN_X, NC_NRN_Y, NC_SYN_X, NC_SYN_Y,
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N_SYN_DLY_CFG,
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N_NRN_MON_X, N_NRN_MON_Y, N_SYN_MON_X, N_SYN_MON_Y,
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N_MON_AMZO_PER_SYN, N_MON_AMZO_PER_NRN,
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N_FLAGS_PER_SYN, N_FLAGS_PER_NRN,
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N_BUFFERS,
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N_LINE_PD_DLY,
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N_BD_DLY_CFG, N_BD_DLY_CFG2,
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REG_NCA, REG_NCW, REG_M> c(.in = in, .out = out,
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.c1_reg_data = c1_reg_data, .c1_dec_req_x = c1_dec_req_x, .c1_dec_req_y = c1_dec_req_y, .c1_dec_ackB = c1_dec_ackB, .c1_syn_pu = c1_syn_pu, .c1_enc_inx = c1_enc_inx, .c1_enc_iny = c1_enc_iny, .c1_nrn_pd_x = c1_nrn_pd_x, .c1_nrn_pd_y = c1_nrn_pd_y, .c1_nrn_mon_x = c1_nrn_mon_x, .c1_nrn_mon_y = c1_nrn_mon_y, .c1_syn_mon_x = c1_syn_mon_x, .c1_syn_mon_y = c1_syn_mon_y, .c1_syn_mon_AMZI = c1_syn_mon_AMZI, .c1_nrn_mon_AMZI = c1_nrn_mon_AMZI, .c1_syn_mon_AMZO = c1_syn_mon_AMZO, .c1_nrn_mon_AMZO = c1_nrn_mon_AMZO, .c1_syn_flags_EFO = c1_syn_flags_EFO, .c1_nrn_flags_EFO = c1_nrn_flags_EFO, .c1_reset_nrn_hs_BO = c1_reset_nrn_hs_BO, .c1_reset_syn_hs_BO = c1_reset_syn_hs_BO, .c1_reset_nrn_stge_BO = c1_reset_nrn_stge_BO, .c1_reset_syn_stge_BO = c1_reset_syn_stge_BO, .c2_reg_data = c2_reg_data, .c2_dec_req_x = c2_dec_req_x, .c2_dec_req_y = c2_dec_req_y, .c2_dec_ackB = c2_dec_ackB, .c2_syn_pu = c2_syn_pu, .c2_enc_inx = c2_enc_inx, .c2_enc_iny = c2_enc_iny, .c2_nrn_pd_x = c2_nrn_pd_x, .c2_nrn_pd_y = c2_nrn_pd_y, .c2_nrn_mon_x = c2_nrn_mon_x, .c2_nrn_mon_y = c2_nrn_mon_y, .c2_syn_mon_x = c2_syn_mon_x, .c2_syn_mon_y = c2_syn_mon_y, .c2_syn_mon_AMZI = c2_syn_mon_AMZI, .c2_nrn_mon_AMZI = c2_nrn_mon_AMZI, .c2_syn_mon_AMZO = c2_syn_mon_AMZO, .c2_nrn_mon_AMZO = c2_nrn_mon_AMZO, .c2_syn_flags_EFO = c2_syn_flags_EFO, .c2_nrn_flags_EFO = c2_nrn_flags_EFO, .c2_reset_nrn_hs_BO = c2_reset_nrn_hs_BO, .c2_reset_syn_hs_BO = c2_reset_syn_hs_BO, .c2_reset_nrn_stge_BO = c2_reset_nrn_stge_BO, .c2_reset_syn_stge_BO = c2_reset_syn_stge_BO,
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.bd_dly_cfg = bd_dly_cfg, .bd_dly_cfg2 = bd_dly_cfg2,
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.loopback_en = loopback_en,
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// .reset_B = _reset_B, .reset_reg_B = _reset_B, .reset_syn_stge_BI = _reset_B,
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.reset_B = reset_B, .reset_reg_B = reset_reg_B, .reset_syn_stge_BI = reset_syn_stge_BI,
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.supply = supply);
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a1of1 c1_synapses[N_SYN_X * N_SYN_Y];
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a1of1 c1_neurons[N_NRN_X * N_NRN_Y];
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a1of1 c2_synapses[N_SYN_X * N_SYN_Y];
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a1of1 c2_neurons[N_NRN_X * N_NRN_Y];
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pint N_NRN = N_NRN_X * N_NRN_Y;
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pint N_SYN_PER_NRN = (N_SYN_X * N_SYN_Y)/N_NRN;
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dummy_neuron_core<N_SYN_PER_NRN, N_NRN, N_NRN_X> c1_dummy_neuron_core(.synapses = c1_synapses, .neurons = c1_neurons,
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.supply = supply);
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dummy_neuron_core<N_SYN_PER_NRN, N_NRN, N_NRN_X> c2_dummy_neuron_core(.synapses = c2_synapses, .neurons = c2_neurons,
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.supply = supply);
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decoder_2d_synapse_hs<N_SYN_X, N_SYN_Y> c1_syn_grid(
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.synapses = c1_synapses,
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.in_req_x = c1_dec_req_x, .in_req_y = c1_dec_req_y,
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.to_pu = c1_syn_pu,
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.out_ackB_decoder = c1_dec_ackB,
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.supply = supply);
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nrn_hs_2d_array<N_NRN_X,N_NRN_Y> c1_nrn_grid(.in = c1_neurons,
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.outx = c1_enc_inx, .outy = c1_enc_iny,
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.to_pd_x = c1_nrn_pd_x, .to_pd_y = c1_nrn_pd_y,
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.supply = supply, .reset_B = _reset_B);
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decoder_2d_synapse_hs<N_SYN_X, N_SYN_Y> c2_syn_grid(
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.synapses = c2_synapses,
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.in_req_x = c2_dec_req_x, .in_req_y = c2_dec_req_y,
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.to_pu = c2_syn_pu,
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.out_ackB_decoder = c2_dec_ackB,
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.supply = supply);
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nrn_hs_2d_array<N_NRN_X,N_NRN_Y> c2_nrn_grid(.in = c2_neurons,
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.outx = c2_enc_inx, .outy = c2_enc_iny,
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.to_pd_x = c2_nrn_pd_x, .to_pd_y = c2_nrn_pd_y,
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.supply = supply, .reset_B = _reset_B);
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}
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// fifo_decoder_neurons_encoder_fifo e;
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texel_dualcore_glue_small c;
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