arbtree init, using or2s for now
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alexmadison
parent
9c27248e12
commit
7f40b48b49
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t.in[0] t.out t.in[2] t.in[3] t.at.tmp[6] t.at.tmp[5] t.at.tmp[8] t.in[4] t.at.arbs[1]._y t.in[1] t.at.arbs[2]._y t.at.arbs[3]._y t.at.arbs[0]._y
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0
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1
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0 t.in[0] : 0
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0 t.in[4] : 0
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0 t.in[3] : 0
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0 t.in[2] : 0
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0 t.in[1] : 0
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1 t.at.arbs[1]._y : 1 [by t.in[2]:=0]
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7092 t.at.arbs[0]._y : 1 [by t.in[1]:=0]
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7094 t.at.tmp[5] : 0 [by t.at.arbs[0]._y:=1]
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10468 t.at.tmp[6] : 0 [by t.at.arbs[1]._y:=1]
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15221 t.at.arbs[2]._y : 1 [by t.at.tmp[6]:=0]
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16358 t.at.tmp[8] : 0 [by t.at.arbs[2]._y:=1]
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16472 t.at.arbs[3]._y : 1 [by t.at.tmp[8]:=0]
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81838 t.out : 0 [by t.at.arbs[3]._y:=1]
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[] setting all low
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[] setting bit 0 high
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81838 t.in[0] : 1
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83564 t.at.arbs[0]._y : 0 [by t.in[0]:=1]
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83603 t.at.tmp[5] : 1 [by t.at.arbs[0]._y:=0]
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83618 t.at.arbs[2]._y : 0 [by t.at.tmp[5]:=1]
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84109 t.at.tmp[8] : 1 [by t.at.arbs[2]._y:=0]
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84122 t.at.arbs[3]._y : 0 [by t.at.tmp[8]:=1]
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84162 t.out : 1 [by t.at.arbs[3]._y:=0]
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[] setting all low
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84162 t.in[0] : 0
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84577 t.at.arbs[0]._y : 1 [by t.in[0]:=0]
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84597 t.at.tmp[5] : 0 [by t.at.arbs[0]._y:=1]
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90658 t.at.arbs[2]._y : 1 [by t.at.tmp[5]:=0]
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90705 t.at.tmp[8] : 0 [by t.at.arbs[2]._y:=1]
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90721 t.at.arbs[3]._y : 1 [by t.at.tmp[8]:=0]
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134819 t.out : 0 [by t.at.arbs[3]._y:=1]
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[] setting bit 1 high
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134819 t.in[1] : 1
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148543 t.at.arbs[0]._y : 0 [by t.in[1]:=1]
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148547 t.at.tmp[5] : 1 [by t.at.arbs[0]._y:=0]
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157676 t.at.arbs[2]._y : 0 [by t.at.tmp[5]:=1]
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157691 t.at.tmp[8] : 1 [by t.at.arbs[2]._y:=0]
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200939 t.at.arbs[3]._y : 0 [by t.at.tmp[8]:=1]
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237870 t.out : 1 [by t.at.arbs[3]._y:=0]
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[] setting all low
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237870 t.in[1] : 0
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237925 t.at.arbs[0]._y : 1 [by t.in[1]:=0]
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289578 t.at.tmp[5] : 0 [by t.at.arbs[0]._y:=1]
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319358 t.at.arbs[2]._y : 1 [by t.at.tmp[5]:=0]
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333207 t.at.tmp[8] : 0 [by t.at.arbs[2]._y:=1]
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358019 t.at.arbs[3]._y : 1 [by t.at.tmp[8]:=0]
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372362 t.out : 0 [by t.at.arbs[3]._y:=1]
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[] setting bit 2 high
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372362 t.in[2] : 1
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372784 t.at.arbs[1]._y : 0 [by t.in[2]:=1]
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421498 t.at.tmp[6] : 1 [by t.at.arbs[1]._y:=0]
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421499 t.at.arbs[2]._y : 0 [by t.at.tmp[6]:=1]
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421500 t.at.tmp[8] : 1 [by t.at.arbs[2]._y:=0]
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441705 t.at.arbs[3]._y : 0 [by t.at.tmp[8]:=1]
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441987 t.out : 1 [by t.at.arbs[3]._y:=0]
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[] setting all low
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441987 t.in[2] : 0
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442755 t.at.arbs[1]._y : 1 [by t.in[2]:=0]
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442758 t.at.tmp[6] : 0 [by t.at.arbs[1]._y:=1]
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465199 t.at.arbs[2]._y : 1 [by t.at.tmp[6]:=0]
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465750 t.at.tmp[8] : 0 [by t.at.arbs[2]._y:=1]
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466821 t.at.arbs[3]._y : 1 [by t.at.tmp[8]:=0]
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467775 t.out : 0 [by t.at.arbs[3]._y:=1]
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[] setting bit 3 high
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467775 t.in[3] : 1
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468856 t.at.arbs[1]._y : 0 [by t.in[3]:=1]
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523326 t.at.tmp[6] : 1 [by t.at.arbs[1]._y:=0]
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524308 t.at.arbs[2]._y : 0 [by t.at.tmp[6]:=1]
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524326 t.at.tmp[8] : 1 [by t.at.arbs[2]._y:=0]
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528339 t.at.arbs[3]._y : 0 [by t.at.tmp[8]:=1]
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532342 t.out : 1 [by t.at.arbs[3]._y:=0]
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[] setting all low
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532342 t.in[3] : 0
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577243 t.at.arbs[1]._y : 1 [by t.in[3]:=0]
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598827 t.at.tmp[6] : 0 [by t.at.arbs[1]._y:=1]
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603587 t.at.arbs[2]._y : 1 [by t.at.tmp[6]:=0]
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604089 t.at.tmp[8] : 0 [by t.at.arbs[2]._y:=1]
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604292 t.at.arbs[3]._y : 1 [by t.at.tmp[8]:=0]
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606146 t.out : 0 [by t.at.arbs[3]._y:=1]
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[] setting bit 4 high
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606146 t.in[4] : 1
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606285 t.at.arbs[3]._y : 0 [by t.in[4]:=1]
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642631 t.out : 1 [by t.at.arbs[3]._y:=0]
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Binary file not shown.
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@ -0,0 +1,55 @@
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= "GND" "GND"
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= "Vdd" "Vdd"
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= "Reset" "Reset"
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"t.at.arbs[0].a"|"t.at.arbs[0].b"->"t.at.arbs[0]._y"-
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~("t.at.arbs[0].a"|"t.at.arbs[0].b")->"t.at.arbs[0]._y"+
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"t.at.arbs[0]._y"->"t.at.arbs[0].y"-
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~("t.at.arbs[0]._y")->"t.at.arbs[0].y"+
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"t.at.arbs[1].a"|"t.at.arbs[1].b"->"t.at.arbs[1]._y"-
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~("t.at.arbs[1].a"|"t.at.arbs[1].b")->"t.at.arbs[1]._y"+
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"t.at.arbs[1]._y"->"t.at.arbs[1].y"-
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~("t.at.arbs[1]._y")->"t.at.arbs[1].y"+
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"t.at.arbs[2].a"|"t.at.arbs[2].b"->"t.at.arbs[2]._y"-
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~("t.at.arbs[2].a"|"t.at.arbs[2].b")->"t.at.arbs[2]._y"+
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"t.at.arbs[2]._y"->"t.at.arbs[2].y"-
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~("t.at.arbs[2]._y")->"t.at.arbs[2].y"+
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"t.at.arbs[3].a"|"t.at.arbs[3].b"->"t.at.arbs[3]._y"-
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~("t.at.arbs[3].a"|"t.at.arbs[3].b")->"t.at.arbs[3]._y"+
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"t.at.arbs[3]._y"->"t.at.arbs[3].y"-
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~("t.at.arbs[3]._y")->"t.at.arbs[3].y"+
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= "t.at.tmp[5]" "t.at.arbs[2].a"
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= "t.at.tmp[5]" "t.at.arbs[0].y"
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= "t.at.tmp[6]" "t.at.arbs[2].b"
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= "t.at.tmp[6]" "t.at.arbs[1].y"
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= "t.at.tmp[8]" "t.at.arbs[3].a"
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= "t.at.tmp[8]" "t.at.arbs[2].y"
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= "t.at.supply.vdd" "t.at.arbs[3].vdd"
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= "t.at.supply.vdd" "t.at.arbs[2].vdd"
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= "t.at.supply.vdd" "t.at.arbs[1].vdd"
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= "t.at.supply.vdd" "t.at.arbs[0].vdd"
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= "t.at.supply.vss" "t.at.arbs[3].vss"
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= "t.at.supply.vss" "t.at.arbs[2].vss"
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= "t.at.supply.vss" "t.at.arbs[1].vss"
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= "t.at.supply.vss" "t.at.arbs[0].vss"
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= "t.at.in[0]" "t.at.arbs[0].a"
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= "t.at.in[0]" "t.at.tmp[0]"
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= "t.at.in[1]" "t.at.arbs[0].b"
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= "t.at.in[1]" "t.at.tmp[1]"
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= "t.at.in[2]" "t.at.arbs[1].a"
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= "t.at.in[2]" "t.at.tmp[2]"
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= "t.at.in[3]" "t.at.arbs[1].b"
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= "t.at.in[3]" "t.at.tmp[3]"
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= "t.at.in[4]" "t.at.arbs[3].b"
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= "t.at.in[4]" "t.at.tmp[9]"
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= "t.at.in[4]" "t.at.tmp[7]"
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= "t.at.in[4]" "t.at.tmp[4]"
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= "t.at.out" "t.at.arbs[3].y"
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= "t.at.out" "t.at.tmp[10]"
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= "Vdd" "t.at.supply.vdd"
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= "GND" "t.at.supply.vss"
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= "t.out" "t.at.out"
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= "t.in[0]" "t.at.in[0]"
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= "t.in[1]" "t.at.in[1]"
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= "t.in[2]" "t.at.in[2]"
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= "t.in[3]" "t.at.in[3]"
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= "t.in[4]" "t.at.in[4]"
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@ -0,0 +1,41 @@
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/*************************************************************************
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*
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* This file is part of ACT dataflow neuro library.
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* It's the testing facility for cell_lib_std.act
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*
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* Copyright (c) 2022 University of Groningen - Ole Richter
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* Copyright (c) 2022 University of Groningen - Hugh Greatorex
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* Copyright (c) 2022 University of Groningen - Michele Mastella
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* Copyright (c) 2022 University of Groningen - Madison Cotteret
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*
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* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
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*
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* You may redistribute and modify this documentation and make products
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* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
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* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
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* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
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* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
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* for applicable conditions.
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*
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* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
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*
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* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
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* these sources, You must maintain the Source Location visible in its
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* documentation.
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*
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**************************************************************************
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*/
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import "../../dataflow_neuro/treegates.act";
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import globals;
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open tmpl::dataflow_neuro;
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defproc arbtree_5 (bool? in[5]; bool! out){
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arbtree<5> at(.in=in, .out=out);
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at.supply.vss = GND;
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at.supply.vdd = Vdd;
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}
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arbtree_5 t;
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watchall
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system "echo '0'"
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set t.in[0] 0
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set t.in[1] 0
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set t.in[2] 0
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set t.in[3] 0
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set t.in[4] 0
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system "echo '1'"
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cycle
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mode run
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# assert t.out 0
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system "echo '[] setting all low'"
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set t.in[0] 0
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set t.in[1] 0
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set t.in[2] 0
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set t.in[3] 0
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set t.in[4] 0
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cycle
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system "echo '[] setting bit 0 high'"
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set t.in[0] 1
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cycle
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system "echo '[] setting all low'"
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set t.in[0] 0
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set t.in[1] 0
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set t.in[2] 0
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set t.in[3] 0
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set t.in[4] 0
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cycle
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system "echo '[] setting bit 1 high'"
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set t.in[0] 0
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set t.in[1] 1
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cycle
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system "echo '[] setting all low'"
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set t.in[0] 0
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set t.in[1] 0
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set t.in[2] 0
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set t.in[3] 0
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set t.in[4] 0
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cycle
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system "echo '[] setting bit 2 high'"
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set t.in[1] 0
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set t.in[2] 1
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cycle
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system "echo '[] setting all low'"
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set t.in[0] 0
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set t.in[1] 0
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set t.in[2] 0
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set t.in[3] 0
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set t.in[4] 0
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cycle
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system "echo '[] setting bit 3 high'"
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set t.in[2] 0
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set t.in[3] 1
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cycle
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system "echo '[] setting all low'"
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set t.in[0] 0
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set t.in[1] 0
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set t.in[2] 0
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set t.in[3] 0
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set t.in[4] 0
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cycle
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system "echo '[] setting bit 4 high'"
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set t.in[3] 0
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set t.in[4] 1
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cycle
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