added sadc encoder with inputs low active for dynapse sadcs

dataflow_neuro/coders.act

@@ -1078,7 +1078,32 @@ defproc decoder_2d_hybrid (avMx1of2<NxC+NyC> in; bool! out_req_x[Nx], out_req_y[
 			fifo<Nc, N_BUFFERS> _fifo(.in = _enc.out, .reset_B = _reset_BX, .supply = supply);
 			qdi2bd<Nc, N_BD_DLY_CFG> _qdi2bd(.in = _fifo.out, .out = out, .dly_cfg = dly_cfg,
 				.reset_B = _reset_BX, .supply = supply);
-		} 
+		}
+
+		/**
+	   * Same as encoder1d_bd above but with inverters on in.a/r bc sadc neuron handshake
+	   * signals are backwards lol.
+	   */
+		export template<pint Nc, N, N_BUFFERS, N_BD_DLY_CFG>
+		defproc encoder1d_bd_sadc(a1of1 in[N]; bd<Nc> out; bool? dly_cfg[N_BD_DLY_CFG], reset_B; power supply) {
+			
+
+			encoder1d_bd<Nc, N, N_BUFFERS, N_BD_DLY_CFG> c(.out = out, .dly_cfg = dly_cfg,
+				.reset_B = reset_B, .supply = supply);
+
+			INV_X1 req_invs[N];
+			INV_X1 ack_invs[N];
+			(i:N:
+				req_invs[i](.a = in[i].r, .y = c.in[i].r, .vdd = supply.vdd, .vss = supply.vss);
+				ack_invs[i](.a = c.in[i].a, .y = in[i].a, .vdd = supply.vdd, .vss = supply.vss);
+
+			)
+			
+
+		}
+
+
+
 
 
 		/**

test/unit_tests/texel_encoder1d_bd_sadc/run/prsim.in

@@ -0,0 +1,93 @@
+random_seed 99
+initialize
+load-scm "helper.scm"
+random
+set GND 0
+set Vdd 1
+set Reset 1
+
+mode reset
+cycle
+status U
+watchall
+
+
+set c.dly_cfg[0] 1
+set c.dly_cfg[1] 1
+set c.dly_cfg[2] 1
+set c.dly_cfg[3] 1
+
+set c.in[0].r 1
+set c.in[1].r 1
+set c.in[2].r 1
+set c.in[3].r 1
+set c.in[4].r 1
+set c.in[5].r 1
+set c.in[6].r 1
+
+set c.out.a 0
+
+set Reset 1
+cycle
+status X
+system "echo '[] Set reset 0'"
+mode run
+set Reset 0
+cycle
+system "echo '[] Reset finished'"
+status X
+
+assert-bd-channel-neutral "c.out" 3
+
+assert c.in[0].a 1
+assert c.in[1].a 1
+assert c.in[2].a 1
+assert c.in[3].a 1
+assert c.in[4].a 1
+assert c.in[5].a 1
+assert c.in[6].a 1
+
+
+
+system "echo '[] Spiking 3'"
+set c.in[3].r 0
+cycle
+assert c.in[3].a 0
+set c.in[3].r 1
+cycle
+assert c.in[3].a 1
+
+
+system "echo '[] Spiking 6'"
+set c.in[6].r 0
+cycle
+assert c.in[6].a 0
+set c.in[6].r 1
+cycle
+assert c.in[6].a 1
+
+system "echo '[] Receive 3'"
+assert-bd-channel-valid "c.out" 3 3
+set c.out.a 1
+cycle
+assert-bd-channel-neutral "c.out" 3
+set c.out.a 0
+cycle
+
+system "echo '[] Receive 6'"
+assert-bd-channel-valid "c.out" 3 6
+set c.out.a 1
+cycle
+assert-bd-channel-neutral "c.out" 6
+set c.out.a 0
+cycle
+
+
+
+
+
+
+
+
+
+

test/unit_tests/texel_encoder1d_bd_sadc/test.act

@@ -0,0 +1,61 @@
+/*************************************************************************
+ *
+ *  This file is part of ACT dataflow neuro library.
+ * It's the testing facility for cell_lib_std.act
+ *
+ *  Copyright (c) 2022 University of Groningen - Ole Richter  
+ *  Copyright (c) 2022 University of Groningen - Hugh Greatorex
+ *  Copyright (c) 2022 University of Groningen - Michele Mastella
+ *  Copyright (c) 2022 University of Groningen - Madison Cotteret
+ *
+ *  This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
+ *
+ *  You may redistribute and modify this documentation and make products
+ *  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
+ *  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
+ *  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
+ *  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
+ *  for applicable conditions.
+ *
+ *  Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
+ *
+ *  As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
+ *  these sources, You must maintain the Source Location visible in its
+ *  documentation.
+ *
+ **************************************************************************
+ */
+
+import "../../dataflow_neuro/coders.act";
+import "../../dataflow_neuro/primitives.act";
+
+import globals;
+import std::data;
+
+open std::data;
+
+
+open tmpl::dataflow_neuro;
+
+pint N = 7;
+pint Nc = std::ceil_log2(N);
+pint N_BUFFERS = 5;
+pint N_BD_DLY_CFG = 4;
+
+defproc texel_encoder1d_bd_sadc (a1of1 in[N]; bd<Nc> out; bool? dly_cfg[N_BD_DLY_CFG]) {
+
+    bool _reset_B;
+    prs {
+       Reset => _reset_B-
+    }
+    power supply;
+    supply.vdd = Vdd;
+    supply.vss = GND;
+    encoder1d_bd_sadc<Nc, N, N_BUFFERS, N_BD_DLY_CFG> c(.in = in, .out = out, .dly_cfg = dly_cfg,
+        .reset_B = _reset_B, .supply = supply);
+
+}
+
+
+// fifo_decoder_neurons_encoder_fifo e;
+texel_encoder1d_bd_sadc c; 

test/unit_tests/texel_encoder1d_bd_sadc/test.prsim

@@ -0,0 +1,82 @@
+watchall
+
+
+set c.dly_cfg[0] 1
+set c.dly_cfg[1] 1
+set c.dly_cfg[2] 1
+set c.dly_cfg[3] 1
+
+set c.in[0].r 1
+set c.in[1].r 1
+set c.in[2].r 1
+set c.in[3].r 1
+set c.in[4].r 1
+set c.in[5].r 1
+set c.in[6].r 1
+
+set c.out.a 0
+
+set Reset 1
+cycle
+status X
+system "echo '[] Set reset 0'"
+mode run
+set Reset 0
+cycle
+system "echo '[] Reset finished'"
+status X
+
+assert-bd-channel-neutral "c.out" 3
+
+assert c.in[0].a 1
+assert c.in[1].a 1
+assert c.in[2].a 1
+assert c.in[3].a 1
+assert c.in[4].a 1
+assert c.in[5].a 1
+assert c.in[6].a 1
+
+
+
+system "echo '[] Spiking 3'"
+set c.in[3].r 0
+cycle
+assert c.in[3].a 0
+set c.in[3].r 1
+cycle
+assert c.in[3].a 1
+
+
+system "echo '[] Spiking 6'"
+set c.in[6].r 0
+cycle
+assert c.in[6].a 0
+set c.in[6].r 1
+cycle
+assert c.in[6].a 1
+
+system "echo '[] Receive 3'"
+assert-bd-channel-valid "c.out" 3 3
+set c.out.a 1
+cycle
+assert-bd-channel-neutral "c.out" 3
+set c.out.a 0
+cycle
+
+system "echo '[] Receive 6'"
+assert-bd-channel-valid "c.out" 3 6
+set c.out.a 1
+cycle
+assert-bd-channel-neutral "c.out" 6
+set c.out.a 0
+cycle
+
+
+
+
+
+
+
+
+
+