bics/actlib_dataflow_neuro
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let delay fifos have N= 0, simplified nrn grids thusly

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alexmadison 2022-03-29 19:07:04 +02:00
parent 8b60b23214
commit 870da14ccd
2 changed files with 19 additions and 20 deletions
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32
dataflow_neuro/coders.act
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@ -604,23 +604,20 @@ namespace tmpl {
)
)
// Hacks to maybe construct some fifos, ignore.
[N_dly >= 1 ->
delay_fifo<N_dly> dly_x[Nx];
delay_fifo<N_dly> dly_y[Ny];
]
// Create delay fifos to emulate the fact that the line pull downs
// are at the end of the line, and thus slow.
// Note that if N_dly = 0, delay fifo is just a pipe.
delay_fifo<N_dly> dly_x[Nx];
delay_fifo<N_dly> dly_y[Ny];
// Create x line req pull downs
line_end_pull_down pd_x[Nx];
sigbuf<Nx> rsb_pd_x(.in = reset_B, .supply = supply);
(i:0..Nx-1:
[ N_dly = 0 ->
pd_x[i].in = _outx[i].a;
[] N_dly >= 1 ->
dly_x[i].supply = supply;
dly_x[i].in = _outx[i].a;
pd_x[i].in = dly_x[i].out;
]
dly_x[i].supply = supply;
dly_x[i].in = _outx[i].a;
pd_x[i].in = dly_x[i].out;
pd_x[i].out = _outx[i].r;
pd_x[i].reset_B = rsb_pd_x.out[i];
pd_x[i].supply = supply;
@ -630,13 +627,10 @@ namespace tmpl {
line_end_pull_down pd_y[Ny];
sigbuf<Ny> rsb_pd_y(.in = reset_B, .supply = supply);
(j:0..Ny-1:
[ N_dly = 0 ->
pd_y[j].in = _outy[j].a;
[] N_dly >= 1 ->
dly_y[j].supply = supply;
dly_y[j].in = _outy[j].a;
pd_y[j].in = dly_y[j].out;
]
dly_y[j].supply = supply;
dly_y[j].in = _outy[j].a;
pd_y[j].in = dly_y[j].out;
pd_y[j].out = _outy[j].r;
pd_y[j].reset_B = rsb_pd_y.out[j];
pd_y[j].supply = supply;

7
dataflow_neuro/primitives.act
View File

@ -690,8 +690,9 @@ namespace tmpl {
// Is useful for testing purposes.
// But should probably remove before running innovus etc.
export template<pint N>
defproc delay_fifo (bool! out; bool? in; power supply) {
defproc delay_fifo (bool out; bool in; power supply) {
{ N >= 0 : "What?" };
[N >= 1 ->
DLY4_X1 dly[N];
dly[0].vdd = supply.vdd;
@ -707,6 +708,10 @@ namespace tmpl {
dly[N-1].vdd = supply.vdd;
dly[N-1].vss = supply.vss;
dly[N-1].y = out;
[] N = 1 ->
in = out;
]
}