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added append, fixed bug in fifo

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alexmadison 2022-03-25 18:57:18 +01:00
parent 3587672e69
commit 8b44a11fd6
1 changed files with 59 additions and 1 deletions
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60
dataflow_neuro/primitives.act
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@ -165,7 +165,7 @@ namespace tmpl {
fifo_element[i].supply = supply;
fifo_element[i].reset_B = _reset_BXX[i];
)
fifo_element[N-1].out = out;
fifo_element[M-1].out = out;
// reset buffers
bool _reset_BX;
@ -697,6 +697,7 @@ namespace tmpl {
PULLUP_X4 pull_up(.a=nor_out, .y=out);
}
export
defproc line_end_pull_down (a1of1 in; bool? reset_B; power supply; bool! out)
{
bool _out, __out, nor_out;
@ -707,4 +708,61 @@ namespace tmpl {
PULLUP_X4 pull_down(.a=nor_out, .y=out);
}
/**
* Appends a hard-coded word "VAL" to an input.
* Works by piping through all sigs, but adding
* some extra sigs when the input is valid.
* N is size of channel to pipe through.
* NVAL is size of word to be put on output.
* VAL is word to be put on output.
*
*/
export template<pint N, NVAL, VAL>
defproc append (avMx1of2<N> in; avMx1of2<N+NVAL> out; power supply)
{
{ N >= 0 : "What?" };
{ NVAL >= 0 : "What?" };
{ NVAL < 1<<VAL : "VAL too big!" };
// valid tree
vtree<N> in_val(.supply = supply);
(i:N:
in_val.in.d[i].t = in.d.d[i].t;
in_val.in.d[i].f = in.d.d[i].f;
)
// wire through most signals
(i:N:
in.d.d[i].t = out.d.d[i].t;
in.d.d[i].f = out.d.d[i].f;
)
in.a = out.a;
in.v = out.v;
// appender
pint bitval;
sigbuf<NVAL> sb(.in = in_val.out, .supply = supply);
TIELO_X1 tielows[NVAL];
(i:NVAL:tielows[i].vss = supply.vss; tielows[i].vdd = supply.vdd;)
(i:0..NVAL-1:
bitval = (VAL & ( 1 << i )) >> i;
[ bitval = 1 ->
out.d.d[i+N].t = sb.out[i];
out.d.d[i+N].f = tielows[i].y;
[] bitval = 0 ->
out.d.d[i+N].f = sb.out[i];
out.d.d[i+N].t = tielows[i].y;
[] bitval >= 2 -> {false : "fuck"};
]
)
}
}}