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wrapped tex_dual_inov

This commit is contained in:
Greatorex 2022-05-02 15:12:21 +02:00
parent 28823c4bca
commit 8d7933bf9c
1 changed files with 99 additions and 4 deletions
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103
test/unit_tests/texel_dualcore_innovus/test.act
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@ -117,7 +117,8 @@ defproc chip_texel_dualcore_innovus (bd<N_IN> in, out;
bool? bd_dly_cfg[N_BD_DLY_CFG], bd_dly_cfg2[N_BD_DLY_CFG2];
bool? loopback_en;
bool? reset_B, reset_reg_B
bool? reset_B, reset_reg_B;
bool vss, vdd
){
// bool _reset_B;
@ -125,8 +126,8 @@ defproc chip_texel_dualcore_innovus (bd<N_IN> in, out;
// Reset => _reset_B-
// }
power supply;
supply.vdd = Vdd;
supply.vss = GND;
supply.vdd = vdd;
supply.vss = vss;
texel_dualcore<N_IN,
N_NRN_X, N_NRN_Y, N_SYN_X, N_SYN_Y,
@ -145,5 +146,99 @@ defproc chip_texel_dualcore_innovus (bd<N_IN> in, out;
}
defproc chip_texel_dualcore_innovus_test (bd<N_IN> in, out;
Mx1of2<REG_NCW> c1_reg_data[REG_M];
// a1of1 c1_synapses[N_SYN_X * N_SYN_Y];
// a1of1 c1_neurons[N_NRN_X * N_NRN_Y];
bool! c1_dec_req_x[N_SYN_X], c1_dec_req_y[N_SYN_Y];
bool? c1_dec_ackB[N_SYN_X];
a1of1 c1_syn_pu[N_SYN_X];
a1of1 c1_enc_inx[N_NRN_X], c1_enc_iny[N_NRN_Y];
a1of1 c1_nrn_pd_x[N_NRN_X], c1_nrn_pd_y[N_NRN_Y];
bool! c1_nrn_mon_x[N_NRN_MON_X], c1_nrn_mon_y[N_NRN_MON_Y];
bool! c1_syn_mon_x[N_SYN_MON_X], c1_syn_mon_y[N_SYN_MON_Y];
bool? c1_syn_mon_AMZI[N_SYN_X * N_MON_AMZO_PER_SYN], c1_nrn_mon_AMZI[N_NRN_X * N_MON_AMZO_PER_NRN];
bool! c1_syn_mon_AMZO[N_MON_AMZO_PER_SYN], c1_nrn_mon_AMZO[N_MON_AMZO_PER_NRN];
bool! c1_syn_flags_EFO[N_FLAGS_PER_SYN], c1_nrn_flags_EFO[N_FLAGS_PER_NRN];
Mx1of2<REG_NCW> c2_reg_data[REG_M];
// a1of1 c2_synapses[N_SYN_X * N_SYN_Y];
// a1of1 c2_neurons[N_NRN_X * N_NRN_Y];
bool! c2_dec_req_x[N_SYN_X], c2_dec_req_y[N_SYN_Y];
bool? c2_dec_ackB[N_SYN_X];
a1of1 c2_syn_pu[N_SYN_X];
a1of1 c2_enc_inx[N_NRN_X], c2_enc_iny[N_NRN_Y];
a1of1 c2_nrn_pd_x[N_NRN_X], c2_nrn_pd_y[N_NRN_Y];
bool! c2_nrn_mon_x[N_NRN_MON_X], c2_nrn_mon_y[N_NRN_MON_Y];
bool! c2_syn_mon_x[N_SYN_MON_X], c2_syn_mon_y[N_SYN_MON_Y];
bool? c2_syn_mon_AMZI[N_SYN_X * N_MON_AMZO_PER_SYN], c2_nrn_mon_AMZI[N_NRN_X * N_MON_AMZO_PER_NRN];
bool! c2_syn_mon_AMZO[N_MON_AMZO_PER_SYN], c2_nrn_mon_AMZO[N_MON_AMZO_PER_NRN];
bool! c2_syn_flags_EFO[N_FLAGS_PER_SYN], c2_nrn_flags_EFO[N_FLAGS_PER_NRN];
bool? bd_dly_cfg[N_BD_DLY_CFG], bd_dly_cfg2[N_BD_DLY_CFG2];
bool? loopback_en;
bool? reset_B, reset_reg_B
){
power supply;
supply.vdd = Vdd;
supply.vss = GND;
chip_texel_dualcore_innovus c(.in=in, .out=out,
.c1_reg_data=c1_reg_data,
// a1of1 c1_synapses[N_SYN_X * N_SYN_Y];
// a1of1 c1_neurons[N_NRN_X * N_NRN_Y];
.c1_dec_req_x=c1_dec_req_x, .c1_dec_req_y=c1_dec_req_y,
.c1_dec_ackB=c1_dec_ackB,
.c1_syn_pu=c1_syn_pu,
.c1_enc_inx=c1_enc_inx, .c1_enc_iny=c1_enc_iny,
.c1_nrn_pd_x=c1_nrn_pd_x, .c1_nrn_pd_y=c1_nrn_pd_y,
.c1_nrn_mon_x=c1_nrn_mon_x, .c1_nrn_mon_y=c1_nrn_mon_y,
.c1_syn_mon_x=c1_syn_mon_x, .c1_syn_mon_y=c1_syn_mon_y,
.c1_syn_mon_AMZI=c1_syn_mon_AMZI, .c1_nrn_mon_AMZI=c1_nrn_mon_AMZI,
.c1_syn_mon_AMZO=c1_syn_mon_AMZO, .c1_nrn_mon_AMZO=c1_nrn_mon_AMZO,
.c1_syn_flags_EFO=c1_syn_flags_EFO, .c1_nrn_flags_EFO=c1_nrn_flags_EFO,
.c2_reg_data=c2_reg_data,
// a1of1 c2_synapses[N_SYN_X * N_SYN_Y];
// a1of1 c2_neurons[N_NRN_X * N_NRN_Y];
.c2_dec_req_x=c2_dec_req_x, .c2_dec_req_y=c2_dec_req_y,
.c2_dec_ackB=c2_dec_ackB,
.c2_syn_pu=c2_syn_pu,
.c2_enc_inx=c2_enc_inx, .c2_enc_iny=c2_enc_iny,
.c2_nrn_pd_x=c2_nrn_pd_x, .c2_nrn_pd_y=c2_nrn_pd_y,
.c2_nrn_mon_x=c2_nrn_mon_x, .c2_nrn_mon_y=c2_nrn_mon_y,
.c2_syn_mon_x=c2_syn_mon_x, .c2_syn_mon_y=c2_syn_mon_y,
.c2_syn_mon_AMZI=c2_syn_mon_AMZI, .c2_nrn_mon_AMZI=c2_nrn_mon_AMZI,
.c2_syn_mon_AMZO=c2_syn_mon_AMZO, .c2_nrn_mon_AMZO=c2_nrn_mon_AMZO,
.c2_syn_flags_EFO=c2_syn_flags_EFO, .c2_nrn_flags_EFO=c2_nrn_flags_EFO,
.bd_dly_cfg=bd_dly_cfg, .bd_dly_cfg2=bd_dly_cfg2,
.loopback_en=loopback_en,
.reset_B=reset_B, .reset_reg_B=reset_reg_B,
.vss=supply.vss, .vdd=supply.vdd
);
}
// fifo_decoder_neurons_encoder_fifo e;
chip_texel_dualcore_innovus c;
chip_texel_dualcore_innovus_test c;