put fake PRs in tiehi/los lol

dataflow_neuro/cell_lib_std.act

@@ -27,14 +27,29 @@
 namespace tmpl {
   namespace dataflow_neuro {
 
+
+    // We have to add a pretend buffer in here
+    // to ensure that act2v doesn't simplify things
+    // and just connect y to vss/vdd lol
     export defproc TIELO_X1(bool! y; bool vdd, vss)
     {
-      y = vss;
+      bool _y, a;
+      a = vss;
+      prs {
+        a => _y-
+        _y => y-
+      }
+
     }
 
     export defproc TIEHI_X1(bool! y; bool vdd, vss)
     {
-      y = vdd;
+      bool _y, a;
+      a = vdd;
+      prs {
+        a => _y-
+        _y => y-
+      }      
     }
 
     /*-- inverters --*/