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Merge branch 'main' into dev

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Greatorex 2022-04-04 17:30:02 +02:00
parent ea3f91d6de 185a4b2d77
commit 8f67c42bdb
14 changed files with 19108 additions and 129 deletions
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76
dataflow_neuro/primitives.act
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@ -242,6 +242,7 @@ namespace tmpl {
OR2_X1 out_or(.a=out1.v, .b=out2.v, .y=_out_v,.vdd=supply.vdd,.vss=supply.vss);
A_3C_RB_X4 inack_ctl(.c1=_en,.c2=_in_c_v_,.c3=_out_v,.y=in.a,.pr_B=_reset_BX,.sr_B=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
cond.a = in.a;
cond.v = _in_c_v_;
A_1C1P_X1 en_ctl(.c1=in.a,.p1=_out_v,.y=_en,.vdd=supply.vdd,.vss=supply.vss);
BUF_X1 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
sigbuf<2*N> reset_bufarray(.in=_reset_BX, .out=_reset_BXX);
@ -428,7 +429,6 @@ namespace tmpl {
BUF_X1 c_buf_tk_inv(.a=cond_inv_t, .y=_c_tk_buf, .vss = supply.vss, .vdd = supply.vdd);
sigbuf<N> c_buf_d_inv(.in=cond_inv_f, .out=_c_d_buf, .supply=supply);
]
vtree<N> vc(.in=in.d,.out=_in_v,.supply=supply);
@ -844,12 +844,57 @@ defproc slice_data(avMx1of2<N> in; avMx1of2<std::min(N1,N)-std::max(N0,0)> out;
// {N0 >= 0 : "N0 can be minimum 0!"};
// {N1 <= N : "N1 can be maximum N"};
export template<pint N; pint CONDITION_BIT>
defproc demux_bit (avMx1of2<N+1> in; avMx1of2<N> out1; avMx1of2<N> out2; bool? reset_B; power supply)
{
demux<N> demux(.reset_B = reset_B, .out1=out1, .out2=out2);
pint _N1, _N0;
export template<pint N; pint CONDITION_BIT>
defproc demux_bit (avMx1of2<N+1> in; avMx1of2<N> out1; avMx1of2<N> out2; bool? reset_B; power supply)
{
demux<N> demux(.reset_B = reset_B, .out1=out1, .out2=out2);
in.d.d[CONDITION_BIT].f = demux.cond.d.d[0].f;
in.d.d[CONDITION_BIT].t = demux.cond.d.d[0].t;
_N1 = std::min(N1,N);
_N0 = std::max(N0,0);
in.d.d[CONDITION_BIT].f = demux.cond.d.d[0].f;
in.d.d[CONDITION_BIT].t = demux.cond.d.d[0].t;
in.v = demux.in.v;
in.a = demux.in.a;
BUF_X1 ack_buf(.a = out.a, .y = in.a, .vss = supply.vss, .vdd = supply.vdd);
in.v = demux.in.v;
in.a = demux.in.a;
(i:0..CONDITION_BIT:
in.d.d[i].f = demux.in.d.d[i].f;
in.d.d[i].t = demux.in.d.d[i].t;)
(i:CONDITION_BIT..N-1:
in.d.d[i].f = demux.in.d.d[i].f;
in.d.d[i].t = demux.in.d.d[i].t;)
}
export template<pint N>
defproc demux_bit_msb (avMx1of2<N+1> in; avMx1of2<N> out1; avMx1of2<N> out2; bool? reset_B; power supply)
{
demux<N> demux(.reset_B = reset_B, .out1=out1, .out2=out2);
in.d.d[N+1].f = demux.cond.d.d[0].f;
in.d.d[N+1].t = demux.cond.d.d[0].t;
in.v = demux.in.v;
in.a = demux.in.a;
(i:0..N:
in.d.d[i].f = demux.in.d.d[i].f;
in.d.d[i].t = demux.in.d.d[i].t;)
}
vtree<N> in_vt(.in = in.d, .out = in.v, .supply = supply);
(i:_N1-_N0:
@ -861,4 +906,33 @@ defproc slice_data(avMx1of2<N> in; avMx1of2<std::min(N1,N)-std::max(N0,0)> out;
(i:0..CONDITION_BIT:
in.d.d[i].f = demux.in.d.d[i].f;
in.d.d[i].t = demux.in.d.d[i].t;)
(i:CONDITION_BIT..N-1:
in.d.d[i].f = demux.in.d.d[i].f;
in.d.d[i].t = demux.in.d.d[i].t;)
}
export template<pint N>
defproc demux_bit_msb (avMx1of2<N+1> in; avMx1of2<N> out1; avMx1of2<N> out2; bool? reset_B; power supply)
{
demux<N> demux(.reset_B = reset_B, .out1=out1, .out2=out2);
in.d.d[N+1].f = demux.cond.d.d[0].f;
in.d.d[N+1].t = demux.cond.d.d[0].t;
in.v = demux.in.v;
in.a = demux.in.a;
(i:0..N:
in.d.d[i].f = demux.in.d.d[i].f;
in.d.d[i].t = demux.in.d.d[i].t;)
}
}}

685
test/unit_tests/buff.v Normal file
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@ -0,0 +1,685 @@
//
// Verilog module for: BUF_X6<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0BUF__X6(y, a);
output y;
input a;
// -- signals ---
wire a;
reg y;
reg _y;
// --- instances
endmodule
//
// Verilog module for: sigbuf<15>
//
module _0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4(in, \out[0] );
input in;
output \out[0] ;
// -- signals ---
reg \out[0] ;
wire in;
// --- instances
_0_0tmpl_0_0dataflow__neuro_0_0BUF__X6 \buf6 (.y(\out[0] ), .a(in));
endmodule
//
// Verilog module for: A_3C_RB_X4<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0A__3C__RB__X4(y, c1, c2, c3, pr_B, sr_B);
output y;
input c1;
input c2;
input c3;
input pr_B;
input sr_B;
// -- signals ---
wire pr_B;
wire c3;
wire c1;
wire sr_B;
wire c2;
reg _y;
reg y;
// --- instances
endmodule
//
// Verilog module for: BUF_X4<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0BUF__X4(y, a);
output y;
input a;
// -- signals ---
reg y;
wire a;
reg _y;
// --- instances
endmodule
//
// Verilog module for: INV_X1<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0INV__X1(y, a);
output y;
input a;
// -- signals ---
reg y;
wire a;
// --- instances
endmodule
//
// Verilog module for: A_2C_B_X1<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1(y, c1, c2);
output y;
input c1;
input c2;
// -- signals ---
wire c2;
wire c1;
reg y;
reg _y;
// --- instances
endmodule
//
// Verilog module for: A_3C_B_X1<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0A__3C__B__X1(y, c1, c2, c3);
output y;
input c1;
input c2;
input c3;
// -- signals ---
wire c1;
reg y;
reg _y;
wire c3;
wire c2;
// --- instances
endmodule
//
// Verilog module for: ctree<15>
//
module _0_0tmpl_0_0dataflow__neuro_0_0ctree_315_4(\in[0] , \in[1] , \in[2] , \in[3] , \in[4] , \in[5] , \in[6] , \in[7] , \in[8] , \in[9] , \in[10] , \in[11] , \in[12] , \in[13] , \in[14] , out);
input \in[0] ;
input \in[1] ;
input \in[2] ;
input \in[3] ;
input \in[4] ;
input \in[5] ;
input \in[6] ;
input \in[7] ;
input \in[8] ;
input \in[9] ;
input \in[10] ;
input \in[11] ;
input \in[12] ;
input \in[13] ;
input \in[14] ;
output out;
// -- signals ---
wire \in[9] ;
wire \in[11] ;
reg \tmp[18] ;
reg \tmp[16] ;
reg \tmp[24] ;
wire \in[0] ;
reg \tmp[22] ;
reg out;
wire \in[7] ;
reg \tmp[23] ;
wire \in[4] ;
wire \in[3] ;
wire \in[12] ;
reg \tmp[20] ;
wire \in[2] ;
reg \tmp[19] ;
wire \in[14] ;
wire \in[6] ;
wire \in[10] ;
wire \in[5] ;
wire \in[8] ;
wire \in[13] ;
wire \in[1] ;
reg \tmp[21] ;
reg \tmp[17] ;
reg \tmp[15] ;
// --- instances
_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[0] (.y(\tmp[15] ), .c1(\in[0] ), .c2(\in[1] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[1] (.y(\tmp[16] ), .c1(\in[2] ), .c2(\in[3] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[2] (.y(\tmp[17] ), .c1(\in[4] ), .c2(\in[5] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[3] (.y(\tmp[18] ), .c1(\in[6] ), .c2(\in[7] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[4] (.y(\tmp[19] ), .c1(\in[8] ), .c2(\in[9] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[5] (.y(\tmp[20] ), .c1(\in[10] ), .c2(\in[11] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[6] (.y(\tmp[22] ), .c1(\tmp[15] ), .c2(\tmp[16] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[7] (.y(\tmp[23] ), .c1(\tmp[17] ), .c2(\tmp[18] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__3C__B__X1 \C3Els[0] (.y(\tmp[21] ), .c1(\in[12] ), .c2(\in[13] ), .c3(\in[14] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__3C__B__X1 \C3Els[1] (.y(\tmp[24] ), .c1(\tmp[19] ), .c2(\tmp[20] ), .c3(\tmp[21] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__3C__B__X1 \C3Els[2] (.y(out), .c1(\tmp[22] ), .c2(\tmp[23] ), .c3(\tmp[24] ));
endmodule
//
// Verilog module for: OR2_X1<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0OR2__X1(y, a, b);
output y;
input a;
input b;
// -- signals ---
wire a;
wire b;
reg y;
reg _y;
// --- instances
endmodule
//
// Verilog module for: vtree<15>
//
module _0_0tmpl_0_0dataflow__neuro_0_0vtree_315_4(\in.d[0].d[0] , \in.d[0].d[1] , \in.d[1].d[0] , \in.d[1].d[1] , \in.d[2].d[0] , \in.d[2].d[1] , \in.d[3].d[0] , \in.d[3].d[1] , \in.d[4].d[0] , \in.d[4].d[1] , \in.d[5].d[0] , \in.d[5].d[1] , \in.d[6].d[0] , \in.d[6].d[1] , \in.d[7].d[0] , \in.d[7].d[1] , \in.d[8].d[0] , \in.d[8].d[1] , \in.d[9].d[0] , \in.d[9].d[1] , \in.d[10].d[0] , \in.d[10].d[1] , \in.d[11].d[0] , \in.d[11].d[1] , \in.d[12].d[0] , \in.d[12].d[1] , \in.d[13].d[0] , \in.d[13].d[1] , \in.d[14].d[0] , \in.d[14].d[1] , out);
input \in.d[0].d[0] ;
input \in.d[0].d[1] ;
input \in.d[1].d[0] ;
input \in.d[1].d[1] ;
input \in.d[2].d[0] ;
input \in.d[2].d[1] ;
input \in.d[3].d[0] ;
input \in.d[3].d[1] ;
input \in.d[4].d[0] ;
input \in.d[4].d[1] ;
input \in.d[5].d[0] ;
input \in.d[5].d[1] ;
input \in.d[6].d[0] ;
input \in.d[6].d[1] ;
input \in.d[7].d[0] ;
input \in.d[7].d[1] ;
input \in.d[8].d[0] ;
input \in.d[8].d[1] ;
input \in.d[9].d[0] ;
input \in.d[9].d[1] ;
input \in.d[10].d[0] ;
input \in.d[10].d[1] ;
input \in.d[11].d[0] ;
input \in.d[11].d[1] ;
input \in.d[12].d[0] ;
input \in.d[12].d[1] ;
input \in.d[13].d[0] ;
input \in.d[13].d[1] ;
input \in.d[14].d[0] ;
input \in.d[14].d[1] ;
output out;
// -- signals ---
wire \in.d[2].d[1] ;
wire \in.d[14].d[1] ;
reg \ct.in[8] ;
wire \in.d[10].d[1] ;
wire \in.d[7].d[1] ;
reg \ct.in[14] ;
wire \in.d[3].d[0] ;
reg \ct.in[0] ;
wire \in.d[8].d[1] ;
wire \in.d[6].d[1] ;
reg out;
wire \in.d[14].d[0] ;
wire \in.d[6].d[0] ;
wire \in.d[10].d[0] ;
wire \in.d[5].d[1] ;
wire \in.d[7].d[0] ;
wire \in.d[3].d[1] ;
wire \in.d[2].d[0] ;
reg \ct.in[6] ;
reg \ct.in[4] ;
wire \in.d[5].d[0] ;
wire \in.d[1].d[1] ;
wire \in.d[0].d[1] ;
reg \ct.in[5] ;
reg \ct.in[1] ;
wire \in.d[9].d[0] ;
wire \in.d[0].d[0] ;
wire \in.d[4].d[1] ;
reg \ct.in[12] ;
wire \in.d[12].d[1] ;
wire \in.d[8].d[0] ;
reg \ct.in[2] ;
wire \in.d[13].d[0] ;
wire \in.d[4].d[0] ;
wire \in.d[12].d[0] ;
wire \in.d[11].d[0] ;
wire \in.d[13].d[1] ;
reg \ct.in[9] ;
reg \ct.in[3] ;
reg \ct.in[11] ;
wire \in.d[1].d[0] ;
reg \ct.in[7] ;
wire \in.d[11].d[1] ;
wire \in.d[9].d[1] ;
reg \ct.in[10] ;
reg \ct.in[13] ;
// --- instances
_0_0tmpl_0_0dataflow__neuro_0_0ctree_315_4 \ct (.\in[0] (\ct.in[0] ), .\in[1] (\ct.in[1] ), .\in[2] (\ct.in[2] ), .\in[3] (\ct.in[3] ), .\in[4] (\ct.in[4] ), .\in[5] (\ct.in[5] ), .\in[6] (\ct.in[6] ), .\in[7] (\ct.in[7] ), .\in[8] (\ct.in[8] ), .\in[9] (\ct.in[9] ), .\in[10] (\ct.in[10] ), .\in[11] (\ct.in[11] ), .\in[12] (\ct.in[12] ), .\in[13] (\ct.in[13] ), .\in[14] (\ct.in[14] ), .out(out));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[0] (.y(\ct.in[0] ), .a(\in.d[0].d[1] ), .b(\in.d[0].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[1] (.y(\ct.in[1] ), .a(\in.d[1].d[1] ), .b(\in.d[1].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[2] (.y(\ct.in[2] ), .a(\in.d[2].d[1] ), .b(\in.d[2].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[3] (.y(\ct.in[3] ), .a(\in.d[3].d[1] ), .b(\in.d[3].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[4] (.y(\ct.in[4] ), .a(\in.d[4].d[1] ), .b(\in.d[4].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[5] (.y(\ct.in[5] ), .a(\in.d[5].d[1] ), .b(\in.d[5].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[6] (.y(\ct.in[6] ), .a(\in.d[6].d[1] ), .b(\in.d[6].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[7] (.y(\ct.in[7] ), .a(\in.d[7].d[1] ), .b(\in.d[7].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[8] (.y(\ct.in[8] ), .a(\in.d[8].d[1] ), .b(\in.d[8].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[9] (.y(\ct.in[9] ), .a(\in.d[9].d[1] ), .b(\in.d[9].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[10] (.y(\ct.in[10] ), .a(\in.d[10].d[1] ), .b(\in.d[10].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[11] (.y(\ct.in[11] ), .a(\in.d[11].d[1] ), .b(\in.d[11].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[12] (.y(\ct.in[12] ), .a(\in.d[12].d[1] ), .b(\in.d[12].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[13] (.y(\ct.in[13] ), .a(\in.d[13].d[1] ), .b(\in.d[13].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[14] (.y(\ct.in[14] ), .a(\in.d[14].d[1] ), .b(\in.d[14].d[0] ));
endmodule
//
// Verilog module for: A_1C1P_X1<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0A__1C1P__X1(y, c1, p1);
output y;
input c1;
input p1;
// -- signals ---
wire c1;
wire p1;
reg y;
// --- instances
endmodule
//
// Verilog module for: BUF_X1<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0BUF__X1(y, a);
output y;
input a;
// -- signals ---
reg y;
wire a;
reg _y;
// --- instances
endmodule
//
// Verilog module for: A_2C1N_RB_X4<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4(y, c1, c2, n1, pr_B, sr_B);
output y;
input c1;
input c2;
input n1;
input pr_B;
input sr_B;
// -- signals ---
reg y;
wire n1;
wire sr_B;
wire pr_B;
wire c2;
wire c1;
reg _y;
// --- instances
endmodule
//
// Verilog module for: buffer<15>
//
module _0_0tmpl_0_0dataflow__neuro_0_0buffer_315_4(\in.d.d[0].d[0] , \in.d.d[0].d[1] , \in.d.d[1].d[0] , \in.d.d[1].d[1] , \in.d.d[2].d[0] , \in.d.d[2].d[1] , \in.d.d[3].d[0] , \in.d.d[3].d[1] , \in.d.d[4].d[0] , \in.d.d[4].d[1] , \in.d.d[5].d[0] , \in.d.d[5].d[1] , \in.d.d[6].d[0] , \in.d.d[6].d[1] , \in.d.d[7].d[0] , \in.d.d[7].d[1] , \in.d.d[8].d[0] , \in.d.d[8].d[1] , \in.d.d[9].d[0] , \in.d.d[9].d[1] , \in.d.d[10].d[0] , \in.d.d[10].d[1] , \in.d.d[11].d[0] , \in.d.d[11].d[1] , \in.d.d[12].d[0] , \in.d.d[12].d[1] , \in.d.d[13].d[0] , \in.d.d[13].d[1] , \in.d.d[14].d[0] , \in.d.d[14].d[1] , \in.a , \in.v , \out.d.d[0].d[0] , \out.d.d[0].d[1] , \out.d.d[1].d[0] , \out.d.d[1].d[1] , \out.d.d[2].d[0] , \out.d.d[2].d[1] , \out.d.d[3].d[0] , \out.d.d[3].d[1] , \out.d.d[4].d[0] , \out.d.d[4].d[1] , \out.d.d[5].d[0] , \out.d.d[5].d[1] , \out.d.d[6].d[0] , \out.d.d[6].d[1] , \out.d.d[7].d[0] , \out.d.d[7].d[1] , \out.d.d[8].d[0] , \out.d.d[8].d[1] , \out.d.d[9].d[0] , \out.d.d[9].d[1] , \out.d.d[10].d[0] , \out.d.d[10].d[1] , \out.d.d[11].d[0] , \out.d.d[11].d[1] , \out.d.d[12].d[0] , \out.d.d[12].d[1] , \out.d.d[13].d[0] , \out.d.d[13].d[1] , \out.d.d[14].d[0] , \out.d.d[14].d[1] , \out.a , \out.v , reset_B);
input \in.d.d[0].d[0] ;
input \in.d.d[0].d[1] ;
input \in.d.d[1].d[0] ;
input \in.d.d[1].d[1] ;
input \in.d.d[2].d[0] ;
input \in.d.d[2].d[1] ;
input \in.d.d[3].d[0] ;
input \in.d.d[3].d[1] ;
input \in.d.d[4].d[0] ;
input \in.d.d[4].d[1] ;
input \in.d.d[5].d[0] ;
input \in.d.d[5].d[1] ;
input \in.d.d[6].d[0] ;
input \in.d.d[6].d[1] ;
input \in.d.d[7].d[0] ;
input \in.d.d[7].d[1] ;
input \in.d.d[8].d[0] ;
input \in.d.d[8].d[1] ;
input \in.d.d[9].d[0] ;
input \in.d.d[9].d[1] ;
input \in.d.d[10].d[0] ;
input \in.d.d[10].d[1] ;
input \in.d.d[11].d[0] ;
input \in.d.d[11].d[1] ;
input \in.d.d[12].d[0] ;
input \in.d.d[12].d[1] ;
input \in.d.d[13].d[0] ;
input \in.d.d[13].d[1] ;
input \in.d.d[14].d[0] ;
input \in.d.d[14].d[1] ;
output \in.a ;
output \in.v ;
output \out.d.d[0].d[0] ;
output \out.d.d[0].d[1] ;
output \out.d.d[1].d[0] ;
output \out.d.d[1].d[1] ;
output \out.d.d[2].d[0] ;
output \out.d.d[2].d[1] ;
output \out.d.d[3].d[0] ;
output \out.d.d[3].d[1] ;
output \out.d.d[4].d[0] ;
output \out.d.d[4].d[1] ;
output \out.d.d[5].d[0] ;
output \out.d.d[5].d[1] ;
output \out.d.d[6].d[0] ;
output \out.d.d[6].d[1] ;
output \out.d.d[7].d[0] ;
output \out.d.d[7].d[1] ;
output \out.d.d[8].d[0] ;
output \out.d.d[8].d[1] ;
output \out.d.d[9].d[0] ;
output \out.d.d[9].d[1] ;
output \out.d.d[10].d[0] ;
output \out.d.d[10].d[1] ;
output \out.d.d[11].d[0] ;
output \out.d.d[11].d[1] ;
output \out.d.d[12].d[0] ;
output \out.d.d[12].d[1] ;
output \out.d.d[13].d[0] ;
output \out.d.d[13].d[1] ;
output \out.d.d[14].d[0] ;
output \out.d.d[14].d[1] ;
input \out.a ;
input \out.v ;
input reset_B;
// -- signals ---
wire \in.d.d[9].d[0] ;
reg _out_a_B;
reg \out.d.d[1].d[0] ;
wire \in.d.d[4].d[0] ;
wire \in.d.d[14].d[0] ;
wire \in.d.d[10].d[1] ;
reg \out.d.d[14].d[1] ;
wire \in.d.d[8].d[1] ;
reg \out.d.d[7].d[0] ;
reg \out.d.d[2].d[1] ;
wire \in.d.d[3].d[1] ;
reg \out.d.d[10].d[0] ;
wire \in.d.d[9].d[1] ;
wire \in.d.d[5].d[0] ;
wire \out.v ;
reg \out.d.d[0].d[0] ;
reg \out.d.d[1].d[1] ;
wire \in.d.d[7].d[0] ;
reg \out.d.d[8].d[1] ;
reg \out.d.d[4].d[1] ;
reg _reset_BX;
reg \in.v ;
reg \out.d.d[6].d[0] ;
reg \out.d.d[8].d[0] ;
reg \out.d.d[12].d[0] ;
reg \out.d.d[5].d[0] ;
reg \out.d.d[10].d[1] ;
reg \out.d.d[9].d[1] ;
reg \out.d.d[7].d[1] ;
reg \out.d.d[3].d[0] ;
wire \in.d.d[8].d[0] ;
wire \in.d.d[6].d[0] ;
wire \in.d.d[5].d[1] ;
reg _en;
reg \_out_a_BX_f[0] ;
reg \out.d.d[9].d[0] ;
wire \in.d.d[13].d[1] ;
reg \out.d.d[11].d[0] ;
wire \in.d.d[12].d[0] ;
wire \in.d.d[11].d[0] ;
wire \in.d.d[1].d[1] ;
wire \in.d.d[1].d[0] ;
wire \in.d.d[14].d[1] ;
wire \in.d.d[4].d[1] ;
reg _in_v;
reg \out.d.d[13].d[0] ;
reg \out.d.d[2].d[0] ;
wire \in.d.d[13].d[0] ;
wire \in.d.d[3].d[0] ;
wire \in.d.d[2].d[1] ;
reg \in.a ;
reg \out.d.d[5].d[1] ;
reg \out.d.d[3].d[1] ;
reg \_out_a_BX_t[0] ;
wire \in.d.d[2].d[0] ;
reg \out.d.d[6].d[1] ;
reg \out.d.d[0].d[1] ;
wire \in.d.d[0].d[0] ;
reg \out.d.d[14].d[0] ;
reg \out.d.d[11].d[1] ;
reg \_en_X_t[0] ;
wire \in.d.d[10].d[0] ;
wire \out.a ;
reg \out.d.d[12].d[1] ;
wire reset_B;
wire \in.d.d[7].d[1] ;
wire \in.d.d[6].d[1] ;
wire \in.d.d[12].d[1] ;
wire \in.d.d[0].d[1] ;
wire \in.d.d[11].d[1] ;
reg \_reset_BXX[0] ;
reg \out.d.d[4].d[0] ;
reg \out.d.d[13].d[1] ;
reg \_en_X_f[0] ;
// --- instances
_0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 \out_a_B_buf_t (.in(_out_a_B), .\out[0] (\_out_a_BX_f[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__3C__RB__X4 \inack_ctl (.y(\in.a ), .c1(_en), .c2(\in.v ), .c3(\out.v ), .pr_B(_reset_BX), .sr_B(_reset_BX));
_0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 \reset_bufarray (.in(_reset_BX), .\out[0] (\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0BUF__X4 \in_v_buf (.y(\in.v ), .a(_in_v));
_0_0tmpl_0_0dataflow__neuro_0_0INV__X1 \out_a_inv (.y(_out_a_B), .a(\out.a ));
_0_0tmpl_0_0dataflow__neuro_0_0vtree_315_4 \vc (.\in.d[0].d[0] (\in.d.d[0].d[0] ), .\in.d[0].d[1] (\in.d.d[0].d[1] ), .\in.d[1].d[0] (\in.d.d[1].d[0] ), .\in.d[1].d[1] (\in.d.d[1].d[1] ), .\in.d[2].d[0] (\in.d.d[2].d[0] ), .\in.d[2].d[1] (\in.d.d[2].d[1] ), .\in.d[3].d[0] (\in.d.d[3].d[0] ), .\in.d[3].d[1] (\in.d.d[3].d[1] ), .\in.d[4].d[0] (\in.d.d[4].d[0] ), .\in.d[4].d[1] (\in.d.d[4].d[1] ), .\in.d[5].d[0] (\in.d.d[5].d[0] ), .\in.d[5].d[1] (\in.d.d[5].d[1] ), .\in.d[6].d[0] (\in.d.d[6].d[0] ), .\in.d[6].d[1] (\in.d.d[6].d[1] ), .\in.d[7].d[0] (\in.d.d[7].d[0] ), .\in.d[7].d[1] (\in.d.d[7].d[1] ), .\in.d[8].d[0] (\in.d.d[8].d[0] ), .\in.d[8].d[1] (\in.d.d[8].d[1] ), .\in.d[9].d[0] (\in.d.d[9].d[0] ), .\in.d[9].d[1] (\in.d.d[9].d[1] ), .\in.d[10].d[0] (\in.d.d[10].d[0] ), .\in.d[10].d[1] (\in.d.d[10].d[1] ), .\in.d[11].d[0] (\in.d.d[11].d[0] ), .\in.d[11].d[1] (\in.d.d[11].d[1] ), .\in.d[12].d[0] (\in.d.d[12].d[0] ), .\in.d[12].d[1] (\in.d.d[12].d[1] ), .\in.d[13].d[0] (\in.d.d[13].d[0] ), .\in.d[13].d[1] (\in.d.d[13].d[1] ), .\in.d[14].d[0] (\in.d.d[14].d[0] ), .\in.d[14].d[1] (\in.d.d[14].d[1] ), .out(_in_v));
_0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 \out_a_B_buf_f (.in(_out_a_B), .\out[0] (\_out_a_BX_t[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__1C1P__X1 \en_ctl (.y(_en), .c1(\in.a ), .p1(\out.v ));
_0_0tmpl_0_0dataflow__neuro_0_0BUF__X1 \reset_buf (.y(_reset_BX), .a(reset_B));
_0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 \en_buf_f (.in(_en), .\out[0] (\_en_X_f[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 \en_buf_t (.in(_en), .\out[0] (\_en_X_t[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[0] (.y(\out.d.d[0].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[0].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[1] (.y(\out.d.d[1].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[1].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[2] (.y(\out.d.d[2].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[2].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[3] (.y(\out.d.d[3].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[3].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[4] (.y(\out.d.d[4].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[4].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[5] (.y(\out.d.d[5].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[5].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[6] (.y(\out.d.d[6].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[6].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[7] (.y(\out.d.d[7].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[7].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[8] (.y(\out.d.d[8].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[8].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[9] (.y(\out.d.d[9].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[9].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[10] (.y(\out.d.d[10].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[10].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[11] (.y(\out.d.d[11].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[11].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[12] (.y(\out.d.d[12].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[12].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[13] (.y(\out.d.d[13].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[13].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[14] (.y(\out.d.d[14].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[14].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[0] (.y(\out.d.d[0].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[0].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[1] (.y(\out.d.d[1].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[1].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[2] (.y(\out.d.d[2].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[2].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[3] (.y(\out.d.d[3].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[3].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[4] (.y(\out.d.d[4].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[4].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[5] (.y(\out.d.d[5].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[5].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[6] (.y(\out.d.d[6].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[6].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[7] (.y(\out.d.d[7].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[7].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[8] (.y(\out.d.d[8].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[8].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[9] (.y(\out.d.d[9].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[9].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[10] (.y(\out.d.d[10].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[10].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[11] (.y(\out.d.d[11].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[11].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[12] (.y(\out.d.d[12].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[12].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[13] (.y(\out.d.d[13].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[13].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[14] (.y(\out.d.d[14].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[14].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
endmodule
//
// Verilog module for: buffer_15<>
//
module buffer__15(\in.d.d[0].d[0] , \in.d.d[0].d[1] , \in.d.d[1].d[0] , \in.d.d[1].d[1] , \in.d.d[2].d[0] , \in.d.d[2].d[1] , \in.d.d[3].d[0] , \in.d.d[3].d[1] , \in.d.d[4].d[0] , \in.d.d[4].d[1] , \in.d.d[5].d[0] , \in.d.d[5].d[1] , \in.d.d[6].d[0] , \in.d.d[6].d[1] , \in.d.d[7].d[0] , \in.d.d[7].d[1] , \in.d.d[8].d[0] , \in.d.d[8].d[1] , \in.d.d[9].d[0] , \in.d.d[9].d[1] , \in.d.d[10].d[0] , \in.d.d[10].d[1] , \in.d.d[11].d[0] , \in.d.d[11].d[1] , \in.d.d[12].d[0] , \in.d.d[12].d[1] , \in.d.d[13].d[0] , \in.d.d[13].d[1] , \in.d.d[14].d[0] , \in.d.d[14].d[1] , \in.a , \in.v , \out.d.d[0].d[0] , \out.d.d[0].d[1] , \out.d.d[1].d[0] , \out.d.d[1].d[1] , \out.d.d[2].d[0] , \out.d.d[2].d[1] , \out.d.d[3].d[0] , \out.d.d[3].d[1] , \out.d.d[4].d[0] , \out.d.d[4].d[1] , \out.d.d[5].d[0] , \out.d.d[5].d[1] , \out.d.d[6].d[0] , \out.d.d[6].d[1] , \out.d.d[7].d[0] , \out.d.d[7].d[1] , \out.d.d[8].d[0] , \out.d.d[8].d[1] , \out.d.d[9].d[0] , \out.d.d[9].d[1] , \out.d.d[10].d[0] , \out.d.d[10].d[1] , \out.d.d[11].d[0] , \out.d.d[11].d[1] , \out.d.d[12].d[0] , \out.d.d[12].d[1] , \out.d.d[13].d[0] , \out.d.d[13].d[1] , \out.d.d[14].d[0] , \out.d.d[14].d[1] , \out.a , \out.v );
input \in.d.d[0].d[0] ;
input \in.d.d[0].d[1] ;
input \in.d.d[1].d[0] ;
input \in.d.d[1].d[1] ;
input \in.d.d[2].d[0] ;
input \in.d.d[2].d[1] ;
input \in.d.d[3].d[0] ;
input \in.d.d[3].d[1] ;
input \in.d.d[4].d[0] ;
input \in.d.d[4].d[1] ;
input \in.d.d[5].d[0] ;
input \in.d.d[5].d[1] ;
input \in.d.d[6].d[0] ;
input \in.d.d[6].d[1] ;
input \in.d.d[7].d[0] ;
input \in.d.d[7].d[1] ;
input \in.d.d[8].d[0] ;
input \in.d.d[8].d[1] ;
input \in.d.d[9].d[0] ;
input \in.d.d[9].d[1] ;
input \in.d.d[10].d[0] ;
input \in.d.d[10].d[1] ;
input \in.d.d[11].d[0] ;
input \in.d.d[11].d[1] ;
input \in.d.d[12].d[0] ;
input \in.d.d[12].d[1] ;
input \in.d.d[13].d[0] ;
input \in.d.d[13].d[1] ;
input \in.d.d[14].d[0] ;
input \in.d.d[14].d[1] ;
output \in.a ;
output \in.v ;
output \out.d.d[0].d[0] ;
output \out.d.d[0].d[1] ;
output \out.d.d[1].d[0] ;
output \out.d.d[1].d[1] ;
output \out.d.d[2].d[0] ;
output \out.d.d[2].d[1] ;
output \out.d.d[3].d[0] ;
output \out.d.d[3].d[1] ;
output \out.d.d[4].d[0] ;
output \out.d.d[4].d[1] ;
output \out.d.d[5].d[0] ;
output \out.d.d[5].d[1] ;
output \out.d.d[6].d[0] ;
output \out.d.d[6].d[1] ;
output \out.d.d[7].d[0] ;
output \out.d.d[7].d[1] ;
output \out.d.d[8].d[0] ;
output \out.d.d[8].d[1] ;
output \out.d.d[9].d[0] ;
output \out.d.d[9].d[1] ;
output \out.d.d[10].d[0] ;
output \out.d.d[10].d[1] ;
output \out.d.d[11].d[0] ;
output \out.d.d[11].d[1] ;
output \out.d.d[12].d[0] ;
output \out.d.d[12].d[1] ;
output \out.d.d[13].d[0] ;
output \out.d.d[13].d[1] ;
output \out.d.d[14].d[0] ;
output \out.d.d[14].d[1] ;
input \out.a ;
input \out.v ;
// -- signals ---
reg \out.d.d[2].d[0] ;
reg \out.d.d[14].d[1] ;
reg \out.d.d[4].d[0] ;
reg \out.d.d[0].d[1] ;
wire \in.d.d[8].d[1] ;
wire \in.d.d[7].d[0] ;
wire \in.d.d[1].d[0] ;
reg _reset_B;
reg \out.d.d[6].d[1] ;
reg \out.d.d[5].d[0] ;
reg \out.d.d[11].d[1] ;
reg \out.d.d[6].d[0] ;
reg \out.d.d[12].d[0] ;
wire \in.d.d[2].d[1] ;
wire \in.d.d[14].d[1] ;
wire \in.d.d[13].d[0] ;
wire \in.d.d[5].d[0] ;
wire \in.d.d[4].d[0] ;
reg \out.d.d[5].d[1] ;
reg \out.d.d[3].d[0] ;
wire \in.d.d[10].d[0] ;
wire \in.d.d[3].d[1] ;
wire \in.d.d[11].d[0] ;
reg \out.d.d[0].d[0] ;
reg \out.d.d[2].d[1] ;
wire \in.d.d[9].d[0] ;
wire \in.d.d[2].d[0] ;
wire \in.d.d[6].d[0] ;
wire \in.d.d[4].d[1] ;
wire \in.d.d[1].d[1] ;
reg \out.d.d[13].d[1] ;
reg \out.d.d[1].d[1] ;
reg \out.d.d[10].d[1] ;
wire \in.d.d[11].d[1] ;
wire \in.d.d[5].d[1] ;
reg \out.d.d[9].d[1] ;
wire \in.d.d[3].d[0] ;
wire \in.d.d[0].d[1] ;
wire \out.v ;
wire \in.d.d[12].d[0] ;
reg \out.d.d[3].d[1] ;
reg \out.d.d[7].d[1] ;
reg \out.d.d[14].d[0] ;
reg \out.d.d[11].d[0] ;
reg \out.d.d[4].d[1] ;
wire \in.d.d[9].d[1] ;
wire \in.d.d[7].d[1] ;
wire \out.a ;
reg \in.a ;
wire \in.d.d[13].d[1] ;
wire \in.d.d[10].d[1] ;
reg \out.d.d[12].d[1] ;
reg \out.d.d[10].d[0] ;
reg \out.d.d[1].d[0] ;
wire \in.d.d[6].d[1] ;
reg \in.v ;
wire \in.d.d[14].d[0] ;
reg \out.d.d[13].d[0] ;
wire \in.d.d[12].d[1] ;
reg \out.d.d[8].d[1] ;
reg \out.d.d[8].d[0] ;
reg \out.d.d[7].d[0] ;
reg \out.d.d[9].d[0] ;
wire \in.d.d[8].d[0] ;
wire \in.d.d[0].d[0] ;
// --- instances
_0_0tmpl_0_0dataflow__neuro_0_0buffer_315_4 \buffer_test (.\in.d.d[0].d[0] (\in.d.d[0].d[0] ), .\in.d.d[0].d[1] (\in.d.d[0].d[1] ), .\in.d.d[1].d[0] (\in.d.d[1].d[0] ), .\in.d.d[1].d[1] (\in.d.d[1].d[1] ), .\in.d.d[2].d[0] (\in.d.d[2].d[0] ), .\in.d.d[2].d[1] (\in.d.d[2].d[1] ), .\in.d.d[3].d[0] (\in.d.d[3].d[0] ), .\in.d.d[3].d[1] (\in.d.d[3].d[1] ), .\in.d.d[4].d[0] (\in.d.d[4].d[0] ), .\in.d.d[4].d[1] (\in.d.d[4].d[1] ), .\in.d.d[5].d[0] (\in.d.d[5].d[0] ), .\in.d.d[5].d[1] (\in.d.d[5].d[1] ), .\in.d.d[6].d[0] (\in.d.d[6].d[0] ), .\in.d.d[6].d[1] (\in.d.d[6].d[1] ), .\in.d.d[7].d[0] (\in.d.d[7].d[0] ), .\in.d.d[7].d[1] (\in.d.d[7].d[1] ), .\in.d.d[8].d[0] (\in.d.d[8].d[0] ), .\in.d.d[8].d[1] (\in.d.d[8].d[1] ), .\in.d.d[9].d[0] (\in.d.d[9].d[0] ), .\in.d.d[9].d[1] (\in.d.d[9].d[1] ), .\in.d.d[10].d[0] (\in.d.d[10].d[0] ), .\in.d.d[10].d[1] (\in.d.d[10].d[1] ), .\in.d.d[11].d[0] (\in.d.d[11].d[0] ), .\in.d.d[11].d[1] (\in.d.d[11].d[1] ), .\in.d.d[12].d[0] (\in.d.d[12].d[0] ), .\in.d.d[12].d[1] (\in.d.d[12].d[1] ), .\in.d.d[13].d[0] (\in.d.d[13].d[0] ), .\in.d.d[13].d[1] (\in.d.d[13].d[1] ), .\in.d.d[14].d[0] (\in.d.d[14].d[0] ), .\in.d.d[14].d[1] (\in.d.d[14].d[1] ), .\in.a (\in.a ), .\in.v (\in.v ), .\out.d.d[0].d[0] (\out.d.d[0].d[0] ), .\out.d.d[0].d[1] (\out.d.d[0].d[1] ), .\out.d.d[1].d[0] (\out.d.d[1].d[0] ), .\out.d.d[1].d[1] (\out.d.d[1].d[1] ), .\out.d.d[2].d[0] (\out.d.d[2].d[0] ), .\out.d.d[2].d[1] (\out.d.d[2].d[1] ), .\out.d.d[3].d[0] (\out.d.d[3].d[0] ), .\out.d.d[3].d[1] (\out.d.d[3].d[1] ), .\out.d.d[4].d[0] (\out.d.d[4].d[0] ), .\out.d.d[4].d[1] (\out.d.d[4].d[1] ), .\out.d.d[5].d[0] (\out.d.d[5].d[0] ), .\out.d.d[5].d[1] (\out.d.d[5].d[1] ), .\out.d.d[6].d[0] (\out.d.d[6].d[0] ), .\out.d.d[6].d[1] (\out.d.d[6].d[1] ), .\out.d.d[7].d[0] (\out.d.d[7].d[0] ), .\out.d.d[7].d[1] (\out.d.d[7].d[1] ), .\out.d.d[8].d[0] (\out.d.d[8].d[0] ), .\out.d.d[8].d[1] (\out.d.d[8].d[1] ), .\out.d.d[9].d[0] (\out.d.d[9].d[0] ), .\out.d.d[9].d[1] (\out.d.d[9].d[1] ), .\out.d.d[10].d[0] (\out.d.d[10].d[0] ), .\out.d.d[10].d[1] (\out.d.d[10].d[1] ), .\out.d.d[11].d[0] (\out.d.d[11].d[0] ), .\out.d.d[11].d[1] (\out.d.d[11].d[1] ), .\out.d.d[12].d[0] (\out.d.d[12].d[0] ), .\out.d.d[12].d[1] (\out.d.d[12].d[1] ), .\out.d.d[13].d[0] (\out.d.d[13].d[0] ), .\out.d.d[13].d[1] (\out.d.d[13].d[1] ), .\out.d.d[14].d[0] (\out.d.d[14].d[0] ), .\out.d.d[14].d[1] (\out.d.d[14].d[1] ), .\out.a (\out.a ), .\out.v (\out.v ), .reset_B(_reset_B));
endmodule

160
test/unit_tests/demux_7/run/prsim.out
View File

@ -1,4 +1,4 @@
my_demux.my_demux._c_f_buf[0] my_demux.my_demux._out1_a_BX_f[0] my_demux.my_demux.out1_f_buf_func[1].n1 my_demux.my_demux._en my_demux.my_demux._en2_X_t[0] my_demux.my_demux.vc.OR2_tf[2]._y my_demux.my_demux.out1_f_buf_func[5].n1 my_demux.my_demux.out1_t_buf_func[2].n1 my_demux.my_demux._c_t_buf[0] my_demux.my_demux._out2_a_BX_t[0] my_demux.my_demux.out1_f_buf_func[6].n1 my_demux.my_demux.out1_t_buf_func[4].n1 my_demux.my_demux._out1_a_B my_demux.my_demux.vc.tmp[9] my_demux.my_demux._out1_a_BX_t[0] my_demux.my_demux._en1_X_t[0] my_demux.my_demux.c_buf_f.in my_demux.my_demux.vc.tmp[7] my_demux.my_demux._out2_a_BX_f[0] my_demux.my_demux._en2_X_f[0] my_demux.my_demux.c_buf_t.in my_demux.my_demux.out1_t_buf_func[1].n1 my_demux.my_demux.out1_f_buf_func[0].n1 my_demux.out1.a my_demux.my_demux.out1_t_buf_func[0].n1 my_demux.my_demux.out1_f_buf_func[2].n1 my_demux.my_demux.c_buf_t.buf2._y my_demux.my_demux.vc.C2Els[1]._y my_demux.my_demux._en1_X_f[0] my_demux.my_demux.out1_f_buf_func[4].n1 my_demux.my_demux.vc.tmp[6] my_demux.my_demux.vc.tmp[1] my_demux.my_demux.out_or._y my_demux.my_demux.out1_f_buf_func[3].n1 my_demux.my_demux.vc.OR2_tf[5]._y my_demux.my_demux.vc.OR2_tf[0]._y my_demux.my_demux.out1_t_buf_func[3].n1 my_demux.my_demux.vc.C2Els[0]._y my_demux.my_demux.out1_t_buf_func[6].n1 my_demux.my_demux.vc.tmp[8] my_demux.my_demux._c_v my_demux.out2.a my_demux.my_demux.out2_a_B_buf_t.buf2._y my_demux.my_demux.out1_t_buf_func[5].n1 my_demux.my_demux._in_c_v_ my_demux.out2.v my_demux.my_demux._in_v my_demux.my_demux.vc.tmp[4] my_demux.my_demux.out1_en_buf_f.buf2._y my_demux.my_demux.out2_en_buf_f.buf2._y my_demux.my_demux.vc.tmp[0] my_demux.my_demux.vc.OR2_tf[3]._y my_demux.my_demux._out2_a_B my_demux.my_demux.vc.tmp[5] my_demux.out1.v my_demux.my_demux.c_buf_f.buf2._y my_demux.my_demux.out1_a_B_buf_t.buf2._y my_demux.my_demux._out_v my_demux.my_demux.vc.C3Els[0]._y my_demux.in.v my_demux.my_demux.vc.C3Els[1]._y my_demux.my_demux.out2_en_buf_t.buf2._y my_demux.my_demux.out2_a_B_buf_f.buf2._y my_demux.my_demux.in_v_buf._y my_demux.my_demux.vc.tmp[3] my_demux.my_demux.vc.OR2_tf[1]._y my_demux.my_demux.vc.OR2_tf[6]._y my_demux.my_demux.vc.tmp[2] my_demux.my_demux.out1_a_B_buf_f.buf2._y my_demux.my_demux.c_f_c_t_or._y my_demux.my_demux.out1_en_buf_t.buf2._y my_demux.my_demux.vc.OR2_tf[4]._y my_demux.my_demux.c_el._y
my_demux.my_demux._c_f_buf[0] my_demux.my_demux._out1_a_BX_f[0] my_demux.my_demux.out1_f_buf_func[1].n1 my_demux.my_demux._en my_demux.my_demux._en2_X_t[0] my_demux.my_demux.vc.OR2_tf[2]._y my_demux.my_demux.out1_f_buf_func[5].n1 my_demux.my_demux.out1_t_buf_func[2].n1 my_demux.my_demux._c_t_buf[0] my_demux.cond.v my_demux.my_demux._out2_a_BX_t[0] my_demux.my_demux.out1_f_buf_func[6].n1 my_demux.my_demux.out1_t_buf_func[4].n1 my_demux.my_demux._out1_a_B my_demux.my_demux.vc.ct.in[4] my_demux.my_demux._out1_a_BX_t[0] my_demux.my_demux._en1_X_t[0] my_demux.my_demux.c_buf_f.in my_demux.my_demux._out2_a_BX_f[0] my_demux.my_demux._en2_X_f[0] my_demux.my_demux.c_buf_t.in my_demux.my_demux.out1_t_buf_func[1].n1 my_demux.my_demux.vc.ct.tmp[9] my_demux.my_demux.out1_f_buf_func[0].n1 my_demux.out1.a my_demux.my_demux.out1_t_buf_func[0].n1 my_demux.my_demux.out1_f_buf_func[2].n1 my_demux.my_demux.c_buf_t.buf2._y my_demux.my_demux.vc.ct.tmp[8] my_demux.my_demux._en1_X_f[0] my_demux.my_demux.out1_f_buf_func[4].n1 my_demux.my_demux.vc.ct.in[5] my_demux.my_demux.vc.ct.in[1] my_demux.my_demux.vc.ct.in[6] my_demux.my_demux.out_or._y my_demux.my_demux.out1_f_buf_func[3].n1 my_demux.my_demux.vc.OR2_tf[5]._y my_demux.my_demux.vc.OR2_tf[0]._y my_demux.my_demux.out1_t_buf_func[3].n1 my_demux.my_demux.vc.ct.in[2] my_demux.my_demux.vc.ct.tmp[7] my_demux.my_demux.out1_t_buf_func[6].n1 my_demux.my_demux._c_v my_demux.out2.a my_demux.my_demux.out2_a_B_buf_t.buf2._y my_demux.my_demux.out1_t_buf_func[5].n1 my_demux.my_demux._in_v my_demux.my_demux.vc.ct.C3Els[0]._y my_demux.my_demux.vc.ct.in[0] my_demux.out2.v my_demux.my_demux.vc.ct.C3Els[1]._y my_demux.my_demux.out1_en_buf_f.buf2._y my_demux.my_demux.out2_en_buf_f.buf2._y my_demux.my_demux.vc.ct.C2Els[0]._y my_demux.my_demux.vc.OR2_tf[3]._y my_demux.my_demux._out2_a_B my_demux.out1.v my_demux.my_demux.c_buf_f.buf2._y my_demux.my_demux.out1_a_B_buf_t.buf2._y my_demux.my_demux.vc.ct.in[3] my_demux.my_demux._out_v my_demux.in.v my_demux.my_demux.out2_en_buf_t.buf2._y my_demux.my_demux.out2_a_B_buf_f.buf2._y my_demux.my_demux.in_v_buf._y my_demux.my_demux.vc.OR2_tf[1]._y my_demux.my_demux.vc.ct.C2Els[1]._y my_demux.my_demux.vc.OR2_tf[6]._y my_demux.my_demux.out1_a_B_buf_f.buf2._y my_demux.my_demux.c_f_c_t_or._y my_demux.my_demux.out1_en_buf_t.buf2._y my_demux.my_demux.vc.OR2_tf[4]._y my_demux.my_demux.c_el._y
119199 my_demux.my_demux.out1_f_buf_func[0].n1 : 0
119199 my_demux.my_demux.c_buf_f.in : 0
119199 my_demux.my_demux.c_buf_t.in : 0
@ -26,7 +26,7 @@ my_demux.my_demux._c_f_buf[0] my_demux.my_demux._out1_a_BX_f[0] my_demux.my_demu
119286 my_demux.my_demux.vc.OR2_tf[0]._y : 1 [by my_demux.my_demux.out1_t_buf_func[0].n1:=0]
119311 my_demux.my_demux._out1_a_B : 1 [by my_demux.out1.a:=0]
119333 my_demux.my_demux.out1_a_B_buf_f.buf2._y : 0 [by my_demux.my_demux._out1_a_B:=1]
119378 my_demux.my_demux.vc.tmp[5] : 0 [by my_demux.my_demux.vc.OR2_tf[5]._y:=1]
119378 my_demux.my_demux.vc.ct.in[5] : 0 [by my_demux.my_demux.vc.OR2_tf[5]._y:=1]
119403 my_demux.my_demux._out_v : 0 [by my_demux.my_demux.out_or._y:=1]
119456 my_demux.my_demux.vc.OR2_tf[6]._y : 1 [by my_demux.my_demux.out1_f_buf_func[6].n1:=0]
119493 my_demux.my_demux.vc.OR2_tf[2]._y : 1 [by my_demux.my_demux.out1_f_buf_func[2].n1:=0]
@ -36,35 +36,35 @@ my_demux.my_demux._c_f_buf[0] my_demux.my_demux._out1_a_BX_f[0] my_demux.my_demu
119757 my_demux.my_demux.out1_en_buf_t.buf2._y : 0 [by my_demux.my_demux._en:=1]
119790 my_demux.my_demux._c_f_buf[0] : 0 [by my_demux.my_demux.c_buf_f.buf2._y:=1]
119848 my_demux.my_demux._en1_X_t[0] : 1 [by my_demux.my_demux.out1_en_buf_t.buf2._y:=0]
119852 my_demux.my_demux.vc.tmp[2] : 0 [by my_demux.my_demux.vc.OR2_tf[2]._y:=1]
119852 my_demux.my_demux.vc.ct.in[2] : 0 [by my_demux.my_demux.vc.OR2_tf[2]._y:=1]
119938 my_demux.my_demux.c_f_c_t_or._y : 1 [by my_demux.my_demux.c_buf_t.in:=0]
120039 my_demux.my_demux._c_t_buf[0] : 0 [by my_demux.my_demux.c_buf_t.buf2._y:=1]
120158 my_demux.my_demux.out1_a_B_buf_t.buf2._y : 0 [by my_demux.my_demux._out1_a_B:=1]
120165 my_demux.my_demux._out1_a_BX_f[0] : 1 [by my_demux.my_demux.out1_a_B_buf_t.buf2._y:=0]
120408 my_demux.my_demux.vc.OR2_tf[3]._y : 1 [by my_demux.my_demux.out1_t_buf_func[3].n1:=0]
121005 my_demux.my_demux.vc.OR2_tf[1]._y : 1 [by my_demux.my_demux.out1_t_buf_func[1].n1:=0]
121111 my_demux.my_demux.vc.tmp[1] : 0 [by my_demux.my_demux.vc.OR2_tf[1]._y:=1]
121111 my_demux.my_demux.vc.ct.in[1] : 0 [by my_demux.my_demux.vc.OR2_tf[1]._y:=1]
121206 my_demux.my_demux.vc.OR2_tf[4]._y : 1 [by my_demux.my_demux.out1_f_buf_func[4].n1:=0]
121284 my_demux.my_demux.vc.tmp[4] : 0 [by my_demux.my_demux.vc.OR2_tf[4]._y:=1]
121481 my_demux.my_demux.vc.tmp[0] : 0 [by my_demux.my_demux.vc.OR2_tf[0]._y:=1]
121756 my_demux.my_demux.vc.C2Els[0]._y : 1 [by my_demux.my_demux.vc.tmp[0]:=0]
121284 my_demux.my_demux.vc.ct.in[4] : 0 [by my_demux.my_demux.vc.OR2_tf[4]._y:=1]
121481 my_demux.my_demux.vc.ct.in[0] : 0 [by my_demux.my_demux.vc.OR2_tf[0]._y:=1]
121756 my_demux.my_demux.vc.ct.C2Els[0]._y : 1 [by my_demux.my_demux.vc.ct.in[0]:=0]
122127 my_demux.my_demux._c_v : 0 [by my_demux.my_demux.c_f_c_t_or._y:=1]
123195 my_demux.my_demux.vc.tmp[3] : 0 [by my_demux.my_demux.vc.OR2_tf[3]._y:=1]
123650 my_demux.my_demux.vc.C2Els[1]._y : 1 [by my_demux.my_demux.vc.tmp[3]:=0]
123662 my_demux.my_demux.vc.tmp[8] : 0 [by my_demux.my_demux.vc.C2Els[1]._y:=1]
123195 my_demux.my_demux.vc.ct.in[3] : 0 [by my_demux.my_demux.vc.OR2_tf[3]._y:=1]
123650 my_demux.my_demux.vc.ct.C2Els[1]._y : 1 [by my_demux.my_demux.vc.ct.in[3]:=0]
123662 my_demux.my_demux.vc.ct.tmp[8] : 0 [by my_demux.my_demux.vc.ct.C2Els[1]._y:=1]
126256 my_demux.my_demux._en2_X_t[0] : 1 [by my_demux.my_demux.out2_en_buf_t.buf2._y:=0]
133652 my_demux.my_demux.out2_en_buf_f.buf2._y : 0 [by my_demux.my_demux._en:=1]
134056 my_demux.my_demux._en2_X_f[0] : 1 [by my_demux.my_demux.out2_en_buf_f.buf2._y:=0]
135118 my_demux.my_demux.vc.tmp[6] : 0 [by my_demux.my_demux.vc.OR2_tf[6]._y:=1]
135130 my_demux.my_demux.vc.C3Els[0]._y : 1 [by my_demux.my_demux.vc.tmp[6]:=0]
140752 my_demux.my_demux.vc.tmp[7] : 0 [by my_demux.my_demux.vc.C2Els[0]._y:=1]
141046 my_demux.my_demux.vc.tmp[9] : 0 [by my_demux.my_demux.vc.C3Els[0]._y:=1]
145322 my_demux.my_demux.vc.C3Els[1]._y : 1 [by my_demux.my_demux.vc.tmp[9]:=0]
148221 my_demux.my_demux._in_v : 0 [by my_demux.my_demux.vc.C3Els[1]._y:=1]
135118 my_demux.my_demux.vc.ct.in[6] : 0 [by my_demux.my_demux.vc.OR2_tf[6]._y:=1]
135130 my_demux.my_demux.vc.ct.C3Els[0]._y : 1 [by my_demux.my_demux.vc.ct.in[6]:=0]
140752 my_demux.my_demux.vc.ct.tmp[7] : 0 [by my_demux.my_demux.vc.ct.C2Els[0]._y:=1]
141046 my_demux.my_demux.vc.ct.tmp[9] : 0 [by my_demux.my_demux.vc.ct.C3Els[0]._y:=1]
145322 my_demux.my_demux.vc.ct.C3Els[1]._y : 1 [by my_demux.my_demux.vc.ct.tmp[9]:=0]
148221 my_demux.my_demux._in_v : 0 [by my_demux.my_demux.vc.ct.C3Els[1]._y:=1]
148223 my_demux.my_demux.c_el._y : 1 [by my_demux.my_demux._in_v:=0]
149461 my_demux.my_demux._out1_a_BX_t[0] : 1 [by my_demux.my_demux.out1_a_B_buf_f.buf2._y:=0]
152516 my_demux.my_demux.in_v_buf._y : 1 [by my_demux.my_demux._in_v:=0]
152758 my_demux.my_demux._in_c_v_ : 0 [by my_demux.my_demux.c_el._y:=1]
152758 my_demux.cond.v : 0 [by my_demux.my_demux.c_el._y:=1]
153765 my_demux.in.v : 0 [by my_demux.my_demux.in_v_buf._y:=1]
166711 my_demux.my_demux._out2_a_B : 1 [by my_demux.out2.a:=0]
166877 my_demux.my_demux.out2_a_B_buf_f.buf2._y : 0 [by my_demux.my_demux._out2_a_B:=1]
@ -94,7 +94,7 @@ Output neutral checked
226364 my_demux.my_demux.vc.OR2_tf[4]._y : 0 [by my_demux.my_demux.out1_t_buf_func[4].n1:=1]
226415 my_demux.my_demux.vc.OR2_tf[1]._y : 0 [by my_demux.my_demux.out1_t_buf_func[1].n1:=1]
226718 my_demux.my_demux.vc.OR2_tf[6]._y : 0 [by my_demux.my_demux.out1_t_buf_func[6].n1:=1]
226720 my_demux.my_demux.vc.tmp[6] : 1 [by my_demux.my_demux.vc.OR2_tf[6]._y:=0]
226720 my_demux.my_demux.vc.ct.in[6] : 1 [by my_demux.my_demux.vc.OR2_tf[6]._y:=0]
226876 my_demux.my_demux.vc.OR2_tf[3]._y : 0 [by my_demux.my_demux.out1_t_buf_func[3].n1:=1]
226896 my_demux.my_demux.c_buf_t.buf2._y : 0 [by my_demux.my_demux.c_buf_t.in:=1]
226899 my_demux.my_demux._c_t_buf[0] : 1 [by my_demux.my_demux.c_buf_t.buf2._y:=0]
@ -109,30 +109,30 @@ Output neutral checked
228500 my_demux.my_demux.out1_t_buf_func[2]._y : 0 [by my_demux.my_demux._c_t_buf[0]:=1]
228783 my_demux.my_demux.vc.OR2_tf[2]._y : 0 [by my_demux.my_demux.out1_t_buf_func[2].n1:=1]
228989 my_demux.my_demux.vc.OR2_tf[5]._y : 0 [by my_demux.my_demux.out1_t_buf_func[5].n1:=1]
229148 my_demux.my_demux.vc.tmp[5] : 1 [by my_demux.my_demux.vc.OR2_tf[5]._y:=0]
229148 my_demux.my_demux.vc.ct.in[5] : 1 [by my_demux.my_demux.vc.OR2_tf[5]._y:=0]
229660 my_demux.my_demux.out1_t_buf_func[5]._y : 0 [by my_demux.my_demux._c_t_buf[0]:=1]
230081 my_demux.my_demux.out1_t_buf_func[2].y : 1 [by my_demux.my_demux.out1_t_buf_func[2]._y:=0]
230910 my_demux.my_demux.vc.OR2_tf[0]._y : 0 [by my_demux.my_demux.out1_t_buf_func[0].n1:=1]
232197 my_demux.my_demux.vc.tmp[0] : 1 [by my_demux.my_demux.vc.OR2_tf[0]._y:=0]
238128 my_demux.my_demux.vc.tmp[2] : 1 [by my_demux.my_demux.vc.OR2_tf[2]._y:=0]
239456 my_demux.my_demux.vc.tmp[1] : 1 [by my_demux.my_demux.vc.OR2_tf[1]._y:=0]
232197 my_demux.my_demux.vc.ct.in[0] : 1 [by my_demux.my_demux.vc.OR2_tf[0]._y:=0]
238128 my_demux.my_demux.vc.ct.in[2] : 1 [by my_demux.my_demux.vc.OR2_tf[2]._y:=0]
239456 my_demux.my_demux.vc.ct.in[1] : 1 [by my_demux.my_demux.vc.OR2_tf[1]._y:=0]
240582 my_demux.my_demux.out1_t_buf_func[6]._y : 0 [by my_demux.my_demux._c_t_buf[0]:=1]
240727 my_demux.my_demux.out1_t_buf_func[6].y : 1 [by my_demux.my_demux.out1_t_buf_func[6]._y:=0]
241688 my_demux.my_demux.vc.C2Els[0]._y : 0 [by my_demux.my_demux.vc.tmp[1]:=1]
244520 my_demux.my_demux.vc.tmp[7] : 1 [by my_demux.my_demux.vc.C2Els[0]._y:=0]
241688 my_demux.my_demux.vc.ct.C2Els[0]._y : 0 [by my_demux.my_demux.vc.ct.in[1]:=1]
244520 my_demux.my_demux.vc.ct.tmp[7] : 1 [by my_demux.my_demux.vc.ct.C2Els[0]._y:=0]
249336 my_demux.my_demux.out1_t_buf_func[5].y : 1 [by my_demux.my_demux.out1_t_buf_func[5]._y:=0]
250289 my_demux.my_demux.vc.tmp[4] : 1 [by my_demux.my_demux.vc.OR2_tf[4]._y:=0]
250289 my_demux.my_demux.vc.ct.in[4] : 1 [by my_demux.my_demux.vc.OR2_tf[4]._y:=0]
253239 my_demux.my_demux._c_v : 1 [by my_demux.my_demux.c_f_c_t_or._y:=0]
256643 my_demux.my_demux.vc.C3Els[0]._y : 0 [by my_demux.my_demux.vc.tmp[4]:=1]
256644 my_demux.my_demux.vc.tmp[9] : 1 [by my_demux.my_demux.vc.C3Els[0]._y:=0]
287834 my_demux.my_demux.vc.tmp[3] : 1 [by my_demux.my_demux.vc.OR2_tf[3]._y:=0]
327118 my_demux.my_demux.vc.C2Els[1]._y : 0 [by my_demux.my_demux.vc.tmp[3]:=1]
327280 my_demux.my_demux.vc.tmp[8] : 1 [by my_demux.my_demux.vc.C2Els[1]._y:=0]
334649 my_demux.my_demux.vc.C3Els[1]._y : 0 [by my_demux.my_demux.vc.tmp[8]:=1]
334663 my_demux.my_demux._in_v : 1 [by my_demux.my_demux.vc.C3Els[1]._y:=0]
256643 my_demux.my_demux.vc.ct.C3Els[0]._y : 0 [by my_demux.my_demux.vc.ct.in[4]:=1]
256644 my_demux.my_demux.vc.ct.tmp[9] : 1 [by my_demux.my_demux.vc.ct.C3Els[0]._y:=0]
287834 my_demux.my_demux.vc.ct.in[3] : 1 [by my_demux.my_demux.vc.OR2_tf[3]._y:=0]
327118 my_demux.my_demux.vc.ct.C2Els[1]._y : 0 [by my_demux.my_demux.vc.ct.in[3]:=1]
327280 my_demux.my_demux.vc.ct.tmp[8] : 1 [by my_demux.my_demux.vc.ct.C2Els[1]._y:=0]
334649 my_demux.my_demux.vc.ct.C3Els[1]._y : 0 [by my_demux.my_demux.vc.ct.tmp[8]:=1]
334663 my_demux.my_demux._in_v : 1 [by my_demux.my_demux.vc.ct.C3Els[1]._y:=0]
334670 my_demux.my_demux.in_v_buf._y : 0 [by my_demux.my_demux._in_v:=1]
334823 my_demux.my_demux.c_el._y : 0 [by my_demux.my_demux._in_v:=1]
334824 my_demux.my_demux._in_c_v_ : 1 [by my_demux.my_demux.c_el._y:=0]
334824 my_demux.cond.v : 1 [by my_demux.my_demux.c_el._y:=0]
356227 my_demux.in.v : 1 [by my_demux.my_demux.in_v_buf._y:=0]
356227 my_demux.out1.v : 1
356228 my_demux.my_demux.out_or._y : 0 [by my_demux.out1.v:=1]
@ -158,25 +158,25 @@ Output neutral checked
393460 my_demux.my_demux.vc.OR2_tf[4]._y : 1 [by my_demux.my_demux.out1_t_buf_func[4].n1:=0]
393462 my_demux.my_demux.vc.OR2_tf[2]._y : 1 [by my_demux.my_demux.out1_t_buf_func[2].n1:=0]
393501 my_demux.my_demux.vc.OR2_tf[3]._y : 1 [by my_demux.my_demux.out1_t_buf_func[3].n1:=0]
393596 my_demux.my_demux.vc.tmp[3] : 0 [by my_demux.my_demux.vc.OR2_tf[3]._y:=1]
393596 my_demux.my_demux.vc.ct.in[3] : 0 [by my_demux.my_demux.vc.OR2_tf[3]._y:=1]
394400 my_demux.my_demux.vc.OR2_tf[5]._y : 1 [by my_demux.my_demux.out1_t_buf_func[5].n1:=0]
394735 my_demux.my_demux.vc.tmp[5] : 0 [by my_demux.my_demux.vc.OR2_tf[5]._y:=1]
394735 my_demux.my_demux.vc.ct.in[5] : 0 [by my_demux.my_demux.vc.OR2_tf[5]._y:=1]
396032 my_demux.my_demux.vc.OR2_tf[0]._y : 1 [by my_demux.my_demux.out1_t_buf_func[0].n1:=0]
396040 my_demux.my_demux.vc.tmp[0] : 0 [by my_demux.my_demux.vc.OR2_tf[0]._y:=1]
396277 my_demux.my_demux.vc.tmp[4] : 0 [by my_demux.my_demux.vc.OR2_tf[4]._y:=1]
396040 my_demux.my_demux.vc.ct.in[0] : 0 [by my_demux.my_demux.vc.OR2_tf[0]._y:=1]
396277 my_demux.my_demux.vc.ct.in[4] : 0 [by my_demux.my_demux.vc.OR2_tf[4]._y:=1]
401820 my_demux.my_demux.vc.OR2_tf[6]._y : 1 [by my_demux.my_demux.out1_t_buf_func[6].n1:=0]
401854 my_demux.my_demux.vc.tmp[6] : 0 [by my_demux.my_demux.vc.OR2_tf[6]._y:=1]
407195 my_demux.my_demux.vc.tmp[2] : 0 [by my_demux.my_demux.vc.OR2_tf[2]._y:=1]
408113 my_demux.my_demux.vc.C2Els[1]._y : 1 [by my_demux.my_demux.vc.tmp[2]:=0]
408117 my_demux.my_demux.vc.tmp[8] : 0 [by my_demux.my_demux.vc.C2Els[1]._y:=1]
415741 my_demux.my_demux.vc.C3Els[0]._y : 1 [by my_demux.my_demux.vc.tmp[6]:=0]
401854 my_demux.my_demux.vc.ct.in[6] : 0 [by my_demux.my_demux.vc.OR2_tf[6]._y:=1]
407195 my_demux.my_demux.vc.ct.in[2] : 0 [by my_demux.my_demux.vc.OR2_tf[2]._y:=1]
408113 my_demux.my_demux.vc.ct.C2Els[1]._y : 1 [by my_demux.my_demux.vc.ct.in[2]:=0]
408117 my_demux.my_demux.vc.ct.tmp[8] : 0 [by my_demux.my_demux.vc.ct.C2Els[1]._y:=1]
415741 my_demux.my_demux.vc.ct.C3Els[0]._y : 1 [by my_demux.my_demux.vc.ct.in[6]:=0]
452421 my_demux.my_demux.vc.OR2_tf[1]._y : 1 [by my_demux.my_demux.out1_t_buf_func[1].n1:=0]
454819 my_demux.my_demux.vc.tmp[1] : 0 [by my_demux.my_demux.vc.OR2_tf[1]._y:=1]
458034 my_demux.my_demux.vc.C2Els[0]._y : 1 [by my_demux.my_demux.vc.tmp[1]:=0]
462119 my_demux.my_demux.vc.tmp[9] : 0 [by my_demux.my_demux.vc.C3Els[0]._y:=1]
505153 my_demux.my_demux.vc.tmp[7] : 0 [by my_demux.my_demux.vc.C2Els[0]._y:=1]
505201 my_demux.my_demux.vc.C3Els[1]._y : 1 [by my_demux.my_demux.vc.tmp[7]:=0]
505204 my_demux.my_demux._in_v : 0 [by my_demux.my_demux.vc.C3Els[1]._y:=1]
454819 my_demux.my_demux.vc.ct.in[1] : 0 [by my_demux.my_demux.vc.OR2_tf[1]._y:=1]
458034 my_demux.my_demux.vc.ct.C2Els[0]._y : 1 [by my_demux.my_demux.vc.ct.in[1]:=0]
462119 my_demux.my_demux.vc.ct.tmp[9] : 0 [by my_demux.my_demux.vc.ct.C3Els[0]._y:=1]
505153 my_demux.my_demux.vc.ct.tmp[7] : 0 [by my_demux.my_demux.vc.ct.C2Els[0]._y:=1]
505201 my_demux.my_demux.vc.ct.C3Els[1]._y : 1 [by my_demux.my_demux.vc.ct.tmp[7]:=0]
505204 my_demux.my_demux._in_v : 0 [by my_demux.my_demux.vc.ct.C3Els[1]._y:=1]
505382 my_demux.my_demux.in_v_buf._y : 1 [by my_demux.my_demux._in_v:=0]
526359 my_demux.in.v : 0 [by my_demux.my_demux.in_v_buf._y:=1]
First Cond Checked
@ -214,7 +214,7 @@ Output neutral checked
585101 my_demux.my_demux._c_v : 0 [by my_demux.my_demux.c_f_c_t_or._y:=1]
585114 my_demux.my_demux.c_el._y : 1 [by my_demux.my_demux._c_v:=0]
586919 my_demux.my_demux._out1_a_BX_f[0] : 1 [by my_demux.my_demux.out1_a_B_buf_t.buf2._y:=0]
602098 my_demux.my_demux._in_c_v_ : 0 [by my_demux.my_demux.c_el._y:=1]
602098 my_demux.cond.v : 0 [by my_demux.my_demux.c_el._y:=1]
606729 my_demux.my_demux.out1_a_B_buf_f.buf2._y : 0 [by my_demux.my_demux._out1_a_B:=1]
607086 my_demux.my_demux._out1_a_BX_t[0] : 1 [by my_demux.my_demux.out1_a_B_buf_f.buf2._y:=0]
628359 my_demux.my_demux.out_or._y : 1 [by my_demux.out1.v:=0]
@ -241,46 +241,46 @@ Output neutral checked
639106 my_demux.my_demux.vc.OR2_tf[1]._y : 0 [by my_demux.my_demux.out1_f_buf_func[1].n1:=1]
639116 my_demux.my_demux.c_buf_f.buf2._y : 0 [by my_demux.my_demux.c_buf_f.in:=1]
639120 my_demux.my_demux.vc.OR2_tf[6]._y : 0 [by my_demux.my_demux.out1_t_buf_func[6].n1:=1]
639190 my_demux.my_demux.vc.tmp[6] : 1 [by my_demux.my_demux.vc.OR2_tf[6]._y:=0]
639190 my_demux.my_demux.vc.ct.in[6] : 1 [by my_demux.my_demux.vc.OR2_tf[6]._y:=0]
639206 my_demux.my_demux.vc.OR2_tf[5]._y : 0 [by my_demux.my_demux.out1_t_buf_func[5].n1:=1]
639330 my_demux.my_demux.vc.OR2_tf[2]._y : 0 [by my_demux.my_demux.out1_t_buf_func[2].n1:=1]
639341 my_demux.my_demux.vc.tmp[2] : 1 [by my_demux.my_demux.vc.OR2_tf[2]._y:=0]
639949 my_demux.my_demux.vc.tmp[1] : 1 [by my_demux.my_demux.vc.OR2_tf[1]._y:=0]
639341 my_demux.my_demux.vc.ct.in[2] : 1 [by my_demux.my_demux.vc.OR2_tf[2]._y:=0]
639949 my_demux.my_demux.vc.ct.in[1] : 1 [by my_demux.my_demux.vc.OR2_tf[1]._y:=0]
640149 my_demux.my_demux.c_f_c_t_or._y : 0 [by my_demux.my_demux.c_buf_f.in:=1]
640152 my_demux.my_demux._c_v : 1 [by my_demux.my_demux.c_f_c_t_or._y:=0]
640306 my_demux.my_demux.vc.OR2_tf[0]._y : 0 [by my_demux.my_demux.out1_f_buf_func[0].n1:=1]
640360 my_demux.my_demux.vc.tmp[0] : 1 [by my_demux.my_demux.vc.OR2_tf[0]._y:=0]
640360 my_demux.my_demux.vc.ct.in[0] : 1 [by my_demux.my_demux.vc.OR2_tf[0]._y:=0]
640575 my_demux.my_demux._c_f_buf[0] : 1 [by my_demux.my_demux.c_buf_f.buf2._y:=0]
640656 my_demux.my_demux.out2_t_buf_func[6]._y : 0 [by my_demux.my_demux._c_f_buf[0]:=1]
640667 my_demux.my_demux.out2_f_buf_func[3]._y : 0 [by my_demux.my_demux._c_f_buf[0]:=1]
641280 my_demux.my_demux.out2_f_buf_func[3].y : 1 [by my_demux.my_demux.out2_f_buf_func[3]._y:=0]
641508 my_demux.my_demux.vc.C2Els[0]._y : 0 [by my_demux.my_demux.vc.tmp[0]:=1]
641508 my_demux.my_demux.vc.ct.C2Els[0]._y : 0 [by my_demux.my_demux.vc.ct.in[0]:=1]
641736 my_demux.my_demux.out2_t_buf_func[2]._y : 0 [by my_demux.my_demux._c_f_buf[0]:=1]
641781 my_demux.my_demux.out2_t_buf_func[2].y : 1 [by my_demux.my_demux.out2_t_buf_func[2]._y:=0]
642400 my_demux.my_demux.out2_t_buf_func[6].y : 1 [by my_demux.my_demux.out2_t_buf_func[6]._y:=0]
647557 my_demux.my_demux.vc.OR2_tf[3]._y : 0 [by my_demux.my_demux.out1_f_buf_func[3].n1:=1]
648554 my_demux.my_demux.vc.tmp[3] : 1 [by my_demux.my_demux.vc.OR2_tf[3]._y:=0]
648554 my_demux.my_demux.vc.ct.in[3] : 1 [by my_demux.my_demux.vc.OR2_tf[3]._y:=0]
648886 my_demux.my_demux.out2_f_buf_func[4]._y : 0 [by my_demux.my_demux._c_f_buf[0]:=1]
649227 my_demux.my_demux.out2_t_buf_func[5]._y : 0 [by my_demux.my_demux._c_f_buf[0]:=1]
649411 my_demux.my_demux.out2_f_buf_func[4].y : 1 [by my_demux.my_demux.out2_f_buf_func[4]._y:=0]
650127 my_demux.my_demux.out2_t_buf_func[5].y : 1 [by my_demux.my_demux.out2_t_buf_func[5]._y:=0]
650203 my_demux.my_demux.vc.C2Els[1]._y : 0 [by my_demux.my_demux.vc.tmp[3]:=1]
650255 my_demux.my_demux.vc.tmp[8] : 1 [by my_demux.my_demux.vc.C2Els[1]._y:=0]
650203 my_demux.my_demux.vc.ct.C2Els[1]._y : 0 [by my_demux.my_demux.vc.ct.in[3]:=1]
650255 my_demux.my_demux.vc.ct.tmp[8] : 1 [by my_demux.my_demux.vc.ct.C2Els[1]._y:=0]
651652 my_demux.my_demux.out2_f_buf_func[0]._y : 0 [by my_demux.my_demux._c_f_buf[0]:=1]
651659 my_demux.my_demux.out2_f_buf_func[0].y : 1 [by my_demux.my_demux.out2_f_buf_func[0]._y:=0]
655530 my_demux.my_demux.vc.tmp[7] : 1 [by my_demux.my_demux.vc.C2Els[0]._y:=0]
655530 my_demux.my_demux.vc.ct.tmp[7] : 1 [by my_demux.my_demux.vc.ct.C2Els[0]._y:=0]
658558 my_demux.my_demux.out2_f_buf_func[1]._y : 0 [by my_demux.my_demux._c_f_buf[0]:=1]
670546 my_demux.my_demux.vc.OR2_tf[4]._y : 0 [by my_demux.my_demux.out1_f_buf_func[4].n1:=1]
674170 my_demux.my_demux.out2_f_buf_func[1].y : 1 [by my_demux.my_demux.out2_f_buf_func[1]._y:=0]
677013 my_demux.my_demux.vc.tmp[4] : 1 [by my_demux.my_demux.vc.OR2_tf[4]._y:=0]
689628 my_demux.my_demux.vc.tmp[5] : 1 [by my_demux.my_demux.vc.OR2_tf[5]._y:=0]
689630 my_demux.my_demux.vc.C3Els[0]._y : 0 [by my_demux.my_demux.vc.tmp[5]:=1]
689984 my_demux.my_demux.vc.tmp[9] : 1 [by my_demux.my_demux.vc.C3Els[0]._y:=0]
690117 my_demux.my_demux.vc.C3Els[1]._y : 0 [by my_demux.my_demux.vc.tmp[9]:=1]
690118 my_demux.my_demux._in_v : 1 [by my_demux.my_demux.vc.C3Els[1]._y:=0]
677013 my_demux.my_demux.vc.ct.in[4] : 1 [by my_demux.my_demux.vc.OR2_tf[4]._y:=0]
689628 my_demux.my_demux.vc.ct.in[5] : 1 [by my_demux.my_demux.vc.OR2_tf[5]._y:=0]
689630 my_demux.my_demux.vc.ct.C3Els[0]._y : 0 [by my_demux.my_demux.vc.ct.in[5]:=1]
689984 my_demux.my_demux.vc.ct.tmp[9] : 1 [by my_demux.my_demux.vc.ct.C3Els[0]._y:=0]
690117 my_demux.my_demux.vc.ct.C3Els[1]._y : 0 [by my_demux.my_demux.vc.ct.tmp[9]:=1]
690118 my_demux.my_demux._in_v : 1 [by my_demux.my_demux.vc.ct.C3Els[1]._y:=0]
690122 my_demux.my_demux.in_v_buf._y : 0 [by my_demux.my_demux._in_v:=1]
690664 my_demux.my_demux.c_el._y : 0 [by my_demux.my_demux._in_v:=1]
690665 my_demux.my_demux._in_c_v_ : 1 [by my_demux.my_demux.c_el._y:=0]
690665 my_demux.cond.v : 1 [by my_demux.my_demux.c_el._y:=0]
735685 my_demux.in.v : 1 [by my_demux.my_demux.in_v_buf._y:=0]
735685 my_demux.out2.v : 1
748063 my_demux.my_demux.out_or._y : 0 [by my_demux.out2.v:=1]
@ -305,26 +305,26 @@ Output neutral checked
817979 my_demux.my_demux.out1_f_buf_func[3].n1 : 0
817982 my_demux.my_demux.vc.OR2_tf[3]._y : 1 [by my_demux.my_demux.out1_f_buf_func[3].n1:=0]
817991 my_demux.my_demux.vc.OR2_tf[5]._y : 1 [by my_demux.my_demux.out1_t_buf_func[5].n1:=0]
817992 my_demux.my_demux.vc.tmp[5] : 0 [by my_demux.my_demux.vc.OR2_tf[5]._y:=1]
818020 my_demux.my_demux.vc.tmp[3] : 0 [by my_demux.my_demux.vc.OR2_tf[3]._y:=1]
817992 my_demux.my_demux.vc.ct.in[5] : 0 [by my_demux.my_demux.vc.OR2_tf[5]._y:=1]
818020 my_demux.my_demux.vc.ct.in[3] : 0 [by my_demux.my_demux.vc.OR2_tf[3]._y:=1]
818022 my_demux.my_demux.vc.OR2_tf[2]._y : 1 [by my_demux.my_demux.out1_t_buf_func[2].n1:=0]
818106 my_demux.my_demux.vc.OR2_tf[0]._y : 1 [by my_demux.my_demux.out1_f_buf_func[0].n1:=0]
818148 my_demux.my_demux.vc.OR2_tf[6]._y : 1 [by my_demux.my_demux.out1_t_buf_func[6].n1:=0]
818198 my_demux.my_demux.vc.tmp[0] : 0 [by my_demux.my_demux.vc.OR2_tf[0]._y:=1]
818198 my_demux.my_demux.vc.ct.in[0] : 0 [by my_demux.my_demux.vc.OR2_tf[0]._y:=1]
818212 my_demux.my_demux.vc.OR2_tf[4]._y : 1 [by my_demux.my_demux.out1_f_buf_func[4].n1:=0]
818214 my_demux.my_demux.vc.tmp[4] : 0 [by my_demux.my_demux.vc.OR2_tf[4]._y:=1]
818214 my_demux.my_demux.vc.ct.in[4] : 0 [by my_demux.my_demux.vc.OR2_tf[4]._y:=1]
819258 my_demux.my_demux.vc.OR2_tf[1]._y : 1 [by my_demux.my_demux.out1_f_buf_func[1].n1:=0]
819259 my_demux.my_demux.vc.tmp[1] : 0 [by my_demux.my_demux.vc.OR2_tf[1]._y:=1]
820760 my_demux.my_demux.vc.C2Els[0]._y : 1 [by my_demux.my_demux.vc.tmp[1]:=0]
820762 my_demux.my_demux.vc.tmp[7] : 0 [by my_demux.my_demux.vc.C2Els[0]._y:=1]
820875 my_demux.my_demux.vc.tmp[6] : 0 [by my_demux.my_demux.vc.OR2_tf[6]._y:=1]
820893 my_demux.my_demux.vc.C3Els[0]._y : 1 [by my_demux.my_demux.vc.tmp[6]:=0]
821012 my_demux.my_demux.vc.tmp[9] : 0 [by my_demux.my_demux.vc.C3Els[0]._y:=1]
830774 my_demux.my_demux.vc.tmp[2] : 0 [by my_demux.my_demux.vc.OR2_tf[2]._y:=1]
836494 my_demux.my_demux.vc.C2Els[1]._y : 1 [by my_demux.my_demux.vc.tmp[2]:=0]
836502 my_demux.my_demux.vc.tmp[8] : 0 [by my_demux.my_demux.vc.C2Els[1]._y:=1]
836556 my_demux.my_demux.vc.C3Els[1]._y : 1 [by my_demux.my_demux.vc.tmp[8]:=0]
887094 my_demux.my_demux._in_v : 0 [by my_demux.my_demux.vc.C3Els[1]._y:=1]
819259 my_demux.my_demux.vc.ct.in[1] : 0 [by my_demux.my_demux.vc.OR2_tf[1]._y:=1]
820760 my_demux.my_demux.vc.ct.C2Els[0]._y : 1 [by my_demux.my_demux.vc.ct.in[1]:=0]
820762 my_demux.my_demux.vc.ct.tmp[7] : 0 [by my_demux.my_demux.vc.ct.C2Els[0]._y:=1]
820875 my_demux.my_demux.vc.ct.in[6] : 0 [by my_demux.my_demux.vc.OR2_tf[6]._y:=1]
820893 my_demux.my_demux.vc.ct.C3Els[0]._y : 1 [by my_demux.my_demux.vc.ct.in[6]:=0]
821012 my_demux.my_demux.vc.ct.tmp[9] : 0 [by my_demux.my_demux.vc.ct.C3Els[0]._y:=1]
830774 my_demux.my_demux.vc.ct.in[2] : 0 [by my_demux.my_demux.vc.OR2_tf[2]._y:=1]
836494 my_demux.my_demux.vc.ct.C2Els[1]._y : 1 [by my_demux.my_demux.vc.ct.in[2]:=0]
836502 my_demux.my_demux.vc.ct.tmp[8] : 0 [by my_demux.my_demux.vc.ct.C2Els[1]._y:=1]
836556 my_demux.my_demux.vc.ct.C3Els[1]._y : 1 [by my_demux.my_demux.vc.ct.tmp[8]:=0]
887094 my_demux.my_demux._in_v : 0 [by my_demux.my_demux.vc.ct.C3Els[1]._y:=1]
887099 my_demux.my_demux.in_v_buf._y : 1 [by my_demux.my_demux._in_v:=0]
888166 my_demux.in.v : 0 [by my_demux.my_demux.in_v_buf._y:=1]
Second Cond Checked

BIN
test/unit_tests/demux_7/run/prsim.pdf
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test/unit_tests/demux_7/run/test.prs
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@ -330,6 +330,7 @@
= "my_demux.my_demux.in.d.d[6].d[0]" "my_demux.my_demux.vc.in.d[6].d[0]"
= "my_demux.my_demux.in.d.d[6].d[1]" "my_demux.my_demux.vc.in.d[6].d[1]"
= "my_demux.my_demux.in.a" "my_demux.my_demux.en_ctl.c1"
= "my_demux.my_demux.in.a" "my_demux.my_demux.cond.a"
= "my_demux.my_demux.in.a" "my_demux.my_demux.inack_ctl.y"
= "my_demux.my_demux.in.v" "my_demux.my_demux.in_v_buf.y"
= "my_demux.my_demux.in.d.d[6].d[0]" "my_demux.my_demux.out2_f_buf_func[6].n1"
@ -426,8 +427,6 @@
~("my_demux.my_demux.out_or.a"|"my_demux.my_demux.out_or.b")->"my_demux.my_demux.out_or._y"+
"my_demux.my_demux.out_or._y"->"my_demux.my_demux.out_or.y"-
~("my_demux.my_demux.out_or._y")->"my_demux.my_demux.out_or.y"+
= "my_demux.my_demux._in_c_v_" "my_demux.my_demux.c_el.y"
= "my_demux.my_demux._in_c_v_" "my_demux.my_demux.inack_ctl.c2"
= "my_demux.my_demux._out1_a_BX_t[0]" "my_demux.my_demux.out1_a_B_buf_f.out[0]"
= "my_demux.my_demux._out1_a_BX_t[1]" "my_demux.my_demux.out1_a_B_buf_f.out[1]"
= "my_demux.my_demux._out1_a_BX_t[2]" "my_demux.my_demux.out1_a_B_buf_f.out[2]"
@ -854,12 +853,20 @@
= "my_demux.my_demux.supply.vdd" "my_demux.my_demux.out2_en_buf_f.supply.vdd"
= "my_demux.my_demux.supply.vss" "my_demux.my_demux.out2_en_buf_t.supply.vss"
= "my_demux.my_demux.supply.vdd" "my_demux.my_demux.out2_en_buf_t.supply.vdd"
= "my_demux.my_demux.supply.vss" "my_demux.my_demux.out1_a_B_buf_t.supply.vss"
= "my_demux.my_demux.supply.vdd" "my_demux.my_demux.out1_a_B_buf_t.supply.vdd"
= "my_demux.my_demux.supply.vss" "my_demux.my_demux.out1_a_B_buf_f.supply.vss"
= "my_demux.my_demux.supply.vdd" "my_demux.my_demux.out1_a_B_buf_f.supply.vdd"
= "my_demux.my_demux.supply.vss" "my_demux.my_demux.out1_en_buf_f.supply.vss"
= "my_demux.my_demux.supply.vdd" "my_demux.my_demux.out1_en_buf_f.supply.vdd"
= "my_demux.my_demux.supply.vss" "my_demux.my_demux.out1_en_buf_t.supply.vss"
= "my_demux.my_demux.supply.vdd" "my_demux.my_demux.out1_en_buf_t.supply.vdd"
= "my_demux.my_demux.supply.vss" "my_demux.my_demux.vc.supply.vss"
= "my_demux.my_demux.supply.vdd" "my_demux.my_demux.vc.supply.vdd"
= "my_demux.my_demux.supply.vss" "my_demux.my_demux.c_buf_f.supply.vss"
= "my_demux.my_demux.supply.vdd" "my_demux.my_demux.c_buf_f.supply.vdd"
= "my_demux.my_demux.supply.vss" "my_demux.my_demux.c_buf_t.supply.vss"
= "my_demux.my_demux.supply.vdd" "my_demux.my_demux.c_buf_t.supply.vdd"
= "my_demux.my_demux.supply.vdd" "my_demux.my_demux.out2_t_buf_func[6].vdd"
= "my_demux.my_demux.supply.vdd" "my_demux.my_demux.out2_f_buf_func[6].vdd"
= "my_demux.my_demux.supply.vdd" "my_demux.my_demux.out2_t_buf_func[5].vdd"
@ -930,22 +937,59 @@
= "my_demux.my_demux.supply.vss" "my_demux.my_demux.en_ctl.vss"
= "my_demux.my_demux.supply.vss" "my_demux.my_demux.inack_ctl.vss"
= "my_demux.my_demux.supply.vss" "my_demux.my_demux.out_or.vss"
~"my_demux.my_demux.vc.C2Els[0].c1"&~"my_demux.my_demux.vc.C2Els[0].c2"->"my_demux.my_demux.vc.C2Els[0]._y"+
"my_demux.my_demux.vc.C2Els[0].c1"&"my_demux.my_demux.vc.C2Els[0].c2"->"my_demux.my_demux.vc.C2Els[0]._y"-
"my_demux.my_demux.vc.C2Els[0]._y"->"my_demux.my_demux.vc.C2Els[0].y"-
~("my_demux.my_demux.vc.C2Els[0]._y")->"my_demux.my_demux.vc.C2Els[0].y"+
~"my_demux.my_demux.vc.C2Els[1].c1"&~"my_demux.my_demux.vc.C2Els[1].c2"->"my_demux.my_demux.vc.C2Els[1]._y"+
"my_demux.my_demux.vc.C2Els[1].c1"&"my_demux.my_demux.vc.C2Els[1].c2"->"my_demux.my_demux.vc.C2Els[1]._y"-
"my_demux.my_demux.vc.C2Els[1]._y"->"my_demux.my_demux.vc.C2Els[1].y"-
~("my_demux.my_demux.vc.C2Els[1]._y")->"my_demux.my_demux.vc.C2Els[1].y"+
~"my_demux.my_demux.vc.C3Els[0].c1"&~"my_demux.my_demux.vc.C3Els[0].c2"&~"my_demux.my_demux.vc.C3Els[0].c3"->"my_demux.my_demux.vc.C3Els[0]._y"+
"my_demux.my_demux.vc.C3Els[0].c1"&"my_demux.my_demux.vc.C3Els[0].c2"&"my_demux.my_demux.vc.C3Els[0].c3"->"my_demux.my_demux.vc.C3Els[0]._y"-
"my_demux.my_demux.vc.C3Els[0]._y"->"my_demux.my_demux.vc.C3Els[0].y"-
~("my_demux.my_demux.vc.C3Els[0]._y")->"my_demux.my_demux.vc.C3Els[0].y"+
~"my_demux.my_demux.vc.C3Els[1].c1"&~"my_demux.my_demux.vc.C3Els[1].c2"&~"my_demux.my_demux.vc.C3Els[1].c3"->"my_demux.my_demux.vc.C3Els[1]._y"+
"my_demux.my_demux.vc.C3Els[1].c1"&"my_demux.my_demux.vc.C3Els[1].c2"&"my_demux.my_demux.vc.C3Els[1].c3"->"my_demux.my_demux.vc.C3Els[1]._y"-
"my_demux.my_demux.vc.C3Els[1]._y"->"my_demux.my_demux.vc.C3Els[1].y"-
~("my_demux.my_demux.vc.C3Els[1]._y")->"my_demux.my_demux.vc.C3Els[1].y"+
~"my_demux.my_demux.vc.ct.C2Els[0].c1"&~"my_demux.my_demux.vc.ct.C2Els[0].c2"->"my_demux.my_demux.vc.ct.C2Els[0]._y"+
"my_demux.my_demux.vc.ct.C2Els[0].c1"&"my_demux.my_demux.vc.ct.C2Els[0].c2"->"my_demux.my_demux.vc.ct.C2Els[0]._y"-
"my_demux.my_demux.vc.ct.C2Els[0]._y"->"my_demux.my_demux.vc.ct.C2Els[0].y"-
~("my_demux.my_demux.vc.ct.C2Els[0]._y")->"my_demux.my_demux.vc.ct.C2Els[0].y"+
~"my_demux.my_demux.vc.ct.C2Els[1].c1"&~"my_demux.my_demux.vc.ct.C2Els[1].c2"->"my_demux.my_demux.vc.ct.C2Els[1]._y"+
"my_demux.my_demux.vc.ct.C2Els[1].c1"&"my_demux.my_demux.vc.ct.C2Els[1].c2"->"my_demux.my_demux.vc.ct.C2Els[1]._y"-
"my_demux.my_demux.vc.ct.C2Els[1]._y"->"my_demux.my_demux.vc.ct.C2Els[1].y"-
~("my_demux.my_demux.vc.ct.C2Els[1]._y")->"my_demux.my_demux.vc.ct.C2Els[1].y"+
~"my_demux.my_demux.vc.ct.C3Els[0].c1"&~"my_demux.my_demux.vc.ct.C3Els[0].c2"&~"my_demux.my_demux.vc.ct.C3Els[0].c3"->"my_demux.my_demux.vc.ct.C3Els[0]._y"+
"my_demux.my_demux.vc.ct.C3Els[0].c1"&"my_demux.my_demux.vc.ct.C3Els[0].c2"&"my_demux.my_demux.vc.ct.C3Els[0].c3"->"my_demux.my_demux.vc.ct.C3Els[0]._y"-
"my_demux.my_demux.vc.ct.C3Els[0]._y"->"my_demux.my_demux.vc.ct.C3Els[0].y"-
~("my_demux.my_demux.vc.ct.C3Els[0]._y")->"my_demux.my_demux.vc.ct.C3Els[0].y"+
~"my_demux.my_demux.vc.ct.C3Els[1].c1"&~"my_demux.my_demux.vc.ct.C3Els[1].c2"&~"my_demux.my_demux.vc.ct.C3Els[1].c3"->"my_demux.my_demux.vc.ct.C3Els[1]._y"+
"my_demux.my_demux.vc.ct.C3Els[1].c1"&"my_demux.my_demux.vc.ct.C3Els[1].c2"&"my_demux.my_demux.vc.ct.C3Els[1].c3"->"my_demux.my_demux.vc.ct.C3Els[1]._y"-
"my_demux.my_demux.vc.ct.C3Els[1]._y"->"my_demux.my_demux.vc.ct.C3Els[1].y"-
~("my_demux.my_demux.vc.ct.C3Els[1]._y")->"my_demux.my_demux.vc.ct.C3Els[1].y"+
= "my_demux.my_demux.vc.ct.tmp[7]" "my_demux.my_demux.vc.ct.C3Els[1].c1"
= "my_demux.my_demux.vc.ct.tmp[7]" "my_demux.my_demux.vc.ct.C2Els[0].y"
= "my_demux.my_demux.vc.ct.tmp[8]" "my_demux.my_demux.vc.ct.C3Els[1].c2"
= "my_demux.my_demux.vc.ct.tmp[8]" "my_demux.my_demux.vc.ct.C2Els[1].y"
= "my_demux.my_demux.vc.ct.tmp[9]" "my_demux.my_demux.vc.ct.C3Els[1].c3"
= "my_demux.my_demux.vc.ct.tmp[9]" "my_demux.my_demux.vc.ct.C3Els[0].y"
= "my_demux.my_demux.vc.ct.supply.vdd" "my_demux.my_demux.vc.ct.C3Els[1].vdd"
= "my_demux.my_demux.vc.ct.supply.vdd" "my_demux.my_demux.vc.ct.C3Els[0].vdd"
= "my_demux.my_demux.vc.ct.supply.vdd" "my_demux.my_demux.vc.ct.C2Els[1].vdd"
= "my_demux.my_demux.vc.ct.supply.vdd" "my_demux.my_demux.vc.ct.C2Els[0].vdd"
= "my_demux.my_demux.vc.ct.supply.vss" "my_demux.my_demux.vc.ct.C3Els[1].vss"
= "my_demux.my_demux.vc.ct.supply.vss" "my_demux.my_demux.vc.ct.C3Els[0].vss"
= "my_demux.my_demux.vc.ct.supply.vss" "my_demux.my_demux.vc.ct.C2Els[1].vss"
= "my_demux.my_demux.vc.ct.supply.vss" "my_demux.my_demux.vc.ct.C2Els[0].vss"
= "my_demux.my_demux.vc.ct.in[0]" "my_demux.my_demux.vc.ct.C2Els[0].c1"
= "my_demux.my_demux.vc.ct.in[0]" "my_demux.my_demux.vc.ct.tmp[0]"
= "my_demux.my_demux.vc.ct.in[1]" "my_demux.my_demux.vc.ct.C2Els[0].c2"
= "my_demux.my_demux.vc.ct.in[1]" "my_demux.my_demux.vc.ct.tmp[1]"
= "my_demux.my_demux.vc.ct.in[2]" "my_demux.my_demux.vc.ct.C2Els[1].c1"
= "my_demux.my_demux.vc.ct.in[2]" "my_demux.my_demux.vc.ct.tmp[2]"
= "my_demux.my_demux.vc.ct.in[3]" "my_demux.my_demux.vc.ct.C2Els[1].c2"
= "my_demux.my_demux.vc.ct.in[3]" "my_demux.my_demux.vc.ct.tmp[3]"
= "my_demux.my_demux.vc.ct.in[4]" "my_demux.my_demux.vc.ct.C3Els[0].c1"
= "my_demux.my_demux.vc.ct.in[4]" "my_demux.my_demux.vc.ct.tmp[4]"
= "my_demux.my_demux.vc.ct.in[5]" "my_demux.my_demux.vc.ct.C3Els[0].c2"
= "my_demux.my_demux.vc.ct.in[5]" "my_demux.my_demux.vc.ct.tmp[5]"
= "my_demux.my_demux.vc.ct.in[6]" "my_demux.my_demux.vc.ct.C3Els[0].c3"
= "my_demux.my_demux.vc.ct.in[6]" "my_demux.my_demux.vc.ct.tmp[6]"
= "my_demux.my_demux.vc.ct.out" "my_demux.my_demux.vc.ct.C3Els[1].y"
= "my_demux.my_demux.vc.ct.out" "my_demux.my_demux.vc.ct.tmp[10]"
= "my_demux.my_demux.vc.ct.in[0]" "my_demux.my_demux.vc.OR2_tf[0].y"
= "my_demux.my_demux.vc.ct.in[1]" "my_demux.my_demux.vc.OR2_tf[1].y"
= "my_demux.my_demux.vc.ct.in[2]" "my_demux.my_demux.vc.OR2_tf[2].y"
= "my_demux.my_demux.vc.ct.in[3]" "my_demux.my_demux.vc.OR2_tf[3].y"
= "my_demux.my_demux.vc.ct.in[4]" "my_demux.my_demux.vc.OR2_tf[4].y"
= "my_demux.my_demux.vc.ct.in[5]" "my_demux.my_demux.vc.OR2_tf[5].y"
= "my_demux.my_demux.vc.ct.in[6]" "my_demux.my_demux.vc.OR2_tf[6].y"
"my_demux.my_demux.vc.OR2_tf[0].a"|"my_demux.my_demux.vc.OR2_tf[0].b"->"my_demux.my_demux.vc.OR2_tf[0]._y"-
~("my_demux.my_demux.vc.OR2_tf[0].a"|"my_demux.my_demux.vc.OR2_tf[0].b")->"my_demux.my_demux.vc.OR2_tf[0]._y"+
"my_demux.my_demux.vc.OR2_tf[0]._y"->"my_demux.my_demux.vc.OR2_tf[0].y"-
@ -974,30 +1018,8 @@
~("my_demux.my_demux.vc.OR2_tf[6].a"|"my_demux.my_demux.vc.OR2_tf[6].b")->"my_demux.my_demux.vc.OR2_tf[6]._y"+
"my_demux.my_demux.vc.OR2_tf[6]._y"->"my_demux.my_demux.vc.OR2_tf[6].y"-
~("my_demux.my_demux.vc.OR2_tf[6]._y")->"my_demux.my_demux.vc.OR2_tf[6].y"+
= "my_demux.my_demux.vc.tmp[0]" "my_demux.my_demux.vc.C2Els[0].c1"
= "my_demux.my_demux.vc.tmp[0]" "my_demux.my_demux.vc.OR2_tf[0].y"
= "my_demux.my_demux.vc.tmp[1]" "my_demux.my_demux.vc.C2Els[0].c2"
= "my_demux.my_demux.vc.tmp[1]" "my_demux.my_demux.vc.OR2_tf[1].y"
= "my_demux.my_demux.vc.tmp[2]" "my_demux.my_demux.vc.C2Els[1].c1"
= "my_demux.my_demux.vc.tmp[2]" "my_demux.my_demux.vc.OR2_tf[2].y"
= "my_demux.my_demux.vc.tmp[3]" "my_demux.my_demux.vc.C2Els[1].c2"
= "my_demux.my_demux.vc.tmp[3]" "my_demux.my_demux.vc.OR2_tf[3].y"
= "my_demux.my_demux.vc.tmp[4]" "my_demux.my_demux.vc.C3Els[0].c1"
= "my_demux.my_demux.vc.tmp[4]" "my_demux.my_demux.vc.OR2_tf[4].y"
= "my_demux.my_demux.vc.tmp[5]" "my_demux.my_demux.vc.C3Els[0].c2"
= "my_demux.my_demux.vc.tmp[5]" "my_demux.my_demux.vc.OR2_tf[5].y"
= "my_demux.my_demux.vc.tmp[6]" "my_demux.my_demux.vc.C3Els[0].c3"
= "my_demux.my_demux.vc.tmp[6]" "my_demux.my_demux.vc.OR2_tf[6].y"
= "my_demux.my_demux.vc.tmp[7]" "my_demux.my_demux.vc.C3Els[1].c1"
= "my_demux.my_demux.vc.tmp[7]" "my_demux.my_demux.vc.C2Els[0].y"
= "my_demux.my_demux.vc.tmp[8]" "my_demux.my_demux.vc.C3Els[1].c2"
= "my_demux.my_demux.vc.tmp[8]" "my_demux.my_demux.vc.C2Els[1].y"
= "my_demux.my_demux.vc.tmp[9]" "my_demux.my_demux.vc.C3Els[1].c3"
= "my_demux.my_demux.vc.tmp[9]" "my_demux.my_demux.vc.C3Els[0].y"
= "my_demux.my_demux.vc.supply.vdd" "my_demux.my_demux.vc.C3Els[1].vdd"
= "my_demux.my_demux.vc.supply.vdd" "my_demux.my_demux.vc.C3Els[0].vdd"
= "my_demux.my_demux.vc.supply.vdd" "my_demux.my_demux.vc.C2Els[1].vdd"
= "my_demux.my_demux.vc.supply.vdd" "my_demux.my_demux.vc.C2Els[0].vdd"
= "my_demux.my_demux.vc.supply.vss" "my_demux.my_demux.vc.ct.supply.vss"
= "my_demux.my_demux.vc.supply.vdd" "my_demux.my_demux.vc.ct.supply.vdd"
= "my_demux.my_demux.vc.supply.vdd" "my_demux.my_demux.vc.OR2_tf[6].vdd"
= "my_demux.my_demux.vc.supply.vdd" "my_demux.my_demux.vc.OR2_tf[5].vdd"
= "my_demux.my_demux.vc.supply.vdd" "my_demux.my_demux.vc.OR2_tf[4].vdd"
@ -1005,10 +1027,6 @@
= "my_demux.my_demux.vc.supply.vdd" "my_demux.my_demux.vc.OR2_tf[2].vdd"
= "my_demux.my_demux.vc.supply.vdd" "my_demux.my_demux.vc.OR2_tf[1].vdd"
= "my_demux.my_demux.vc.supply.vdd" "my_demux.my_demux.vc.OR2_tf[0].vdd"
= "my_demux.my_demux.vc.supply.vss" "my_demux.my_demux.vc.C3Els[1].vss"
= "my_demux.my_demux.vc.supply.vss" "my_demux.my_demux.vc.C3Els[0].vss"
= "my_demux.my_demux.vc.supply.vss" "my_demux.my_demux.vc.C2Els[1].vss"
= "my_demux.my_demux.vc.supply.vss" "my_demux.my_demux.vc.C2Els[0].vss"
= "my_demux.my_demux.vc.supply.vss" "my_demux.my_demux.vc.OR2_tf[6].vss"
= "my_demux.my_demux.vc.supply.vss" "my_demux.my_demux.vc.OR2_tf[5].vss"
= "my_demux.my_demux.vc.supply.vss" "my_demux.my_demux.vc.OR2_tf[4].vss"
@ -1016,6 +1034,7 @@
= "my_demux.my_demux.vc.supply.vss" "my_demux.my_demux.vc.OR2_tf[2].vss"
= "my_demux.my_demux.vc.supply.vss" "my_demux.my_demux.vc.OR2_tf[1].vss"
= "my_demux.my_demux.vc.supply.vss" "my_demux.my_demux.vc.OR2_tf[0].vss"
= "my_demux.my_demux.vc.out" "my_demux.my_demux.vc.ct.out"
= "my_demux.my_demux.vc.in.d[0].d[0]" "my_demux.my_demux.vc.in.d[0].f"
= "my_demux.my_demux.vc.in.d[0].d[1]" "my_demux.my_demux.vc.in.d[0].t"
= "my_demux.my_demux.vc.in.d[1].d[0]" "my_demux.my_demux.vc.in.d[1].f"
@ -1072,8 +1091,6 @@
= "my_demux.my_demux.vc.in.d[0].d[0]" "my_demux.my_demux.vc.in.d[0].f"
= "my_demux.my_demux.vc.in.d[0].d[1]" "my_demux.my_demux.vc.OR2_tf[0].a"
= "my_demux.my_demux.vc.in.d[0].d[1]" "my_demux.my_demux.vc.in.d[0].t"
= "my_demux.my_demux.vc.out" "my_demux.my_demux.vc.C3Els[1].y"
= "my_demux.my_demux.vc.out" "my_demux.my_demux.vc.tmp[10]"
"my_demux.my_demux.out2_a_B_buf_f.buf2.a"->"my_demux.my_demux.out2_a_B_buf_f.buf2._y"-
~("my_demux.my_demux.out2_a_B_buf_f.buf2.a")->"my_demux.my_demux.out2_a_B_buf_f.buf2._y"+
"my_demux.my_demux.out2_a_B_buf_f.buf2._y"->"my_demux.my_demux.out2_a_B_buf_f.buf2.y"-
@ -1110,6 +1127,9 @@
= "my_demux.my_demux.cond.d.d[0].d[1]" "my_demux.my_demux.cond.d.d[0].t"
= "my_demux.my_demux.cond.d.d[0].d[0]" "my_demux.my_demux.cond.d.d[0].f"
= "my_demux.my_demux.cond.d.d[0].d[1]" "my_demux.my_demux.cond.d.d[0].t"
= "my_demux.my_demux.cond.v" "my_demux.my_demux.c_el.y"
= "my_demux.my_demux.cond.v" "my_demux.my_demux.inack_ctl.c2"
= "my_demux.my_demux.cond.v" "my_demux.my_demux._in_c_v_"
= "my_demux.my_demux.cond.d.d[0].d[0]" "my_demux.my_demux.c_f_c_t_or.b"
= "my_demux.my_demux.cond.d.d[0].d[0]" "my_demux.my_demux.c_buf_f.in"
= "my_demux.my_demux.cond.d.d[0].d[0]" "my_demux.my_demux.cond.d.d[0].f"
@ -1386,6 +1406,7 @@
= "my_demux.in.d.d[6].t" "my_demux.my_demux.in.d.d[6].t"
= "my_demux.in.d.d[6].d[0]" "my_demux.my_demux.in.d.d[6].d[0]"
= "my_demux.in.d.d[6].d[1]" "my_demux.my_demux.in.d.d[6].d[1]"
= "my_demux.in.a" "my_demux.cond.a"
= "my_demux.in.d.d[6].d[0]" "my_demux.in.d.d[6].f"
= "my_demux.in.d.d[6].d[1]" "my_demux.in.d.d[6].t"
= "my_demux.in.d.d[5].d[0]" "my_demux.in.d.d[5].f"

3
test/unit_tests/demux_7/test.prsim
View File

@ -18,6 +18,7 @@ mode run
assert-qdi-channel-neutral "my_demux.out1" 7
assert-qdi-channel-neutral "my_demux.out2" 7
assert-qdi-channel-neutral "my_demux.in" 7
assert my_demux.cond.v 0
cycle
system "echo 'Output neutral checked'"
@ -28,6 +29,7 @@ set-qdi-channel-valid "my_demux.in" 7 127
cycle
assert my_demux.in.v 1
assert my_demux.in.a 0
assert my_demux.cond.v 1
assert-qdi-channel-valid "my_demux.out1" 7 127
set my_demux.out1.v 1
@ -68,6 +70,7 @@ set-qdi-channel-valid "my_demux.in" 7 100
cycle
assert my_demux.in.v 1
assert my_demux.in.a 0
assert my_demux.cond.v 1
assert-qdi-channel-valid "my_demux.out2" 7 100
set my_demux.out2.v 1

336
test/unit_tests/demux_bit_7/run/prsim.out Normal file
View File

@ -0,0 +1,336 @@
my_demux.in.d.d[5].t my_demux.my_demux.demux._en2_X_t[0] my_demux.in.d.d[2].f my_demux.my_demux.demux._out1_a_BX_f[0] my_demux.my_demux.demux._out2_a_BX_t[0] my_demux.in.d.d[5].f my_demux.my_demux.demux._out1_a_B my_demux.my_demux.demux._en1_X_t[0] my_demux.my_demux.demux._out_v my_demux.in.d.d[1].f my_demux.my_demux.demux._out2_a_BX_f[0] my_demux.my_demux.demux._en1_X_f[0] my_demux.in.d.d[6].f my_demux.in.d.d[2].t my_demux.my_demux.demux.vc.OR2_tf[2]._y my_demux.my_demux.demux.out1_a_B_buf_t.buf2._y my_demux.in.d.d[0].f my_demux.my_demux.demux._c_f_buf[0] my_demux.my_demux.demux.vc.ct.in[1] my_demux.my_demux.demux._out1_a_BX_t[0] my_demux.my_demux.demux._c_t_buf[0] my_demux.out1.a my_demux.my_demux.demux.out2_a_B_buf_f.buf2._y my_demux.my_demux.demux.vc.ct.tmp[8] my_demux.in.d.d[4].f my_demux.in.d.d[4].t my_demux.my_demux.demux._in_c_v_ my_demux.my_demux.demux.out_or._y my_demux.my_demux.demux._c_v my_demux.my_demux.demux._en2_X_f[0] my_demux.my_demux.demux.vc.ct.in[6] my_demux.in.d.d[6].t my_demux.in.d.d[1].t my_demux.in.d.d[0].t my_demux.my_demux.demux._out2_a_B my_demux.in.d.d[3].f my_demux.out2.a my_demux.in.v my_demux.my_demux.demux.vc.OR2_tf[1]._y my_demux.my_demux.demux.vc.ct.C3Els[0]._y my_demux.my_demux.demux.vc.ct.C2Els[1]._y my_demux.my_demux.demux._en my_demux.in.d.d[3].t my_demux.my_demux.demux.vc.ct.tmp[9] my_demux.my_demux.demux.vc.ct.in[5] my_demux.my_demux.demux.vc.ct.in[4] my_demux.my_demux.demux.vc.ct.in[2] my_demux.out2.v my_demux.my_demux.demux.vc.ct.C3Els[1]._y my_demux.my_demux.demux.vc.ct.C2Els[0]._y my_demux.my_demux.demux.vc.OR2_tf[0]._y my_demux.my_demux.demux.vc.ct.in[3] my_demux.my_demux.demux.c_buf_f.buf2._y my_demux.my_demux.demux.vc.ct.tmp[7] my_demux.my_demux.demux.vc.OR2_tf[6]._y my_demux.my_demux.demux.vc.ct.in[0] my_demux.my_demux.demux._in_v my_demux.my_demux.demux.c_buf_t.buf2._y my_demux.out1.v my_demux.my_demux.demux.out2_a_B_buf_t.buf2._y my_demux.my_demux.demux.vc.OR2_tf[5]._y my_demux.my_demux.demux.c_el._y my_demux.my_demux.demux.out2_en_buf_t.buf2._y my_demux.my_demux.demux.in_v_buf._y my_demux.my_demux.demux.vc.OR2_tf[4]._y my_demux.my_demux.demux.c_f_c_t_or._y my_demux.my_demux.demux.out1_en_buf_f.buf2._y my_demux.my_demux.demux.out2_en_buf_f.buf2._y my_demux.my_demux.demux.out1_en_buf_t.buf2._y my_demux.my_demux.demux.out1_a_B_buf_f.buf2._y my_demux.my_demux.demux.vc.OR2_tf[3]._y
119199 my_demux.in.d.d[0].f : 0
119199 my_demux.in.d.d[0].t : 0
119199 my_demux.in.d.d[1].f : 0
119199 my_demux.in.d.d[3].f : 0
119199 my_demux.in.d.d[7].f : 0
119199 my_demux.in.d.d[6].t : 0
119199 my_demux.out2.v : 0
119199 my_demux.out2.a : 0
119199 my_demux.out1.v : 0
119199 my_demux.in.d.d[2].t : 0
119199 my_demux.in.d.d[6].f : 0
119199 my_demux.out1.a : 0
119199 my_demux.in.d.d[5].t : 0
119199 my_demux.in.d.d[7].t : 0
119199 my_demux.in.d.d[2].f : 0
119199 my_demux.in.d.d[5].f : 0
119199 my_demux.in.d.d[4].t : 0
119199 my_demux.in.d.d[1].t : 0
119199 my_demux.in.d.d[4].f : 0
119199 my_demux.in.d.d[3].t : 0
119200 my_demux.my_demux.demux.c_buf_f.buf2._y : 1 [by my_demux.in.d.d[0].f:=0]
119200 my_demux.my_demux.demux.vc.OR2_tf[5]._y : 1 [by my_demux.in.d.d[5].f:=0]
119236 my_demux.my_demux.demux.c_buf_t.buf2._y : 1 [by my_demux.in.d.d[0].t:=0]
119239 my_demux.my_demux.demux.out_or._y : 1 [by my_demux.out1.v:=0]
119286 my_demux.my_demux.demux._out1_a_B : 1 [by my_demux.out1.a:=0]
119308 my_demux.my_demux.demux.out1_a_B_buf_t.buf2._y : 0 [by my_demux.my_demux.demux._out1_a_B:=1]
119311 my_demux.my_demux.demux.vc.OR2_tf[0]._y : 1 [by my_demux.in.d.d[0].t:=0]
119378 my_demux.my_demux.demux.vc.ct.in[5] : 0 [by my_demux.my_demux.demux.vc.OR2_tf[5]._y:=1]
119403 my_demux.my_demux.demux._out_v : 0 [by my_demux.my_demux.demux.out_or._y:=1]
119456 my_demux.my_demux.demux.vc.OR2_tf[6]._y : 1 [by my_demux.in.d.d[6].f:=0]
119493 my_demux.my_demux.demux.vc.OR2_tf[2]._y : 1 [by my_demux.in.d.d[2].f:=0]
119536 my_demux.my_demux.demux._en : 1 [by my_demux.my_demux.demux._out_v:=0]
119543 my_demux.my_demux.demux.out2_en_buf_t.buf2._y : 0 [by my_demux.my_demux.demux._en:=1]
119566 my_demux.my_demux.demux.out1_en_buf_f.buf2._y : 0 [by my_demux.my_demux.demux._en:=1]
119757 my_demux.my_demux.demux.out1_en_buf_t.buf2._y : 0 [by my_demux.my_demux.demux._en:=1]
119790 my_demux.my_demux.demux._c_f_buf[0] : 0 [by my_demux.my_demux.demux.c_buf_f.buf2._y:=1]
119848 my_demux.my_demux.demux._en1_X_t[0] : 1 [by my_demux.my_demux.demux.out1_en_buf_t.buf2._y:=0]
119852 my_demux.my_demux.demux.vc.ct.in[2] : 0 [by my_demux.my_demux.demux.vc.OR2_tf[2]._y:=1]
119938 my_demux.my_demux.demux.c_f_c_t_or._y : 1 [by my_demux.in.d.d[0].t:=0]
120039 my_demux.my_demux.demux._c_t_buf[0] : 0 [by my_demux.my_demux.demux.c_buf_t.buf2._y:=1]
120155 my_demux.my_demux.demux._out1_a_BX_f[0] : 1 [by my_demux.my_demux.demux.out1_a_B_buf_t.buf2._y:=0]
120408 my_demux.my_demux.demux.vc.OR2_tf[3]._y : 1 [by my_demux.in.d.d[3].t:=0]
120415 my_demux.my_demux.demux.vc.ct.in[3] : 0 [by my_demux.my_demux.demux.vc.OR2_tf[3]._y:=1]
121005 my_demux.my_demux.demux.vc.OR2_tf[1]._y : 1 [by my_demux.in.d.d[1].t:=0]
121111 my_demux.my_demux.demux.vc.ct.in[1] : 0 [by my_demux.my_demux.demux.vc.OR2_tf[1]._y:=1]
121206 my_demux.my_demux.demux.vc.OR2_tf[4]._y : 1 [by my_demux.in.d.d[4].f:=0]
121284 my_demux.my_demux.demux.vc.ct.in[4] : 0 [by my_demux.my_demux.demux.vc.OR2_tf[4]._y:=1]
121481 my_demux.my_demux.demux.out1_a_B_buf_f.buf2._y : 0 [by my_demux.my_demux.demux._out1_a_B:=1]
121756 my_demux.my_demux.demux._out1_a_BX_t[0] : 1 [by my_demux.my_demux.demux.out1_a_B_buf_f.buf2._y:=0]
122127 my_demux.my_demux.demux._c_v : 0 [by my_demux.my_demux.demux.c_f_c_t_or._y:=1]
123202 my_demux.my_demux.demux.vc.ct.C2Els[1]._y : 1 [by my_demux.my_demux.demux.vc.ct.in[3]:=0]
126256 my_demux.my_demux.demux._en2_X_t[0] : 1 [by my_demux.my_demux.demux.out2_en_buf_t.buf2._y:=0]
133652 my_demux.my_demux.demux.out2_en_buf_f.buf2._y : 0 [by my_demux.my_demux.demux._en:=1]
134107 my_demux.my_demux.demux._en2_X_f[0] : 1 [by my_demux.my_demux.demux.out2_en_buf_f.buf2._y:=0]
135118 my_demux.my_demux.demux.vc.ct.in[6] : 0 [by my_demux.my_demux.demux.vc.OR2_tf[6]._y:=1]
135130 my_demux.my_demux.demux.vc.ct.C3Els[0]._y : 1 [by my_demux.my_demux.demux.vc.ct.in[6]:=0]
135534 my_demux.my_demux.demux.vc.ct.tmp[9] : 0 [by my_demux.my_demux.demux.vc.ct.C3Els[0]._y:=1]
142198 my_demux.my_demux.demux.vc.ct.tmp[8] : 0 [by my_demux.my_demux.demux.vc.ct.C2Els[1]._y:=1]
149439 my_demux.my_demux.demux.vc.ct.in[0] : 0 [by my_demux.my_demux.demux.vc.OR2_tf[0]._y:=1]
149451 my_demux.my_demux.demux.vc.ct.C2Els[0]._y : 1 [by my_demux.my_demux.demux.vc.ct.in[0]:=0]
155367 my_demux.my_demux.demux.vc.ct.tmp[7] : 0 [by my_demux.my_demux.demux.vc.ct.C2Els[0]._y:=1]
159643 my_demux.my_demux.demux.vc.ct.C3Els[1]._y : 1 [by my_demux.my_demux.demux.vc.ct.tmp[7]:=0]
162542 my_demux.my_demux.demux._in_v : 0 [by my_demux.my_demux.demux.vc.ct.C3Els[1]._y:=1]
162544 my_demux.my_demux.demux.c_el._y : 1 [by my_demux.my_demux.demux._in_v:=0]
166711 my_demux.my_demux.demux._out2_a_B : 1 [by my_demux.out2.a:=0]
166837 my_demux.my_demux.demux.in_v_buf._y : 1 [by my_demux.my_demux.demux._in_v:=0]
167003 my_demux.in.v : 0 [by my_demux.my_demux.demux.in_v_buf._y:=1]
167079 my_demux.my_demux.demux._in_c_v_ : 0 [by my_demux.my_demux.demux.c_el._y:=1]
167960 my_demux.my_demux.demux.out2_a_B_buf_t.buf2._y : 0 [by my_demux.my_demux.demux._out2_a_B:=1]
168035 my_demux.my_demux.demux._out2_a_BX_f[0] : 1 [by my_demux.my_demux.demux.out2_a_B_buf_t.buf2._y:=0]
170210 my_demux.my_demux.demux.out2_a_B_buf_f.buf2._y : 0 [by my_demux.my_demux.demux._out2_a_B:=1]
170555 my_demux.my_demux.demux._out2_a_BX_t[0] : 1 [by my_demux.my_demux.demux.out2_a_B_buf_f.buf2._y:=0]
177027 my_demux.my_demux.demux._en1_X_f[0] : 1 [by my_demux.my_demux.demux.out1_en_buf_f.buf2._y:=0]
System initialized
177027 Reset : 0
177165 my_demux._reset_B : 1 [by Reset:=0]
182428 my_demux.my_demux.demux.reset_buf._y : 0 [by my_demux._reset_B:=1]
182430 my_demux.my_demux.demux._reset_BX : 1 [by my_demux.my_demux.demux.reset_buf._y:=0]
226347 my_demux.my_demux.demux.reset_bufarray.buf4._y : 0 [by my_demux.my_demux.demux._reset_BX:=1]
226348 my_demux.my_demux.demux._reset_BXX[0] : 1 [by my_demux.my_demux.demux.reset_bufarray.buf4._y:=0]
System reset completed
Output neutral checked
226348 my_demux.in.d.d[0].t : 1
226348 my_demux.in.d.d[7].t : 1
226348 my_demux.in.d.d[2].t : 1
226348 my_demux.in.d.d[6].t : 1
226348 my_demux.in.d.d[5].t : 1
226348 my_demux.in.d.d[1].t : 1
226348 my_demux.in.d.d[4].t : 1
226348 my_demux.in.d.d[3].t : 1
226359 my_demux.my_demux.demux.c_f_c_t_or._y : 0 [by my_demux.in.d.d[0].t:=1]
226364 my_demux.my_demux.demux.vc.OR2_tf[5]._y : 0 [by my_demux.in.d.d[5].t:=1]
226415 my_demux.my_demux.demux.vc.OR2_tf[2]._y : 0 [by my_demux.in.d.d[2].t:=1]
226718 my_demux.my_demux.demux.vc.OR2_tf[0]._y : 0 [by my_demux.in.d.d[0].t:=1]
226720 my_demux.my_demux.demux.vc.ct.in[0] : 1 [by my_demux.my_demux.demux.vc.OR2_tf[0]._y:=0]
226876 my_demux.my_demux.demux.vc.OR2_tf[4]._y : 0 [by my_demux.in.d.d[4].t:=1]
226896 my_demux.my_demux.demux.c_buf_t.buf2._y : 0 [by my_demux.in.d.d[0].t:=1]
226899 my_demux.my_demux.demux._c_t_buf[0] : 1 [by my_demux.my_demux.demux.c_buf_t.buf2._y:=0]
226928 my_demux.my_demux.demux.out1_t_buf_func[0]._y : 0 [by my_demux.my_demux.demux._c_t_buf[0]:=1]
226929 my_demux.out1.d.d[0].t : 1 [by my_demux.my_demux.demux.out1_t_buf_func[0]._y:=0]
226943 my_demux.my_demux.demux.out1_t_buf_func[4]._y : 0 [by my_demux.my_demux.demux._c_t_buf[0]:=1]
227052 my_demux.my_demux.demux.out1_t_buf_func[3]._y : 0 [by my_demux.my_demux.demux._c_t_buf[0]:=1]
227074 my_demux.out1.d.d[3].t : 1 [by my_demux.my_demux.demux.out1_t_buf_func[3]._y:=0]
227160 my_demux.out1.d.d[4].t : 1 [by my_demux.my_demux.demux.out1_t_buf_func[4]._y:=0]
227216 my_demux.my_demux.demux.out1_t_buf_func[1]._y : 0 [by my_demux.my_demux.demux._c_t_buf[0]:=1]
227217 my_demux.out1.d.d[1].t : 1 [by my_demux.my_demux.demux.out1_t_buf_func[1]._y:=0]
228500 my_demux.my_demux.demux.out1_t_buf_func[2]._y : 0 [by my_demux.my_demux.demux._c_t_buf[0]:=1]
228783 my_demux.my_demux.demux.vc.OR2_tf[3]._y : 0 [by my_demux.in.d.d[3].t:=1]
228989 my_demux.my_demux.demux.vc.OR2_tf[6]._y : 0 [by my_demux.in.d.d[6].t:=1]
229148 my_demux.my_demux.demux.vc.ct.in[6] : 1 [by my_demux.my_demux.demux.vc.OR2_tf[6]._y:=0]
229660 my_demux.my_demux.demux.out1_t_buf_func[5]._y : 0 [by my_demux.my_demux.demux._c_t_buf[0]:=1]
230081 my_demux.out1.d.d[2].t : 1 [by my_demux.my_demux.demux.out1_t_buf_func[2]._y:=0]
230910 my_demux.my_demux.demux.vc.OR2_tf[1]._y : 0 [by my_demux.in.d.d[1].t:=1]
232197 my_demux.my_demux.demux.vc.ct.in[1] : 1 [by my_demux.my_demux.demux.vc.OR2_tf[1]._y:=0]
234429 my_demux.my_demux.demux.vc.ct.C2Els[0]._y : 0 [by my_demux.my_demux.demux.vc.ct.in[1]:=1]
234574 my_demux.my_demux.demux.vc.ct.tmp[7] : 1 [by my_demux.my_demux.demux.vc.ct.C2Els[0]._y:=0]
238128 my_demux.my_demux.demux.vc.ct.in[3] : 1 [by my_demux.my_demux.demux.vc.OR2_tf[3]._y:=0]
239456 my_demux.my_demux.demux.vc.ct.in[2] : 1 [by my_demux.my_demux.demux.vc.OR2_tf[2]._y:=0]
240582 my_demux.my_demux.demux.out1_t_buf_func[6]._y : 0 [by my_demux.my_demux.demux._c_t_buf[0]:=1]
242288 my_demux.my_demux.demux.vc.ct.C2Els[1]._y : 0 [by my_demux.my_demux.demux.vc.ct.in[2]:=1]
242289 my_demux.my_demux.demux.vc.ct.tmp[8] : 1 [by my_demux.my_demux.demux.vc.ct.C2Els[1]._y:=0]
246936 my_demux.out1.d.d[6].t : 1 [by my_demux.my_demux.demux.out1_t_buf_func[6]._y:=0]
249336 my_demux.out1.d.d[5].t : 1 [by my_demux.my_demux.demux.out1_t_buf_func[5]._y:=0]
250289 my_demux.my_demux.demux.vc.ct.in[5] : 1 [by my_demux.my_demux.demux.vc.OR2_tf[5]._y:=0]
253239 my_demux.my_demux.demux._c_v : 1 [by my_demux.my_demux.demux.c_f_c_t_or._y:=0]
287834 my_demux.my_demux.demux.vc.ct.in[4] : 1 [by my_demux.my_demux.demux.vc.OR2_tf[4]._y:=0]
327118 my_demux.my_demux.demux.vc.ct.C3Els[0]._y : 0 [by my_demux.my_demux.demux.vc.ct.in[4]:=1]
327280 my_demux.my_demux.demux.vc.ct.tmp[9] : 1 [by my_demux.my_demux.demux.vc.ct.C3Els[0]._y:=0]
334649 my_demux.my_demux.demux.vc.ct.C3Els[1]._y : 0 [by my_demux.my_demux.demux.vc.ct.tmp[9]:=1]
334663 my_demux.my_demux.demux._in_v : 1 [by my_demux.my_demux.demux.vc.ct.C3Els[1]._y:=0]
334670 my_demux.my_demux.demux.in_v_buf._y : 0 [by my_demux.my_demux.demux._in_v:=1]
334823 my_demux.my_demux.demux.c_el._y : 0 [by my_demux.my_demux.demux._in_v:=1]
334824 my_demux.my_demux.demux._in_c_v_ : 1 [by my_demux.my_demux.demux.c_el._y:=0]
356227 my_demux.in.v : 1 [by my_demux.my_demux.demux.in_v_buf._y:=0]
356227 my_demux.out1.v : 1
356228 my_demux.my_demux.demux.out_or._y : 0 [by my_demux.out1.v:=1]
356229 my_demux.my_demux.demux._out_v : 1 [by my_demux.my_demux.demux.out_or._y:=0]
358472 my_demux.my_demux.demux.inack_ctl._y : 0 [by my_demux.my_demux.demux._out_v:=1]
358659 my_demux.in.a : 1 [by my_demux.my_demux.demux.inack_ctl._y:=0]
358660 my_demux.my_demux.demux._en : 0 [by my_demux.in.a:=1]
358661 my_demux.my_demux.demux.out2_en_buf_t.buf2._y : 1 [by my_demux.my_demux.demux._en:=0]
358666 my_demux.my_demux.demux._en2_X_t[0] : 0 [by my_demux.my_demux.demux.out2_en_buf_t.buf2._y:=1]
359513 my_demux.my_demux.demux.out1_en_buf_f.buf2._y : 1 [by my_demux.my_demux.demux._en:=0]
360404 my_demux.my_demux.demux._en1_X_f[0] : 0 [by my_demux.my_demux.demux.out1_en_buf_f.buf2._y:=1]
362842 my_demux.my_demux.demux.out2_en_buf_f.buf2._y : 1 [by my_demux.my_demux.demux._en:=0]
362843 my_demux.my_demux.demux._en2_X_f[0] : 0 [by my_demux.my_demux.demux.out2_en_buf_f.buf2._y:=1]
393442 my_demux.my_demux.demux.out1_en_buf_t.buf2._y : 1 [by my_demux.my_demux.demux._en:=0]
393459 my_demux.my_demux.demux._en1_X_t[0] : 0 [by my_demux.my_demux.demux.out1_en_buf_t.buf2._y:=1]
393459 my_demux.in.d.d[0].t : 0
393459 my_demux.in.d.d[7].t : 0
393459 my_demux.in.d.d[2].t : 0
393459 my_demux.in.d.d[6].t : 0
393459 my_demux.in.d.d[5].t : 0
393459 my_demux.in.d.d[1].t : 0
393459 my_demux.in.d.d[4].t : 0
393459 my_demux.in.d.d[3].t : 0
393460 my_demux.my_demux.demux.vc.OR2_tf[5]._y : 1 [by my_demux.in.d.d[5].t:=0]
393462 my_demux.my_demux.demux.vc.OR2_tf[0]._y : 1 [by my_demux.in.d.d[0].t:=0]
393501 my_demux.my_demux.demux.vc.OR2_tf[1]._y : 1 [by my_demux.in.d.d[1].t:=0]
393509 my_demux.my_demux.demux.vc.ct.in[1] : 0 [by my_demux.my_demux.demux.vc.OR2_tf[1]._y:=1]
393555 my_demux.my_demux.demux.vc.ct.in[5] : 0 [by my_demux.my_demux.demux.vc.OR2_tf[5]._y:=1]
393797 my_demux.my_demux.demux.vc.ct.in[0] : 0 [by my_demux.my_demux.demux.vc.OR2_tf[0]._y:=1]
393831 my_demux.my_demux.demux.vc.ct.C2Els[0]._y : 1 [by my_demux.my_demux.demux.vc.ct.in[0]:=0]
394400 my_demux.my_demux.demux.vc.OR2_tf[2]._y : 1 [by my_demux.in.d.d[2].t:=0]
395318 my_demux.my_demux.demux.vc.ct.in[2] : 0 [by my_demux.my_demux.demux.vc.OR2_tf[2]._y:=1]
396032 my_demux.my_demux.demux.c_buf_t.buf2._y : 1 [by my_demux.in.d.d[0].t:=0]
396036 my_demux.my_demux.demux._c_t_buf[0] : 0 [by my_demux.my_demux.demux.c_buf_t.buf2._y:=1]
396276 my_demux.my_demux.demux.vc.OR2_tf[4]._y : 1 [by my_demux.in.d.d[4].t:=0]
401820 my_demux.my_demux.demux.c_f_c_t_or._y : 1 [by my_demux.in.d.d[0].t:=0]
404218 my_demux.my_demux.demux._c_v : 0 [by my_demux.my_demux.demux.c_f_c_t_or._y:=1]
407192 my_demux.my_demux.demux.vc.OR2_tf[3]._y : 1 [by my_demux.in.d.d[3].t:=0]
407718 my_demux.my_demux.demux.vc.ct.tmp[7] : 0 [by my_demux.my_demux.demux.vc.ct.C2Els[0]._y:=1]
410407 my_demux.my_demux.demux.vc.ct.in[3] : 0 [by my_demux.my_demux.demux.vc.OR2_tf[3]._y:=1]
442654 my_demux.my_demux.demux.vc.ct.in[4] : 0 [by my_demux.my_demux.demux.vc.OR2_tf[4]._y:=1]
452421 my_demux.my_demux.demux.vc.OR2_tf[6]._y : 1 [by my_demux.in.d.d[6].t:=0]
452469 my_demux.my_demux.demux.vc.ct.in[6] : 0 [by my_demux.my_demux.demux.vc.OR2_tf[6]._y:=1]
452472 my_demux.my_demux.demux.vc.ct.C3Els[0]._y : 1 [by my_demux.my_demux.demux.vc.ct.in[6]:=0]
452650 my_demux.my_demux.demux.vc.ct.tmp[9] : 0 [by my_demux.my_demux.demux.vc.ct.C3Els[0]._y:=1]
457526 my_demux.my_demux.demux.vc.ct.C2Els[1]._y : 1 [by my_demux.my_demux.demux.vc.ct.in[3]:=0]
478503 my_demux.my_demux.demux.vc.ct.tmp[8] : 0 [by my_demux.my_demux.demux.vc.ct.C2Els[1]._y:=1]
490402 my_demux.my_demux.demux.vc.ct.C3Els[1]._y : 1 [by my_demux.my_demux.demux.vc.ct.tmp[8]:=0]
496353 my_demux.my_demux.demux._in_v : 0 [by my_demux.my_demux.demux.vc.ct.C3Els[1]._y:=1]
497180 my_demux.my_demux.demux.c_el._y : 1 [by my_demux.my_demux.demux._in_v:=0]
497353 my_demux.my_demux.demux._in_c_v_ : 0 [by my_demux.my_demux.demux.c_el._y:=1]
535838 my_demux.my_demux.demux.in_v_buf._y : 1 [by my_demux.my_demux.demux._in_v:=0]
536022 my_demux.in.v : 0 [by my_demux.my_demux.demux.in_v_buf._y:=1]
First Cond Checked
536022 my_demux.out1.a : 1
536023 my_demux.my_demux.demux._out1_a_B : 0 [by my_demux.out1.a:=1]
536027 my_demux.my_demux.demux.out1_a_B_buf_t.buf2._y : 1 [by my_demux.my_demux.demux._out1_a_B:=0]
536096 my_demux.my_demux.demux.out1_a_B_buf_f.buf2._y : 1 [by my_demux.my_demux.demux._out1_a_B:=0]
536192 my_demux.my_demux.demux._out1_a_BX_t[0] : 0 [by my_demux.my_demux.demux.out1_a_B_buf_f.buf2._y:=1]
536193 my_demux.my_demux.demux.out1_t_buf_func[1]._y : 1 [by my_demux.my_demux.demux._out1_a_BX_t[0]:=0]
536204 my_demux.my_demux.demux.out1_t_buf_func[5]._y : 1 [by my_demux.my_demux.demux._out1_a_BX_t[0]:=0]
536205 my_demux.out1.d.d[5].t : 0 [by my_demux.my_demux.demux.out1_t_buf_func[5]._y:=1]
536328 my_demux.my_demux.demux.out1_t_buf_func[0]._y : 1 [by my_demux.my_demux.demux._out1_a_BX_t[0]:=0]
536384 my_demux.out1.d.d[0].t : 0 [by my_demux.my_demux.demux.out1_t_buf_func[0]._y:=1]
536433 my_demux.my_demux.demux.out1_t_buf_func[3]._y : 1 [by my_demux.my_demux.demux._out1_a_BX_t[0]:=0]
537222 my_demux.out1.d.d[1].t : 0 [by my_demux.my_demux.demux.out1_t_buf_func[1]._y:=1]
540092 my_demux.my_demux.demux.out1_t_buf_func[6]._y : 1 [by my_demux.my_demux.demux._out1_a_BX_t[0]:=0]
540093 my_demux.out1.d.d[6].t : 0 [by my_demux.my_demux.demux.out1_t_buf_func[6]._y:=1]
540151 my_demux.my_demux.demux.out1_t_buf_func[4]._y : 1 [by my_demux.my_demux.demux._out1_a_BX_t[0]:=0]
540188 my_demux.out1.d.d[4].t : 0 [by my_demux.my_demux.demux.out1_t_buf_func[4]._y:=1]
555238 my_demux.my_demux.demux.out1_t_buf_func[2]._y : 1 [by my_demux.my_demux.demux._out1_a_BX_t[0]:=0]
573315 my_demux.my_demux.demux._out1_a_BX_f[0] : 0 [by my_demux.my_demux.demux.out1_a_B_buf_t.buf2._y:=1]
578613 my_demux.out1.d.d[2].t : 0 [by my_demux.my_demux.demux.out1_t_buf_func[2]._y:=1]
581439 my_demux.out1.d.d[3].t : 0 [by my_demux.my_demux.demux.out1_t_buf_func[3]._y:=1]
System reset completed
Output neutral checked
581439 my_demux.out1.a : 0
581439 my_demux.out1.v : 0
581440 my_demux.my_demux.demux._out1_a_B : 1 [by my_demux.out1.a:=0]
581453 my_demux.my_demux.demux.out1_a_B_buf_t.buf2._y : 0 [by my_demux.my_demux.demux._out1_a_B:=1]
583132 my_demux.my_demux.demux.out1_a_B_buf_f.buf2._y : 0 [by my_demux.my_demux.demux._out1_a_B:=1]
583489 my_demux.my_demux.demux._out1_a_BX_t[0] : 1 [by my_demux.my_demux.demux.out1_a_B_buf_f.buf2._y:=0]
585003 my_demux.my_demux.demux.out_or._y : 1 [by my_demux.out1.v:=0]
585028 my_demux.my_demux.demux._out_v : 0 [by my_demux.my_demux.demux.out_or._y:=1]
585049 my_demux.my_demux.demux.inack_ctl._y : 1 [by my_demux.my_demux.demux._out_v:=0]
585050 my_demux.in.a : 0 [by my_demux.my_demux.demux.inack_ctl._y:=1]
594698 my_demux.my_demux.demux._en : 1 [by my_demux.in.a:=0]
594699 my_demux.my_demux.demux.out2_en_buf_f.buf2._y : 0 [by my_demux.my_demux.demux._en:=1]
594699 my_demux.my_demux.demux.out1_en_buf_t.buf2._y : 0 [by my_demux.my_demux.demux._en:=1]
594704 my_demux.my_demux.demux._en2_X_f[0] : 1 [by my_demux.my_demux.demux.out2_en_buf_f.buf2._y:=0]
594859 my_demux.my_demux.demux.out2_en_buf_t.buf2._y : 0 [by my_demux.my_demux.demux._en:=1]
595267 my_demux.my_demux.demux._en2_X_t[0] : 1 [by my_demux.my_demux.demux.out2_en_buf_t.buf2._y:=0]
595280 my_demux.my_demux.demux._en1_X_t[0] : 1 [by my_demux.my_demux.demux.out1_en_buf_t.buf2._y:=0]
595735 my_demux.my_demux.demux.out1_en_buf_f.buf2._y : 0 [by my_demux.my_demux.demux._en:=1]
595746 my_demux.my_demux.demux._en1_X_f[0] : 1 [by my_demux.my_demux.demux.out1_en_buf_f.buf2._y:=0]
598437 my_demux.my_demux.demux._out1_a_BX_f[0] : 1 [by my_demux.my_demux.demux.out1_a_B_buf_t.buf2._y:=0]
598437 my_demux.in.d.d[0].f : 1
598437 my_demux.in.d.d[7].f : 1
598437 my_demux.in.d.d[2].t : 1
598437 my_demux.in.d.d[6].t : 1
598437 my_demux.in.d.d[5].t : 1
598437 my_demux.in.d.d[1].f : 1
598437 my_demux.in.d.d[4].f : 1
598437 my_demux.in.d.d[3].f : 1
598441 my_demux.my_demux.demux.vc.OR2_tf[2]._y : 0 [by my_demux.in.d.d[2].t:=1]
598451 my_demux.my_demux.demux.c_buf_f.buf2._y : 0 [by my_demux.in.d.d[0].f:=1]
598455 my_demux.my_demux.demux.vc.OR2_tf[0]._y : 0 [by my_demux.in.d.d[0].f:=1]
598525 my_demux.my_demux.demux.vc.ct.in[0] : 1 [by my_demux.my_demux.demux.vc.OR2_tf[0]._y:=0]
598541 my_demux.my_demux.demux.vc.OR2_tf[6]._y : 0 [by my_demux.in.d.d[6].t:=1]
598665 my_demux.my_demux.demux.vc.OR2_tf[3]._y : 0 [by my_demux.in.d.d[3].f:=1]
598676 my_demux.my_demux.demux.vc.ct.in[3] : 1 [by my_demux.my_demux.demux.vc.OR2_tf[3]._y:=0]
599284 my_demux.my_demux.demux.vc.ct.in[2] : 1 [by my_demux.my_demux.demux.vc.OR2_tf[2]._y:=0]
599287 my_demux.my_demux.demux.vc.ct.C2Els[1]._y : 0 [by my_demux.my_demux.demux.vc.ct.in[2]:=1]
599341 my_demux.my_demux.demux.vc.ct.tmp[8] : 1 [by my_demux.my_demux.demux.vc.ct.C2Els[1]._y:=0]
599484 my_demux.my_demux.demux.c_f_c_t_or._y : 0 [by my_demux.in.d.d[0].f:=1]
599641 my_demux.my_demux.demux.vc.OR2_tf[1]._y : 0 [by my_demux.in.d.d[1].f:=1]
599910 my_demux.my_demux.demux._c_f_buf[0] : 1 [by my_demux.my_demux.demux.c_buf_f.buf2._y:=0]
599991 my_demux.my_demux.demux.out2_t_buf_func[5]._y : 0 [by my_demux.my_demux.demux._c_f_buf[0]:=1]
600002 my_demux.my_demux.demux.out2_f_buf_func[1]._y : 0 [by my_demux.my_demux.demux._c_f_buf[0]:=1]
600604 my_demux.out2.d.d[5].t : 1 [by my_demux.my_demux.demux.out2_t_buf_func[5]._y:=0]
600632 my_demux.my_demux.demux._c_v : 1 [by my_demux.my_demux.demux.c_f_c_t_or._y:=0]
600802 my_demux.my_demux.demux.vc.ct.in[1] : 1 [by my_demux.my_demux.demux.vc.OR2_tf[1]._y:=0]
600847 my_demux.my_demux.demux.vc.ct.C2Els[0]._y : 0 [by my_demux.my_demux.demux.vc.ct.in[1]:=1]
601654 my_demux.my_demux.demux.out2_f_buf_func[4]._y : 0 [by my_demux.my_demux.demux._c_f_buf[0]:=1]
601844 my_demux.my_demux.demux.vc.ct.tmp[7] : 1 [by my_demux.my_demux.demux.vc.ct.C2Els[0]._y:=0]
603303 my_demux.out2.d.d[4].f : 1 [by my_demux.my_demux.demux.out2_f_buf_func[4]._y:=0]
606892 my_demux.my_demux.demux.vc.OR2_tf[4]._y : 0 [by my_demux.in.d.d[4].f:=1]
607417 my_demux.my_demux.demux.vc.ct.in[4] : 1 [by my_demux.my_demux.demux.vc.OR2_tf[4]._y:=0]
608221 my_demux.my_demux.demux.out2_f_buf_func[3]._y : 0 [by my_demux.my_demux.demux._c_f_buf[0]:=1]
608562 my_demux.my_demux.demux.out2_t_buf_func[2]._y : 0 [by my_demux.my_demux.demux._c_f_buf[0]:=1]
608614 my_demux.out2.d.d[2].t : 1 [by my_demux.my_demux.demux.out2_t_buf_func[2]._y:=0]
609121 my_demux.out2.d.d[3].f : 1 [by my_demux.my_demux.demux.out2_f_buf_func[3]._y:=0]
610987 my_demux.my_demux.demux.out2_t_buf_func[6]._y : 0 [by my_demux.my_demux.demux._c_f_buf[0]:=1]
610994 my_demux.out2.d.d[6].t : 1 [by my_demux.my_demux.demux.out2_t_buf_func[6]._y:=0]
614024 my_demux.out2.d.d[1].f : 1 [by my_demux.my_demux.demux.out2_f_buf_func[1]._y:=0]
617893 my_demux.my_demux.demux.out2_f_buf_func[0]._y : 0 [by my_demux.my_demux.demux._c_f_buf[0]:=1]
629881 my_demux.my_demux.demux.vc.OR2_tf[5]._y : 0 [by my_demux.in.d.d[5].t:=1]
633505 my_demux.out2.d.d[0].f : 1 [by my_demux.my_demux.demux.out2_f_buf_func[0]._y:=0]
636348 my_demux.my_demux.demux.vc.ct.in[5] : 1 [by my_demux.my_demux.demux.vc.OR2_tf[5]._y:=0]
648963 my_demux.my_demux.demux.vc.ct.in[6] : 1 [by my_demux.my_demux.demux.vc.OR2_tf[6]._y:=0]
648965 my_demux.my_demux.demux.vc.ct.C3Els[0]._y : 0 [by my_demux.my_demux.demux.vc.ct.in[6]:=1]
649319 my_demux.my_demux.demux.vc.ct.tmp[9] : 1 [by my_demux.my_demux.demux.vc.ct.C3Els[0]._y:=0]
649452 my_demux.my_demux.demux.vc.ct.C3Els[1]._y : 0 [by my_demux.my_demux.demux.vc.ct.tmp[9]:=1]
649453 my_demux.my_demux.demux._in_v : 1 [by my_demux.my_demux.demux.vc.ct.C3Els[1]._y:=0]
649457 my_demux.my_demux.demux.in_v_buf._y : 0 [by my_demux.my_demux.demux._in_v:=1]
649999 my_demux.my_demux.demux.c_el._y : 0 [by my_demux.my_demux.demux._in_v:=1]
650000 my_demux.my_demux.demux._in_c_v_ : 1 [by my_demux.my_demux.demux.c_el._y:=0]
695020 my_demux.in.v : 1 [by my_demux.my_demux.demux.in_v_buf._y:=0]
695020 my_demux.out2.v : 1
707398 my_demux.my_demux.demux.out_or._y : 0 [by my_demux.out2.v:=1]
707477 my_demux.my_demux.demux._out_v : 1 [by my_demux.my_demux.demux.out_or._y:=0]
709910 my_demux.my_demux.demux.inack_ctl._y : 0 [by my_demux.my_demux.demux._out_v:=1]
709998 my_demux.in.a : 1 [by my_demux.my_demux.demux.inack_ctl._y:=0]
717780 my_demux.my_demux.demux._en : 0 [by my_demux.in.a:=1]
717810 my_demux.my_demux.demux.out2_en_buf_t.buf2._y : 1 [by my_demux.my_demux.demux._en:=0]
717839 my_demux.my_demux.demux.out1_en_buf_t.buf2._y : 1 [by my_demux.my_demux.demux._en:=0]
719247 my_demux.my_demux.demux.out1_en_buf_f.buf2._y : 1 [by my_demux.my_demux.demux._en:=0]
719932 my_demux.my_demux.demux._en1_X_f[0] : 0 [by my_demux.my_demux.demux.out1_en_buf_f.buf2._y:=1]
737223 my_demux.my_demux.demux._en1_X_t[0] : 0 [by my_demux.my_demux.demux.out1_en_buf_t.buf2._y:=1]
746107 my_demux.my_demux.demux.out2_en_buf_f.buf2._y : 1 [by my_demux.my_demux.demux._en:=0]
762822 my_demux.my_demux.demux._en2_X_f[0] : 0 [by my_demux.my_demux.demux.out2_en_buf_f.buf2._y:=1]
777314 my_demux.my_demux.demux._en2_X_t[0] : 0 [by my_demux.my_demux.demux.out2_en_buf_t.buf2._y:=1]
777314 my_demux.in.d.d[0].f : 0
777314 my_demux.in.d.d[6].t : 0
777314 my_demux.in.d.d[2].t : 0
777314 my_demux.in.d.d[5].t : 0
777314 my_demux.in.d.d[1].f : 0
777314 my_demux.in.d.d[4].f : 0
777314 my_demux.in.d.d[3].f : 0
777315 my_demux.my_demux.demux.vc.OR2_tf[3]._y : 1 [by my_demux.in.d.d[3].f:=0]
777317 my_demux.my_demux.demux.vc.OR2_tf[1]._y : 1 [by my_demux.in.d.d[1].f:=0]
777326 my_demux.my_demux.demux.vc.OR2_tf[6]._y : 1 [by my_demux.in.d.d[6].t:=0]
777352 my_demux.my_demux.demux.vc.OR2_tf[4]._y : 1 [by my_demux.in.d.d[4].f:=0]
777354 my_demux.my_demux.demux.vc.ct.in[4] : 0 [by my_demux.my_demux.demux.vc.OR2_tf[4]._y:=1]
777357 my_demux.my_demux.demux.vc.OR2_tf[0]._y : 1 [by my_demux.in.d.d[0].f:=0]
777358 my_demux.my_demux.demux.vc.ct.in[0] : 0 [by my_demux.my_demux.demux.vc.OR2_tf[0]._y:=1]
777409 my_demux.my_demux.demux.vc.ct.in[1] : 0 [by my_demux.my_demux.demux.vc.OR2_tf[1]._y:=1]
777441 my_demux.my_demux.demux.c_f_c_t_or._y : 1 [by my_demux.in.d.d[0].f:=0]
777443 my_demux.my_demux.demux._c_v : 0 [by my_demux.my_demux.demux.c_f_c_t_or._y:=1]
777483 my_demux.my_demux.demux.c_buf_f.buf2._y : 1 [by my_demux.in.d.d[0].f:=0]
777501 my_demux.my_demux.demux._c_f_buf[0] : 0 [by my_demux.my_demux.demux.c_buf_f.buf2._y:=1]
777547 my_demux.my_demux.demux.vc.OR2_tf[5]._y : 1 [by my_demux.in.d.d[5].t:=0]
777666 my_demux.my_demux.demux.vc.ct.in[5] : 0 [by my_demux.my_demux.demux.vc.OR2_tf[5]._y:=1]
778593 my_demux.my_demux.demux.vc.OR2_tf[2]._y : 1 [by my_demux.in.d.d[2].t:=0]
778910 my_demux.my_demux.demux.vc.ct.C2Els[0]._y : 1 [by my_demux.my_demux.demux.vc.ct.in[1]:=0]
778918 my_demux.my_demux.demux.vc.ct.tmp[7] : 0 [by my_demux.my_demux.demux.vc.ct.C2Els[0]._y:=1]
780053 my_demux.my_demux.demux.vc.ct.in[6] : 0 [by my_demux.my_demux.demux.vc.OR2_tf[6]._y:=1]
780107 my_demux.my_demux.demux.vc.ct.C3Els[0]._y : 1 [by my_demux.my_demux.demux.vc.ct.in[6]:=0]
784313 my_demux.my_demux.demux.vc.ct.in[2] : 0 [by my_demux.my_demux.demux.vc.OR2_tf[2]._y:=1]
790067 my_demux.my_demux.demux.vc.ct.in[3] : 0 [by my_demux.my_demux.demux.vc.OR2_tf[3]._y:=1]
790072 my_demux.my_demux.demux.vc.ct.C2Els[1]._y : 1 [by my_demux.my_demux.demux.vc.ct.in[3]:=0]
791139 my_demux.my_demux.demux.vc.ct.tmp[8] : 0 [by my_demux.my_demux.demux.vc.ct.C2Els[1]._y:=1]
830645 my_demux.my_demux.demux.vc.ct.tmp[9] : 0 [by my_demux.my_demux.demux.vc.ct.C3Els[0]._y:=1]
830646 my_demux.my_demux.demux.vc.ct.C3Els[1]._y : 1 [by my_demux.my_demux.demux.vc.ct.tmp[9]:=0]
830784 my_demux.my_demux.demux._in_v : 0 [by my_demux.my_demux.demux.vc.ct.C3Els[1]._y:=1]
830785 my_demux.my_demux.demux.in_v_buf._y : 1 [by my_demux.my_demux.demux._in_v:=0]
830848 my_demux.my_demux.demux.c_el._y : 1 [by my_demux.my_demux.demux._in_v:=0]
830850 my_demux.my_demux.demux._in_c_v_ : 0 [by my_demux.my_demux.demux.c_el._y:=1]
830908 my_demux.in.v : 0 [by my_demux.my_demux.demux.in_v_buf._y:=1]
Second Cond Checked

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test/unit_tests/demux_bit_7/run/test.prs Normal file
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test/unit_tests/demux_bit_7/test.act Normal file
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/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/primitives.act";
import globals;
open tmpl::dataflow_neuro;
defproc demux_bit_7 (avMx1of2<8> in; avMx1of2<7> out1; avMx1of2<7> out2){
demux_bit<7,0> my_demux(.in=in, .out1=out1,.out2 = out2);
//Low active Reset
bool _reset_B;
prs {
Reset => _reset_B-
}
my_demux.supply.vss = GND;
my_demux.supply.vdd = Vdd;
my_demux.reset_B = _reset_B;
}
demux_bit_7 my_demux;

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watchall
set-qdi-channel-neutral "my_demux.in" 8
set my_demux.out1.a 0
set my_demux.out1.v 0
set my_demux.out2.a 0
set my_demux.out2.v 0
set my_demux.in.d.d[0].t 0
set my_demux.in.d.d[0].f 0
cycle
system "echo 'System initialized'"
set Reset 0
cycle
system "echo 'System reset completed'"
status X
mode run
assert-qdi-channel-neutral "my_demux.out1" 7
assert-qdi-channel-neutral "my_demux.out2" 7
assert-qdi-channel-neutral "my_demux.in" 8
cycle
system "echo 'Output neutral checked'"
set-qdi-channel-valid "my_demux.in" 8 255
cycle
assert my_demux.in.v 1
assert my_demux.in.a 0
assert-qdi-channel-valid "my_demux.out1" 7 127
assert-qdi-channel-neutral "my_demux.out2" 7
set my_demux.out1.v 1
cycle
assert my_demux.in.a 1
set-qdi-channel-neutral "my_demux.in" 8
cycle
set my_demux.out1.a 1
system "echo 'First Cond Checked'"
set Reset 0
cycle
system "echo 'System reset completed'"
status X
mode run
assert-qdi-channel-neutral "my_demux.out1" 7
assert-qdi-channel-neutral "my_demux.out2" 7
assert-qdi-channel-neutral "my_demux.in" 8
cycle
system "echo 'Output neutral checked'"
set my_demux.out1.a 0
set my_demux.out1.v 0
set my_demux.out2.a 0
set my_demux.out2.v 0
cycle
set-qdi-channel-valid "my_demux.in" 8 100
cycle
assert my_demux.in.v 1
assert my_demux.in.a 0
assert-qdi-channel-valid "my_demux.out2" 7 100
set my_demux.out2.v 1
cycle
assert my_demux.in.a 1
set-qdi-channel-neutral "my_demux.in" 7
cycle
system "echo 'Second Cond Checked'"

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test/unit_tests/fifo_demux_bit_7_fifo/run/prsim.out Normal file
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/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/primitives.act";
import globals;
open tmpl::dataflow_neuro;
defproc fifo_demux_bit_7_fifo (avMx1of2<8> in; avMx1of2<7> out1; avMx1of2<7> out2){
bool _reset_B;
prs {
Reset => _reset_B-
}
power supply;
supply.vdd = Vdd;
supply.vss = GND;
fifo<8,5> fifo_pre(.in = in, .reset_B = _reset_B, .supply = supply);
demux_bit<7,0> demux(.in = fifo_pre.out);
//Low active Reset
demux.supply.vss = GND;
demux.supply.vdd = Vdd;
demux.reset_B = _reset_B;
fifo<7,5> fifo_post1(.in = demux.out1, .out=out1, .reset_B = _reset_B, .supply = supply);
fifo<7,5> fifo_post2(.in = demux.out2, .out=out2, .reset_B = _reset_B, .supply = supply);
}
fifo_demux_bit_7_fifo b;

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watchall
set-qdi-channel-neutral "b.in" 8
set b.out1.a 0
set b.out1.v 0
set b.out2.a 0
set b.out2.v 0
cycle
mode run
system "echo '[] Set reset 0'"
status X
set Reset 0
cycle
assert b.in.a 0
assert b.in.v 0
set-qdi-channel-valid "b.in" 8 255
cycle
assert b.in.v 1
assert b.in.a 1
assert-qdi-channel-valid "b.out1" 7 127
assert-qdi-channel-neutral "b.out2" 7
set b.out1.v 1
cycle
assert b.in.a 1
set-qdi-channel-neutral "b.in" 8
cycle
set b.out1.a 1
system "echo 'First Cond Checked'"
set Reset 0
cycle
system "echo 'System reset completed'"
status X
mode run
assert-qdi-channel-neutral "b.out1" 7
assert-qdi-channel-neutral "b.out2" 7
assert-qdi-channel-neutral "b.in" 8
cycle
system "echo 'Output neutral checked'"
set b.out1.a 0
set b.out1.v 0
set b.out2.a 0
set b.out2.v 0
cycle
set-qdi-channel-valid "b.in" 8 100
cycle
assert b.in.v 1
assert b.in.a 1
assert-qdi-channel-valid "b.out2" 7 100
set b.out2.v 1
cycle
assert b.in.a 1
set-qdi-channel-neutral "b.in" 7
cycle
system "echo 'Second Cond Checked'"