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removed extra supply vss lines from tiehi/lows

This commit is contained in:
alexmadison 2022-06-29 18:25:44 +02:00
parent 9a7a34c02f
commit a70c9a1b6d
9 changed files with 200 additions and 200 deletions
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test/unit_tests/texel_dualcore_glue/netlist_clean.v
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@ -70087,7 +70087,7 @@ module tmpl_0_0dataflow__neuro_0_0append_331_71_71_4(Iin_d_d0_d0 , Iin_d_d0_d1 ,
wire Iin_d_d10_d1 ;
// --- instances
TIELO_X1 Itielows0 (.y(Iout_d_d31_d0 ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows0 (.y(Iout_d_d31_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0vtree_331_4 Iin_val (.Iin_d0_d0 (Iin_d_d0_d0 ), .Iin_d0_d1 (Iin_d_d0_d1 ), .Iin_d1_d0 (Iin_d_d1_d0 ), .Iin_d1_d1 (Iin_d_d1_d1 ), .Iin_d2_d0 (Iin_d_d2_d0 ), .Iin_d2_d1 (Iin_d_d2_d1 ), .Iin_d3_d0 (Iin_d_d3_d0 ), .Iin_d3_d1 (Iin_d_d3_d1 ), .Iin_d4_d0 (Iin_d_d4_d0 ), .Iin_d4_d1 (Iin_d_d4_d1 ), .Iin_d5_d0 (Iin_d_d5_d0 ), .Iin_d5_d1 (Iin_d_d5_d1 ), .Iin_d6_d0 (Iin_d_d6_d0 ), .Iin_d6_d1 (Iin_d_d6_d1 ), .Iin_d7_d0 (Iin_d_d7_d0 ), .Iin_d7_d1 (Iin_d_d7_d1 ), .Iin_d8_d0 (Iin_d_d8_d0 ), .Iin_d8_d1 (Iin_d_d8_d1 ), .Iin_d9_d0 (Iin_d_d9_d0 ), .Iin_d9_d1 (Iin_d_d9_d1 ), .Iin_d10_d0 (Iin_d_d10_d0 ), .Iin_d10_d1 (Iin_d_d10_d1 ), .Iin_d11_d0 (Iin_d_d11_d0 ), .Iin_d11_d1 (Iin_d_d11_d1 ), .Iin_d12_d0 (Iin_d_d12_d0 ), .Iin_d12_d1 (Iin_d_d12_d1 ), .Iin_d13_d0 (Iin_d_d13_d0 ), .Iin_d13_d1 (Iin_d_d13_d1 ), .Iin_d14_d0 (Iin_d_d14_d0 ), .Iin_d14_d1 (Iin_d_d14_d1 ), .Iin_d15_d0 (Iin_d_d15_d0 ), .Iin_d15_d1 (Iin_d_d15_d1 ), .Iin_d16_d0 (Iin_d_d16_d0 ), .Iin_d16_d1 (Iin_d_d16_d1 ), .Iin_d17_d0 (Iin_d_d17_d0 ), .Iin_d17_d1 (Iin_d_d17_d1 ), .Iin_d18_d0 (Iin_d_d18_d0 ), .Iin_d18_d1 (Iin_d_d18_d1 ), .Iin_d19_d0 (Iin_d_d19_d0 ), .Iin_d19_d1 (Iin_d_d19_d1 ), .Iin_d20_d0 (Iin_d_d20_d0 ), .Iin_d20_d1 (Iin_d_d20_d1 ), .Iin_d21_d0 (Iin_d_d21_d0 ), .Iin_d21_d1 (Iin_d_d21_d1 ), .Iin_d22_d0 (Iin_d_d22_d0 ), .Iin_d22_d1 (Iin_d_d22_d1 ), .Iin_d23_d0 (Iin_d_d23_d0 ), .Iin_d23_d1 (Iin_d_d23_d1 ), .Iin_d24_d0 (Iin_d_d24_d0 ), .Iin_d24_d1 (Iin_d_d24_d1 ), .Iin_d25_d0 (Iin_d_d25_d0 ), .Iin_d25_d1 (Iin_d_d25_d1 ), .Iin_d26_d0 (Iin_d_d26_d0 ), .Iin_d26_d1 (Iin_d_d26_d1 ), .Iin_d27_d0 (Iin_d_d27_d0 ), .Iin_d27_d1 (Iin_d_d27_d1 ), .Iin_d28_d0 (Iin_d_d28_d0 ), .Iin_d28_d1 (Iin_d_d28_d1 ), .Iin_d29_d0 (Iin_d_d29_d0 ), .Iin_d29_d1 (Iin_d_d29_d1 ), .Iin_d30_d0 (Iin_d_d30_d0 ), .Iin_d30_d1 (Iin_d_d30_d1 ), .out(Isb_in ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0sigbuf_31_4 Isb (.in(Isb_in ), .Iout0 (Iout_d_d31_d1 ), .vdd(vdd), .vss(vss));
endmodule
@ -76131,30 +76131,30 @@ module tmpl_0_0dataflow__neuro_0_0append_37_724_70_4(Iin_d_d0_d0 , Iin_d_d0_d1 ,
output Iout_d_d23_d1 ;
// --- instances
TIELO_X1 Itielows0 (.y(Iout_d_d7_d1 ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows1 (.y(Iout_d_d8_d1 ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows2 (.y(Iout_d_d9_d1 ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows3 (.y(Iout_d_d10_d1 ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows4 (.y(Iout_d_d11_d1 ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows5 (.y(Iout_d_d12_d1 ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows6 (.y(Iout_d_d13_d1 ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows7 (.y(Iout_d_d14_d1 ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows8 (.y(Iout_d_d15_d1 ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows9 (.y(Iout_d_d16_d1 ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows10 (.y(Iout_d_d17_d1 ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows11 (.y(Iout_d_d18_d1 ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows12 (.y(Iout_d_d19_d1 ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows13 (.y(Iout_d_d20_d1 ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows14 (.y(Iout_d_d21_d1 ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows15 (.y(Iout_d_d22_d1 ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows16 (.y(Iout_d_d23_d1 ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows17 (.y(Iout_d_d24_d1 ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows18 (.y(Iout_d_d25_d1 ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows19 (.y(Iout_d_d26_d1 ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows20 (.y(Iout_d_d27_d1 ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows21 (.y(Iout_d_d28_d1 ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows22 (.y(Iout_d_d29_d1 ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows23 (.y(Iout_d_d30_d1 ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows0 (.y(Iout_d_d7_d1 ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows1 (.y(Iout_d_d8_d1 ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows2 (.y(Iout_d_d9_d1 ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows3 (.y(Iout_d_d10_d1 ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows4 (.y(Iout_d_d11_d1 ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows5 (.y(Iout_d_d12_d1 ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows6 (.y(Iout_d_d13_d1 ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows7 (.y(Iout_d_d14_d1 ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows8 (.y(Iout_d_d15_d1 ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows9 (.y(Iout_d_d16_d1 ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows10 (.y(Iout_d_d17_d1 ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows11 (.y(Iout_d_d18_d1 ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows12 (.y(Iout_d_d19_d1 ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows13 (.y(Iout_d_d20_d1 ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows14 (.y(Iout_d_d21_d1 ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows15 (.y(Iout_d_d22_d1 ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows16 (.y(Iout_d_d23_d1 ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows17 (.y(Iout_d_d24_d1 ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows18 (.y(Iout_d_d25_d1 ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows19 (.y(Iout_d_d26_d1 ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows20 (.y(Iout_d_d27_d1 ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows21 (.y(Iout_d_d28_d1 ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows22 (.y(Iout_d_d29_d1 ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows23 (.y(Iout_d_d30_d1 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0vtree_37_4 Iin_val (.Iin_d0_d0 (Iin_d_d0_d0 ), .Iin_d0_d1 (Iin_d_d0_d1 ), .Iin_d1_d0 (Iin_d_d1_d0 ), .Iin_d1_d1 (Iin_d_d1_d1 ), .Iin_d2_d0 (Iin_d_d2_d0 ), .Iin_d2_d1 (Iin_d_d2_d1 ), .Iin_d3_d0 (Iin_d_d3_d0 ), .Iin_d3_d1 (Iin_d_d3_d1 ), .Iin_d4_d0 (Iin_d_d4_d0 ), .Iin_d4_d1 (Iin_d_d4_d1 ), .Iin_d5_d0 (Iin_d_d5_d0 ), .Iin_d5_d1 (Iin_d_d5_d1 ), .Iin_d6_d0 (Iin_d_d6_d0 ), .Iin_d6_d1 (Iin_d_d6_d1 ), .out(Isb_in ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0sigbuf_324_4 Isb (.in(Isb_in ), .Iout0 (Iout_d_d7_d0 ), .vdd(vdd), .vss(vss));
endmodule
@ -89689,70 +89689,70 @@ tmpl_0_0dataflow__neuro_0_0decoder__dualrail_36_764_4 Idecoder (.Iin_d0_d0 (Iin
tmpl_0_0dataflow__neuro_0_0vtree_330_4 Iinput_valid (.Iin_d0_d0 (Iin_d_d0_d0 ), .Iin_d0_d1 (Iin_d_d0_d1 ), .Iin_d1_d0 (Iin_d_d1_d0 ), .Iin_d1_d1 (Iin_d_d1_d1 ), .Iin_d2_d0 (Iin_d_d2_d0 ), .Iin_d2_d1 (Iin_d_d2_d1 ), .Iin_d3_d0 (Iin_d_d3_d0 ), .Iin_d3_d1 (Iin_d_d3_d1 ), .Iin_d4_d0 (Iin_d_d4_d0 ), .Iin_d4_d1 (Iin_d_d4_d1 ), .Iin_d5_d0 (Iin_d_d5_d0 ), .Iin_d5_d1 (Iin_d_d5_d1 ), .Iin_d6_d0 (Iin_d_d6_d0 ), .Iin_d6_d1 (Iin_d_d6_d1 ), .Iin_d7_d0 (Iin_d_d7_d0 ), .Iin_d7_d1 (Iin_d_d7_d1 ), .Iin_d8_d0 (Iin_d_d8_d0 ), .Iin_d8_d1 (Iin_d_d8_d1 ), .Iin_d9_d0 (Iin_d_d9_d0 ), .Iin_d9_d1 (Iin_d_d9_d1 ), .Iin_d10_d0 (Iin_d_d10_d0 ), .Iin_d10_d1 (Iin_d_d10_d1 ), .Iin_d11_d0 (Iin_d_d11_d0 ), .Iin_d11_d1 (Iin_d_d11_d1 ), .Iin_d12_d0 (Iin_d_d12_d0 ), .Iin_d12_d1 (Iin_d_d12_d1 ), .Iin_d13_d0 (Iin_d_d13_d0 ), .Iin_d13_d1 (Iin_d_d13_d1 ), .Iin_d14_d0 (Iin_d_d14_d0 ), .Iin_d14_d1 (Iin_d_d14_d1 ), .Iin_d15_d0 (Iin_d_d15_d0 ), .Iin_d15_d1 (Iin_d_d15_d1 ), .Iin_d16_d0 (Iin_d_d16_d0 ), .Iin_d16_d1 (Iin_d_d16_d1 ), .Iin_d17_d0 (Iin_d_d17_d0 ), .Iin_d17_d1 (Iin_d_d17_d1 ), .Iin_d18_d0 (Iin_d_d18_d0 ), .Iin_d18_d1 (Iin_d_d18_d1 ), .Iin_d19_d0 (Iin_d_d19_d0 ), .Iin_d19_d1 (Iin_d_d19_d1 ), .Iin_d20_d0 (Iin_d_d20_d0 ), .Iin_d20_d1 (Iin_d_d20_d1 ), .Iin_d21_d0 (Iin_d_d21_d0 ), .Iin_d21_d1 (Iin_d_d21_d1 ), .Iin_d22_d0 (Iin_d_d22_d0 ), .Iin_d22_d1 (Iin_d_d22_d1 ), .Iin_d23_d0 (Iin_d_d23_d0 ), .Iin_d23_d1 (Iin_d_d23_d1 ), .Iin_d24_d0 (Iin_d_d24_d0 ), .Iin_d24_d1 (Iin_d_d24_d1 ), .Iin_d25_d0 (Iin_d_d25_d0 ), .Iin_d25_d1 (Iin_d_d25_d1 ), .Iin_d26_d0 (Iin_d_d26_d0 ), .Iin_d26_d1 (Iin_d_d26_d1 ), .Iin_d27_d0 (Iin_d_d27_d0 ), .Iin_d27_d1 (Iin_d_d27_d1 ), .Iin_d28_d0 (Iin_d_d28_d0 ), .Iin_d28_d1 (Iin_d_d28_d1 ), .Iin_d29_d0 (Iin_d_d29_d0 ), .Iin_d29_d1 (Iin_d_d29_d1 ), .out(Iin_v ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0ortree_364_4 Iack_ortree (.Iin0 (Iack_ortree_in0 ), .Iin1 (Iack_ortree_in1 ), .Iin2 (Iack_ortree_in2 ), .Iin3 (Iack_ortree_in3 ), .Iin4 (Iack_ortree_in4 ), .Iin5 (Iack_ortree_in5 ), .Iin6 (Iack_ortree_in6 ), .Iin7 (Iack_ortree_in7 ), .Iin8 (Iack_ortree_in8 ), .Iin9 (Iack_ortree_in9 ), .Iin10 (Iack_ortree_in10 ), .Iin11 (Iack_ortree_in11 ), .Iin12 (Iack_ortree_in12 ), .Iin13 (Iack_ortree_in13 ), .Iin14 (Iack_ortree_in14 ), .Iin15 (Iack_ortree_in15 ), .Iin16 (Iack_ortree_in16 ), .Iin17 (Iack_ortree_in17 ), .Iin18 (Iack_ortree_in18 ), .Iin19 (Iack_ortree_in19 ), .Iin20 (Iack_ortree_in20 ), .Iin21 (Iack_ortree_in21 ), .Iin22 (Iack_ortree_in22 ), .Iin23 (Iack_ortree_in23 ), .Iin24 (Iack_ortree_in24 ), .Iin25 (Iack_ortree_in25 ), .Iin26 (Iack_ortree_in26 ), .Iin27 (Iack_ortree_in27 ), .Iin28 (Iack_ortree_in28 ), .Iin29 (Iack_ortree_in29 ), .Iin30 (Iack_ortree_in30 ), .Iin31 (Iack_ortree_in31 ), .Iin32 (Iack_ortree_in32 ), .Iin33 (Iack_ortree_in33 ), .Iin34 (Iack_ortree_in34 ), .Iin35 (Iack_ortree_in35 ), .Iin36 (Iack_ortree_in36 ), .Iin37 (Iack_ortree_in37 ), .Iin38 (Iack_ortree_in38 ), .Iin39 (Iack_ortree_in39 ), .Iin40 (Iack_ortree_in40 ), .Iin41 (Iack_ortree_in41 ), .Iin42 (Iack_ortree_in42 ), .Iin43 (Iack_ortree_in43 ), .Iin44 (Iack_ortree_in44 ), .Iin45 (Iack_ortree_in45 ), .Iin46 (Iack_ortree_in46 ), .Iin47 (Iack_ortree_in47 ), .Iin48 (Iack_ortree_in48 ), .Iin49 (Iack_ortree_in49 ), .Iin50 (Iack_ortree_in50 ), .Iin51 (Iack_ortree_in51 ), .Iin52 (Iack_ortree_in52 ), .Iin53 (Iack_ortree_in53 ), .Iin54 (Iack_ortree_in54 ), .Iin55 (Iack_ortree_in55 ), .Iin56 (Iack_ortree_in56 ), .Iin57 (Iack_ortree_in57 ), .Iin58 (Iack_ortree_in58 ), .Iin59 (Iack_ortree_in59 ), .Iin60 (Iack_ortree_in60 ), .Iin61 (Iack_ortree_in61 ), .Iin62 (Iack_ortree_in62 ), .Iin63 (Iack_ortree_in63 ), .out(Iack_ortree_out ), .vdd(vdd), .vss(vss));
A_2C_B_X1 Iack_safety (.y(Iin_a ), .c1(Iack_rw_or_y ), .c2(Iin_v ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f0 (.y(Itielow_writebit_f0_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f1 (.y(Itielow_writebit_f1_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f2 (.y(Itielow_writebit_f2_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f3 (.y(Itielow_writebit_f3_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f4 (.y(Itielow_writebit_f4_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f5 (.y(Itielow_writebit_f5_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f6 (.y(Itielow_writebit_f6_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f7 (.y(Itielow_writebit_f7_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f8 (.y(Itielow_writebit_f8_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f9 (.y(Itielow_writebit_f9_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f10 (.y(Itielow_writebit_f10_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f11 (.y(Itielow_writebit_f11_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f12 (.y(Itielow_writebit_f12_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f13 (.y(Itielow_writebit_f13_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f14 (.y(Itielow_writebit_f14_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f15 (.y(Itielow_writebit_f15_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f16 (.y(Itielow_writebit_f16_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f17 (.y(Itielow_writebit_f17_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f18 (.y(Itielow_writebit_f18_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f19 (.y(Itielow_writebit_f19_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f20 (.y(Itielow_writebit_f20_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f21 (.y(Itielow_writebit_f21_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f22 (.y(Itielow_writebit_f22_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f23 (.y(Itielow_writebit_f23_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f24 (.y(Itielow_writebit_f24_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f25 (.y(Itielow_writebit_f25_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f26 (.y(Itielow_writebit_f26_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f27 (.y(Itielow_writebit_f27_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f28 (.y(Itielow_writebit_f28_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f29 (.y(Itielow_writebit_f29_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f30 (.y(Itielow_writebit_f30_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f31 (.y(Itielow_writebit_f31_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f32 (.y(Itielow_writebit_f32_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f33 (.y(Itielow_writebit_f33_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f34 (.y(Itielow_writebit_f34_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f35 (.y(Itielow_writebit_f35_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f36 (.y(Itielow_writebit_f36_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f37 (.y(Itielow_writebit_f37_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f38 (.y(Itielow_writebit_f38_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f39 (.y(Itielow_writebit_f39_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f40 (.y(Itielow_writebit_f40_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f41 (.y(Itielow_writebit_f41_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f42 (.y(Itielow_writebit_f42_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f43 (.y(Itielow_writebit_f43_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f44 (.y(Itielow_writebit_f44_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f45 (.y(Itielow_writebit_f45_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f46 (.y(Itielow_writebit_f46_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f47 (.y(Itielow_writebit_f47_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f48 (.y(Itielow_writebit_f48_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f49 (.y(Itielow_writebit_f49_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f50 (.y(Itielow_writebit_f50_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f51 (.y(Itielow_writebit_f51_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f52 (.y(Itielow_writebit_f52_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f53 (.y(Itielow_writebit_f53_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f54 (.y(Itielow_writebit_f54_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f55 (.y(Itielow_writebit_f55_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f56 (.y(Itielow_writebit_f56_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f57 (.y(Itielow_writebit_f57_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f58 (.y(Itielow_writebit_f58_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f59 (.y(Itielow_writebit_f59_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f60 (.y(Itielow_writebit_f60_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f61 (.y(Itielow_writebit_f61_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f62 (.y(Itielow_writebit_f62_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f63 (.y(Itielow_writebit_f63_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f0 (.y(Itielow_writebit_f0_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f1 (.y(Itielow_writebit_f1_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f2 (.y(Itielow_writebit_f2_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f3 (.y(Itielow_writebit_f3_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f4 (.y(Itielow_writebit_f4_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f5 (.y(Itielow_writebit_f5_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f6 (.y(Itielow_writebit_f6_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f7 (.y(Itielow_writebit_f7_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f8 (.y(Itielow_writebit_f8_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f9 (.y(Itielow_writebit_f9_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f10 (.y(Itielow_writebit_f10_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f11 (.y(Itielow_writebit_f11_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f12 (.y(Itielow_writebit_f12_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f13 (.y(Itielow_writebit_f13_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f14 (.y(Itielow_writebit_f14_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f15 (.y(Itielow_writebit_f15_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f16 (.y(Itielow_writebit_f16_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f17 (.y(Itielow_writebit_f17_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f18 (.y(Itielow_writebit_f18_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f19 (.y(Itielow_writebit_f19_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f20 (.y(Itielow_writebit_f20_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f21 (.y(Itielow_writebit_f21_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f22 (.y(Itielow_writebit_f22_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f23 (.y(Itielow_writebit_f23_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f24 (.y(Itielow_writebit_f24_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f25 (.y(Itielow_writebit_f25_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f26 (.y(Itielow_writebit_f26_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f27 (.y(Itielow_writebit_f27_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f28 (.y(Itielow_writebit_f28_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f29 (.y(Itielow_writebit_f29_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f30 (.y(Itielow_writebit_f30_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f31 (.y(Itielow_writebit_f31_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f32 (.y(Itielow_writebit_f32_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f33 (.y(Itielow_writebit_f33_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f34 (.y(Itielow_writebit_f34_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f35 (.y(Itielow_writebit_f35_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f36 (.y(Itielow_writebit_f36_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f37 (.y(Itielow_writebit_f37_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f38 (.y(Itielow_writebit_f38_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f39 (.y(Itielow_writebit_f39_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f40 (.y(Itielow_writebit_f40_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f41 (.y(Itielow_writebit_f41_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f42 (.y(Itielow_writebit_f42_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f43 (.y(Itielow_writebit_f43_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f44 (.y(Itielow_writebit_f44_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f45 (.y(Itielow_writebit_f45_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f46 (.y(Itielow_writebit_f46_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f47 (.y(Itielow_writebit_f47_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f48 (.y(Itielow_writebit_f48_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f49 (.y(Itielow_writebit_f49_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f50 (.y(Itielow_writebit_f50_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f51 (.y(Itielow_writebit_f51_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f52 (.y(Itielow_writebit_f52_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f53 (.y(Itielow_writebit_f53_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f54 (.y(Itielow_writebit_f54_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f55 (.y(Itielow_writebit_f55_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f56 (.y(Itielow_writebit_f56_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f57 (.y(Itielow_writebit_f57_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f58 (.y(Itielow_writebit_f58_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f59 (.y(Itielow_writebit_f59_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f60 (.y(Itielow_writebit_f60_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f61 (.y(Itielow_writebit_f61_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f62 (.y(Itielow_writebit_f62_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f63 (.y(Itielow_writebit_f63_y ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0sigbuf__boolarray_364_746_4 Iread_selectorsX (.Iin0 (Iread_selectors0_y ), .Iin1 (Iread_selectors1_y ), .Iin2 (Iread_selectors2_y ), .Iin3 (Iread_selectors3_y ), .Iin4 (Iread_selectors4_y ), .Iin5 (Iread_selectors5_y ), .Iin6 (Iread_selectors6_y ), .Iin7 (Iread_selectors7_y ), .Iin8 (Iread_selectors8_y ), .Iin9 (Iread_selectors9_y ), .Iin10 (Iread_selectors10_y ), .Iin11 (Iread_selectors11_y ), .Iin12 (Iread_selectors12_y ), .Iin13 (Iread_selectors13_y ), .Iin14 (Iread_selectors14_y ), .Iin15 (Iread_selectors15_y ), .Iin16 (Iread_selectors16_y ), .Iin17 (Iread_selectors17_y ), .Iin18 (Iread_selectors18_y ), .Iin19 (Iread_selectors19_y ), .Iin20 (Iread_selectors20_y ), .Iin21 (Iread_selectors21_y ), .Iin22 (Iread_selectors22_y ), .Iin23 (Iread_selectors23_y ), .Iin24 (Iread_selectors24_y ), .Iin25 (Iread_selectors25_y ), .Iin26 (Iread_selectors26_y ), .Iin27 (Iread_selectors27_y ), .Iin28 (Iread_selectors28_y ), .Iin29 (Iread_selectors29_y ), .Iin30 (Iread_selectors30_y ), .Iin31 (Iread_selectors31_y ), .Iin32 (Iread_selectors32_y ), .Iin33 (Iread_selectors33_y ), .Iin34 (Iread_selectors34_y ), .Iin35 (Iread_selectors35_y ), .Iin36 (Iread_selectors36_y ), .Iin37 (Iread_selectors37_y ), .Iin38 (Iread_selectors38_y ), .Iin39 (Iread_selectors39_y ), .Iin40 (Iread_selectors40_y ), .Iin41 (Iread_selectors41_y ), .Iin42 (Iread_selectors42_y ), .Iin43 (Iread_selectors43_y ), .Iin44 (Iread_selectors44_y ), .Iin45 (Iread_selectors45_y ), .Iin46 (Iread_selectors46_y ), .Iin47 (Iread_selectors47_y ), .Iin48 (Iread_selectors48_y ), .Iin49 (Iread_selectors49_y ), .Iin50 (Iread_selectors50_y ), .Iin51 (Iread_selectors51_y ), .Iin52 (Iread_selectors52_y ), .Iin53 (Iread_selectors53_y ), .Iin54 (Iread_selectors54_y ), .Iin55 (Iread_selectors55_y ), .Iin56 (Iread_selectors56_y ), .Iin57 (Iread_selectors57_y ), .Iin58 (Iread_selectors58_y ), .Iin59 (Iread_selectors59_y ), .Iin60 (Iread_selectors60_y ), .Iin61 (Iread_selectors61_y ), .Iin62 (Iread_selectors62_y ), .Iin63 (Iread_selectors63_y ), .Iout0 (Iand_reads_f22_b ), .Iout1 (Iand_reads_f45_b ), .Iout2 (Iand_reads_f68_b ), .Iout3 (Iand_reads_f91_b ), .Iout4 (Iand_reads_f114_b ), .Iout5 (Iand_reads_f137_b ), .Iout6 (Iand_reads_f160_b ), .Iout7 (Iand_reads_f183_b ), .Iout8 (Iand_reads_f206_b ), .Iout9 (Iand_reads_f229_b ), .Iout10 (Iand_reads_f252_b ), .Iout11 (Iand_reads_f275_b ), .Iout12 (Iand_reads_f298_b ), .Iout13 (Iand_reads_f321_b ), .Iout14 (Iand_reads_f344_b ), .Iout15 (Iand_reads_f367_b ), .Iout16 (Iand_reads_f390_b ), .Iout17 (Iand_reads_f413_b ), .Iout18 (Iand_reads_f436_b ), .Iout19 (Iand_reads_f459_b ), .Iout20 (Iand_reads_f482_b ), .Iout21 (Iand_reads_f505_b ), .Iout22 (Iand_reads_f528_b ), .Iout23 (Iand_reads_f551_b ), .Iout24 (Iand_reads_f574_b ), .Iout25 (Iand_reads_f597_b ), .Iout26 (Iand_reads_f620_b ), .Iout27 (Iand_reads_f643_b ), .Iout28 (Iand_reads_f666_b ), .Iout29 (Iand_reads_f689_b ), .Iout30 (Iand_reads_f712_b ), .Iout31 (Iand_reads_f735_b ), .Iout32 (Iand_reads_f758_b ), .Iout33 (Iand_reads_f781_b ), .Iout34 (Iand_reads_f804_b ), .Iout35 (Iand_reads_f827_b ), .Iout36 (Iand_reads_f850_b ), .Iout37 (Iand_reads_f873_b ), .Iout38 (Iand_reads_f896_b ), .Iout39 (Iand_reads_f919_b ), .Iout40 (Iand_reads_f942_b ), .Iout41 (Iand_reads_f965_b ), .Iout42 (Iand_reads_f988_b ), .Iout43 (Iand_reads_f1011_b ), .Iout44 (Iand_reads_f1034_b ), .Iout45 (Iand_reads_f1057_b ), .Iout46 (Iand_reads_f1080_b ), .Iout47 (Iand_reads_f1103_b ), .Iout48 (Iand_reads_f1126_b ), .Iout49 (Iand_reads_f1149_b ), .Iout50 (Iand_reads_f1172_b ), .Iout51 (Iand_reads_f1195_b ), .Iout52 (Iand_reads_f1218_b ), .Iout53 (Iand_reads_f1241_b ), .Iout54 (Iand_reads_f1264_b ), .Iout55 (Iand_reads_f1287_b ), .Iout56 (Iand_reads_f1310_b ), .Iout57 (Iand_reads_f1333_b ), .Iout58 (Iand_reads_f1356_b ), .Iout59 (Iand_reads_f1379_b ), .Iout60 (Iand_reads_f1402_b ), .Iout61 (Iand_reads_f1425_b ), .Iout62 (Iand_reads_f1448_b ), .Iout63 (Iand_reads_f1471_b ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0ortree_364_4 Iout_ortrees_t0 (.Iin0 (Iand_reads_t0_y ), .Iin1 (Iand_reads_t23_y ), .Iin2 (Iand_reads_t46_y ), .Iin3 (Iand_reads_t69_y ), .Iin4 (Iand_reads_t92_y ), .Iin5 (Iand_reads_t115_y ), .Iin6 (Iand_reads_t138_y ), .Iin7 (Iand_reads_t161_y ), .Iin8 (Iand_reads_t184_y ), .Iin9 (Iand_reads_t207_y ), .Iin10 (Iand_reads_t230_y ), .Iin11 (Iand_reads_t253_y ), .Iin12 (Iand_reads_t276_y ), .Iin13 (Iand_reads_t299_y ), .Iin14 (Iand_reads_t322_y ), .Iin15 (Iand_reads_t345_y ), .Iin16 (Iand_reads_t368_y ), .Iin17 (Iand_reads_t391_y ), .Iin18 (Iand_reads_t414_y ), .Iin19 (Iand_reads_t437_y ), .Iin20 (Iand_reads_t460_y ), .Iin21 (Iand_reads_t483_y ), .Iin22 (Iand_reads_t506_y ), .Iin23 (Iand_reads_t529_y ), .Iin24 (Iand_reads_t552_y ), .Iin25 (Iand_reads_t575_y ), .Iin26 (Iand_reads_t598_y ), .Iin27 (Iand_reads_t621_y ), .Iin28 (Iand_reads_t644_y ), .Iin29 (Iand_reads_t667_y ), .Iin30 (Iand_reads_t690_y ), .Iin31 (Iand_reads_t713_y ), .Iin32 (Iand_reads_t736_y ), .Iin33 (Iand_reads_t759_y ), .Iin34 (Iand_reads_t782_y ), .Iin35 (Iand_reads_t805_y ), .Iin36 (Iand_reads_t828_y ), .Iin37 (Iand_reads_t851_y ), .Iin38 (Iand_reads_t874_y ), .Iin39 (Iand_reads_t897_y ), .Iin40 (Iand_reads_t920_y ), .Iin41 (Iand_reads_t943_y ), .Iin42 (Iand_reads_t966_y ), .Iin43 (Iand_reads_t989_y ), .Iin44 (Iand_reads_t1012_y ), .Iin45 (Iand_reads_t1035_y ), .Iin46 (Iand_reads_t1058_y ), .Iin47 (Iand_reads_t1081_y ), .Iin48 (Iand_reads_t1104_y ), .Iin49 (Iand_reads_t1127_y ), .Iin50 (Iand_reads_t1150_y ), .Iin51 (Iand_reads_t1173_y ), .Iin52 (Iand_reads_t1196_y ), .Iin53 (Iand_reads_t1219_y ), .Iin54 (Iand_reads_t1242_y ), .Iin55 (Iand_reads_t1265_y ), .Iin56 (Iand_reads_t1288_y ), .Iin57 (Iand_reads_t1311_y ), .Iin58 (Iand_reads_t1334_y ), .Iin59 (Iand_reads_t1357_y ), .Iin60 (Iand_reads_t1380_y ), .Iin61 (Iand_reads_t1403_y ), .Iin62 (Iand_reads_t1426_y ), .Iin63 (Iand_reads_t1449_y ), .out(Iout_d_d6_d1 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0ortree_364_4 Iout_ortrees_t1 (.Iin0 (Iand_reads_t1_y ), .Iin1 (Iand_reads_t24_y ), .Iin2 (Iand_reads_t47_y ), .Iin3 (Iand_reads_t70_y ), .Iin4 (Iand_reads_t93_y ), .Iin5 (Iand_reads_t116_y ), .Iin6 (Iand_reads_t139_y ), .Iin7 (Iand_reads_t162_y ), .Iin8 (Iand_reads_t185_y ), .Iin9 (Iand_reads_t208_y ), .Iin10 (Iand_reads_t231_y ), .Iin11 (Iand_reads_t254_y ), .Iin12 (Iand_reads_t277_y ), .Iin13 (Iand_reads_t300_y ), .Iin14 (Iand_reads_t323_y ), .Iin15 (Iand_reads_t346_y ), .Iin16 (Iand_reads_t369_y ), .Iin17 (Iand_reads_t392_y ), .Iin18 (Iand_reads_t415_y ), .Iin19 (Iand_reads_t438_y ), .Iin20 (Iand_reads_t461_y ), .Iin21 (Iand_reads_t484_y ), .Iin22 (Iand_reads_t507_y ), .Iin23 (Iand_reads_t530_y ), .Iin24 (Iand_reads_t553_y ), .Iin25 (Iand_reads_t576_y ), .Iin26 (Iand_reads_t599_y ), .Iin27 (Iand_reads_t622_y ), .Iin28 (Iand_reads_t645_y ), .Iin29 (Iand_reads_t668_y ), .Iin30 (Iand_reads_t691_y ), .Iin31 (Iand_reads_t714_y ), .Iin32 (Iand_reads_t737_y ), .Iin33 (Iand_reads_t760_y ), .Iin34 (Iand_reads_t783_y ), .Iin35 (Iand_reads_t806_y ), .Iin36 (Iand_reads_t829_y ), .Iin37 (Iand_reads_t852_y ), .Iin38 (Iand_reads_t875_y ), .Iin39 (Iand_reads_t898_y ), .Iin40 (Iand_reads_t921_y ), .Iin41 (Iand_reads_t944_y ), .Iin42 (Iand_reads_t967_y ), .Iin43 (Iand_reads_t990_y ), .Iin44 (Iand_reads_t1013_y ), .Iin45 (Iand_reads_t1036_y ), .Iin46 (Iand_reads_t1059_y ), .Iin47 (Iand_reads_t1082_y ), .Iin48 (Iand_reads_t1105_y ), .Iin49 (Iand_reads_t1128_y ), .Iin50 (Iand_reads_t1151_y ), .Iin51 (Iand_reads_t1174_y ), .Iin52 (Iand_reads_t1197_y ), .Iin53 (Iand_reads_t1220_y ), .Iin54 (Iand_reads_t1243_y ), .Iin55 (Iand_reads_t1266_y ), .Iin56 (Iand_reads_t1289_y ), .Iin57 (Iand_reads_t1312_y ), .Iin58 (Iand_reads_t1335_y ), .Iin59 (Iand_reads_t1358_y ), .Iin60 (Iand_reads_t1381_y ), .Iin61 (Iand_reads_t1404_y ), .Iin62 (Iand_reads_t1427_y ), .Iin63 (Iand_reads_t1450_y ), .out(Iout_d_d7_d1 ), .vdd(vdd), .vss(vss));
@ -96288,10 +96288,10 @@ module tmpl_0_0dataflow__neuro_0_0dualrail__encoder_34_715_4(Iin0 , Iin1 , Iin2
wire I_inX9 ;
// --- instances
TIELO_X1 Itielo0 (.y(Itielo0_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielo1 (.y(Itielo1_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielo2 (.y(Itielo2_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielo3 (.y(Itielo3_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielo0 (.y(Itielo0_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielo1 (.y(Itielo1_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielo2 (.y(Itielo2_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielo3 (.y(Itielo3_y ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0ortree_38_4 Iors_t0 (.Iin0 (I_inX1 ), .Iin1 (I_inX3 ), .Iin2 (I_inX5 ), .Iin3 (I_inX7 ), .Iin4 (I_inX9 ), .Iin5 (I_inX11 ), .Iin6 (I_inX13 ), .Iin7 (Itielo0_y ), .out(Iout_d0_d1 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0ortree_38_4 Iors_t1 (.Iin0 (I_inX2 ), .Iin1 (I_inX3 ), .Iin2 (I_inX6 ), .Iin3 (I_inX7 ), .Iin4 (I_inX10 ), .Iin5 (I_inX11 ), .Iin6 (I_inX14 ), .Iin7 (Itielo1_y ), .out(Iout_d1_d1 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0ortree_38_4 Iors_t2 (.Iin0 (I_inX4 ), .Iin1 (I_inX5 ), .Iin2 (I_inX6 ), .Iin3 (I_inX7 ), .Iin4 (I_inX12 ), .Iin5 (I_inX13 ), .Iin6 (I_inX14 ), .Iin7 (Itielo2_y ), .out(Iout_d2_d1 ), .vdd(vdd), .vss(vss));
@ -96348,7 +96348,7 @@ module tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down(in, reset_B, Isuppl
// --- instances
A_2N_U_X4 Ipull_down (.n1(in), .n2(Itiehi_y ), .y(out), .vdd(vdd), .vss(vss));
TIEHI_X1 Itiehi (.y(Itiehi_y ), .vdd(Isupply_vdd ), .vdd(vdd), .vss(vss));
TIEHI_X1 Itiehi (.y(Itiehi_y ), .vdd(vdd), .vss(vss));
A_2N_U_X4 Ipull_downR (.n1(Iinv_y ), .n2(Itiehi_y ), .y(out), .vdd(vdd), .vss(vss));
INV_X1 Iinv (.y(Iinv_y ), .a(reset_B), .vdd(vdd), .vss(vss));
endmodule
@ -96645,9 +96645,9 @@ module tmpl_0_0dataflow__neuro_0_0dualrail__encoder_33_76_4(Iin0 , Iin1 , Iin2 ,
wire Isupply_vss ;
// --- instances
TIELO_X1 Itielo0 (.y(Itielo0_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielo1 (.y(Itielo1_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielo2 (.y(Itielo2_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielo0 (.y(Itielo0_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielo1 (.y(Itielo1_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielo2 (.y(Itielo2_y ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0ortree_34_4 Iors_t0 (.Iin0 (I_inX1 ), .Iin1 (I_inX3 ), .Iin2 (I_inX5 ), .Iin3 (Itielo0_y ), .out(Iout_d0_d1 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0ortree_34_4 Iors_t1 (.Iin0 (I_inX2 ), .Iin1 (I_inX3 ), .Iin2 (Itielo1_y ), .Iin3 (Itielo1_y ), .out(Iout_d1_d1 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0ortree_34_4 Iors_t2 (.Iin0 (I_inX4 ), .Iin1 (I_inX5 ), .Iin2 (Itielo2_y ), .Iin3 (Itielo2_y ), .out(Iout_d2_d1 ), .vdd(vdd), .vss(vss));
@ -97186,8 +97186,8 @@ module tmpl_0_0dataflow__neuro_0_0append_329_72_72_4(Iin_d_d0_d0 , Iin_d_d0_d1 ,
wire Iin_d_d7_d1 ;
// --- instances
TIELO_X1 Itielows0 (.y(Iout_d_d29_d1 ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows1 (.y(Iout_d_d30_d0 ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows0 (.y(Iout_d_d29_d1 ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows1 (.y(Iout_d_d30_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0vtree_329_4 Iin_val (.Iin_d0_d0 (Iin_d_d0_d0 ), .Iin_d0_d1 (Iin_d_d0_d1 ), .Iin_d1_d0 (Iin_d_d1_d0 ), .Iin_d1_d1 (Iin_d_d1_d1 ), .Iin_d2_d0 (Iin_d_d2_d0 ), .Iin_d2_d1 (Iin_d_d2_d1 ), .Iin_d3_d0 (Iin_d_d3_d0 ), .Iin_d3_d1 (Iin_d_d3_d1 ), .Iin_d4_d0 (Iin_d_d4_d0 ), .Iin_d4_d1 (Iin_d_d4_d1 ), .Iin_d5_d0 (Iin_d_d5_d0 ), .Iin_d5_d1 (Iin_d_d5_d1 ), .Iin_d6_d0 (Iin_d_d6_d0 ), .Iin_d6_d1 (Iin_d_d6_d1 ), .Iin_d7_d0 (Iin_d_d7_d0 ), .Iin_d7_d1 (Iin_d_d7_d1 ), .Iin_d8_d0 (Iin_d_d8_d0 ), .Iin_d8_d1 (Iin_d_d8_d1 ), .Iin_d9_d0 (Iin_d_d9_d0 ), .Iin_d9_d1 (Iin_d_d9_d1 ), .Iin_d10_d0 (Iin_d_d10_d0 ), .Iin_d10_d1 (Iin_d_d10_d1 ), .Iin_d11_d0 (Iin_d_d11_d0 ), .Iin_d11_d1 (Iin_d_d11_d1 ), .Iin_d12_d0 (Iin_d_d12_d0 ), .Iin_d12_d1 (Iin_d_d12_d1 ), .Iin_d13_d0 (Iin_d_d13_d0 ), .Iin_d13_d1 (Iin_d_d13_d1 ), .Iin_d14_d0 (Iin_d_d14_d0 ), .Iin_d14_d1 (Iin_d_d14_d1 ), .Iin_d15_d0 (Iin_d_d15_d0 ), .Iin_d15_d1 (Iin_d_d15_d1 ), .Iin_d16_d0 (Iin_d_d16_d0 ), .Iin_d16_d1 (Iin_d_d16_d1 ), .Iin_d17_d0 (Iin_d_d17_d0 ), .Iin_d17_d1 (Iin_d_d17_d1 ), .Iin_d18_d0 (Iin_d_d18_d0 ), .Iin_d18_d1 (Iin_d_d18_d1 ), .Iin_d19_d0 (Iin_d_d19_d0 ), .Iin_d19_d1 (Iin_d_d19_d1 ), .Iin_d20_d0 (Iin_d_d20_d0 ), .Iin_d20_d1 (Iin_d_d20_d1 ), .Iin_d21_d0 (Iin_d_d21_d0 ), .Iin_d21_d1 (Iin_d_d21_d1 ), .Iin_d22_d0 (Iin_d_d22_d0 ), .Iin_d22_d1 (Iin_d_d22_d1 ), .Iin_d23_d0 (Iin_d_d23_d0 ), .Iin_d23_d1 (Iin_d_d23_d1 ), .Iin_d24_d0 (Iin_d_d24_d0 ), .Iin_d24_d1 (Iin_d_d24_d1 ), .Iin_d25_d0 (Iin_d_d25_d0 ), .Iin_d25_d1 (Iin_d_d25_d1 ), .Iin_d26_d0 (Iin_d_d26_d0 ), .Iin_d26_d1 (Iin_d_d26_d1 ), .Iin_d27_d0 (Iin_d_d27_d0 ), .Iin_d27_d1 (Iin_d_d27_d1 ), .Iin_d28_d0 (Iin_d_d28_d0 ), .Iin_d28_d1 (Iin_d_d28_d1 ), .out(Isb_in ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0sigbuf_32_4 Isb (.in(Isb_in ), .Iout0 (Iout_d_d29_d0 ), .vdd(vdd), .vss(vss));
endmodule
@ -109931,7 +109931,7 @@ module tmpl_0_0dataflow__neuro_0_0append_331_71_70_4(Iin_d_d0_d0 , Iin_d_d0_d1 ,
wire Isupply_vss ;
// --- instances
TIELO_X1 Itielows0 (.y(Iout_d_d31_d1 ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows0 (.y(Iout_d_d31_d1 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0vtree_331_4 Iin_val (.Iin_d0_d0 (Iin_d_d0_d0 ), .Iin_d0_d1 (Iin_d_d0_d1 ), .Iin_d1_d0 (Iin_d_d1_d0 ), .Iin_d1_d1 (Iin_d_d1_d1 ), .Iin_d2_d0 (Iin_d_d2_d0 ), .Iin_d2_d1 (Iin_d_d2_d1 ), .Iin_d3_d0 (Iin_d_d3_d0 ), .Iin_d3_d1 (Iin_d_d3_d1 ), .Iin_d4_d0 (Iin_d_d4_d0 ), .Iin_d4_d1 (Iin_d_d4_d1 ), .Iin_d5_d0 (Iin_d_d5_d0 ), .Iin_d5_d1 (Iin_d_d5_d1 ), .Iin_d6_d0 (Iin_d_d6_d0 ), .Iin_d6_d1 (Iin_d_d6_d1 ), .Iin_d7_d0 (Iin_d_d7_d0 ), .Iin_d7_d1 (Iin_d_d7_d1 ), .Iin_d8_d0 (Iin_d_d8_d0 ), .Iin_d8_d1 (Iin_d_d8_d1 ), .Iin_d9_d0 (Iin_d_d9_d0 ), .Iin_d9_d1 (Iin_d_d9_d1 ), .Iin_d10_d0 (Iin_d_d10_d0 ), .Iin_d10_d1 (Iin_d_d10_d1 ), .Iin_d11_d0 (Iin_d_d11_d0 ), .Iin_d11_d1 (Iin_d_d11_d1 ), .Iin_d12_d0 (Iin_d_d12_d0 ), .Iin_d12_d1 (Iin_d_d12_d1 ), .Iin_d13_d0 (Iin_d_d13_d0 ), .Iin_d13_d1 (Iin_d_d13_d1 ), .Iin_d14_d0 (Iin_d_d14_d0 ), .Iin_d14_d1 (Iin_d_d14_d1 ), .Iin_d15_d0 (Iin_d_d15_d0 ), .Iin_d15_d1 (Iin_d_d15_d1 ), .Iin_d16_d0 (Iin_d_d16_d0 ), .Iin_d16_d1 (Iin_d_d16_d1 ), .Iin_d17_d0 (Iin_d_d17_d0 ), .Iin_d17_d1 (Iin_d_d17_d1 ), .Iin_d18_d0 (Iin_d_d18_d0 ), .Iin_d18_d1 (Iin_d_d18_d1 ), .Iin_d19_d0 (Iin_d_d19_d0 ), .Iin_d19_d1 (Iin_d_d19_d1 ), .Iin_d20_d0 (Iin_d_d20_d0 ), .Iin_d20_d1 (Iin_d_d20_d1 ), .Iin_d21_d0 (Iin_d_d21_d0 ), .Iin_d21_d1 (Iin_d_d21_d1 ), .Iin_d22_d0 (Iin_d_d22_d0 ), .Iin_d22_d1 (Iin_d_d22_d1 ), .Iin_d23_d0 (Iin_d_d23_d0 ), .Iin_d23_d1 (Iin_d_d23_d1 ), .Iin_d24_d0 (Iin_d_d24_d0 ), .Iin_d24_d1 (Iin_d_d24_d1 ), .Iin_d25_d0 (Iin_d_d25_d0 ), .Iin_d25_d1 (Iin_d_d25_d1 ), .Iin_d26_d0 (Iin_d_d26_d0 ), .Iin_d26_d1 (Iin_d_d26_d1 ), .Iin_d27_d0 (Iin_d_d27_d0 ), .Iin_d27_d1 (Iin_d_d27_d1 ), .Iin_d28_d0 (Iin_d_d28_d0 ), .Iin_d28_d1 (Iin_d_d28_d1 ), .Iin_d29_d0 (Iin_d_d29_d0 ), .Iin_d29_d1 (Iin_d_d29_d1 ), .Iin_d30_d0 (Iin_d_d30_d0 ), .Iin_d30_d1 (Iin_d_d30_d1 ), .out(Isb_in ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0sigbuf_31_4 Isb (.in(Isb_in ), .Iout0 (Iout_d_d31_d0 ), .vdd(vdd), .vss(vss));
endmodule

4
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0append_329_72_72_4/netlist/verilog.v
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@ -130,8 +130,8 @@ module tmpl_0_0dataflow__neuro_0_0append_329_72_72_4(Iin_d_d0_d0 , Iin_d_d0_d1 ,
wire Iin_d_d7_d1 ;
// --- instances
TIELO_X1 Itielows0 (.y(Iout_d_d29_d1 ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows1 (.y(Iout_d_d30_d0 ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows0 (.y(Iout_d_d29_d1 ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows1 (.y(Iout_d_d30_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0vtree_329_4 Iin_val (.Iin_d0_d0 (Iin_d_d0_d0 ), .Iin_d0_d1 (Iin_d_d0_d1 ), .Iin_d1_d0 (Iin_d_d1_d0 ), .Iin_d1_d1 (Iin_d_d1_d1 ), .Iin_d2_d0 (Iin_d_d2_d0 ), .Iin_d2_d1 (Iin_d_d2_d1 ), .Iin_d3_d0 (Iin_d_d3_d0 ), .Iin_d3_d1 (Iin_d_d3_d1 ), .Iin_d4_d0 (Iin_d_d4_d0 ), .Iin_d4_d1 (Iin_d_d4_d1 ), .Iin_d5_d0 (Iin_d_d5_d0 ), .Iin_d5_d1 (Iin_d_d5_d1 ), .Iin_d6_d0 (Iin_d_d6_d0 ), .Iin_d6_d1 (Iin_d_d6_d1 ), .Iin_d7_d0 (Iin_d_d7_d0 ), .Iin_d7_d1 (Iin_d_d7_d1 ), .Iin_d8_d0 (Iin_d_d8_d0 ), .Iin_d8_d1 (Iin_d_d8_d1 ), .Iin_d9_d0 (Iin_d_d9_d0 ), .Iin_d9_d1 (Iin_d_d9_d1 ), .Iin_d10_d0 (Iin_d_d10_d0 ), .Iin_d10_d1 (Iin_d_d10_d1 ), .Iin_d11_d0 (Iin_d_d11_d0 ), .Iin_d11_d1 (Iin_d_d11_d1 ), .Iin_d12_d0 (Iin_d_d12_d0 ), .Iin_d12_d1 (Iin_d_d12_d1 ), .Iin_d13_d0 (Iin_d_d13_d0 ), .Iin_d13_d1 (Iin_d_d13_d1 ), .Iin_d14_d0 (Iin_d_d14_d0 ), .Iin_d14_d1 (Iin_d_d14_d1 ), .Iin_d15_d0 (Iin_d_d15_d0 ), .Iin_d15_d1 (Iin_d_d15_d1 ), .Iin_d16_d0 (Iin_d_d16_d0 ), .Iin_d16_d1 (Iin_d_d16_d1 ), .Iin_d17_d0 (Iin_d_d17_d0 ), .Iin_d17_d1 (Iin_d_d17_d1 ), .Iin_d18_d0 (Iin_d_d18_d0 ), .Iin_d18_d1 (Iin_d_d18_d1 ), .Iin_d19_d0 (Iin_d_d19_d0 ), .Iin_d19_d1 (Iin_d_d19_d1 ), .Iin_d20_d0 (Iin_d_d20_d0 ), .Iin_d20_d1 (Iin_d_d20_d1 ), .Iin_d21_d0 (Iin_d_d21_d0 ), .Iin_d21_d1 (Iin_d_d21_d1 ), .Iin_d22_d0 (Iin_d_d22_d0 ), .Iin_d22_d1 (Iin_d_d22_d1 ), .Iin_d23_d0 (Iin_d_d23_d0 ), .Iin_d23_d1 (Iin_d_d23_d1 ), .Iin_d24_d0 (Iin_d_d24_d0 ), .Iin_d24_d1 (Iin_d_d24_d1 ), .Iin_d25_d0 (Iin_d_d25_d0 ), .Iin_d25_d1 (Iin_d_d25_d1 ), .Iin_d26_d0 (Iin_d_d26_d0 ), .Iin_d26_d1 (Iin_d_d26_d1 ), .Iin_d27_d0 (Iin_d_d27_d0 ), .Iin_d27_d1 (Iin_d_d27_d1 ), .Iin_d28_d0 (Iin_d_d28_d0 ), .Iin_d28_d1 (Iin_d_d28_d1 ), .out(Isb_in ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0sigbuf_32_4 Isb (.in(Isb_in ), .Iout0 (Iout_d_d29_d0 ), .vdd(vdd), .vss(vss));
endmodule

2
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0append_331_71_70_4/netlist/verilog.v
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@ -136,7 +136,7 @@ module tmpl_0_0dataflow__neuro_0_0append_331_71_70_4(Iin_d_d0_d0 , Iin_d_d0_d1 ,
wire Isupply_vss ;
// --- instances
TIELO_X1 Itielows0 (.y(Iout_d_d31_d1 ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows0 (.y(Iout_d_d31_d1 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0vtree_331_4 Iin_val (.Iin_d0_d0 (Iin_d_d0_d0 ), .Iin_d0_d1 (Iin_d_d0_d1 ), .Iin_d1_d0 (Iin_d_d1_d0 ), .Iin_d1_d1 (Iin_d_d1_d1 ), .Iin_d2_d0 (Iin_d_d2_d0 ), .Iin_d2_d1 (Iin_d_d2_d1 ), .Iin_d3_d0 (Iin_d_d3_d0 ), .Iin_d3_d1 (Iin_d_d3_d1 ), .Iin_d4_d0 (Iin_d_d4_d0 ), .Iin_d4_d1 (Iin_d_d4_d1 ), .Iin_d5_d0 (Iin_d_d5_d0 ), .Iin_d5_d1 (Iin_d_d5_d1 ), .Iin_d6_d0 (Iin_d_d6_d0 ), .Iin_d6_d1 (Iin_d_d6_d1 ), .Iin_d7_d0 (Iin_d_d7_d0 ), .Iin_d7_d1 (Iin_d_d7_d1 ), .Iin_d8_d0 (Iin_d_d8_d0 ), .Iin_d8_d1 (Iin_d_d8_d1 ), .Iin_d9_d0 (Iin_d_d9_d0 ), .Iin_d9_d1 (Iin_d_d9_d1 ), .Iin_d10_d0 (Iin_d_d10_d0 ), .Iin_d10_d1 (Iin_d_d10_d1 ), .Iin_d11_d0 (Iin_d_d11_d0 ), .Iin_d11_d1 (Iin_d_d11_d1 ), .Iin_d12_d0 (Iin_d_d12_d0 ), .Iin_d12_d1 (Iin_d_d12_d1 ), .Iin_d13_d0 (Iin_d_d13_d0 ), .Iin_d13_d1 (Iin_d_d13_d1 ), .Iin_d14_d0 (Iin_d_d14_d0 ), .Iin_d14_d1 (Iin_d_d14_d1 ), .Iin_d15_d0 (Iin_d_d15_d0 ), .Iin_d15_d1 (Iin_d_d15_d1 ), .Iin_d16_d0 (Iin_d_d16_d0 ), .Iin_d16_d1 (Iin_d_d16_d1 ), .Iin_d17_d0 (Iin_d_d17_d0 ), .Iin_d17_d1 (Iin_d_d17_d1 ), .Iin_d18_d0 (Iin_d_d18_d0 ), .Iin_d18_d1 (Iin_d_d18_d1 ), .Iin_d19_d0 (Iin_d_d19_d0 ), .Iin_d19_d1 (Iin_d_d19_d1 ), .Iin_d20_d0 (Iin_d_d20_d0 ), .Iin_d20_d1 (Iin_d_d20_d1 ), .Iin_d21_d0 (Iin_d_d21_d0 ), .Iin_d21_d1 (Iin_d_d21_d1 ), .Iin_d22_d0 (Iin_d_d22_d0 ), .Iin_d22_d1 (Iin_d_d22_d1 ), .Iin_d23_d0 (Iin_d_d23_d0 ), .Iin_d23_d1 (Iin_d_d23_d1 ), .Iin_d24_d0 (Iin_d_d24_d0 ), .Iin_d24_d1 (Iin_d_d24_d1 ), .Iin_d25_d0 (Iin_d_d25_d0 ), .Iin_d25_d1 (Iin_d_d25_d1 ), .Iin_d26_d0 (Iin_d_d26_d0 ), .Iin_d26_d1 (Iin_d_d26_d1 ), .Iin_d27_d0 (Iin_d_d27_d0 ), .Iin_d27_d1 (Iin_d_d27_d1 ), .Iin_d28_d0 (Iin_d_d28_d0 ), .Iin_d28_d1 (Iin_d_d28_d1 ), .Iin_d29_d0 (Iin_d_d29_d0 ), .Iin_d29_d1 (Iin_d_d29_d1 ), .Iin_d30_d0 (Iin_d_d30_d0 ), .Iin_d30_d1 (Iin_d_d30_d1 ), .out(Isb_in ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0sigbuf_31_4 Isb (.in(Isb_in ), .Iout0 (Iout_d_d31_d0 ), .vdd(vdd), .vss(vss));
endmodule

2
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0append_331_71_71_4/netlist/verilog.v
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@ -136,7 +136,7 @@ module tmpl_0_0dataflow__neuro_0_0append_331_71_71_4(Iin_d_d0_d0 , Iin_d_d0_d1 ,
wire Iin_d_d10_d1 ;
// --- instances
TIELO_X1 Itielows0 (.y(Iout_d_d31_d0 ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows0 (.y(Iout_d_d31_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0vtree_331_4 Iin_val (.Iin_d0_d0 (Iin_d_d0_d0 ), .Iin_d0_d1 (Iin_d_d0_d1 ), .Iin_d1_d0 (Iin_d_d1_d0 ), .Iin_d1_d1 (Iin_d_d1_d1 ), .Iin_d2_d0 (Iin_d_d2_d0 ), .Iin_d2_d1 (Iin_d_d2_d1 ), .Iin_d3_d0 (Iin_d_d3_d0 ), .Iin_d3_d1 (Iin_d_d3_d1 ), .Iin_d4_d0 (Iin_d_d4_d0 ), .Iin_d4_d1 (Iin_d_d4_d1 ), .Iin_d5_d0 (Iin_d_d5_d0 ), .Iin_d5_d1 (Iin_d_d5_d1 ), .Iin_d6_d0 (Iin_d_d6_d0 ), .Iin_d6_d1 (Iin_d_d6_d1 ), .Iin_d7_d0 (Iin_d_d7_d0 ), .Iin_d7_d1 (Iin_d_d7_d1 ), .Iin_d8_d0 (Iin_d_d8_d0 ), .Iin_d8_d1 (Iin_d_d8_d1 ), .Iin_d9_d0 (Iin_d_d9_d0 ), .Iin_d9_d1 (Iin_d_d9_d1 ), .Iin_d10_d0 (Iin_d_d10_d0 ), .Iin_d10_d1 (Iin_d_d10_d1 ), .Iin_d11_d0 (Iin_d_d11_d0 ), .Iin_d11_d1 (Iin_d_d11_d1 ), .Iin_d12_d0 (Iin_d_d12_d0 ), .Iin_d12_d1 (Iin_d_d12_d1 ), .Iin_d13_d0 (Iin_d_d13_d0 ), .Iin_d13_d1 (Iin_d_d13_d1 ), .Iin_d14_d0 (Iin_d_d14_d0 ), .Iin_d14_d1 (Iin_d_d14_d1 ), .Iin_d15_d0 (Iin_d_d15_d0 ), .Iin_d15_d1 (Iin_d_d15_d1 ), .Iin_d16_d0 (Iin_d_d16_d0 ), .Iin_d16_d1 (Iin_d_d16_d1 ), .Iin_d17_d0 (Iin_d_d17_d0 ), .Iin_d17_d1 (Iin_d_d17_d1 ), .Iin_d18_d0 (Iin_d_d18_d0 ), .Iin_d18_d1 (Iin_d_d18_d1 ), .Iin_d19_d0 (Iin_d_d19_d0 ), .Iin_d19_d1 (Iin_d_d19_d1 ), .Iin_d20_d0 (Iin_d_d20_d0 ), .Iin_d20_d1 (Iin_d_d20_d1 ), .Iin_d21_d0 (Iin_d_d21_d0 ), .Iin_d21_d1 (Iin_d_d21_d1 ), .Iin_d22_d0 (Iin_d_d22_d0 ), .Iin_d22_d1 (Iin_d_d22_d1 ), .Iin_d23_d0 (Iin_d_d23_d0 ), .Iin_d23_d1 (Iin_d_d23_d1 ), .Iin_d24_d0 (Iin_d_d24_d0 ), .Iin_d24_d1 (Iin_d_d24_d1 ), .Iin_d25_d0 (Iin_d_d25_d0 ), .Iin_d25_d1 (Iin_d_d25_d1 ), .Iin_d26_d0 (Iin_d_d26_d0 ), .Iin_d26_d1 (Iin_d_d26_d1 ), .Iin_d27_d0 (Iin_d_d27_d0 ), .Iin_d27_d1 (Iin_d_d27_d1 ), .Iin_d28_d0 (Iin_d_d28_d0 ), .Iin_d28_d1 (Iin_d_d28_d1 ), .Iin_d29_d0 (Iin_d_d29_d0 ), .Iin_d29_d1 (Iin_d_d29_d1 ), .Iin_d30_d0 (Iin_d_d30_d0 ), .Iin_d30_d1 (Iin_d_d30_d1 ), .out(Isb_in ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0sigbuf_31_4 Isb (.in(Isb_in ), .Iout0 (Iout_d_d31_d1 ), .vdd(vdd), .vss(vss));
endmodule

48
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0append_37_724_70_4/netlist/verilog.v
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@ -86,30 +86,30 @@ module tmpl_0_0dataflow__neuro_0_0append_37_724_70_4(Iin_d_d0_d0 , Iin_d_d0_d1 ,
output Iout_d_d23_d1 ;
// --- instances
TIELO_X1 Itielows0 (.y(Iout_d_d7_d1 ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows1 (.y(Iout_d_d8_d1 ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows2 (.y(Iout_d_d9_d1 ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows3 (.y(Iout_d_d10_d1 ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows4 (.y(Iout_d_d11_d1 ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows5 (.y(Iout_d_d12_d1 ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows6 (.y(Iout_d_d13_d1 ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows7 (.y(Iout_d_d14_d1 ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows8 (.y(Iout_d_d15_d1 ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows9 (.y(Iout_d_d16_d1 ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows10 (.y(Iout_d_d17_d1 ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows11 (.y(Iout_d_d18_d1 ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows12 (.y(Iout_d_d19_d1 ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows13 (.y(Iout_d_d20_d1 ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows14 (.y(Iout_d_d21_d1 ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows15 (.y(Iout_d_d22_d1 ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows16 (.y(Iout_d_d23_d1 ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows17 (.y(Iout_d_d24_d1 ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows18 (.y(Iout_d_d25_d1 ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows19 (.y(Iout_d_d26_d1 ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows20 (.y(Iout_d_d27_d1 ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows21 (.y(Iout_d_d28_d1 ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows22 (.y(Iout_d_d29_d1 ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows23 (.y(Iout_d_d30_d1 ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows0 (.y(Iout_d_d7_d1 ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows1 (.y(Iout_d_d8_d1 ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows2 (.y(Iout_d_d9_d1 ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows3 (.y(Iout_d_d10_d1 ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows4 (.y(Iout_d_d11_d1 ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows5 (.y(Iout_d_d12_d1 ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows6 (.y(Iout_d_d13_d1 ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows7 (.y(Iout_d_d14_d1 ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows8 (.y(Iout_d_d15_d1 ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows9 (.y(Iout_d_d16_d1 ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows10 (.y(Iout_d_d17_d1 ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows11 (.y(Iout_d_d18_d1 ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows12 (.y(Iout_d_d19_d1 ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows13 (.y(Iout_d_d20_d1 ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows14 (.y(Iout_d_d21_d1 ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows15 (.y(Iout_d_d22_d1 ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows16 (.y(Iout_d_d23_d1 ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows17 (.y(Iout_d_d24_d1 ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows18 (.y(Iout_d_d25_d1 ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows19 (.y(Iout_d_d26_d1 ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows20 (.y(Iout_d_d27_d1 ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows21 (.y(Iout_d_d28_d1 ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows22 (.y(Iout_d_d29_d1 ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows23 (.y(Iout_d_d30_d1 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0vtree_37_4 Iin_val (.Iin_d0_d0 (Iin_d_d0_d0 ), .Iin_d0_d1 (Iin_d_d0_d1 ), .Iin_d1_d0 (Iin_d_d1_d0 ), .Iin_d1_d1 (Iin_d_d1_d1 ), .Iin_d2_d0 (Iin_d_d2_d0 ), .Iin_d2_d1 (Iin_d_d2_d1 ), .Iin_d3_d0 (Iin_d_d3_d0 ), .Iin_d3_d1 (Iin_d_d3_d1 ), .Iin_d4_d0 (Iin_d_d4_d0 ), .Iin_d4_d1 (Iin_d_d4_d1 ), .Iin_d5_d0 (Iin_d_d5_d0 ), .Iin_d5_d1 (Iin_d_d5_d1 ), .Iin_d6_d0 (Iin_d_d6_d0 ), .Iin_d6_d1 (Iin_d_d6_d1 ), .out(Isb_in ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0sigbuf_324_4 Isb (.in(Isb_in ), .Iout0 (Iout_d_d7_d0 ), .vdd(vdd), .vss(vss));
endmodule

6
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0dualrail__encoder_33_76_4/netlist/verilog.v
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@ -40,9 +40,9 @@ module tmpl_0_0dataflow__neuro_0_0dualrail__encoder_33_76_4(Iin0 , Iin1 , Iin2 ,
wire Isupply_vss ;
// --- instances
TIELO_X1 Itielo0 (.y(Itielo0_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielo1 (.y(Itielo1_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielo2 (.y(Itielo2_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielo0 (.y(Itielo0_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielo1 (.y(Itielo1_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielo2 (.y(Itielo2_y ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0ortree_34_4 Iors_t0 (.Iin0 (I_inX1 ), .Iin1 (I_inX3 ), .Iin2 (I_inX5 ), .Iin3 (Itielo0_y ), .out(Iout_d0_d1 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0ortree_34_4 Iors_t1 (.Iin0 (I_inX2 ), .Iin1 (I_inX3 ), .Iin2 (Itielo1_y ), .Iin3 (Itielo1_y ), .out(Iout_d1_d1 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0ortree_34_4 Iors_t2 (.Iin0 (I_inX4 ), .Iin1 (I_inX5 ), .Iin2 (Itielo2_y ), .Iin3 (Itielo2_y ), .out(Iout_d2_d1 ), .vdd(vdd), .vss(vss));

8
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0dualrail__encoder_34_715_4/netlist/verilog.v
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@ -72,10 +72,10 @@ module tmpl_0_0dataflow__neuro_0_0dualrail__encoder_34_715_4(Iin0 , Iin1 , Iin2
wire I_inX9 ;
// --- instances
TIELO_X1 Itielo0 (.y(Itielo0_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielo1 (.y(Itielo1_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielo2 (.y(Itielo2_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielo3 (.y(Itielo3_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielo0 (.y(Itielo0_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielo1 (.y(Itielo1_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielo2 (.y(Itielo2_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielo3 (.y(Itielo3_y ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0ortree_38_4 Iors_t0 (.Iin0 (I_inX1 ), .Iin1 (I_inX3 ), .Iin2 (I_inX5 ), .Iin3 (I_inX7 ), .Iin4 (I_inX9 ), .Iin5 (I_inX11 ), .Iin6 (I_inX13 ), .Iin7 (Itielo0_y ), .out(Iout_d0_d1 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0ortree_38_4 Iors_t1 (.Iin0 (I_inX2 ), .Iin1 (I_inX3 ), .Iin2 (I_inX6 ), .Iin3 (I_inX7 ), .Iin4 (I_inX10 ), .Iin5 (I_inX11 ), .Iin6 (I_inX14 ), .Iin7 (Itielo1_y ), .out(Iout_d1_d1 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0ortree_38_4 Iors_t2 (.Iin0 (I_inX4 ), .Iin1 (I_inX5 ), .Iin2 (I_inX6 ), .Iin3 (I_inX7 ), .Iin4 (I_inX12 ), .Iin5 (I_inX13 ), .Iin6 (I_inX14 ), .Iin7 (Itielo2_y ), .out(Iout_d2_d1 ), .vdd(vdd), .vss(vss));

2
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down/netlist/verilog.v
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@ -16,7 +16,7 @@ module tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down(in, reset_B, Isuppl
// --- instances
A_2N_U_X4 Ipull_down (.n1(in), .n2(Itiehi_y ), .y(out), .vdd(vdd), .vss(vss));
TIEHI_X1 Itiehi (.y(Itiehi_y ), .vdd(Isupply_vdd ), .vdd(vdd), .vss(vss));
TIEHI_X1 Itiehi (.y(Itiehi_y ), .vdd(vdd), .vss(vss));
A_2N_U_X4 Ipull_downR (.n1(Iinv_y ), .n2(Itiehi_y ), .y(out), .vdd(vdd), .vss(vss));
INV_X1 Iinv (.y(Iinv_y ), .a(reset_B), .vdd(vdd), .vss(vss));
endmodule

128
test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0register__wr__array_36_723_764_4/netlist/verilog.v
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@ -9476,70 +9476,70 @@ tmpl_0_0dataflow__neuro_0_0decoder__dualrail_36_764_4 Idecoder (.Iin_d0_d0 (Iin
tmpl_0_0dataflow__neuro_0_0vtree_330_4 Iinput_valid (.Iin_d0_d0 (Iin_d_d0_d0 ), .Iin_d0_d1 (Iin_d_d0_d1 ), .Iin_d1_d0 (Iin_d_d1_d0 ), .Iin_d1_d1 (Iin_d_d1_d1 ), .Iin_d2_d0 (Iin_d_d2_d0 ), .Iin_d2_d1 (Iin_d_d2_d1 ), .Iin_d3_d0 (Iin_d_d3_d0 ), .Iin_d3_d1 (Iin_d_d3_d1 ), .Iin_d4_d0 (Iin_d_d4_d0 ), .Iin_d4_d1 (Iin_d_d4_d1 ), .Iin_d5_d0 (Iin_d_d5_d0 ), .Iin_d5_d1 (Iin_d_d5_d1 ), .Iin_d6_d0 (Iin_d_d6_d0 ), .Iin_d6_d1 (Iin_d_d6_d1 ), .Iin_d7_d0 (Iin_d_d7_d0 ), .Iin_d7_d1 (Iin_d_d7_d1 ), .Iin_d8_d0 (Iin_d_d8_d0 ), .Iin_d8_d1 (Iin_d_d8_d1 ), .Iin_d9_d0 (Iin_d_d9_d0 ), .Iin_d9_d1 (Iin_d_d9_d1 ), .Iin_d10_d0 (Iin_d_d10_d0 ), .Iin_d10_d1 (Iin_d_d10_d1 ), .Iin_d11_d0 (Iin_d_d11_d0 ), .Iin_d11_d1 (Iin_d_d11_d1 ), .Iin_d12_d0 (Iin_d_d12_d0 ), .Iin_d12_d1 (Iin_d_d12_d1 ), .Iin_d13_d0 (Iin_d_d13_d0 ), .Iin_d13_d1 (Iin_d_d13_d1 ), .Iin_d14_d0 (Iin_d_d14_d0 ), .Iin_d14_d1 (Iin_d_d14_d1 ), .Iin_d15_d0 (Iin_d_d15_d0 ), .Iin_d15_d1 (Iin_d_d15_d1 ), .Iin_d16_d0 (Iin_d_d16_d0 ), .Iin_d16_d1 (Iin_d_d16_d1 ), .Iin_d17_d0 (Iin_d_d17_d0 ), .Iin_d17_d1 (Iin_d_d17_d1 ), .Iin_d18_d0 (Iin_d_d18_d0 ), .Iin_d18_d1 (Iin_d_d18_d1 ), .Iin_d19_d0 (Iin_d_d19_d0 ), .Iin_d19_d1 (Iin_d_d19_d1 ), .Iin_d20_d0 (Iin_d_d20_d0 ), .Iin_d20_d1 (Iin_d_d20_d1 ), .Iin_d21_d0 (Iin_d_d21_d0 ), .Iin_d21_d1 (Iin_d_d21_d1 ), .Iin_d22_d0 (Iin_d_d22_d0 ), .Iin_d22_d1 (Iin_d_d22_d1 ), .Iin_d23_d0 (Iin_d_d23_d0 ), .Iin_d23_d1 (Iin_d_d23_d1 ), .Iin_d24_d0 (Iin_d_d24_d0 ), .Iin_d24_d1 (Iin_d_d24_d1 ), .Iin_d25_d0 (Iin_d_d25_d0 ), .Iin_d25_d1 (Iin_d_d25_d1 ), .Iin_d26_d0 (Iin_d_d26_d0 ), .Iin_d26_d1 (Iin_d_d26_d1 ), .Iin_d27_d0 (Iin_d_d27_d0 ), .Iin_d27_d1 (Iin_d_d27_d1 ), .Iin_d28_d0 (Iin_d_d28_d0 ), .Iin_d28_d1 (Iin_d_d28_d1 ), .Iin_d29_d0 (Iin_d_d29_d0 ), .Iin_d29_d1 (Iin_d_d29_d1 ), .out(Iin_v ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0ortree_364_4 Iack_ortree (.Iin0 (Iack_ortree_in0 ), .Iin1 (Iack_ortree_in1 ), .Iin2 (Iack_ortree_in2 ), .Iin3 (Iack_ortree_in3 ), .Iin4 (Iack_ortree_in4 ), .Iin5 (Iack_ortree_in5 ), .Iin6 (Iack_ortree_in6 ), .Iin7 (Iack_ortree_in7 ), .Iin8 (Iack_ortree_in8 ), .Iin9 (Iack_ortree_in9 ), .Iin10 (Iack_ortree_in10 ), .Iin11 (Iack_ortree_in11 ), .Iin12 (Iack_ortree_in12 ), .Iin13 (Iack_ortree_in13 ), .Iin14 (Iack_ortree_in14 ), .Iin15 (Iack_ortree_in15 ), .Iin16 (Iack_ortree_in16 ), .Iin17 (Iack_ortree_in17 ), .Iin18 (Iack_ortree_in18 ), .Iin19 (Iack_ortree_in19 ), .Iin20 (Iack_ortree_in20 ), .Iin21 (Iack_ortree_in21 ), .Iin22 (Iack_ortree_in22 ), .Iin23 (Iack_ortree_in23 ), .Iin24 (Iack_ortree_in24 ), .Iin25 (Iack_ortree_in25 ), .Iin26 (Iack_ortree_in26 ), .Iin27 (Iack_ortree_in27 ), .Iin28 (Iack_ortree_in28 ), .Iin29 (Iack_ortree_in29 ), .Iin30 (Iack_ortree_in30 ), .Iin31 (Iack_ortree_in31 ), .Iin32 (Iack_ortree_in32 ), .Iin33 (Iack_ortree_in33 ), .Iin34 (Iack_ortree_in34 ), .Iin35 (Iack_ortree_in35 ), .Iin36 (Iack_ortree_in36 ), .Iin37 (Iack_ortree_in37 ), .Iin38 (Iack_ortree_in38 ), .Iin39 (Iack_ortree_in39 ), .Iin40 (Iack_ortree_in40 ), .Iin41 (Iack_ortree_in41 ), .Iin42 (Iack_ortree_in42 ), .Iin43 (Iack_ortree_in43 ), .Iin44 (Iack_ortree_in44 ), .Iin45 (Iack_ortree_in45 ), .Iin46 (Iack_ortree_in46 ), .Iin47 (Iack_ortree_in47 ), .Iin48 (Iack_ortree_in48 ), .Iin49 (Iack_ortree_in49 ), .Iin50 (Iack_ortree_in50 ), .Iin51 (Iack_ortree_in51 ), .Iin52 (Iack_ortree_in52 ), .Iin53 (Iack_ortree_in53 ), .Iin54 (Iack_ortree_in54 ), .Iin55 (Iack_ortree_in55 ), .Iin56 (Iack_ortree_in56 ), .Iin57 (Iack_ortree_in57 ), .Iin58 (Iack_ortree_in58 ), .Iin59 (Iack_ortree_in59 ), .Iin60 (Iack_ortree_in60 ), .Iin61 (Iack_ortree_in61 ), .Iin62 (Iack_ortree_in62 ), .Iin63 (Iack_ortree_in63 ), .out(Iack_ortree_out ), .vdd(vdd), .vss(vss));
A_2C_B_X1 Iack_safety (.y(Iin_a ), .c1(Iack_rw_or_y ), .c2(Iin_v ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f0 (.y(Itielow_writebit_f0_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f1 (.y(Itielow_writebit_f1_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f2 (.y(Itielow_writebit_f2_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f3 (.y(Itielow_writebit_f3_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f4 (.y(Itielow_writebit_f4_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f5 (.y(Itielow_writebit_f5_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f6 (.y(Itielow_writebit_f6_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f7 (.y(Itielow_writebit_f7_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f8 (.y(Itielow_writebit_f8_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f9 (.y(Itielow_writebit_f9_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f10 (.y(Itielow_writebit_f10_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f11 (.y(Itielow_writebit_f11_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f12 (.y(Itielow_writebit_f12_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f13 (.y(Itielow_writebit_f13_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f14 (.y(Itielow_writebit_f14_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f15 (.y(Itielow_writebit_f15_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f16 (.y(Itielow_writebit_f16_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f17 (.y(Itielow_writebit_f17_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f18 (.y(Itielow_writebit_f18_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f19 (.y(Itielow_writebit_f19_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f20 (.y(Itielow_writebit_f20_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f21 (.y(Itielow_writebit_f21_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f22 (.y(Itielow_writebit_f22_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f23 (.y(Itielow_writebit_f23_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f24 (.y(Itielow_writebit_f24_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f25 (.y(Itielow_writebit_f25_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f26 (.y(Itielow_writebit_f26_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f27 (.y(Itielow_writebit_f27_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f28 (.y(Itielow_writebit_f28_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f29 (.y(Itielow_writebit_f29_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f30 (.y(Itielow_writebit_f30_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f31 (.y(Itielow_writebit_f31_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f32 (.y(Itielow_writebit_f32_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f33 (.y(Itielow_writebit_f33_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f34 (.y(Itielow_writebit_f34_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f35 (.y(Itielow_writebit_f35_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f36 (.y(Itielow_writebit_f36_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f37 (.y(Itielow_writebit_f37_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f38 (.y(Itielow_writebit_f38_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f39 (.y(Itielow_writebit_f39_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f40 (.y(Itielow_writebit_f40_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f41 (.y(Itielow_writebit_f41_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f42 (.y(Itielow_writebit_f42_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f43 (.y(Itielow_writebit_f43_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f44 (.y(Itielow_writebit_f44_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f45 (.y(Itielow_writebit_f45_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f46 (.y(Itielow_writebit_f46_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f47 (.y(Itielow_writebit_f47_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f48 (.y(Itielow_writebit_f48_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f49 (.y(Itielow_writebit_f49_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f50 (.y(Itielow_writebit_f50_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f51 (.y(Itielow_writebit_f51_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f52 (.y(Itielow_writebit_f52_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f53 (.y(Itielow_writebit_f53_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f54 (.y(Itielow_writebit_f54_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f55 (.y(Itielow_writebit_f55_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f56 (.y(Itielow_writebit_f56_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f57 (.y(Itielow_writebit_f57_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f58 (.y(Itielow_writebit_f58_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f59 (.y(Itielow_writebit_f59_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f60 (.y(Itielow_writebit_f60_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f61 (.y(Itielow_writebit_f61_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f62 (.y(Itielow_writebit_f62_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f63 (.y(Itielow_writebit_f63_y ), .vss(Isupply_vss ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f0 (.y(Itielow_writebit_f0_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f1 (.y(Itielow_writebit_f1_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f2 (.y(Itielow_writebit_f2_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f3 (.y(Itielow_writebit_f3_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f4 (.y(Itielow_writebit_f4_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f5 (.y(Itielow_writebit_f5_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f6 (.y(Itielow_writebit_f6_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f7 (.y(Itielow_writebit_f7_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f8 (.y(Itielow_writebit_f8_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f9 (.y(Itielow_writebit_f9_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f10 (.y(Itielow_writebit_f10_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f11 (.y(Itielow_writebit_f11_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f12 (.y(Itielow_writebit_f12_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f13 (.y(Itielow_writebit_f13_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f14 (.y(Itielow_writebit_f14_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f15 (.y(Itielow_writebit_f15_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f16 (.y(Itielow_writebit_f16_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f17 (.y(Itielow_writebit_f17_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f18 (.y(Itielow_writebit_f18_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f19 (.y(Itielow_writebit_f19_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f20 (.y(Itielow_writebit_f20_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f21 (.y(Itielow_writebit_f21_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f22 (.y(Itielow_writebit_f22_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f23 (.y(Itielow_writebit_f23_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f24 (.y(Itielow_writebit_f24_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f25 (.y(Itielow_writebit_f25_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f26 (.y(Itielow_writebit_f26_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f27 (.y(Itielow_writebit_f27_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f28 (.y(Itielow_writebit_f28_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f29 (.y(Itielow_writebit_f29_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f30 (.y(Itielow_writebit_f30_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f31 (.y(Itielow_writebit_f31_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f32 (.y(Itielow_writebit_f32_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f33 (.y(Itielow_writebit_f33_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f34 (.y(Itielow_writebit_f34_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f35 (.y(Itielow_writebit_f35_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f36 (.y(Itielow_writebit_f36_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f37 (.y(Itielow_writebit_f37_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f38 (.y(Itielow_writebit_f38_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f39 (.y(Itielow_writebit_f39_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f40 (.y(Itielow_writebit_f40_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f41 (.y(Itielow_writebit_f41_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f42 (.y(Itielow_writebit_f42_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f43 (.y(Itielow_writebit_f43_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f44 (.y(Itielow_writebit_f44_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f45 (.y(Itielow_writebit_f45_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f46 (.y(Itielow_writebit_f46_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f47 (.y(Itielow_writebit_f47_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f48 (.y(Itielow_writebit_f48_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f49 (.y(Itielow_writebit_f49_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f50 (.y(Itielow_writebit_f50_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f51 (.y(Itielow_writebit_f51_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f52 (.y(Itielow_writebit_f52_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f53 (.y(Itielow_writebit_f53_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f54 (.y(Itielow_writebit_f54_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f55 (.y(Itielow_writebit_f55_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f56 (.y(Itielow_writebit_f56_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f57 (.y(Itielow_writebit_f57_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f58 (.y(Itielow_writebit_f58_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f59 (.y(Itielow_writebit_f59_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f60 (.y(Itielow_writebit_f60_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f61 (.y(Itielow_writebit_f61_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f62 (.y(Itielow_writebit_f62_y ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielow_writebit_f63 (.y(Itielow_writebit_f63_y ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0sigbuf__boolarray_364_746_4 Iread_selectorsX (.Iin0 (Iread_selectors0_y ), .Iin1 (Iread_selectors1_y ), .Iin2 (Iread_selectors2_y ), .Iin3 (Iread_selectors3_y ), .Iin4 (Iread_selectors4_y ), .Iin5 (Iread_selectors5_y ), .Iin6 (Iread_selectors6_y ), .Iin7 (Iread_selectors7_y ), .Iin8 (Iread_selectors8_y ), .Iin9 (Iread_selectors9_y ), .Iin10 (Iread_selectors10_y ), .Iin11 (Iread_selectors11_y ), .Iin12 (Iread_selectors12_y ), .Iin13 (Iread_selectors13_y ), .Iin14 (Iread_selectors14_y ), .Iin15 (Iread_selectors15_y ), .Iin16 (Iread_selectors16_y ), .Iin17 (Iread_selectors17_y ), .Iin18 (Iread_selectors18_y ), .Iin19 (Iread_selectors19_y ), .Iin20 (Iread_selectors20_y ), .Iin21 (Iread_selectors21_y ), .Iin22 (Iread_selectors22_y ), .Iin23 (Iread_selectors23_y ), .Iin24 (Iread_selectors24_y ), .Iin25 (Iread_selectors25_y ), .Iin26 (Iread_selectors26_y ), .Iin27 (Iread_selectors27_y ), .Iin28 (Iread_selectors28_y ), .Iin29 (Iread_selectors29_y ), .Iin30 (Iread_selectors30_y ), .Iin31 (Iread_selectors31_y ), .Iin32 (Iread_selectors32_y ), .Iin33 (Iread_selectors33_y ), .Iin34 (Iread_selectors34_y ), .Iin35 (Iread_selectors35_y ), .Iin36 (Iread_selectors36_y ), .Iin37 (Iread_selectors37_y ), .Iin38 (Iread_selectors38_y ), .Iin39 (Iread_selectors39_y ), .Iin40 (Iread_selectors40_y ), .Iin41 (Iread_selectors41_y ), .Iin42 (Iread_selectors42_y ), .Iin43 (Iread_selectors43_y ), .Iin44 (Iread_selectors44_y ), .Iin45 (Iread_selectors45_y ), .Iin46 (Iread_selectors46_y ), .Iin47 (Iread_selectors47_y ), .Iin48 (Iread_selectors48_y ), .Iin49 (Iread_selectors49_y ), .Iin50 (Iread_selectors50_y ), .Iin51 (Iread_selectors51_y ), .Iin52 (Iread_selectors52_y ), .Iin53 (Iread_selectors53_y ), .Iin54 (Iread_selectors54_y ), .Iin55 (Iread_selectors55_y ), .Iin56 (Iread_selectors56_y ), .Iin57 (Iread_selectors57_y ), .Iin58 (Iread_selectors58_y ), .Iin59 (Iread_selectors59_y ), .Iin60 (Iread_selectors60_y ), .Iin61 (Iread_selectors61_y ), .Iin62 (Iread_selectors62_y ), .Iin63 (Iread_selectors63_y ), .Iout0 (Iand_reads_f22_b ), .Iout1 (Iand_reads_f45_b ), .Iout2 (Iand_reads_f68_b ), .Iout3 (Iand_reads_f91_b ), .Iout4 (Iand_reads_f114_b ), .Iout5 (Iand_reads_f137_b ), .Iout6 (Iand_reads_f160_b ), .Iout7 (Iand_reads_f183_b ), .Iout8 (Iand_reads_f206_b ), .Iout9 (Iand_reads_f229_b ), .Iout10 (Iand_reads_f252_b ), .Iout11 (Iand_reads_f275_b ), .Iout12 (Iand_reads_f298_b ), .Iout13 (Iand_reads_f321_b ), .Iout14 (Iand_reads_f344_b ), .Iout15 (Iand_reads_f367_b ), .Iout16 (Iand_reads_f390_b ), .Iout17 (Iand_reads_f413_b ), .Iout18 (Iand_reads_f436_b ), .Iout19 (Iand_reads_f459_b ), .Iout20 (Iand_reads_f482_b ), .Iout21 (Iand_reads_f505_b ), .Iout22 (Iand_reads_f528_b ), .Iout23 (Iand_reads_f551_b ), .Iout24 (Iand_reads_f574_b ), .Iout25 (Iand_reads_f597_b ), .Iout26 (Iand_reads_f620_b ), .Iout27 (Iand_reads_f643_b ), .Iout28 (Iand_reads_f666_b ), .Iout29 (Iand_reads_f689_b ), .Iout30 (Iand_reads_f712_b ), .Iout31 (Iand_reads_f735_b ), .Iout32 (Iand_reads_f758_b ), .Iout33 (Iand_reads_f781_b ), .Iout34 (Iand_reads_f804_b ), .Iout35 (Iand_reads_f827_b ), .Iout36 (Iand_reads_f850_b ), .Iout37 (Iand_reads_f873_b ), .Iout38 (Iand_reads_f896_b ), .Iout39 (Iand_reads_f919_b ), .Iout40 (Iand_reads_f942_b ), .Iout41 (Iand_reads_f965_b ), .Iout42 (Iand_reads_f988_b ), .Iout43 (Iand_reads_f1011_b ), .Iout44 (Iand_reads_f1034_b ), .Iout45 (Iand_reads_f1057_b ), .Iout46 (Iand_reads_f1080_b ), .Iout47 (Iand_reads_f1103_b ), .Iout48 (Iand_reads_f1126_b ), .Iout49 (Iand_reads_f1149_b ), .Iout50 (Iand_reads_f1172_b ), .Iout51 (Iand_reads_f1195_b ), .Iout52 (Iand_reads_f1218_b ), .Iout53 (Iand_reads_f1241_b ), .Iout54 (Iand_reads_f1264_b ), .Iout55 (Iand_reads_f1287_b ), .Iout56 (Iand_reads_f1310_b ), .Iout57 (Iand_reads_f1333_b ), .Iout58 (Iand_reads_f1356_b ), .Iout59 (Iand_reads_f1379_b ), .Iout60 (Iand_reads_f1402_b ), .Iout61 (Iand_reads_f1425_b ), .Iout62 (Iand_reads_f1448_b ), .Iout63 (Iand_reads_f1471_b ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0ortree_364_4 Iout_ortrees_t0 (.Iin0 (Iand_reads_t0_y ), .Iin1 (Iand_reads_t23_y ), .Iin2 (Iand_reads_t46_y ), .Iin3 (Iand_reads_t69_y ), .Iin4 (Iand_reads_t92_y ), .Iin5 (Iand_reads_t115_y ), .Iin6 (Iand_reads_t138_y ), .Iin7 (Iand_reads_t161_y ), .Iin8 (Iand_reads_t184_y ), .Iin9 (Iand_reads_t207_y ), .Iin10 (Iand_reads_t230_y ), .Iin11 (Iand_reads_t253_y ), .Iin12 (Iand_reads_t276_y ), .Iin13 (Iand_reads_t299_y ), .Iin14 (Iand_reads_t322_y ), .Iin15 (Iand_reads_t345_y ), .Iin16 (Iand_reads_t368_y ), .Iin17 (Iand_reads_t391_y ), .Iin18 (Iand_reads_t414_y ), .Iin19 (Iand_reads_t437_y ), .Iin20 (Iand_reads_t460_y ), .Iin21 (Iand_reads_t483_y ), .Iin22 (Iand_reads_t506_y ), .Iin23 (Iand_reads_t529_y ), .Iin24 (Iand_reads_t552_y ), .Iin25 (Iand_reads_t575_y ), .Iin26 (Iand_reads_t598_y ), .Iin27 (Iand_reads_t621_y ), .Iin28 (Iand_reads_t644_y ), .Iin29 (Iand_reads_t667_y ), .Iin30 (Iand_reads_t690_y ), .Iin31 (Iand_reads_t713_y ), .Iin32 (Iand_reads_t736_y ), .Iin33 (Iand_reads_t759_y ), .Iin34 (Iand_reads_t782_y ), .Iin35 (Iand_reads_t805_y ), .Iin36 (Iand_reads_t828_y ), .Iin37 (Iand_reads_t851_y ), .Iin38 (Iand_reads_t874_y ), .Iin39 (Iand_reads_t897_y ), .Iin40 (Iand_reads_t920_y ), .Iin41 (Iand_reads_t943_y ), .Iin42 (Iand_reads_t966_y ), .Iin43 (Iand_reads_t989_y ), .Iin44 (Iand_reads_t1012_y ), .Iin45 (Iand_reads_t1035_y ), .Iin46 (Iand_reads_t1058_y ), .Iin47 (Iand_reads_t1081_y ), .Iin48 (Iand_reads_t1104_y ), .Iin49 (Iand_reads_t1127_y ), .Iin50 (Iand_reads_t1150_y ), .Iin51 (Iand_reads_t1173_y ), .Iin52 (Iand_reads_t1196_y ), .Iin53 (Iand_reads_t1219_y ), .Iin54 (Iand_reads_t1242_y ), .Iin55 (Iand_reads_t1265_y ), .Iin56 (Iand_reads_t1288_y ), .Iin57 (Iand_reads_t1311_y ), .Iin58 (Iand_reads_t1334_y ), .Iin59 (Iand_reads_t1357_y ), .Iin60 (Iand_reads_t1380_y ), .Iin61 (Iand_reads_t1403_y ), .Iin62 (Iand_reads_t1426_y ), .Iin63 (Iand_reads_t1449_y ), .out(Iout_d_d6_d1 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0ortree_364_4 Iout_ortrees_t1 (.Iin0 (Iand_reads_t1_y ), .Iin1 (Iand_reads_t24_y ), .Iin2 (Iand_reads_t47_y ), .Iin3 (Iand_reads_t70_y ), .Iin4 (Iand_reads_t93_y ), .Iin5 (Iand_reads_t116_y ), .Iin6 (Iand_reads_t139_y ), .Iin7 (Iand_reads_t162_y ), .Iin8 (Iand_reads_t185_y ), .Iin9 (Iand_reads_t208_y ), .Iin10 (Iand_reads_t231_y ), .Iin11 (Iand_reads_t254_y ), .Iin12 (Iand_reads_t277_y ), .Iin13 (Iand_reads_t300_y ), .Iin14 (Iand_reads_t323_y ), .Iin15 (Iand_reads_t346_y ), .Iin16 (Iand_reads_t369_y ), .Iin17 (Iand_reads_t392_y ), .Iin18 (Iand_reads_t415_y ), .Iin19 (Iand_reads_t438_y ), .Iin20 (Iand_reads_t461_y ), .Iin21 (Iand_reads_t484_y ), .Iin22 (Iand_reads_t507_y ), .Iin23 (Iand_reads_t530_y ), .Iin24 (Iand_reads_t553_y ), .Iin25 (Iand_reads_t576_y ), .Iin26 (Iand_reads_t599_y ), .Iin27 (Iand_reads_t622_y ), .Iin28 (Iand_reads_t645_y ), .Iin29 (Iand_reads_t668_y ), .Iin30 (Iand_reads_t691_y ), .Iin31 (Iand_reads_t714_y ), .Iin32 (Iand_reads_t737_y ), .Iin33 (Iand_reads_t760_y ), .Iin34 (Iand_reads_t783_y ), .Iin35 (Iand_reads_t806_y ), .Iin36 (Iand_reads_t829_y ), .Iin37 (Iand_reads_t852_y ), .Iin38 (Iand_reads_t875_y ), .Iin39 (Iand_reads_t898_y ), .Iin40 (Iand_reads_t921_y ), .Iin41 (Iand_reads_t944_y ), .Iin42 (Iand_reads_t967_y ), .Iin43 (Iand_reads_t990_y ), .Iin44 (Iand_reads_t1013_y ), .Iin45 (Iand_reads_t1036_y ), .Iin46 (Iand_reads_t1059_y ), .Iin47 (Iand_reads_t1082_y ), .Iin48 (Iand_reads_t1105_y ), .Iin49 (Iand_reads_t1128_y ), .Iin50 (Iand_reads_t1151_y ), .Iin51 (Iand_reads_t1174_y ), .Iin52 (Iand_reads_t1197_y ), .Iin53 (Iand_reads_t1220_y ), .Iin54 (Iand_reads_t1243_y ), .Iin55 (Iand_reads_t1266_y ), .Iin56 (Iand_reads_t1289_y ), .Iin57 (Iand_reads_t1312_y ), .Iin58 (Iand_reads_t1335_y ), .Iin59 (Iand_reads_t1358_y ), .Iin60 (Iand_reads_t1381_y ), .Iin61 (Iand_reads_t1404_y ), .Iin62 (Iand_reads_t1427_y ), .Iin63 (Iand_reads_t1450_y ), .out(Iout_d_d7_d1 ), .vdd(vdd), .vss(vss));