reset working
This commit is contained in:
alexmadison
@@ -27,52 +27,13 @@
|
||||
*/
|
||||
|
||||
|
||||
import "../../dataflow_neuro/cell_lib_async.act";
|
||||
import "../../dataflow_neuro/cell_lib_std.act";
|
||||
import "../../dataflow_neuro/treegates.act";
|
||||
import "../../dataflow_neuro/primitives.act";
|
||||
import "../../dataflow_neuro/coders.act";
|
||||
// import tmpl::dataflow_neuro;
|
||||
// import tmpl::dataflow_neuro;
|
||||
import std::channel;
|
||||
open std::channel;
|
||||
|
||||
|
||||
/*************************************************************************
|
||||
*
|
||||
* This file is part of ACT dataflow neuro library
|
||||
*
|
||||
* Copyright (c) 2022 University of Groningen - Ole Richter
|
||||
* Copyright (c) 2022 University of Groningen - Michele Mastella
|
||||
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
|
||||
* Copyright (c) 2022 University of Groningen - Madison Cotteret
|
||||
*
|
||||
*
|
||||
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
|
||||
*
|
||||
* You may redistribute and modify this documentation and make products
|
||||
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
|
||||
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
|
||||
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
|
||||
* for applicable conditions.
|
||||
*
|
||||
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
|
||||
*
|
||||
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
|
||||
* these sources, You must maintain the Source Location visible in its
|
||||
* documentation.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
|
||||
import "../../dataflow_neuro/cell_lib_async.act";
|
||||
import "../../dataflow_neuro/cell_lib_std.act";
|
||||
import "../../dataflow_neuro/treegates.act";
|
||||
import "../../dataflow_neuro/primitives.act";
|
||||
import "../../dataflow_neuro/registers.act";
|
||||
import "../../dataflow_neuro/coders.act";
|
||||
import "../../dataflow_neuro/interfaces.act";
|
||||
// import tmpl::dataflow_neuro;
|
||||
// import tmpl::dataflow_neuro;
|
||||
import std::channel;
|
||||
@@ -81,7 +42,7 @@ open std::channel;
|
||||
namespace tmpl {
|
||||
namespace dataflow_neuro {
|
||||
|
||||
export template<N_IN, // Size of input data from outside world
|
||||
export template<pint N_IN, // Size of input data from outside world
|
||||
N_NRN_X, N_NRN_Y, N_SYN_X, N_SYN_Y, // Number of neurons / synapses
|
||||
NC_NRN_X, NC_NRN_Y, NC_SYN_X, NC_SYN_Y,
|
||||
N_SYN_DLY_CFG,
|
||||
@@ -100,7 +61,8 @@ defproc chip_texel (bd<N_IN> in, out;
|
||||
power supply;
|
||||
bool? reset_B){
|
||||
|
||||
bd2qdi<N_IN, N_BD_DLY_CFG> _bd2qdi(.in = in, .supply = supply);
|
||||
bd2qdi<N_IN, N_BD_DLY_CFG> _bd2qdi(.in = in, .dly_cfg = bd_dly_cfg,
|
||||
.reset_B = reset_B, .supply = supply);
|
||||
fifo<N_IN,N_BUFFERS> fifo_in2fork(.in = _bd2qdi.out, .reset_B = reset_B, .supply = supply);
|
||||
|
||||
fork<N_IN> _fork(.in = fifo_in2fork.out, .reset_B = reset_B, .supply = supply);
|
||||
@@ -112,7 +74,7 @@ defproc chip_texel (bd<N_IN> in, out;
|
||||
|
||||
// Onwards
|
||||
fifo<N_IN,N_BUFFERS> fifo_fork2dmx(.in = _fork.out2, .reset_B = reset_B, .supply = supply);
|
||||
demux_msb<N_IN-1> _demux(.in = fifo_fork2dmx.out, .reset_B = reset_B, .supply = supply);
|
||||
demux_bit_msb<N_IN-1> _demux(.in = fifo_fork2dmx.out, .reset_B = reset_B, .supply = supply);
|
||||
|
||||
// Register
|
||||
fifo<N_IN-1,N_BUFFERS> fifo_dmx2reg(.in = _demux.out2, .reset_B = reset_B, .supply = supply);
|
||||
@@ -123,17 +85,18 @@ defproc chip_texel (bd<N_IN> in, out;
|
||||
// TO ADD: nrn/syn mon decoders
|
||||
|
||||
// Decoder
|
||||
// slice_data<N_IN-1>
|
||||
fifo<N_IN-1,N_BUFFERS> fifo_dmx2dec(.in = _demux.out, .reset_B = reset_B, .supply = supply);
|
||||
pint NC_SYN;
|
||||
NC_SYN = NC_SYN_X + NC_SYN_Y;
|
||||
slice_data<N_IN-1, 0, NC_SYN> slice_pre_dec(.in = _demux.out1, .supply = supply);
|
||||
fifo<NC_SYN,N_BUFFERS> fifo_dmx2dec(.in = slice_pre_dec.out, .reset_B = reset_B, .supply = supply);
|
||||
decoder_2d_hybrid<NC_SYN_X, NC_SYN_Y, N_SYN_X, N_SYN_Y, N_SYN_DLY_CFG> decoder(.in = fifo_dmx2dec.in,
|
||||
.out = synapses,
|
||||
.hs_en = register.data[0].d[0].f, // Defaults to handshake disable
|
||||
.supply = supply, .reset_B = reset_B);
|
||||
(i:N_SYN_DLY_CFG: decoder.dly_cfg[i] = register.data[0].d[1 + i].t); // Defaults to max delay
|
||||
|
||||
(i:N_SYN_DLY_CFG: decoder.dly_cfg[i] = register.data[0].d[1 + i].t;) // Defaults to max delay
|
||||
|
||||
// Neurons + encoder
|
||||
pbool NC_NRN;
|
||||
pint NC_NRN;
|
||||
NC_NRN = NC_NRN_X + NC_NRN_Y;
|
||||
nrn_hs_2D_array<N_NRN_X,N_NRN_Y,N_LINE_PD_DLY> nrn_grid(.in = neurons,
|
||||
.supply = supply, .reset_B = reset_B);
|
||||
@@ -141,15 +104,25 @@ defproc chip_texel (bd<N_IN> in, out;
|
||||
.inx = nrn_grid.outx,
|
||||
.iny = nrn_grid.outy,
|
||||
.reset_B = reset_B, .supply = supply
|
||||
)
|
||||
);
|
||||
fifo<NC_NRN, N_BUFFERS> fifo_enc2mrg(.in = encoder.out,
|
||||
.reset_B = reset_B, .supply = supply);
|
||||
append<NC_NRN, N_IN-NC_NRN,0> append_enc(.in = fifo_enc2mrg.in, )
|
||||
|
||||
|
||||
// Merge
|
||||
append<NC_NRN, N_IN-NC_NRN, 0> append_enc(.in = fifo_enc2mrg.out, .supply = supply);
|
||||
append<N_IN-2, 2, 0> append_reg(.in = fifo_reg2mrg.out, .supply = supply);
|
||||
merge<N_IN> merge_enc8reg(.in1 = append_enc.out, .in2 = append_reg.out,
|
||||
.supply = supply, .reset_B = reset_B);
|
||||
|
||||
merge<> merge_enc8reg
|
||||
merge<N_IN> merge_loop8mrg(.in1 = merge_enc8reg.out, .in2 = _loopback_dropper.out,
|
||||
.reset_B = reset_B, .supply = supply);
|
||||
|
||||
// qdi2bd
|
||||
fifo<N_IN, N_BUFFERS> fifo_mrg2bd(.in = merge_loop8mrg.out,
|
||||
.reset_B = reset_B, .supply = supply);
|
||||
qdi2bd<N_IN, N_BD_DLY_CFG> _qdi2b(.in = fifo_mrg2bd.out, .out = out, .dly_cfg = bd_dly_cfg,
|
||||
.reset_B = reset_B, .supply = supply);
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
1292
test/unit_tests/chip_nomap/run/prsim.out
Normal file
1292
test/unit_tests/chip_nomap/run/prsim.out
Normal file
File diff suppressed because one or more lines are too long
84038
test/unit_tests/chip_nomap/run/test.prs
Normal file
84038
test/unit_tests/chip_nomap/run/test.prs
Normal file
File diff suppressed because it is too large
Load Diff
102
test/unit_tests/chip_nomap/test.act
Normal file
102
test/unit_tests/chip_nomap/test.act
Normal file
@@ -0,0 +1,102 @@
|
||||
/*************************************************************************
|
||||
*
|
||||
* This file is part of ACT dataflow neuro library.
|
||||
* It's the testing facility for cell_lib_std.act
|
||||
*
|
||||
* Copyright (c) 2022 University of Groningen - Ole Richter
|
||||
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
|
||||
* Copyright (c) 2022 University of Groningen - Michele Mastella
|
||||
* Copyright (c) 2022 University of Groningen - Madison Cotteret
|
||||
*
|
||||
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
|
||||
*
|
||||
* You may redistribute and modify this documentation and make products
|
||||
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
|
||||
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
|
||||
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
|
||||
* for applicable conditions.
|
||||
*
|
||||
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
|
||||
*
|
||||
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
|
||||
* these sources, You must maintain the Source Location visible in its
|
||||
* documentation.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
import "../../dataflow_neuro/coders.act";
|
||||
import "../../dataflow_neuro/primitives.act";
|
||||
import "../../dataflow_neuro/chips.act";
|
||||
|
||||
import globals;
|
||||
import std::data;
|
||||
|
||||
open std::data;
|
||||
|
||||
|
||||
open tmpl::dataflow_neuro;
|
||||
|
||||
defproc chip_texel_test (bd<14> in; bd<14> out; Mx1of2<8> reg_data[16];
|
||||
bool? bd_dly_cfg[4], loopback_en){
|
||||
|
||||
bool _reset_B;
|
||||
prs {
|
||||
Reset => _reset_B-
|
||||
}
|
||||
power supply;
|
||||
supply.vdd = Vdd;
|
||||
supply.vss = GND;
|
||||
|
||||
pint N_IN = 14;
|
||||
|
||||
pint N_NRN_X = 2;
|
||||
pint N_NRN_Y = 4;
|
||||
// pint NC_NRN_X = std:ceil_log2(N_NRN_X);
|
||||
// pint NC_NRN_Y = std:ceil_log2(N_NRN_Y);
|
||||
pint NC_NRN_X = 1;
|
||||
pint NC_NRN_Y = 2;
|
||||
|
||||
pint N_SYN_X = 2;
|
||||
pint N_SYN_Y = 4;
|
||||
// pint NC_SYN_X = std:ceil_log2(N_SYN_X);
|
||||
// pint NC_SYN_Y = std:ceil_log2(N_SYN_Y);
|
||||
pint NC_SYN_X = 1;
|
||||
pint NC_SYN_Y = 2;
|
||||
|
||||
pint N_SYN_DLY_CFG = 4;
|
||||
pint N_BD_DLY_CFG = 4;
|
||||
|
||||
pint N_NRN_MON_X = 2;
|
||||
pint N_NRN_MON_Y = 4;
|
||||
pint N_SYN_MON_X = 2;
|
||||
pint N_SYN_MON_Y = 4;
|
||||
|
||||
pint N_BUFFERS = 3;
|
||||
|
||||
pint N_LINE_PD_DLY = 3;
|
||||
|
||||
pint REG_NCA = 4;
|
||||
pint REG_M = 1<<REG_NCA;
|
||||
pint REG_NCW = 8;
|
||||
|
||||
chip_texel<N_IN,
|
||||
N_NRN_X, N_NRN_Y, N_SYN_X, N_SYN_Y,
|
||||
NC_NRN_X, NC_NRN_Y, NC_SYN_X, NC_SYN_Y,
|
||||
N_SYN_DLY_CFG,
|
||||
N_NRN_MON_X, N_NRN_MON_Y, N_SYN_MON_X, N_SYN_MON_Y,
|
||||
N_BUFFERS,
|
||||
N_LINE_PD_DLY,
|
||||
N_BD_DLY_CFG,
|
||||
REG_NCA, REG_NCW, REG_M> c(.in = in, .out = out, .reg_data = reg_data,
|
||||
.bd_dly_cfg = bd_dly_cfg, .loopback_en = loopback_en,
|
||||
.reset_B = _reset_B, .supply = supply);
|
||||
|
||||
c.synapses = c.neurons; // Connect each synapse hs to a neuron hs
|
||||
|
||||
}
|
||||
|
||||
|
||||
// fifo_decoder_neurons_encoder_fifo e;
|
||||
chip_texel_test c;
|
||||
22
test/unit_tests/chip_nomap/test.prsim
Normal file
22
test/unit_tests/chip_nomap/test.prsim
Normal file
@@ -0,0 +1,22 @@
|
||||
watchall
|
||||
|
||||
|
||||
# set-bool-array "c.bd_dly_cfg" 4 15
|
||||
set c.bd_dly_cfg[0] 1
|
||||
set c.bd_dly_cfg[1] 1
|
||||
set c.bd_dly_cfg[2] 1
|
||||
set c.bd_dly_cfg[3] 1
|
||||
|
||||
set-bd-channel-neutral "c.in" 14
|
||||
set-bd-channel-neutral "c.out" 14
|
||||
set c.loopback_en 1
|
||||
set Reset 1
|
||||
|
||||
cycle
|
||||
|
||||
mode run
|
||||
system "echo '[] Set reset 0'"
|
||||
status X
|
||||
set Reset 0
|
||||
cycle
|
||||
|
||||
Reference in New Issue
Block a user