bics/actlib_dataflow_neuro
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added decoder dualrail refresh

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This commit is contained in:
alexmadison
2022-04-13 17:35:41 +02:00
parent 4cca8c14fe
commit bf4af13e04
6 changed files with 28645 additions and 6082 deletions
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1225
test/unit_tests/texel_dualcore/run/prsim.in
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test/unit_tests/texel_dualcore/run/prsim.out
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test/unit_tests/texel_dualcore/run/test.prs
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45
test/unit_tests/texel_dualcore/test.act
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@ -42,8 +42,12 @@ open tmpl::dataflow_neuro;
pint N_IN = 32;
pint N_NRN_X = 15;
pint N_NRN_Y = 6;
// pint N_NRN_X = 15;
// pint N_NRN_Y = 6;
// pint NC_NRN_X = 4;
// pint NC_NRN_Y = 3;
pint N_NRN_X = 16;
pint N_NRN_Y = 8;
pint NC_NRN_X = 4;
pint NC_NRN_Y = 3;
@ -51,8 +55,8 @@ pint NC_NRN_Y = 3;
// pint N_SYN_Y = 348;
// pint NC_SYN_X = 6;
// pint NC_SYN_Y = 9;
pint N_SYN_X = 15;
pint N_SYN_Y = 6;
pint N_SYN_X = 16;
pint N_SYN_Y = 8;
pint NC_SYN_X = 4;
pint NC_SYN_Y = 3;
@ -86,10 +90,10 @@ defproc chip_texel_dualcore (bd<N_IN> in, out;
Mx1of2<REG_NCW> c1_reg_data[REG_M];
// a1of1 c1_synapses[N_SYN_X * N_SYN_Y];
// a1of1 c1_neurons[N_NRN_X * N_NRN_Y];
bool! c1_syn_r[N_SYN_X * N_SYN_Y];
bool? c1_syn_a[N_SYN_X * N_SYN_Y];
bool? c1_nrn_r[N_NRN_X * N_NRN_Y];
bool! c1_nrn_a[N_NRN_X * N_NRN_Y];
bool c1_syn_r[N_SYN_X * N_SYN_Y];
bool c1_syn_a[N_SYN_X * N_SYN_Y];
bool c1_nrn_r[N_NRN_X * N_NRN_Y];
bool c1_nrn_a[N_NRN_X * N_NRN_Y];
bool! c1_nrn_mon_x[N_NRN_MON_X], c1_nrn_mon_y[N_NRN_MON_Y];
bool! c1_syn_mon_x[N_SYN_MON_X], c1_syn_mon_y[N_SYN_MON_Y];
@ -100,10 +104,10 @@ defproc chip_texel_dualcore (bd<N_IN> in, out;
Mx1of2<REG_NCW> c2_reg_data[REG_M];
// a1of1 c2_synapses[N_SYN_X * N_SYN_Y];
// a1of1 c2_neurons[N_NRN_X * N_NRN_Y];
bool! c2_syn_r[N_SYN_X * N_SYN_Y];
bool? c2_syn_a[N_SYN_X * N_SYN_Y];
bool? c2_nrn_r[N_NRN_X * N_NRN_Y];
bool! c2_nrn_a[N_NRN_X * N_NRN_Y];
bool c2_syn_r[N_SYN_X * N_SYN_Y];
bool c2_syn_a[N_SYN_X * N_SYN_Y];
bool c2_nrn_r[N_NRN_X * N_NRN_Y];
bool c2_nrn_a[N_NRN_X * N_NRN_Y];
bool! c2_nrn_mon_x[N_NRN_MON_X], c2_nrn_mon_y[N_NRN_MON_Y];
bool! c2_syn_mon_x[N_SYN_MON_X], c2_syn_mon_y[N_SYN_MON_Y];
@ -155,7 +159,22 @@ defproc chip_texel_dualcore (bd<N_IN> in, out;
.c1_reg_data = c1_reg_data, .c1_synapses = c1_synapses, .c1_neurons = c1_neurons, .c1_nrn_mon_x = c1_nrn_mon_x, .c1_nrn_mon_y = c1_nrn_mon_y, .c1_syn_mon_x = c1_syn_mon_x, .c1_syn_mon_y = c1_syn_mon_y, .c1_syn_mon_AMZI = c1_syn_mon_AMZI, .c1_nrn_mon_AMZI = c1_nrn_mon_AMZI, .c1_syn_mon_AMZO = c1_syn_mon_AMZO, .c1_nrn_mon_AMZO = c1_nrn_mon_AMZO, .c1_syn_flags_EFO = c1_syn_flags_EFO, .c1_nrn_flags_EFO = c1_nrn_flags_EFO, .c2_reg_data = c2_reg_data, .c2_synapses = c2_synapses, .c2_neurons = c2_neurons, .c2_nrn_mon_x = c2_nrn_mon_x, .c2_nrn_mon_y = c2_nrn_mon_y, .c2_syn_mon_x = c2_syn_mon_x, .c2_syn_mon_y = c2_syn_mon_y, .c2_syn_mon_AMZI = c2_syn_mon_AMZI, .c2_nrn_mon_AMZI = c2_nrn_mon_AMZI, .c2_syn_mon_AMZO = c2_syn_mon_AMZO, .c2_nrn_mon_AMZO = c2_nrn_mon_AMZO, .c2_syn_flags_EFO = c2_syn_flags_EFO, .c2_nrn_flags_EFO = c2_nrn_flags_EFO, .bd_dly_cfg = bd_dly_cfg, .bd_dly_cfg2 = bd_dly_cfg2,
.loopback_en = loopback_en, .supply = supply, .reset_B = _reset_B);
pint N_SYNS = N_SYN_X * N_SYN_Y;
BUF_X4 syn2nrns_r[N_SYNS*2];
BUF_X4 syn2nrns_a[N_SYNS*2];
(i:N_SYNS:
syn2nrns_r[i].a = c1_synapses[i].r;
syn2nrns_r[i].y = c1_neurons[i].r;
syn2nrns_a[i].a = c1_neurons[i].a;
syn2nrns_a[i].y = c1_synapses[i].a;
syn2nrns_r[i+N_SYNS].a = c2_synapses[i].r;
syn2nrns_r[i+N_SYNS].y = c2_neurons[i].r;
syn2nrns_a[i+N_SYNS].a = c2_neurons[i].a;
syn2nrns_a[i+N_SYNS].y = c2_synapses[i].a;
)
}

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test/unit_tests/texel_dualcore/test.prsim
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