fixed unit tests
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@ -35,7 +35,7 @@ open std::data;
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open tmpl::dataflow_neuro;
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open tmpl::dataflow_neuro;
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defproc registerA_w_array_3x5x8 (avMx1of2<3+5+1> in; Mx1of2<5> data[8]){
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defproc registerA_w_array_3x5x8 (avMx1of2<3+5> in; Mx1of2<5> data[8]){
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bool _reset_B;
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bool _reset_B;
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prs {
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prs {
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Reset => _reset_B-
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Reset => _reset_B-
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@ -46,7 +46,7 @@ defproc registerA_w_array_3x5x8 (avMx1of2<3+5+1> in; Mx1of2<5> data[8]){
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// Make a register array with 3 bit address (-> 8 registers),
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// Make a register array with 3 bit address (-> 8 registers),
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// each register holding 5 bits.
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// each register holding 5 bits.
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registerA_w_array<3,5,8> b(.in = in, .data = data, .reset_B = _reset_B, .supply = supply);
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register_w_array<3,5,8> b(.in = in, .data = data, .reset_B = _reset_B, .supply = supply);
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}
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}
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@ -1,6 +1,6 @@
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watchall
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watchall
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set-qdi-channel-neutral "b.in" 9
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set-qdi-channel-neutral "b.in" 8
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cycle
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cycle
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@ -13,42 +13,42 @@ assert b.in.a 0
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assert b.in.v 0
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assert b.in.v 0
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system "echo '[] Sending packet write 0s to reg0'"
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system "echo '[] Sending packet write 0s to reg0'"
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set-qdi-channel-valid "b.in" 9 256
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set-qdi-channel-valid "b.in" 8 256
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cycle
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cycle
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assert b.in.a 1
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assert b.in.a 1
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assert b.in.v 1
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assert b.in.v 1
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assert-var-int "b.data[0]" 5 0
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assert-var-int "b.data[0]" 5 0
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system "echo '[] Removing input'"
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system "echo '[] Removing input'"
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set-qdi-channel-neutral "b.in" 9
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set-qdi-channel-neutral "b.in" 8
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cycle
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cycle
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assert b.in.a 0
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assert b.in.a 0
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assert b.in.v 0
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assert b.in.v 0
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assert-var-int "b.data[0]" 5 0
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assert-var-int "b.data[0]" 5 0
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system "echo '[] Sending packet write 0s to reg0'"
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system "echo '[] Sending packet write 0s to reg0'"
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set-qdi-channel-valid "b.in" 9 256
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set-qdi-channel-valid "b.in" 8 256
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cycle
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cycle
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assert b.in.a 1
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assert b.in.a 1
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assert b.in.v 1
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assert b.in.v 1
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assert-var-int "b.data[0]" 5 0
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assert-var-int "b.data[0]" 5 0
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system "echo '[] Removing input'"
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system "echo '[] Removing input'"
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set-qdi-channel-neutral "b.in" 9
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set-qdi-channel-neutral "b.in" 8
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cycle
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cycle
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assert b.in.a 0
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assert b.in.a 0
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assert b.in.v 0
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assert b.in.v 0
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assert-var-int "b.data[0]" 5 0
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assert-var-int "b.data[0]" 5 0
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system "echo '[] Sending packet write 01100 to reg0'"
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system "echo '[] Sending packet write 01100 to reg0'"
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set-qdi-channel-valid "b.in" 9 352
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set-qdi-channel-valid "b.in" 8 352
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cycle
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cycle
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assert b.in.a 1
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assert b.in.a 1
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assert b.in.v 1
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assert b.in.v 1
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assert-var-int "b.data[0]" 5 12
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assert-var-int "b.data[0]" 5 12
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system "echo '[] Removing input'"
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system "echo '[] Removing input'"
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set-qdi-channel-neutral "b.in" 9
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set-qdi-channel-neutral "b.in" 8
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cycle
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cycle
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assert b.in.a 0
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assert b.in.a 0
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assert b.in.v 0
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assert b.in.v 0
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@ -56,88 +56,88 @@ assert-var-int "b.data[0]" 5 12
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system "echo '[] Sending packet write 0s to reg1'"
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system "echo '[] Sending packet write 0s to reg1'"
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set-qdi-channel-valid "b.in" 9 257
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set-qdi-channel-valid "b.in" 8 257
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cycle
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cycle
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assert b.in.a 1
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assert b.in.a 1
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assert b.in.v 1
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assert b.in.v 1
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assert-var-int "b.data[1]" 5 0
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assert-var-int "b.data[1]" 5 0
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system "echo '[] Removing input'"
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system "echo '[] Removing input'"
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set-qdi-channel-neutral "b.in" 9
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set-qdi-channel-neutral "b.in" 8
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cycle
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cycle
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assert b.in.a 0
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assert b.in.a 0
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assert b.in.v 0
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assert b.in.v 0
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system "echo '[] Sending packet write 0s to reg2'"
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system "echo '[] Sending packet write 0s to reg2'"
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set-qdi-channel-valid "b.in" 9 258
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set-qdi-channel-valid "b.in" 8 258
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cycle
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cycle
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assert b.in.a 1
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assert b.in.a 1
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assert b.in.v 1
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assert b.in.v 1
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assert-var-int "b.data[2]" 5 0
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assert-var-int "b.data[2]" 5 0
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system "echo '[] Removing input'"
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system "echo '[] Removing input'"
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set-qdi-channel-neutral "b.in" 9
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set-qdi-channel-neutral "b.in" 8
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cycle
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cycle
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assert b.in.a 0
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assert b.in.a 0
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assert b.in.v 0
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assert b.in.v 0
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assert-var-int "b.data[2]" 5 0
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assert-var-int "b.data[2]" 5 0
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system "echo '[] Sending packet write 0s to reg3'"
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system "echo '[] Sending packet write 0s to reg3'"
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set-qdi-channel-valid "b.in" 9 259
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set-qdi-channel-valid "b.in" 8 259
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cycle
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cycle
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assert b.in.a 1
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assert b.in.a 1
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assert b.in.v 1
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assert b.in.v 1
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system "echo '[] Removing input'"
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system "echo '[] Removing input'"
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set-qdi-channel-neutral "b.in" 9
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set-qdi-channel-neutral "b.in" 8
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cycle
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cycle
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assert b.in.a 0
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assert b.in.a 0
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assert b.in.v 0
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assert b.in.v 0
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system "echo '[] Sending packet write 0s to reg4'"
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system "echo '[] Sending packet write 0s to reg4'"
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set-qdi-channel-valid "b.in" 9 260
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set-qdi-channel-valid "b.in" 8 260
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cycle
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cycle
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assert b.in.a 1
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assert b.in.a 1
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assert b.in.v 1
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assert b.in.v 1
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system "echo '[] Removing input'"
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system "echo '[] Removing input'"
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set-qdi-channel-neutral "b.in" 9
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set-qdi-channel-neutral "b.in" 8
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cycle
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cycle
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assert b.in.a 0
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assert b.in.a 0
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assert b.in.v 0
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assert b.in.v 0
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system "echo '[] Sending packet write 0s to reg5'"
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system "echo '[] Sending packet write 0s to reg5'"
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set-qdi-channel-valid "b.in" 9 261
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set-qdi-channel-valid "b.in" 8 261
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cycle
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cycle
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assert b.in.a 1
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assert b.in.a 1
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assert b.in.v 1
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assert b.in.v 1
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system "echo '[] Removing input'"
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system "echo '[] Removing input'"
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set-qdi-channel-neutral "b.in" 9
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set-qdi-channel-neutral "b.in" 8
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cycle
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cycle
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assert b.in.a 0
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assert b.in.a 0
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assert b.in.v 0
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assert b.in.v 0
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system "echo '[] Sending packet write 0s to reg6'"
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system "echo '[] Sending packet write 0s to reg6'"
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set-qdi-channel-valid "b.in" 9 262
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set-qdi-channel-valid "b.in" 8 262
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cycle
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cycle
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assert b.in.a 1
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assert b.in.a 1
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assert b.in.v 1
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assert b.in.v 1
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system "echo '[] Removing input'"
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system "echo '[] Removing input'"
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set-qdi-channel-neutral "b.in" 9
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set-qdi-channel-neutral "b.in" 8
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cycle
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cycle
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assert b.in.a 0
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assert b.in.a 0
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assert b.in.v 0
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assert b.in.v 0
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system "echo '[] Sending packet write 0s to reg7'"
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system "echo '[] Sending packet write 0s to reg7'"
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set-qdi-channel-valid "b.in" 9 263
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set-qdi-channel-valid "b.in" 8 263
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cycle
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cycle
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assert b.in.a 1
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assert b.in.a 1
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assert b.in.v 1
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assert b.in.v 1
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system "echo '[] Removing input'"
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system "echo '[] Removing input'"
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set-qdi-channel-neutral "b.in" 9
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set-qdi-channel-neutral "b.in" 8
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cycle
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cycle
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assert b.in.a 0
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assert b.in.a 0
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assert b.in.v 0
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assert b.in.v 0
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