fixed wiring bug in prog delay

2022-03-02 15:11:22 +01:00 · 2022-03-02 15:11:22 +01:00 · c61a570f80
commit c61a570f80
parent 6bece2f459
1 changed files with 1 additions and 1 deletions
--- a/dataflow_neuro/primitives.act
+++ b/dataflow_neuro/primitives.act
@ -647,7 +647,7 @@ namespace tmpl {
                // Delays
                dly[i_delay].a = and2[i].y;
                i_delay = i_delay + 1;
-                (j:1..i-1:
+                (j:1..(1<<i)-1:
                    dly[i_delay].a = dly[i_delay-1].y;
                    i_delay = i_delay +1;
                )