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started register_v2 with reading and writing abilities

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This commit is contained in:
M. Mastella
2022-03-09 13:05:08 +01:00
parent 422a90ad71
commit c8ac3cf37d
7 changed files with 1172 additions and 1045 deletions
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9
dataflow_neuro/primitives.act
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@ -624,6 +624,15 @@ namespace tmpl {
// Programmable delay line.
// N is the number of layers,
// the longest layer having 2**N DLY elements
// Circuit for creating delays, there are N delay layers.
// The block has the parameters:
// N -> the number is the number of layers with the longest being 2**N elements
// wl -> word length, length of each word
// N_dly_cfg -> the number of config bits in the ACK delay line
// The block has the pins:
// in -> input data
// out -> output data
// s -> bit word with size N that sets delay configuration. int(s) = number of delays
export template<pint N>
defproc delayprog (bool! out; bool? in, s[N]; power supply)
{

88
dataflow_neuro/registers.act
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@ -59,7 +59,7 @@ defproc register_rw (avMx1of2<1+lognw+wl> in; d1of<wl> data[1<<lognw]; power sup
(i:1+lognw+wl:_in_temp.d[i] = in.d.d[i];)
vtree<1+lognw+wl> val_input(.in = _in_temp,.out = _in_v_temp, .supply = supply);
sigbuf_1output<4> val_input_X(.in = _in_v_temp,.out = in.v,.supply = supply);
// Generation of the fake clock pulse
// Generation of the fake clock pulse (inverted because the ff clocks are low_active)
delayprog<N_dly_cfg> clk_dly(.in = _in_v_temp, .out = _clock_temp,.s = dly_cfg, .supply = supply);
INV_X1 inv_clk(.a = _clock_temp,.y = _clock_temp_inv,.vdd = supply.vdd,.vss = supply.vss);
sigbuf_1output<4> clk_X(.in = _clock_temp_inv,.out = _clock,.supply = supply);
@ -109,6 +109,90 @@ defproc register_rw (avMx1of2<1+lognw+wl> in; d1of<wl> data[1<<lognw]; power sup
ff[bit_idx+word_idx*(wl)].vss = supply.vss;
)
)
}
}
export template<pint lognw,wl,N_dly_cfg>
defproc register_rw_v2 (avMx1of2<1+lognw+wl> in; d1of<wl> data[1<<lognw]; power supply; bool? reset_B,reset_mem_B,dly_cfg[N_dly_cfg]){
bool _in_v_temp,_in_a_temp,_clock_temp,_clock,_clock_temp_inv;
pint nw = 1<<lognw;
//Validation of the input
avMx1of2<lognw+wl> _in_temp2,_in_read,_in_write;
avMx1of2<1>_in_flag;
// bool _in_stable;
// (i:1+lognw+wl:_in_temp.d[i] = in.d.d[i];)
// vtree<1+lognw+wl> val_input(.in = _in_temp,.out = _in_v_temp, .supply = supply);
// sigbuf_1output<4> val_input_X(.in = _in_v_temp,.out = in.v,.supply = supply);
// Read or write?
AND2_X1 ack_and(.a = _in_temp2.a,.b = _in_flag.a,.y = in.a,.vdd = supply.vdd,.vss = supply.vss);
in.v = _in_temp2.v;
_in_flag.d.d[0] = in.d.d[lognw+wl];
(i:lognw+wl:_in_temp2.d.d[i] = in.d.d[i];)
demux<lognw+wl> read_write_demux(.in = _in_temp2,.out1 = _in_write, .out2 = _in_read, .cond = _in_flag,.reset_B = reset_B);
read_write_demux.supply= supply;
//WRITE PATH
// Validation
vtree<lognw+wl> val_input(.in = _in_write,.out = _in_write.v, .supply = supply);
vtree<wl>
// Generation of the fake clock pulse (inverted because the ff clocks are low_active)
delayprog<N_dly_cfg> clk_dly(.in = _in_write.v, .out = _clock_temp,.s = dly_cfg, .supply = supply);
INV_X1 inv_clk(.a = _clock_temp,.y = _clock_temp_inv,.vdd = supply.vdd,.vss = supply.vss);
sigbuf_1output<4> clk_X(.in = _clock_temp_inv,.out = _clock,.supply = supply);
//READ PATH
//Validation
vtree<lognw+wl> val_input(.in = _in_read,.out = _in_read.v, .supply = supply);
// Sending signal to the output
//Reset Buffers
bool _reset_BX,_reset_mem_BX,_reset_mem_BXX[nw*wl];
BUF_X1 reset_buf_BX(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
BUF_X1 reset_buf_BXX(.a=reset_mem_B, .y=_reset_mem_BX,.vdd=supply.vdd,.vss=supply.vss);
sigbuf<nw*wl*2> reset_bufarray(.in=_reset_mem_BX, .out=_reset_mem_BXX,.supply=supply);
// Creating the different flip flop arrays
bool _out_encoder[nw],_clock_word_temp[nw],_clock_word[nw],_clock_buffer_out[nw*wl];
andtree<lognw> atree[nw];
d1of<wl> _data_f;
AND2_X1 and_encoder[nw];
sigbuf<wl*2> clock_buffer[nw];
DFFQ_R_X1 ff_t[2*nw*wl],ff_f[2*nw*wl];
pint bitval;
(k:nw:atree[k].supply = supply;)
(word_idx:nw:
// Decoding the bit pattern to understand which word we are looking at
(pin_idx:lognw:
bitval = (word_idx & ( 1 << pin_idx )) >> pin_idx; // Get binary digit of integer i, column j
[bitval = 1 ->
atree[word_idx].in[pin_idx] = in.d.d[pin_idx+wl].t;
[] bitval = 0 ->
atree[word_idx].in[pin_idx] = in.d.d[pin_idx+wl].f;
[]bitval >= 2 -> {false : "fuck"};
]
)
// Activating the fake clock for the right word
atree[word_idx].out = _out_encoder[word_idx];
and_encoder[word_idx].a = _out_encoder[word_idx];
and_encoder[word_idx].b = _clock;
and_encoder[word_idx].y = _clock_word_temp[word_idx];
and_encoder[word_idx].vdd = supply.vdd;
and_encoder[word_idx].vss = supply.vss;
clock_buffer[word_idx].in = _clock_word_temp[word_idx];
clock_buffer[word_idx].supply = supply;
// Describing all the FF and their connection
(bit_idx:wl:
ff_t[bit_idx+word_idx*(wl)].clk_B = clock_buffer[word_idx].out[bit_idx];
ff_t[bit_idx+word_idx*(wl)].d = in.d.d[bit_idx].t;
ff_t[bit_idx+word_idx*(wl)].q = data[word_idx].d[bit_idx];
ff_t[bit_idx+word_idx*(wl)].reset_B = _reset_mem_BXX[bit_idx+word_idx*(wl)];
ff_t[bit_idx+word_idx*(wl)].vdd = supply.vdd;
ff_t[bit_idx+word_idx*(wl)].vss = supply.vss;
ff_f[bit_idx+word_idx*(wl)].clk_B = clock_buffer[word_idx+nw-1].out[bit_idx];
ff_f[bit_idx+word_idx*(wl)].d = in.d.d[bit_idx].f;
ff_f[bit_idx+word_idx*(wl)].q = data[word_idx].d[bit_idx];
ff_f[bit_idx+word_idx*(wl)].reset_B = _reset_mem_BXX[bit_idx+word_idx*(wl)+nw-1];
ff_f[bit_idx+word_idx*(wl)].vdd = supply.vdd;
ff_f[bit_idx+word_idx*(wl)].vss = supply.vss;
)
)
}
}}