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started register_v2 with reading and writing abilities

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This commit is contained in:
M. Mastella
2022-03-09 13:05:08 +01:00
parent 422a90ad71
commit c8ac3cf37d
7 changed files with 1172 additions and 1045 deletions
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11
test/unit_tests/register_write/test.prsim
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@@ -2,10 +2,17 @@ watchall
system "echo '[0] start test'"
set-qdi-channel-neutral "t.in" 5
set-qdi-channel-neutral "t._in_write" 5
set-qdi-channel-neutral "t._in_read" 5
set t.data[0].d[0] 0
set t.data[0].d[1] 0
set t.data[1].d[0] 0
set t.data[1].d[1] 0
set t.registers._in_write.a 0
set t.registers._in_read.a 0
set t.registers._in_write.v 0
set t.registers._in_read.v 0
set Reset 0
cycle
status X
@@ -23,9 +30,9 @@ set t.dly_cfg[1] 1
cycle
assert-qdi-channel-neutral "t.in" 5
system "echo '[2] delay line set'"
set-qdi-channel-valid "t.in" 5 3
set-qdi-channel-valid "t.in" 5 19
cycle
assert-qdi-channel-valid "t.in" 5 3
assert-qdi-channel-valid "t.registers._in_write" 4 3
assert t.registers._clock 0
assert t.registers._out_encoder[0] 1
assert t.registers._out_encoder[1] 0