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prepared things for having unit test ready

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This commit is contained in:
M. Mastella
2022-02-21 13:01:45 +01:00
parent 6dc79383da
commit ca0e5df048
16 changed files with 216 additions and 64 deletions
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3
test/run.sh
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@ -37,8 +37,7 @@ run_test () {
fi
}
if [ ! ( command -v aflat && command -v prsim ) ];
then
if [ ! $(command -v aflat) ]; then #&& ! command -v prsim ]; then
echo "${bold}Error:${bold} aflat & prsim necessary for tests."
exit 1
fi

1
test/unit_tests/async_instantiate/run/prsim.out Normal file
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@ -0,0 +1 @@
cell27._y cell25.c3 cell18._y cell14._y cell27.pr_B cell21.y cell23.c3 cell10._y cell30.p3 cell20.c1 cell10.n1 cell30._y cell12.sr_B cell8.c1 cell16.c2 cell2.p1 cell28.c2 cell5.c1 cell21._y cell19.c2 cell6.p2 cell9.pr_B cell9.p3 cell4.p1 cell28.sr_B cell11.pr_B cell26.c4 cell9.n2 cell27.c2 cell12.c2 cell28.pr_B cell21.pr_B cell22.pr_B cell11.c2 cell13.y cell9.n1 cell1.n1 cell12.c1 cell28.c4 cell1.n2 cell22.sr_B cell26.y cell11.n2 cell13.n4 cell15.rs_B cell6.c1 cell28._y cell2.n2 cell10.pr_B cell16.y cell16.c1 cell11.sr_B cell15._y cell2.pr_B cell11._y cell20.y cell21.c2 cell22.c1 cell27.sr_B cell4.y cell10.n4 cell23.pr_B cell2.sr_B cell6.p1 cell9.p4 cell23._y cell11.c1 cell9.sr_B cell9.c1 cell27.y cell29.c3 cell12.n1 cell1.sr_B cell29.sr_B cell13.n3 cell13.n2 cell11.n4 cell15.n2 cell15.rp_B cell2.y cell3.n1 cell15.c2 cell26.c3 cell24.c2 cell17._y cell28.c1 cell6.n1 cell14.n1 cell31.n1 cell21.c3 cell27.c3 cell19.sr_B cell26._y cell7._y cell20.c2 cell10.n2 cell9.p2 cell14.rs_B cell31.y cell13.pr_B cell31.p1 cell30.n2 cell18.sr_B cell10.y cell6.y cell24.sr_B cell14.n2 cell30.n1 cell22.y cell10.sr_B cell10.n3 cell13.c2 cell13.n1 cell24.y cell12.pr_B cell29.pr_B cell24.c1 cell16.n1 cell24.pr_B cell28.c3 cell17.c2 cell11.n3 cell16.rs_B cell4._y cell14.c1 cell8.p2 cell14.c2 cell8.p1 cell15.n1 cell15.y cell23.c2 cell18.c1 cell7.p2 cell9.y cell7.y cell29.c1 cell30.p1 cell12.n3 cell11.n1 cell26.pr_B cell29.y cell22._y cell13.c1 cell18.y cell7.c1 cell19.y cell27.c4 cell25.c1 cell21.c1 cell30.y cell1.y cell26.c1 cell17.c1 cell2.n1 cell25.y cell5.y cell30.p4 cell31.p3 cell25.c2 cell3.p1 cell9.p5 cell9.p1 cell26.sr_B cell19.c1 cell8.y cell23.c1 cell18.c2 cell7.p1 cell22.c2 cell23.y cell14.rp_B cell30.p2 cell29.c4 cell23.sr_B cell1.c1 cell26.c2 cell3.y cell10.c1 cell16.n2 cell21.sr_B cell24.c3 cell31.p4 cell1.pr_B cell12.n2 cell31.p2 cell11.y cell12.n4 cell12._y cell18.pr_B cell10.c2 cell2.c1 cell5.p1 cell31.n2 cell13.sr_B cell12.y cell27.c1 cell1._y cell14.y cell16.rp_B cell15.c1 cell4.c1 cell29.c2 cell17.y cell19.pr_B cell3.c1 cell22.c3 cell28.y cell1.p1

96
test/unit_tests/async_instantiate/run/test.prs Normal file
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@ -0,0 +1,96 @@
~"cell26.c1"&~"cell26.c2"&~"cell26.c3"&~"cell26.c4"|~"cell26.pr_B"->"cell26._y"+
"cell26.c1"&"cell26.c2"&"cell26.c3"&"cell26.c4"&"cell26.sr_B"->"cell26._y"-
"cell26._y"->"cell26.y"-
~("cell26._y")->"cell26.y"+
~"cell16.c1"&~"cell16.c2"|~"cell16.rp_B"->"cell16.y"+
"cell16.c1"&"cell16.c2"&"cell16.n1"&"cell16.n2"&"cell16.rs_B"->"cell16.y"-
~"cell8.p1"&~"cell8.p2"&~"cell8.c1"->"cell8.y"+
"cell8.c1"->"cell8.y"-
~"cell22.c1"&~"cell22.c2"&~"cell22.c3"|~"cell22.pr_B"->"cell22._y"+
"cell22.c1"&"cell22.c2"&"cell22.c3"&"cell22.sr_B"->"cell22._y"-
"cell22._y"->"cell22.y"-
~("cell22._y")->"cell22.y"+
~"cell19.c1"&~"cell19.c2"|~"cell19.pr_B"->"cell19.y"+
"cell19.c1"&"cell19.c2"&"cell19.sr_B"->"cell19.y"-
~"cell12.c1"&~"cell12.c2"|~"cell12.pr_B"->"cell12._y"+
"cell12.c1"&"cell12.c2"&("cell12.n1"&"cell12.n2"|"cell12.n3"&"cell12.n4")&"cell12.sr_B"->"cell12._y"-
"cell12._y"->"cell12.y"-
~("cell12._y")->"cell12.y"+
~"cell30.p1"&~"cell30.p2"&~"cell30.p3"&~"cell30.p4"->"cell30._y"+
"cell30.n1"|"cell30.n2"->"cell30._y"-
"cell30._y"->"cell30.y"-
~("cell30._y")->"cell30.y"+
~"cell17.c1"&~"cell17.c2"->"cell17._y"+
"cell17.c1"&"cell17.c2"->"cell17._y"-
"cell17._y"->"cell17.y"-
~("cell17._y")->"cell17.y"+
~"cell14.c1"&~"cell14.c2"|~"cell14.rp_B"->"cell14._y"+
"cell14.c1"&"cell14.c2"&"cell14.n1"&"cell14.n2"&"cell14.rs_B"->"cell14._y"-
"cell14._y"->"cell14.y"-
~("cell14._y")->"cell14.y"+
~"cell7.p1"&~"cell7.p2"&~"cell7.c1"->"cell7._y"-
"cell7.c1"->"cell7._y"+
"cell7._y"->"cell7.y"-
~("cell7._y")->"cell7.y"+
~"cell1.p1"&~"cell1.c1"|~"cell1.pr_B"->"cell1._y"+
"cell1.c1"&"cell1.n1"&"cell1.n2"&"cell1.sr_B"->"cell1._y"-
"cell1._y"->"cell1.y"-
~("cell1._y")->"cell1.y"+
~"cell21.c1"&~"cell21.c2"&~"cell21.c3"|~"cell21.pr_B"->"cell21._y"+
"cell21.c1"&"cell21.c2"&"cell21.c3"&"cell21.sr_B"->"cell21._y"-
"cell21._y"->"cell21.y"-
~("cell21._y")->"cell21.y"+
~"cell18.c1"&~"cell18.c2"|~"cell18.pr_B"->"cell18._y"+
"cell18.c1"&"cell18.c2"&"cell18.sr_B"->"cell18._y"-
"cell18._y"->"cell18.y"-
~("cell18._y")->"cell18.y"+
~"cell15.c1"&~"cell15.c2"|~"cell15.rp_B"->"cell15._y"+
"cell15.c1"&"cell15.c2"&"cell15.n1"&"cell15.n2"&"cell15.rs_B"->"cell15._y"-
"cell15._y"->"cell15.y"-
~("cell15._y")->"cell15.y"+
~"cell13.c1"&~"cell13.c2"|~"cell13.pr_B"->"cell13.y"+
"cell13.c1"&"cell13.c2"&("cell13.n1"&"cell13.n2"|"cell13.n3"&"cell13.n4")&"cell13.sr_B"->"cell13.y"-
~"cell11.c1"&~"cell11.c2"|~"cell11.pr_B"->"cell11._y"+
"cell11.c1"&"cell11.c2"&("cell11.n1"&"cell11.n2"|"cell11.n3"&"cell11.n4")&"cell11.sr_B"->"cell11._y"-
"cell11._y"->"cell11.y"-
~("cell11._y")->"cell11.y"+
~"cell28.c1"&~"cell28.c2"&~"cell28.c3"&~"cell28.c4"|~"cell28.pr_B"->"cell28._y"+
"cell28.c1"&"cell28.c2"&"cell28.c3"&"cell28.c4"&"cell28.sr_B"->"cell28._y"-
"cell28._y"->"cell28.y"-
~("cell28._y")->"cell28.y"+
~"cell24.c1"&~"cell24.c2"&~"cell24.c3"|~"cell24.pr_B"->"cell24.y"+
"cell24.c1"&"cell24.c2"&"cell24.c3"&"cell24.sr_B"->"cell24.y"-
~"cell23.c1"&~"cell23.c2"&~"cell23.c3"|~"cell23.pr_B"->"cell23._y"+
"cell23.c1"&"cell23.c2"&"cell23.c3"&"cell23.sr_B"->"cell23._y"-
"cell23._y"->"cell23.y"-
~("cell23._y")->"cell23.y"+
~"cell10.c1"&~"cell10.c2"|~"cell10.pr_B"->"cell10._y"+
"cell10.c1"&"cell10.c2"&("cell10.n1"&"cell10.n2"|"cell10.n3"&"cell10.n4")&"cell10.sr_B"->"cell10._y"-
"cell10._y"->"cell10.y"-
~("cell10._y")->"cell10.y"+
~"cell3.p1"&~"cell3.c1"->"cell3.y"+
"cell3.c1"&"cell3.n1"->"cell3.y"-
~"cell29.c1"&~"cell29.c2"&~"cell29.c3"&~"cell29.c4"|~"cell29.pr_B"->"cell29.y"+
"cell29.c1"&"cell29.c2"&"cell29.c3"&"cell29.c4"&"cell29.sr_B"->"cell29.y"-
~"cell25.c1"&~"cell25.c2"&~"cell25.c3"->"cell25.y"+
"cell25.c1"&"cell25.c2"&"cell25.c3"->"cell25.y"-
~"cell5.p1"&~"cell5.c1"->"cell5.y"+
"cell5.c1"->"cell5.y"-
~"cell4.p1"&~"cell4.c1"->"cell4._y"-
"cell4.c1"->"cell4._y"+
"cell4._y"->"cell4.y"-
~("cell4._y")->"cell4.y"+
~"cell31.p1"&~"cell31.p2"&~"cell31.p3"&~"cell31.p4"->"cell31.y"+
"cell31.n1"|"cell31.n2"->"cell31.y"-
~"cell27.c1"&~"cell27.c2"&~"cell27.c3"&~"cell27.c4"|~"cell27.pr_B"->"cell27._y"+
"cell27.c1"&"cell27.c2"&"cell27.c3"&"cell27.c4"&"cell27.sr_B"->"cell27._y"-
"cell27._y"->"cell27.y"-
~("cell27._y")->"cell27.y"+
~"cell20.c1"&~"cell20.c2"->"cell20.y"+
"cell20.c1"&"cell20.c2"->"cell20.y"-
~"cell9.p1"&~"cell9.p2"&~"cell9.p3"&~"cell9.c1"|~"cell9.p4"&~"cell9.p5"&~"cell9.c1"|~"cell9.pr_B"->"cell9.y"+
"cell9.c1"&"cell9.n1"&"cell9.n2"&"cell9.sr_B"->"cell9.y"-
~"cell6.p1"&~"cell6.p2"&~"cell6.c1"->"cell6.y"+
"cell6.c1"&"cell6.n1"->"cell6.y"-
~"cell2.p1"&~"cell2.c1"|~"cell2.pr_B"->"cell2.y"-
"cell2.c1"&"cell2.n1"&"cell2.n2"&"cell2.sr_B"->"cell2.y"+

60
test/unit_tests/async_instantiate/test.act Normal file
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@ -0,0 +1,60 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_async.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/cell_lib_async.act";
open tmpl::dataflow_neuro;
A_1C1P2N_RB_X1 cell1;
A_1C1P2N_R_X1 cell2;
A_1C1P_1N_X1 cell3;
A_1C1P_B cell4;
A_1C1P cell5;
A_1C2P1N_X1 cell6;
A_1C2P_B_X1 cell7;
A_1C2P cell8;
A_1C3P2P2N_R_X1 cell9;
A_2C2N2N_RB_X1 cell10;
A_2C2N2N_RB_X2 cell11;
A_2C2N2N_RB_X4 cell12;
A_2C2N2N_R_X1 cell13;
A_2C2N_R_B_X2 cell14;
A_2C2N_R_B_X4 cell15;
A_2C2N_R_X1 cell16;
A_2C_B_X1 cell17;
A_2C_RB_X1 cell18;
A_2C_R_X1 cell19;
A_2C_X1 cell20;
A_3C_RB_X1 cell21;
A_3C_RB_X2 cell22;
A_3C_RB_X4 cell23;
A_3C_R_X1 cell24;
A_3C_X1 cell25;
A_4C_RB_X1 cell26;
A_4C_RB_X2 cell27;
A_4C_RB_X4 cell28;
A_4C_R_X1 cell29;
A_4P1N1N_B_X1 cell30;
A_4P1N1N_X1 cell31;

0
test/unit_tests/async_instantiate/test.prsim Normal file
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2
test/unit_tests/fifo3_8bit/test.act
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@ -1,4 +1,4 @@
import template::dataflow_neuro
import tmpl::dataflow_neuro
defproc fifo3_8bit (avMx1of2<8> A; avMx1of2<8> Y)
{

1
test/unit_tests/fifo3_8bit/test.prsim
View File

@ -5,7 +5,6 @@ set t.Y.a 0
cycle
system "echo 'reset completed'"
status X
set Reset 0
mode run
cycle

0
test/unit_tests/init.prs Normal file
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3
test/unit_tests/init_qdi.prsim
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@ -1,11 +1,8 @@
initialize
load-scm "helper.scm"
random
set GND 0
set Vdd 1
mode reset
set Reset 1
cycle
status U