Auto stash before merge of "dev" and "origin/dev"
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@ -8749,51 +8749,51 @@
|
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= "b.demux.in.a" "b.demux.demux.cond.a"
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= "b.demux.in.a" "b.demux.demux.in.a"
|
||||
= "b.demux.in.v" "b.demux.demux.in.v"
|
||||
= "b.demux.in.d.d[7].d[0]" "b.demux.demux.in.d.d[6].f"
|
||||
= "b.demux.in.d.d[7].d[0]" "b.demux.demux.in.d.d[6].d[0]"
|
||||
= "b.demux.in.d.d[7].d[0]" "b.demux.in.d.d[7].f"
|
||||
= "b.demux.in.d.d[7].d[1]" "b.demux.demux.in.d.d[6].t"
|
||||
= "b.demux.in.d.d[7].d[1]" "b.demux.demux.in.d.d[6].d[1]"
|
||||
= "b.demux.in.d.d[7].d[1]" "b.demux.in.d.d[7].t"
|
||||
= "b.demux.in.d.d[6].d[0]" "b.demux.demux.in.d.d[6].f"
|
||||
= "b.demux.in.d.d[6].d[0]" "b.demux.demux.in.d.d[6].d[0]"
|
||||
= "b.demux.in.d.d[6].d[0]" "b.demux.demux.in.d.d[5].f"
|
||||
= "b.demux.in.d.d[6].d[0]" "b.demux.demux.in.d.d[5].d[0]"
|
||||
= "b.demux.in.d.d[6].d[0]" "b.demux.in.d.d[6].f"
|
||||
= "b.demux.in.d.d[6].d[1]" "b.demux.demux.in.d.d[6].t"
|
||||
= "b.demux.in.d.d[6].d[1]" "b.demux.demux.in.d.d[6].d[1]"
|
||||
= "b.demux.in.d.d[6].d[1]" "b.demux.demux.in.d.d[5].t"
|
||||
= "b.demux.in.d.d[6].d[1]" "b.demux.demux.in.d.d[5].d[1]"
|
||||
= "b.demux.in.d.d[6].d[1]" "b.demux.in.d.d[6].t"
|
||||
= "b.demux.in.d.d[5].d[0]" "b.demux.demux.in.d.d[5].f"
|
||||
= "b.demux.in.d.d[5].d[0]" "b.demux.demux.in.d.d[5].d[0]"
|
||||
= "b.demux.in.d.d[5].d[0]" "b.demux.demux.in.d.d[4].f"
|
||||
= "b.demux.in.d.d[5].d[0]" "b.demux.demux.in.d.d[4].d[0]"
|
||||
= "b.demux.in.d.d[5].d[0]" "b.demux.in.d.d[5].f"
|
||||
= "b.demux.in.d.d[5].d[1]" "b.demux.demux.in.d.d[5].t"
|
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= "b.demux.in.d.d[5].d[1]" "b.demux.demux.in.d.d[5].d[1]"
|
||||
= "b.demux.in.d.d[5].d[1]" "b.demux.demux.in.d.d[4].t"
|
||||
= "b.demux.in.d.d[5].d[1]" "b.demux.demux.in.d.d[4].d[1]"
|
||||
= "b.demux.in.d.d[5].d[1]" "b.demux.in.d.d[5].t"
|
||||
= "b.demux.in.d.d[4].d[0]" "b.demux.demux.in.d.d[4].f"
|
||||
= "b.demux.in.d.d[4].d[0]" "b.demux.demux.in.d.d[4].d[0]"
|
||||
= "b.demux.in.d.d[4].d[0]" "b.demux.demux.in.d.d[3].f"
|
||||
= "b.demux.in.d.d[4].d[0]" "b.demux.demux.in.d.d[3].d[0]"
|
||||
= "b.demux.in.d.d[4].d[0]" "b.demux.in.d.d[4].f"
|
||||
= "b.demux.in.d.d[4].d[1]" "b.demux.demux.in.d.d[4].t"
|
||||
= "b.demux.in.d.d[4].d[1]" "b.demux.demux.in.d.d[4].d[1]"
|
||||
= "b.demux.in.d.d[4].d[1]" "b.demux.demux.in.d.d[3].t"
|
||||
= "b.demux.in.d.d[4].d[1]" "b.demux.demux.in.d.d[3].d[1]"
|
||||
= "b.demux.in.d.d[4].d[1]" "b.demux.in.d.d[4].t"
|
||||
= "b.demux.in.d.d[3].d[0]" "b.demux.demux.in.d.d[3].f"
|
||||
= "b.demux.in.d.d[3].d[0]" "b.demux.demux.in.d.d[3].d[0]"
|
||||
= "b.demux.in.d.d[3].d[0]" "b.demux.demux.in.d.d[2].f"
|
||||
= "b.demux.in.d.d[3].d[0]" "b.demux.demux.in.d.d[2].d[0]"
|
||||
= "b.demux.in.d.d[3].d[0]" "b.demux.in.d.d[3].f"
|
||||
= "b.demux.in.d.d[3].d[1]" "b.demux.demux.in.d.d[3].t"
|
||||
= "b.demux.in.d.d[3].d[1]" "b.demux.demux.in.d.d[3].d[1]"
|
||||
= "b.demux.in.d.d[3].d[1]" "b.demux.demux.in.d.d[2].t"
|
||||
= "b.demux.in.d.d[3].d[1]" "b.demux.demux.in.d.d[2].d[1]"
|
||||
= "b.demux.in.d.d[3].d[1]" "b.demux.in.d.d[3].t"
|
||||
= "b.demux.in.d.d[2].d[0]" "b.demux.demux.in.d.d[2].f"
|
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= "b.demux.in.d.d[2].d[0]" "b.demux.demux.in.d.d[2].d[0]"
|
||||
= "b.demux.in.d.d[2].d[0]" "b.demux.demux.in.d.d[1].f"
|
||||
= "b.demux.in.d.d[2].d[0]" "b.demux.demux.in.d.d[1].d[0]"
|
||||
= "b.demux.in.d.d[2].d[0]" "b.demux.in.d.d[2].f"
|
||||
= "b.demux.in.d.d[2].d[1]" "b.demux.demux.in.d.d[2].t"
|
||||
= "b.demux.in.d.d[2].d[1]" "b.demux.demux.in.d.d[2].d[1]"
|
||||
= "b.demux.in.d.d[2].d[1]" "b.demux.demux.in.d.d[1].t"
|
||||
= "b.demux.in.d.d[2].d[1]" "b.demux.demux.in.d.d[1].d[1]"
|
||||
= "b.demux.in.d.d[2].d[1]" "b.demux.in.d.d[2].t"
|
||||
= "b.demux.in.d.d[1].d[0]" "b.demux.demux.in.d.d[1].f"
|
||||
= "b.demux.in.d.d[1].d[0]" "b.demux.demux.in.d.d[1].d[0]"
|
||||
= "b.demux.in.d.d[1].d[0]" "b.demux.demux.in.d.d[0].f"
|
||||
= "b.demux.in.d.d[1].d[0]" "b.demux.demux.in.d.d[0].d[0]"
|
||||
= "b.demux.in.d.d[1].d[0]" "b.demux.in.d.d[1].f"
|
||||
= "b.demux.in.d.d[1].d[1]" "b.demux.demux.in.d.d[1].t"
|
||||
= "b.demux.in.d.d[1].d[1]" "b.demux.demux.in.d.d[1].d[1]"
|
||||
= "b.demux.in.d.d[1].d[1]" "b.demux.demux.in.d.d[0].t"
|
||||
= "b.demux.in.d.d[1].d[1]" "b.demux.demux.in.d.d[0].d[1]"
|
||||
= "b.demux.in.d.d[1].d[1]" "b.demux.in.d.d[1].t"
|
||||
= "b.demux.in.d.d[0].d[0]" "b.demux.demux.in.d.d[0].f"
|
||||
= "b.demux.in.d.d[0].d[0]" "b.demux.demux.in.d.d[0].d[0]"
|
||||
= "b.demux.in.d.d[0].d[0]" "b.demux.demux.cond.d.d[0].f"
|
||||
= "b.demux.in.d.d[0].d[0]" "b.demux.demux.cond.d.d[0].d[0]"
|
||||
= "b.demux.in.d.d[0].d[0]" "b.demux.in.d.d[0].f"
|
||||
= "b.demux.in.d.d[0].d[1]" "b.demux.demux.in.d.d[0].t"
|
||||
= "b.demux.in.d.d[0].d[1]" "b.demux.demux.in.d.d[0].d[1]"
|
||||
= "b.demux.in.d.d[0].d[1]" "b.demux.demux.cond.d.d[0].t"
|
||||
= "b.demux.in.d.d[0].d[1]" "b.demux.demux.cond.d.d[0].d[1]"
|
||||
= "b.demux.in.d.d[0].d[1]" "b.demux.in.d.d[0].t"
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@ -59,6 +59,7 @@ assert b.in.v 1
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assert b.in.a 1
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assert-qdi-channel-valid "b.out2" 7 100
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assert-qdi-channel-neutral "b.out1" 7
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set b.out2.v 1
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cycle
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assert b.in.a 1
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204
test/unit_tests/nrn_hs_2d.v
Normal file
204
test/unit_tests/nrn_hs_2d.v
Normal file
@ -0,0 +1,204 @@
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//
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// Verilog module for: INV_X1<>
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//
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module _0_0tmpl_0_0dataflow__neuro_0_0INV__X1(y, a);
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output y;
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input a;
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// -- signals ---
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reg y;
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wire a;
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// --- instances
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endmodule
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//
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// Verilog module for: A_2P_U_X4<>
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//
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module _0_0tmpl_0_0dataflow__neuro_0_0A__2P__U__X4(p1, p2, y);
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input p1;
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input p2;
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output y;
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// -- signals ---
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reg y;
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wire p2;
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wire p1;
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// --- instances
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endmodule
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//
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// Verilog module for: INV_X2<>
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//
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module _0_0tmpl_0_0dataflow__neuro_0_0INV__X2(y, a);
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output y;
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input a;
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// -- signals ---
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reg y;
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wire a;
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// --- instances
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endmodule
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//
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// Verilog module for: A_2C1N_RB_X1<>
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//
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module _0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X1(y, c1, c2, n1, pr_B, sr_B);
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output y;
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input c1;
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input c2;
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input n1;
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input pr_B;
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input sr_B;
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|
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// -- signals ---
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wire sr_B;
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reg y;
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wire c2;
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wire c1;
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reg _y;
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wire pr_B;
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wire n1;
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||||
// --- instances
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||||
endmodule
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|
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//
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// Verilog module for: BUF_X2<>
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//
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module _0_0tmpl_0_0dataflow__neuro_0_0BUF__X2(y, a);
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output y;
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input a;
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// -- signals ---
|
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reg y;
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reg _y;
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wire a;
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// --- instances
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||||
endmodule
|
||||
|
||||
//
|
||||
// Verilog module for: A_1C1P_X1<>
|
||||
//
|
||||
module _0_0tmpl_0_0dataflow__neuro_0_0A__1C1P__X1(y, c1, p1);
|
||||
output y;
|
||||
input c1;
|
||||
input p1;
|
||||
|
||||
// -- signals ---
|
||||
wire c1;
|
||||
wire p1;
|
||||
reg y;
|
||||
|
||||
// --- instances
|
||||
endmodule
|
||||
|
||||
//
|
||||
// Verilog module for: A_2C1P1N_RB_X1<>
|
||||
//
|
||||
module _0_0tmpl_0_0dataflow__neuro_0_0A__2C1P1N__RB__X1(y, c1, c2, p1, n1, pr_B, sr_B);
|
||||
output y;
|
||||
input c1;
|
||||
input c2;
|
||||
input p1;
|
||||
input n1;
|
||||
input pr_B;
|
||||
input sr_B;
|
||||
|
||||
// -- signals ---
|
||||
wire sr_B;
|
||||
wire n1;
|
||||
wire p1;
|
||||
wire c2;
|
||||
reg y;
|
||||
wire c1;
|
||||
reg _y;
|
||||
wire pr_B;
|
||||
|
||||
// --- instances
|
||||
endmodule
|
||||
|
||||
//
|
||||
// Verilog module for: A_3P_U_X4<>
|
||||
//
|
||||
module _0_0tmpl_0_0dataflow__neuro_0_0A__3P__U__X4(p1, p2, p3, y);
|
||||
input p1;
|
||||
input p2;
|
||||
input p3;
|
||||
output y;
|
||||
|
||||
// -- signals ---
|
||||
wire p2;
|
||||
wire p3;
|
||||
wire p1;
|
||||
reg y;
|
||||
|
||||
// --- instances
|
||||
endmodule
|
||||
|
||||
//
|
||||
// Verilog module for: nrn_hs_2d<>
|
||||
//
|
||||
module _0_0tmpl_0_0dataflow__neuro_0_0nrn__hs__2d(\in.d.d[0] , \in.a , \outx.d.d[0] , \outx.a , \outy.d.d[0] , \outy.a , reset_B);
|
||||
input \in.d.d[0] ;
|
||||
output \in.a ;
|
||||
output \outx.d.d[0] ;
|
||||
input \outx.a ;
|
||||
output \outy.d.d[0] ;
|
||||
input \outy.a ;
|
||||
input reset_B;
|
||||
|
||||
// -- signals ---
|
||||
reg \outx.d.d[0] ;
|
||||
reg \in.a ;
|
||||
reg _reqB;
|
||||
reg \outy.d.d[0] ;
|
||||
wire reset_B;
|
||||
reg _y_a_B;
|
||||
wire \outy.a ;
|
||||
reg _x_a_B;
|
||||
reg _reset_BX;
|
||||
wire \in.d.d[0] ;
|
||||
wire \outx.a ;
|
||||
reg _en;
|
||||
reg _req;
|
||||
|
||||
// --- instances
|
||||
_0_0tmpl_0_0dataflow__neuro_0_0INV__X1 \req_inv (.y(_reqB), .a(_req));
|
||||
_0_0tmpl_0_0dataflow__neuro_0_0A__2P__U__X4 \pu_y (.p1(_reqB), .p2(\outy.a ), .y(\outy.d.d[0] ));
|
||||
_0_0tmpl_0_0dataflow__neuro_0_0INV__X2 \inv_x (.y(_x_a_B), .a(\outx.a ));
|
||||
_0_0tmpl_0_0dataflow__neuro_0_0INV__X2 \inv_y (.y(_y_a_B), .a(\outy.a ));
|
||||
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X1 \A_ack (.y(\in.a ), .c1(_en), .c2(\in.d.d[0] ), .n1(_req), .pr_B(_reset_BX), .sr_B(_reset_BX));
|
||||
_0_0tmpl_0_0dataflow__neuro_0_0BUF__X2 \reset_buf (.y(_reset_BX), .a(reset_B));
|
||||
_0_0tmpl_0_0dataflow__neuro_0_0A__1C1P__X1 \A_en (.y(_en), .c1(\in.a ), .p1(_req));
|
||||
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1P1N__RB__X1 \A_req (.y(_req), .c1(_en), .c2(_y_a_B), .p1(_x_a_B), .n1(\in.d.d[0] ), .pr_B(_reset_BX), .sr_B(_reset_BX));
|
||||
_0_0tmpl_0_0dataflow__neuro_0_0A__3P__U__X4 \pu_x (.p1(\outx.a ), .p2(_reqB), .p3(_y_a_B), .y(\outx.d.d[0] ));
|
||||
endmodule
|
||||
|
||||
//
|
||||
// Verilog module for: nrn_hs_2d_inst<>
|
||||
//
|
||||
module nrn__hs__2d__inst(\in.d.d[0] , \in.a , \outx.d.d[0] , \outx.a , \outy.d.d[0] , \outy.a );
|
||||
input \in.d.d[0] ;
|
||||
output \in.a ;
|
||||
output \outx.d.d[0] ;
|
||||
input \outx.a ;
|
||||
output \outy.d.d[0] ;
|
||||
input \outy.a ;
|
||||
|
||||
// -- signals ---
|
||||
reg \outx.d.d[0] ;
|
||||
wire \outy.a ;
|
||||
wire \in.d.d[0] ;
|
||||
reg \outy.d.d[0] ;
|
||||
reg _reset_B;
|
||||
wire \outx.a ;
|
||||
reg \in.a ;
|
||||
|
||||
// --- instances
|
||||
_0_0tmpl_0_0dataflow__neuro_0_0nrn__hs__2d \b (.\in.d.d[0] (\in.d.d[0] ), .\in.a (\in.a ), .\outx.d.d[0] (\outx.d.d[0] ), .\outx.a (\outx.a ), .\outy.d.d[0] (\outy.d.d[0] ), .\outy.a (\outy.a ), .reset_B(_reset_B));
|
||||
endmodule
|
||||
|
||||
746
test/unit_tests/nrn_hs_2d/run/prsim.out
Normal file
746
test/unit_tests/nrn_hs_2d/run/prsim.out
Normal file
File diff suppressed because one or more lines are too long
BIN
test/unit_tests/nrn_hs_2d/run/prsim.pdf
Normal file
BIN
test/unit_tests/nrn_hs_2d/run/prsim.pdf
Normal file
Binary file not shown.
2508
test/unit_tests/nrn_hs_2d/run/test.prs
Normal file
2508
test/unit_tests/nrn_hs_2d/run/test.prs
Normal file
File diff suppressed because it is too large
Load Diff
46
test/unit_tests/nrn_hs_2d/test.act
Normal file
46
test/unit_tests/nrn_hs_2d/test.act
Normal file
@ -0,0 +1,46 @@
|
||||
/*************************************************************************
|
||||
*
|
||||
* This file is part of ACT dataflow neuro library.
|
||||
* It's the testing facility for cell_lib_std.act
|
||||
*
|
||||
* Copyright (c) 2022 University of Groningen - Ole Richter
|
||||
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
|
||||
* Copyright (c) 2022 University of Groningen - Michele Mastella
|
||||
* Copyright (c) 2022 University of Groningen - Madison Cotteret
|
||||
*
|
||||
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
|
||||
*
|
||||
* You may redistribute and modify this documentation and make products
|
||||
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
|
||||
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
|
||||
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
|
||||
* for applicable conditions.
|
||||
*
|
||||
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
|
||||
*
|
||||
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
|
||||
* these sources, You must maintain the Source Location visible in its
|
||||
* documentation.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
import "../../dataflow_neuro/coders.act";
|
||||
import globals;
|
||||
|
||||
open tmpl::dataflow_neuro;
|
||||
|
||||
defproc nrn_hs_2d_inst(a1of1 in; a1of1 outx, outy)
|
||||
{
|
||||
bool _reset_B;
|
||||
prs {
|
||||
Reset => _reset_B-
|
||||
}
|
||||
nrn_hs_2d b(.in = in, .outx = outx, .outy = outy);
|
||||
b.supply.vdd = Vdd;
|
||||
b.supply.vss = GND;
|
||||
b.reset_B = _reset_B;
|
||||
}
|
||||
|
||||
nrn_hs_2d_inst b;
|
||||
202
test/unit_tests/nrn_hs_2d/test.prsim
Normal file
202
test/unit_tests/nrn_hs_2d/test.prsim
Normal file
@ -0,0 +1,202 @@
|
||||
watchall
|
||||
|
||||
set b.in[0].r 0
|
||||
set b.in[1].r 0
|
||||
set b.in[2].r 0
|
||||
set b.in[3].r 0
|
||||
set b.in[4].r 0
|
||||
set b.in[5].r 0
|
||||
set b.in[6].r 0
|
||||
set b.in[7].r 0
|
||||
set b.in[8].r 0
|
||||
set b.in[9].r 0
|
||||
set b.in[10].r 0
|
||||
set b.in[11].r 0
|
||||
set b.in[12].r 0
|
||||
set b.in[13].r 0
|
||||
set b.in[14].r 0
|
||||
|
||||
set b.outx[0].a 0
|
||||
set b.outx[1].a 0
|
||||
set b.outx[2].a 0
|
||||
|
||||
set b.outy[0].a 0
|
||||
set b.outy[1].a 0
|
||||
set b.outy[2].a 0
|
||||
set b.outy[3].a 0
|
||||
set b.outy[4].a 0
|
||||
|
||||
set b.outx[0].r 1
|
||||
set b.outx[1].r 1
|
||||
set b.outx[2].r 1
|
||||
|
||||
set b.outy[0].r 1
|
||||
set b.outy[1].r 1
|
||||
set b.outy[2].r 1
|
||||
set b.outy[3].r 1
|
||||
set b.outy[4].r 0
|
||||
|
||||
set b.b.neurons[0]._en 0
|
||||
set b.b.neurons[0]._req 1
|
||||
|
||||
# set Reset 0
|
||||
cycle
|
||||
|
||||
system "echo '[] set Reset 1'"
|
||||
set Reset 1
|
||||
cycle
|
||||
status X
|
||||
|
||||
|
||||
system "echo '[] set Reset 0'"
|
||||
set Reset 0
|
||||
mode run
|
||||
cycle
|
||||
|
||||
assert b.outx[0].r 0
|
||||
assert b.outx[1].r 0
|
||||
assert b.outx[2].r 0
|
||||
|
||||
assert b.outy[0].r 0
|
||||
assert b.outy[1].r 0
|
||||
assert b.outy[2].r 0
|
||||
assert b.outy[3].r 0
|
||||
assert b.outy[4].r 0
|
||||
|
||||
|
||||
system "echo '[] Neurons 0,1,3 spike'"
|
||||
set b.in[0].r 1
|
||||
set b.in[1].r 1
|
||||
set b.in[3].r 1
|
||||
cycle
|
||||
assert b.outx[0].r 0
|
||||
assert b.outx[1].r 0
|
||||
assert b.outx[2].r 0
|
||||
|
||||
assert b.outy[0].r 1
|
||||
assert b.outy[1].r 1
|
||||
assert b.outy[2].r 0
|
||||
assert b.outy[3].r 0
|
||||
assert b.outy[4].r 0
|
||||
|
||||
assert b.in[0].a 1
|
||||
assert b.in[1].a 1
|
||||
assert b.in[3].a 1
|
||||
|
||||
system "echo '[] removing in reqs'"
|
||||
set b.in[0].r 0
|
||||
set b.in[1].r 0
|
||||
set b.in[3].r 0
|
||||
cycle
|
||||
assert b.in[0].a 0
|
||||
assert b.in[1].a 0
|
||||
assert b.in[3].a 0
|
||||
|
||||
|
||||
system "echo '[] y0 chosen, give ack'"
|
||||
set b.outy[0].a 1
|
||||
cycle
|
||||
assert b.outx[0].r 1
|
||||
assert b.outx[1].r 1
|
||||
assert b.outx[2].r 0
|
||||
|
||||
assert b.outy[0].r 0
|
||||
assert b.outy[1].r 1
|
||||
assert b.outy[2].r 0
|
||||
assert b.outy[3].r 0
|
||||
assert b.outy[4].r 0
|
||||
|
||||
system "echo '[] x0 chosen, give ack'"
|
||||
set b.outx[0].a 1
|
||||
cycle
|
||||
assert b.outx[0].r 0
|
||||
assert b.outx[1].r 1
|
||||
assert b.outx[2].r 0
|
||||
|
||||
assert b.outy[0].r 0
|
||||
assert b.outy[1].r 1
|
||||
assert b.outy[2].r 0
|
||||
assert b.outy[3].r 0
|
||||
assert b.outy[4].r 0
|
||||
|
||||
system "echo '[] remove x ack'"
|
||||
set b.outx[0].a 0
|
||||
cycle
|
||||
assert b.outx[0].r 0
|
||||
assert b.outx[1].r 1
|
||||
assert b.outx[2].r 0
|
||||
|
||||
assert b.outy[0].r 0
|
||||
assert b.outy[1].r 1
|
||||
assert b.outy[2].r 0
|
||||
assert b.outy[3].r 0
|
||||
assert b.outy[4].r 0
|
||||
|
||||
system "echo '[] x1 remaining, give ack'"
|
||||
set b.outx[1].a 1
|
||||
cycle
|
||||
assert b.outx[0].r 0
|
||||
assert b.outx[1].r 0
|
||||
assert b.outx[2].r 0
|
||||
|
||||
assert b.outy[0].r 0
|
||||
assert b.outy[1].r 1
|
||||
assert b.outy[2].r 0
|
||||
assert b.outy[3].r 0
|
||||
assert b.outy[4].r 0
|
||||
|
||||
system "echo '[] remove acks'"
|
||||
set b.outx[1].a 0
|
||||
set b.outy[0].a 0
|
||||
cycle
|
||||
assert b.outx[0].r 0
|
||||
assert b.outx[1].r 0
|
||||
assert b.outx[2].r 0
|
||||
|
||||
assert b.outy[0].r 0
|
||||
assert b.outy[1].r 1
|
||||
assert b.outy[2].r 0
|
||||
assert b.outy[3].r 0
|
||||
assert b.outy[4].r 0
|
||||
|
||||
system "echo '[] y1 remaining, give ack'"
|
||||
set b.outy[1].a 1
|
||||
cycle
|
||||
assert b.outx[0].r 1
|
||||
assert b.outx[1].r 0
|
||||
assert b.outx[2].r 0
|
||||
|
||||
assert b.outy[0].r 0
|
||||
assert b.outy[1].r 0
|
||||
assert b.outy[2].r 0
|
||||
assert b.outy[3].r 0
|
||||
assert b.outy[4].r 0
|
||||
|
||||
system "echo '[] x0 req, give ack'"
|
||||
set b.outx[0].a 1
|
||||
cycle
|
||||
assert b.outx[0].r 0
|
||||
assert b.outx[1].r 0
|
||||
assert b.outx[2].r 0
|
||||
|
||||
assert b.outy[0].r 0
|
||||
assert b.outy[1].r 0
|
||||
assert b.outy[2].r 0
|
||||
assert b.outy[3].r 0
|
||||
assert b.outy[4].r 0
|
||||
|
||||
|
||||
system "echo '[] remove acks'"
|
||||
set b.outx[0].a 0
|
||||
set b.outy[1].a 0
|
||||
cycle
|
||||
assert b.outx[0].r 0
|
||||
assert b.outx[1].r 0
|
||||
assert b.outx[2].r 0
|
||||
|
||||
assert b.outy[0].r 0
|
||||
assert b.outy[1].r 0
|
||||
assert b.outy[2].r 0
|
||||
assert b.outy[3].r 0
|
||||
assert b.outy[4].r 0
|
||||
|
||||
107
test/unit_tests/nrn_hs_2d_clean.v
Normal file
107
test/unit_tests/nrn_hs_2d_clean.v
Normal file
@ -0,0 +1,107 @@
|
||||
//
|
||||
// Verilog module for: INV_X1<>
|
||||
//
|
||||
|
||||
|
||||
//
|
||||
// Verilog module for: A_2P_U_X4<>
|
||||
//
|
||||
|
||||
|
||||
//
|
||||
// Verilog module for: INV_X2<>
|
||||
//
|
||||
|
||||
|
||||
//
|
||||
// Verilog module for: A_2C1N_RB_X1<>
|
||||
//
|
||||
|
||||
|
||||
//
|
||||
// Verilog module for: BUF_X2<>
|
||||
//
|
||||
|
||||
|
||||
//
|
||||
// Verilog module for: A_1C1P_X1<>
|
||||
//
|
||||
|
||||
|
||||
//
|
||||
// Verilog module for: A_2C1P1N_RB_X1<>
|
||||
//
|
||||
|
||||
|
||||
//
|
||||
// Verilog module for: A_3P_U_X4<>
|
||||
//
|
||||
|
||||
|
||||
//
|
||||
// Verilog module for: nrn_hs_2d<>
|
||||
//
|
||||
module _0_0tmpl_0_0dataflow__neuro_0_0nrn__hs__2d(\in.d.d[0] , \in.a , \outx.d.d[0] , \outx.a , \outy.d.d[0] , \outy.a , reset_B, vdd, vss);
|
||||
input vdd;
|
||||
input vss;
|
||||
input \in.d.d[0] ;
|
||||
output \in.a ;
|
||||
output \outx.d.d[0] ;
|
||||
input \outx.a ;
|
||||
output \outy.d.d[0] ;
|
||||
input \outy.a ;
|
||||
input reset_B;
|
||||
|
||||
// -- signals ---
|
||||
reg \outx.d.d[0] ;
|
||||
reg \in.a ;
|
||||
reg _reqB;
|
||||
reg \outy.d.d[0] ;
|
||||
wire reset_B;
|
||||
reg _y_a_B;
|
||||
wire \outy.a ;
|
||||
reg _x_a_B;
|
||||
reg _reset_BX;
|
||||
wire \in.d.d[0] ;
|
||||
wire \outx.a ;
|
||||
reg _en;
|
||||
reg _req;
|
||||
|
||||
// --- instances
|
||||
INV_X1 \req_inv (.y(_reqB), .a(_req), .vdd(vdd), .vss(vss));
|
||||
A_2P_U_X4 \pu_y (.p1(_reqB), .p2(\outy.a ), .y(\outy.d.d[0] ), .vdd(vdd), .vss(vss));
|
||||
INV_X2 \inv_x (.y(_x_a_B), .a(\outx.a ), .vdd(vdd), .vss(vss));
|
||||
INV_X2 \inv_y (.y(_y_a_B), .a(\outy.a ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X1 \A_ack (.y(\in.a ), .c1(_en), .c2(\in.d.d[0] ), .n1(_req), .pr_B(_reset_BX), .sr_B(_reset_BX), .vdd(vdd), .vss(vss));
|
||||
BUF_X2 \reset_buf (.y(_reset_BX), .a(reset_B), .vdd(vdd), .vss(vss));
|
||||
A_1C1P_X1 \A_en (.y(_en), .c1(\in.a ), .p1(_req), .vdd(vdd), .vss(vss));
|
||||
A_2C1P1N_RB_X1 \A_req (.y(_req), .c1(_en), .c2(_y_a_B), .p1(_x_a_B), .n1(\in.d.d[0] ), .pr_B(_reset_BX), .sr_B(_reset_BX), .vdd(vdd), .vss(vss));
|
||||
A_3P_U_X4 \pu_x (.p1(\outx.a ), .p2(_reqB), .p3(_y_a_B), .y(\outx.d.d[0] ), .vdd(vdd), .vss(vss));
|
||||
endmodule
|
||||
|
||||
//
|
||||
// Verilog module for: nrn_hs_2d_inst<>
|
||||
//
|
||||
module nrn__hs__2d__inst(\in.d.d[0] , \in.a , \outx.d.d[0] , \outx.a , \outy.d.d[0] , \outy.a , vdd, vss);
|
||||
input vdd;
|
||||
input vss;
|
||||
input \in.d.d[0] ;
|
||||
output \in.a ;
|
||||
output \outx.d.d[0] ;
|
||||
input \outx.a ;
|
||||
output \outy.d.d[0] ;
|
||||
input \outy.a ;
|
||||
|
||||
// -- signals ---
|
||||
reg \outx.d.d[0] ;
|
||||
wire \outy.a ;
|
||||
wire \in.d.d[0] ;
|
||||
reg \outy.d.d[0] ;
|
||||
reg _reset_B;
|
||||
wire \outx.a ;
|
||||
reg \in.a ;
|
||||
|
||||
// --- instances
|
||||
_0_0tmpl_0_0dataflow__neuro_0_0nrn__hs__2d \b (.\in.d.d[0] (\in.d.d[0] ), .\in.a (\in.a ), .\outx.d.d[0] (\outx.d.d[0] ), .\outx.a (\outx.a ), .\outy.d.d[0] (\outy.d.d[0] ), .\outy.a (\outy.a ), .reset_B(_reset_B), .vdd(vdd), .vss(vss));
|
||||
endmodule
|
||||
|
||||
3706
test/unit_tests/texel_small.net
Normal file
3706
test/unit_tests/texel_small.net
Normal file
File diff suppressed because one or more lines are too long
3617
test/unit_tests/texel_small.v
Normal file
3617
test/unit_tests/texel_small.v
Normal file
File diff suppressed because one or more lines are too long
@ -39,12 +39,11 @@ open std::data;
|
||||
open tmpl::dataflow_neuro;
|
||||
|
||||
defproc chip_texel_test (bd<14> in; bd<14> out; Mx1of2<8> reg_data[16];
|
||||
bool? bd_dly_cfg[4], bd_dly_cfg2[2], loopback_en){
|
||||
bool? bd_dly_cfg[4], bd_dly_cfg2[2], loopback_en, _reset_B){
|
||||
|
||||
bool _reset_B;
|
||||
prs {
|
||||
Reset => _reset_B-
|
||||
}
|
||||
// prs {
|
||||
// Reset => _reset_B-
|
||||
// }
|
||||
power supply;
|
||||
supply.vdd = Vdd;
|
||||
supply.vss = GND;
|
||||
@ -121,4 +120,4 @@ defproc chip_texel_test (bd<14> in; bd<14> out; Mx1of2<8> reg_data[16];
|
||||
|
||||
|
||||
// fifo_decoder_neurons_encoder_fifo e;
|
||||
chip_texel_test c;
|
||||
chip_texel_test c;
|
||||
|
||||
9498
test/unit_tests/texel_small_clean.v
Normal file
9498
test/unit_tests/texel_small_clean.v
Normal file
File diff suppressed because one or more lines are too long
Reference in New Issue
Block a user