bics/actlib_dataflow_neuro
23
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

Auto stash before merge of "dev" and "origin/dev"

Browse Source
This commit is contained in:
Greatorex
2022-04-15 12:48:50 +02:00
parent c41d7f4fdf
commit cd1947a2ce
16 changed files with 23323 additions and 3028 deletions
Download Patch File Download Diff File Expand all files Collapse all files

107
test/unit_tests/nrn_hs_2d_clean.v Normal file
View File

@@ -0,0 +1,107 @@
//
// Verilog module for: INV_X1<>
//
//
// Verilog module for: A_2P_U_X4<>
//
//
// Verilog module for: INV_X2<>
//
//
// Verilog module for: A_2C1N_RB_X1<>
//
//
// Verilog module for: BUF_X2<>
//
//
// Verilog module for: A_1C1P_X1<>
//
//
// Verilog module for: A_2C1P1N_RB_X1<>
//
//
// Verilog module for: A_3P_U_X4<>
//
//
// Verilog module for: nrn_hs_2d<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0nrn__hs__2d(\in.d.d[0] , \in.a , \outx.d.d[0] , \outx.a , \outy.d.d[0] , \outy.a , reset_B, vdd, vss);
input vdd;
input vss;
input \in.d.d[0] ;
output \in.a ;
output \outx.d.d[0] ;
input \outx.a ;
output \outy.d.d[0] ;
input \outy.a ;
input reset_B;
// -- signals ---
reg \outx.d.d[0] ;
reg \in.a ;
reg _reqB;
reg \outy.d.d[0] ;
wire reset_B;
reg _y_a_B;
wire \outy.a ;
reg _x_a_B;
reg _reset_BX;
wire \in.d.d[0] ;
wire \outx.a ;
reg _en;
reg _req;
// --- instances
INV_X1 \req_inv (.y(_reqB), .a(_req), .vdd(vdd), .vss(vss));
A_2P_U_X4 \pu_y (.p1(_reqB), .p2(\outy.a ), .y(\outy.d.d[0] ), .vdd(vdd), .vss(vss));
INV_X2 \inv_x (.y(_x_a_B), .a(\outx.a ), .vdd(vdd), .vss(vss));
INV_X2 \inv_y (.y(_y_a_B), .a(\outy.a ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X1 \A_ack (.y(\in.a ), .c1(_en), .c2(\in.d.d[0] ), .n1(_req), .pr_B(_reset_BX), .sr_B(_reset_BX), .vdd(vdd), .vss(vss));
BUF_X2 \reset_buf (.y(_reset_BX), .a(reset_B), .vdd(vdd), .vss(vss));
A_1C1P_X1 \A_en (.y(_en), .c1(\in.a ), .p1(_req), .vdd(vdd), .vss(vss));
A_2C1P1N_RB_X1 \A_req (.y(_req), .c1(_en), .c2(_y_a_B), .p1(_x_a_B), .n1(\in.d.d[0] ), .pr_B(_reset_BX), .sr_B(_reset_BX), .vdd(vdd), .vss(vss));
A_3P_U_X4 \pu_x (.p1(\outx.a ), .p2(_reqB), .p3(_y_a_B), .y(\outx.d.d[0] ), .vdd(vdd), .vss(vss));
endmodule
//
// Verilog module for: nrn_hs_2d_inst<>
//
module nrn__hs__2d__inst(\in.d.d[0] , \in.a , \outx.d.d[0] , \outx.a , \outy.d.d[0] , \outy.a , vdd, vss);
input vdd;
input vss;
input \in.d.d[0] ;
output \in.a ;
output \outx.d.d[0] ;
input \outx.a ;
output \outy.d.d[0] ;
input \outy.a ;
// -- signals ---
reg \outx.d.d[0] ;
wire \outy.a ;
wire \in.d.d[0] ;
reg \outy.d.d[0] ;
reg _reset_B;
wire \outx.a ;
reg \in.a ;
// --- instances
_0_0tmpl_0_0dataflow__neuro_0_0nrn__hs__2d \b (.\in.d.d[0] (\in.d.d[0] ), .\in.a (\in.a ), .\outx.d.d[0] (\outx.d.d[0] ), .\outx.a (\outx.a ), .\outy.d.d[0] (\outy.d.d[0] ), .\outy.a (\outy.a ), .reset_B(_reset_B), .vdd(vdd), .vss(vss));
endmodule