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Greatorex 2022-04-15 12:48:50 +02:00
parent c41d7f4fdf
commit cd1947a2ce
16 changed files with 23323 additions and 3028 deletions
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501
dataflow_neuro/cell_lib_std.act
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@ -1,427 +1,80 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library
*
* Copyright (c) 2020-2021 Rajit Manohar
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
namespace tmpl {
namespace dataflow_neuro {
export defproc TIELO_X1(bool! y; bool vdd, vss)
{
y = vss;
}
export defproc TIEHI_X1(bool! y; bool vdd, vss)
{
y = vdd;
}
/*-- inverters --*/
defproc inv (bool! y; bool? a, vdd, vss)
{
prs {
a => y-
}
}
template<pint nf>
defproc szinv <: inv()
{
[nf = 0 -> sizing { y {-1} }
[] else -> sizing { y {-2*nf,svt,nf} }
]
}
export defcell INV_X1<: szinv<0>() { }
export defcell INV_X2<: szinv<1>() { }
export defcell INV_X4<: szinv<2>() { }
export defcell INV_X8<: szinv<4>() { }
/*-- signal buffers --*/
defproc buf (bool! y; bool? a, vdd, vss)
{
bool _y;
prs {
a => _y-
_y => y-
}
}
export defcell BUF_X1<: buf()
{
sizing { _y {-1}; y {-1} }
}
export defcell BUF_X2<: buf()
{
sizing { _y {-1}; y {-2} }
}
export defcell BUF_X3<: buf()
{
sizing { _y {-1.5}; y {-3} }
}
export defcell BUF_X4<: buf()
{
sizing { _y {-1.5}; y {-4,2} }
}
export defcell BUF_X6<: buf()
{
sizing { _y {-3}; y {-6,2} }
}
export defcell BUF_X8<: buf()
{
sizing { _y {-4,2}; y {-8,4} }
}
export defcell BUF_X12<: buf()
{
sizing { _y {-6,2}; y {-12,4} }
}
/*-- delay cells --*/
// TODO properly
// export defcell DLY4_X1(bool! y; bool? a, vdd, vss)
// {
// bool _y, __y, ___y;
// prs {
// a => _y-
// _y => __y-
// __y => ___y-
// ___y => y-
// }
// }
export defcell DLY4_X1(bool! y; bool? a, vdd, vss)
{
BUF_X1 bufchain[16];
(i:0..14: bufchain[i].y = bufchain[i+1].a;)
bufchain[0].a = a;
bufchain[15].y = y;
}
/*-- simple gates --*/
export defcell NOR2_X1(bool! y; bool? a, b, vdd, vss)
{
prs {
a | b => y-
}
sizing { y {-1} }
}
export defcell NOR3_X1(bool! y; bool? a, b, c, vdd, vss)
{
prs {
a | b | c => y-
}
sizing { y {-1} }
}
export defcell NOR4_X1(bool! y; bool? a, b, c, d, vdd, vss)
{
prs {
a | b | c | d => y-
}
sizing { y {-1} }
}
export defcell OR2_X1(bool! y; bool? a, b, vdd, vss)
{
bool _y;
prs {
a | b => _y-
_y => y-
}
sizing { _y{-1}; y{-1} }
}
export defcell OR2_X2(bool! y; bool? a, b, vdd, vss)
{
bool _y;
prs {
a | b => _y-
_y => y-
}
sizing { _y{-1}; y{-2} }
}
export defcell OR3_X1(bool! y; bool? a, b, c, vdd, vss)
{
bool _y;
prs {
a | b | c => _y-
_y => y-
}
sizing { _y{-1}; y{-1} }
}
export defcell OR4_X1(bool! y; bool? a, b, c, d, vdd, vss)
{
bool _y;
prs {
a | b | c | d => _y-
_y => y-
}
sizing { _y{-1}; y{-1} }
}
export defcell NAND2_X1(bool! y; bool? a, b, vdd, vss)
{
prs {
a & b => y-
}
sizing { y{-1} }
}
export defcell NAND3_X1(bool! y; bool? a, b, c, vdd, vss)
{
prs {
a & b & c => y-
}
sizing { y{-1} }
}
export defcell NAND4_X1(bool! y; bool? a, b, c, d, vdd, vss)
{
prs {
a & b & c & d => y-
}
sizing { y{-1} }
}
export defcell AND2_X1(bool! y; bool? a, b, vdd, vss)
{
bool _y;
prs {
a & b => _y-
_y => y-
}
sizing { _y{-1}; y{-1} }
}
export defcell AND2_X2(bool! y; bool? a, b, vdd, vss)
{
bool _y;
prs {
a & b => _y-
_y => y-
}
sizing { _y{-1}; y{-2} }
}
export defcell AND3_X1(bool! y; bool? a, b, c, vdd, vss)
{
bool _y;
prs {
a & b & c => _y-
_y => y-
}
sizing { _y{-1}; y{-1} }
}
export defcell AND4_X1(bool! y; bool? a, b, c, d, vdd, vss)
{
bool _y;
prs {
a & b & c & d => _y-
_y => y-
}
sizing { _y{-1}; y{-1} }
}
export defcell XOR2_X1(bool! y; bool? a, b, vdd, vss)
{
bool _a, _b;
prs {
a => _a-
b => _b-
[keeper=0] ~b & ~_a | ~_b & ~a -> y+
_b & _a | b & a -> y-
}
sizing { _a{-1}; _b{-1}; y{-1} }
}
export defcell XNOR2_X1(bool! y; bool? a, b, vdd, vss)
{
bool _a, _b;
prs {
a => _a-
b => _b-
[keeper=0] ~b & ~a | ~_b & ~_a -> y+
b & _a | _b & a -> y-
}
sizing { _a{-1}; _b{-1}; y{-1} }
}
export defcell MUX2_X1(bool! y; bool? a, b, s, vdd, vss)
{
// y = !( S ? b : a )
// Actually looks more like
// if s = 0 -> use A
// Adjusted to fit the XFAB Muxes
bool _s;
bool _y;
prs {
s => _s-
[keeper=0] ~a & ~s | ~b & ~_s -> _y+
a & _s | b & s -> _y-
_y => y-
}
sizing { _s{-1}; y{-1}; _y{-1}}
}
export defcell MUX4_X1(bool! y; bool? a, b, c, d, s0, s1, vdd, vss)
{
// y = !( S ? a : b )
bool _s0;
bool _s1;
bool _yab;
bool _ycd;
prs {
s0 => _s0-
s1 => _s1-
[keeper=0] a & _s0 | b & s0 -> _yab-
~a & ~s0 | ~b & ~_s0 -> _yab+
[keeper=0] c & _s0 | d & s0 -> _ycd-
~c & ~s0 | ~d & ~_s0 -> _ycd+
[keeper=0]_yab & _s1 | _ycd & s1 -> y-
~_yab & ~s1 | ~_ycd & ~_s1 -> y+
}
sizing {_s0{-1}; _s1{-1}; y{-1}; _yab{-1}; _ycd{-1}}
}
export defcell OAI21_X1(bool! y; bool? a, b, c, vdd, vss)
{
prs {
(a | b) & c => y-
}
sizing { y{-1} }
}
export defcell AOI21_X1(bool! y; bool? a, b, c, vdd, vss)
{
prs {
a & b | c => y-
}
sizing { y{-1} }
}
export defcell OAI22_X1(bool! y; bool? a, b, c, d, vdd, vss)
{
// y = !((a|b) & (c|d))
prs {
(a | b) & (c | d) => y-
}
sizing { y{-1} }
}
export defcell AOI22_X1(bool! y; bool? a, b, c, d, vdd, vss)
{
prs {
a & b | c & d => y-
}
sizing { y{-1} }
}
/*--- buffered transmission gates ---*/
export defcell TBUF1_X1 (bool! y; bool? a, en, vdd, vss)
{
bool _en;
prs {
en => _en-
~a & ~_en -> y+
a & en -> y-
}
sizing { _en{-1}; y{-1} }
}
export defcell TBUF_X2 (bool! y; bool? a, en, vdd, vss)
{
bool _en;
prs {
en => _en-
~a & ~_en -> y+
a & en -> y-
}
sizing { _en{-2}; y{-2,2} }
}
export defcell TBUF_X4 (bool! y; bool? a, en, vdd, vss)
{
bool _en;
prs {
en => _en-
~a & ~_en -> y+
a & en -> y-
}
sizing { _en{-4}; y{-4,4} }
}
export defproc DFFQ_R_X1 (bool? clk_B, reset_B, d; bool! q,q_B; bool? vdd,vss)
{
bool _clk_B, __clk_B, _mqi,_mqib,_sqi,_sqib;
prs {
// Creating delayed versions of the clock
clk_B => _clk_B-
_clk_B => __clk_B-
(~d & ~_clk_B)|(~reset_B)|(~__clk_B&~_mqi) -> _mqib+
((d & __clk_B)|(_mqi & _clk_B))&reset_B -> _mqib-
_mqib => _mqi-
(~_mqi &~__clk_B)|(~reset_B)|(~_sqi&~_clk_B) -> _sqib+
((_mqi &_clk_B)|(_sqi&__clk_B))&reset_B -> _sqib-
_sqib => _sqi-
_sqib => q-
q => q_B-
}
}
}
namespace cell {
export defcell g0x0 (bool? in[2]; bool! out)
{
prs {
[keeper=0] ~in[0] & ~in[1] -> out+
}
}
export defcell g1x0 (bool? in[2]; bool! out)
{
prs {
[keeper=0] in[0] & in[1] -> out-
}
}
export defcell g2x0 (bool? in[1]; bool! out)
{
prs {
[keeper=0] ~in[0] -> out+
}
}
export defcell g3x0 (bool? in[2]; bool! out)
{
prs {
[keeper=0] in[0] & in[1] -> out-
[keeper=0] ~in[0] | ~in[1] -> out+
}
}
export defcell g4x0 (bool? in[2]; bool! out)
{
prs {
[keeper=0] in[0] | in[1] -> out-
~(in[0] | in[1]) -> out+
}
}
export defcell g5x0 (bool? in[1]; bool! out)
{
prs {
[keeper=0] in[0] -> out-
}
}
export defcell g6x0 (bool? in[3]; bool! out)
{
prs {
[keeper=0] ~in[0] & ~in[1] & ~in[2] -> out+
}
}
export template<pint w,l> defcell p0(bool? in[2]; bool! out) {
prs { passp<w,l> (in[0],in[1],out) }
}
export template<pint w,l> defcell n0(bool? in[2]; bool! out) {
prs { passn<w,l> (in[0],in[1],out) }
}
export template<pint w,l> defcell t0(bool? in[3]; bool! out) {
prs { transgate<w,l> (in[0],in[1],in[2],out) }
}
export defcell p1(bool? in[2]; bool! out) {
prs { passp (in[0],in[1],out) }
}
export defcell n1(bool? in[2]; bool! out) {
prs { passn (in[0],in[1],out) }
}
export defcell t1(bool? in[3]; bool! out) {
prs { transgate (in[0],in[1],in[2],out) }
}
}

4
dataflow_neuro/treegates.act
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@ -418,7 +418,7 @@ defproc sigbuf (bool? in; bool! out[N]; power supply)
{
{ N >= 0 : "sigbuf: parameter error" };
{ N <= 128 : "sigbuf: parameter error, N too big" };
// { N <= 43 : "sigbuf: parameter error, N too big" };
/* -- just use in sized driver here -- */
[ N <= 4 ->
@ -433,7 +433,7 @@ defproc sigbuf (bool? in; bool! out[N]; power supply)
BUF_X6 buf6 (.a = in, .y = out[0], .vdd = supply.vdd, .vss = supply.vss);
[] N >= 19 & N <= 29 ->
BUF_X8 buf8 (.a = in, .y = out[0], .vdd = supply.vdd, .vss = supply.vss);
[] N >= 30 & N <= 48->
[] N >= 30 ->
BUF_X12 buf12 (.a = in, .y = out[0], .vdd = supply.vdd, .vss = supply.vss);
[] N >= 49 & N <= 64 ->
BUF_X16 buf16 (.a = in, .y = out[0], .vdd = supply.vdd, .vss = supply.vss);

5170
test/unit_tests/fifo_demux_bit_7_fifo/run/prsim.out
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File diff suppressed because it is too large Load Diff

56
test/unit_tests/fifo_demux_bit_7_fifo/run/test.prs
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@ -8749,51 +8749,51 @@
= "b.demux.in.a" "b.demux.demux.cond.a"
= "b.demux.in.a" "b.demux.demux.in.a"
= "b.demux.in.v" "b.demux.demux.in.v"
= "b.demux.in.d.d[7].d[0]" "b.demux.demux.in.d.d[6].f"
= "b.demux.in.d.d[7].d[0]" "b.demux.demux.in.d.d[6].d[0]"
= "b.demux.in.d.d[7].d[0]" "b.demux.in.d.d[7].f"
= "b.demux.in.d.d[7].d[1]" "b.demux.demux.in.d.d[6].t"
= "b.demux.in.d.d[7].d[1]" "b.demux.demux.in.d.d[6].d[1]"
= "b.demux.in.d.d[7].d[1]" "b.demux.in.d.d[7].t"
= "b.demux.in.d.d[6].d[0]" "b.demux.demux.in.d.d[6].f"
= "b.demux.in.d.d[6].d[0]" "b.demux.demux.in.d.d[6].d[0]"
= "b.demux.in.d.d[6].d[0]" "b.demux.demux.in.d.d[5].f"
= "b.demux.in.d.d[6].d[0]" "b.demux.demux.in.d.d[5].d[0]"
= "b.demux.in.d.d[6].d[0]" "b.demux.in.d.d[6].f"
= "b.demux.in.d.d[6].d[1]" "b.demux.demux.in.d.d[6].t"
= "b.demux.in.d.d[6].d[1]" "b.demux.demux.in.d.d[6].d[1]"
= "b.demux.in.d.d[6].d[1]" "b.demux.demux.in.d.d[5].t"
= "b.demux.in.d.d[6].d[1]" "b.demux.demux.in.d.d[5].d[1]"
= "b.demux.in.d.d[6].d[1]" "b.demux.in.d.d[6].t"
= "b.demux.in.d.d[5].d[0]" "b.demux.demux.in.d.d[5].f"
= "b.demux.in.d.d[5].d[0]" "b.demux.demux.in.d.d[5].d[0]"
= "b.demux.in.d.d[5].d[0]" "b.demux.demux.in.d.d[4].f"
= "b.demux.in.d.d[5].d[0]" "b.demux.demux.in.d.d[4].d[0]"
= "b.demux.in.d.d[5].d[0]" "b.demux.in.d.d[5].f"
= "b.demux.in.d.d[5].d[1]" "b.demux.demux.in.d.d[5].t"
= "b.demux.in.d.d[5].d[1]" "b.demux.demux.in.d.d[5].d[1]"
= "b.demux.in.d.d[5].d[1]" "b.demux.demux.in.d.d[4].t"
= "b.demux.in.d.d[5].d[1]" "b.demux.demux.in.d.d[4].d[1]"
= "b.demux.in.d.d[5].d[1]" "b.demux.in.d.d[5].t"
= "b.demux.in.d.d[4].d[0]" "b.demux.demux.in.d.d[4].f"
= "b.demux.in.d.d[4].d[0]" "b.demux.demux.in.d.d[4].d[0]"
= "b.demux.in.d.d[4].d[0]" "b.demux.demux.in.d.d[3].f"
= "b.demux.in.d.d[4].d[0]" "b.demux.demux.in.d.d[3].d[0]"
= "b.demux.in.d.d[4].d[0]" "b.demux.in.d.d[4].f"
= "b.demux.in.d.d[4].d[1]" "b.demux.demux.in.d.d[4].t"
= "b.demux.in.d.d[4].d[1]" "b.demux.demux.in.d.d[4].d[1]"
= "b.demux.in.d.d[4].d[1]" "b.demux.demux.in.d.d[3].t"
= "b.demux.in.d.d[4].d[1]" "b.demux.demux.in.d.d[3].d[1]"
= "b.demux.in.d.d[4].d[1]" "b.demux.in.d.d[4].t"
= "b.demux.in.d.d[3].d[0]" "b.demux.demux.in.d.d[3].f"
= "b.demux.in.d.d[3].d[0]" "b.demux.demux.in.d.d[3].d[0]"
= "b.demux.in.d.d[3].d[0]" "b.demux.demux.in.d.d[2].f"
= "b.demux.in.d.d[3].d[0]" "b.demux.demux.in.d.d[2].d[0]"
= "b.demux.in.d.d[3].d[0]" "b.demux.in.d.d[3].f"
= "b.demux.in.d.d[3].d[1]" "b.demux.demux.in.d.d[3].t"
= "b.demux.in.d.d[3].d[1]" "b.demux.demux.in.d.d[3].d[1]"
= "b.demux.in.d.d[3].d[1]" "b.demux.demux.in.d.d[2].t"
= "b.demux.in.d.d[3].d[1]" "b.demux.demux.in.d.d[2].d[1]"
= "b.demux.in.d.d[3].d[1]" "b.demux.in.d.d[3].t"
= "b.demux.in.d.d[2].d[0]" "b.demux.demux.in.d.d[2].f"
= "b.demux.in.d.d[2].d[0]" "b.demux.demux.in.d.d[2].d[0]"
= "b.demux.in.d.d[2].d[0]" "b.demux.demux.in.d.d[1].f"
= "b.demux.in.d.d[2].d[0]" "b.demux.demux.in.d.d[1].d[0]"
= "b.demux.in.d.d[2].d[0]" "b.demux.in.d.d[2].f"
= "b.demux.in.d.d[2].d[1]" "b.demux.demux.in.d.d[2].t"
= "b.demux.in.d.d[2].d[1]" "b.demux.demux.in.d.d[2].d[1]"
= "b.demux.in.d.d[2].d[1]" "b.demux.demux.in.d.d[1].t"
= "b.demux.in.d.d[2].d[1]" "b.demux.demux.in.d.d[1].d[1]"
= "b.demux.in.d.d[2].d[1]" "b.demux.in.d.d[2].t"
= "b.demux.in.d.d[1].d[0]" "b.demux.demux.in.d.d[1].f"
= "b.demux.in.d.d[1].d[0]" "b.demux.demux.in.d.d[1].d[0]"
= "b.demux.in.d.d[1].d[0]" "b.demux.demux.in.d.d[0].f"
= "b.demux.in.d.d[1].d[0]" "b.demux.demux.in.d.d[0].d[0]"
= "b.demux.in.d.d[1].d[0]" "b.demux.in.d.d[1].f"
= "b.demux.in.d.d[1].d[1]" "b.demux.demux.in.d.d[1].t"
= "b.demux.in.d.d[1].d[1]" "b.demux.demux.in.d.d[1].d[1]"
= "b.demux.in.d.d[1].d[1]" "b.demux.demux.in.d.d[0].t"
= "b.demux.in.d.d[1].d[1]" "b.demux.demux.in.d.d[0].d[1]"
= "b.demux.in.d.d[1].d[1]" "b.demux.in.d.d[1].t"
= "b.demux.in.d.d[0].d[0]" "b.demux.demux.in.d.d[0].f"
= "b.demux.in.d.d[0].d[0]" "b.demux.demux.in.d.d[0].d[0]"
= "b.demux.in.d.d[0].d[0]" "b.demux.demux.cond.d.d[0].f"
= "b.demux.in.d.d[0].d[0]" "b.demux.demux.cond.d.d[0].d[0]"
= "b.demux.in.d.d[0].d[0]" "b.demux.in.d.d[0].f"
= "b.demux.in.d.d[0].d[1]" "b.demux.demux.in.d.d[0].t"
= "b.demux.in.d.d[0].d[1]" "b.demux.demux.in.d.d[0].d[1]"
= "b.demux.in.d.d[0].d[1]" "b.demux.demux.cond.d.d[0].t"
= "b.demux.in.d.d[0].d[1]" "b.demux.demux.cond.d.d[0].d[1]"
= "b.demux.in.d.d[0].d[1]" "b.demux.in.d.d[0].t"

1
test/unit_tests/fifo_demux_bit_7_fifo/test.prsim
View File

@ -59,6 +59,7 @@ assert b.in.v 1
assert b.in.a 1
assert-qdi-channel-valid "b.out2" 7 100
assert-qdi-channel-neutral "b.out1" 7
set b.out2.v 1
cycle
assert b.in.a 1

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//
// Verilog module for: INV_X1<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0INV__X1(y, a);
output y;
input a;
// -- signals ---
reg y;
wire a;
// --- instances
endmodule
//
// Verilog module for: A_2P_U_X4<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0A__2P__U__X4(p1, p2, y);
input p1;
input p2;
output y;
// -- signals ---
reg y;
wire p2;
wire p1;
// --- instances
endmodule
//
// Verilog module for: INV_X2<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0INV__X2(y, a);
output y;
input a;
// -- signals ---
reg y;
wire a;
// --- instances
endmodule
//
// Verilog module for: A_2C1N_RB_X1<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X1(y, c1, c2, n1, pr_B, sr_B);
output y;
input c1;
input c2;
input n1;
input pr_B;
input sr_B;
// -- signals ---
wire sr_B;
reg y;
wire c2;
wire c1;
reg _y;
wire pr_B;
wire n1;
// --- instances
endmodule
//
// Verilog module for: BUF_X2<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0BUF__X2(y, a);
output y;
input a;
// -- signals ---
reg y;
reg _y;
wire a;
// --- instances
endmodule
//
// Verilog module for: A_1C1P_X1<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0A__1C1P__X1(y, c1, p1);
output y;
input c1;
input p1;
// -- signals ---
wire c1;
wire p1;
reg y;
// --- instances
endmodule
//
// Verilog module for: A_2C1P1N_RB_X1<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0A__2C1P1N__RB__X1(y, c1, c2, p1, n1, pr_B, sr_B);
output y;
input c1;
input c2;
input p1;
input n1;
input pr_B;
input sr_B;
// -- signals ---
wire sr_B;
wire n1;
wire p1;
wire c2;
reg y;
wire c1;
reg _y;
wire pr_B;
// --- instances
endmodule
//
// Verilog module for: A_3P_U_X4<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0A__3P__U__X4(p1, p2, p3, y);
input p1;
input p2;
input p3;
output y;
// -- signals ---
wire p2;
wire p3;
wire p1;
reg y;
// --- instances
endmodule
//
// Verilog module for: nrn_hs_2d<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0nrn__hs__2d(\in.d.d[0] , \in.a , \outx.d.d[0] , \outx.a , \outy.d.d[0] , \outy.a , reset_B);
input \in.d.d[0] ;
output \in.a ;
output \outx.d.d[0] ;
input \outx.a ;
output \outy.d.d[0] ;
input \outy.a ;
input reset_B;
// -- signals ---
reg \outx.d.d[0] ;
reg \in.a ;
reg _reqB;
reg \outy.d.d[0] ;
wire reset_B;
reg _y_a_B;
wire \outy.a ;
reg _x_a_B;
reg _reset_BX;
wire \in.d.d[0] ;
wire \outx.a ;
reg _en;
reg _req;
// --- instances
_0_0tmpl_0_0dataflow__neuro_0_0INV__X1 \req_inv (.y(_reqB), .a(_req));
_0_0tmpl_0_0dataflow__neuro_0_0A__2P__U__X4 \pu_y (.p1(_reqB), .p2(\outy.a ), .y(\outy.d.d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0INV__X2 \inv_x (.y(_x_a_B), .a(\outx.a ));
_0_0tmpl_0_0dataflow__neuro_0_0INV__X2 \inv_y (.y(_y_a_B), .a(\outy.a ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X1 \A_ack (.y(\in.a ), .c1(_en), .c2(\in.d.d[0] ), .n1(_req), .pr_B(_reset_BX), .sr_B(_reset_BX));
_0_0tmpl_0_0dataflow__neuro_0_0BUF__X2 \reset_buf (.y(_reset_BX), .a(reset_B));
_0_0tmpl_0_0dataflow__neuro_0_0A__1C1P__X1 \A_en (.y(_en), .c1(\in.a ), .p1(_req));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1P1N__RB__X1 \A_req (.y(_req), .c1(_en), .c2(_y_a_B), .p1(_x_a_B), .n1(\in.d.d[0] ), .pr_B(_reset_BX), .sr_B(_reset_BX));
_0_0tmpl_0_0dataflow__neuro_0_0A__3P__U__X4 \pu_x (.p1(\outx.a ), .p2(_reqB), .p3(_y_a_B), .y(\outx.d.d[0] ));
endmodule
//
// Verilog module for: nrn_hs_2d_inst<>
//
module nrn__hs__2d__inst(\in.d.d[0] , \in.a , \outx.d.d[0] , \outx.a , \outy.d.d[0] , \outy.a );
input \in.d.d[0] ;
output \in.a ;
output \outx.d.d[0] ;
input \outx.a ;
output \outy.d.d[0] ;
input \outy.a ;
// -- signals ---
reg \outx.d.d[0] ;
wire \outy.a ;
wire \in.d.d[0] ;
reg \outy.d.d[0] ;
reg _reset_B;
wire \outx.a ;
reg \in.a ;
// --- instances
_0_0tmpl_0_0dataflow__neuro_0_0nrn__hs__2d \b (.\in.d.d[0] (\in.d.d[0] ), .\in.a (\in.a ), .\outx.d.d[0] (\outx.d.d[0] ), .\outx.a (\outx.a ), .\outy.d.d[0] (\outy.d.d[0] ), .\outy.a (\outy.a ), .reset_B(_reset_B));
endmodule

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/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/coders.act";
import globals;
open tmpl::dataflow_neuro;
defproc nrn_hs_2d_inst(a1of1 in; a1of1 outx, outy)
{
bool _reset_B;
prs {
Reset => _reset_B-
}
nrn_hs_2d b(.in = in, .outx = outx, .outy = outy);
b.supply.vdd = Vdd;
b.supply.vss = GND;
b.reset_B = _reset_B;
}
nrn_hs_2d_inst b;

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watchall
set b.in[0].r 0
set b.in[1].r 0
set b.in[2].r 0
set b.in[3].r 0
set b.in[4].r 0
set b.in[5].r 0
set b.in[6].r 0
set b.in[7].r 0
set b.in[8].r 0
set b.in[9].r 0
set b.in[10].r 0
set b.in[11].r 0
set b.in[12].r 0
set b.in[13].r 0
set b.in[14].r 0
set b.outx[0].a 0
set b.outx[1].a 0
set b.outx[2].a 0
set b.outy[0].a 0
set b.outy[1].a 0
set b.outy[2].a 0
set b.outy[3].a 0
set b.outy[4].a 0
set b.outx[0].r 1
set b.outx[1].r 1
set b.outx[2].r 1
set b.outy[0].r 1
set b.outy[1].r 1
set b.outy[2].r 1
set b.outy[3].r 1
set b.outy[4].r 0
set b.b.neurons[0]._en 0
set b.b.neurons[0]._req 1
# set Reset 0
cycle
system "echo '[] set Reset 1'"
set Reset 1
cycle
status X
system "echo '[] set Reset 0'"
set Reset 0
mode run
cycle
assert b.outx[0].r 0
assert b.outx[1].r 0
assert b.outx[2].r 0
assert b.outy[0].r 0
assert b.outy[1].r 0
assert b.outy[2].r 0
assert b.outy[3].r 0
assert b.outy[4].r 0
system "echo '[] Neurons 0,1,3 spike'"
set b.in[0].r 1
set b.in[1].r 1
set b.in[3].r 1
cycle
assert b.outx[0].r 0
assert b.outx[1].r 0
assert b.outx[2].r 0
assert b.outy[0].r 1
assert b.outy[1].r 1
assert b.outy[2].r 0
assert b.outy[3].r 0
assert b.outy[4].r 0
assert b.in[0].a 1
assert b.in[1].a 1
assert b.in[3].a 1
system "echo '[] removing in reqs'"
set b.in[0].r 0
set b.in[1].r 0
set b.in[3].r 0
cycle
assert b.in[0].a 0
assert b.in[1].a 0
assert b.in[3].a 0
system "echo '[] y0 chosen, give ack'"
set b.outy[0].a 1
cycle
assert b.outx[0].r 1
assert b.outx[1].r 1
assert b.outx[2].r 0
assert b.outy[0].r 0
assert b.outy[1].r 1
assert b.outy[2].r 0
assert b.outy[3].r 0
assert b.outy[4].r 0
system "echo '[] x0 chosen, give ack'"
set b.outx[0].a 1
cycle
assert b.outx[0].r 0
assert b.outx[1].r 1
assert b.outx[2].r 0
assert b.outy[0].r 0
assert b.outy[1].r 1
assert b.outy[2].r 0
assert b.outy[3].r 0
assert b.outy[4].r 0
system "echo '[] remove x ack'"
set b.outx[0].a 0
cycle
assert b.outx[0].r 0
assert b.outx[1].r 1
assert b.outx[2].r 0
assert b.outy[0].r 0
assert b.outy[1].r 1
assert b.outy[2].r 0
assert b.outy[3].r 0
assert b.outy[4].r 0
system "echo '[] x1 remaining, give ack'"
set b.outx[1].a 1
cycle
assert b.outx[0].r 0
assert b.outx[1].r 0
assert b.outx[2].r 0
assert b.outy[0].r 0
assert b.outy[1].r 1
assert b.outy[2].r 0
assert b.outy[3].r 0
assert b.outy[4].r 0
system "echo '[] remove acks'"
set b.outx[1].a 0
set b.outy[0].a 0
cycle
assert b.outx[0].r 0
assert b.outx[1].r 0
assert b.outx[2].r 0
assert b.outy[0].r 0
assert b.outy[1].r 1
assert b.outy[2].r 0
assert b.outy[3].r 0
assert b.outy[4].r 0
system "echo '[] y1 remaining, give ack'"
set b.outy[1].a 1
cycle
assert b.outx[0].r 1
assert b.outx[1].r 0
assert b.outx[2].r 0
assert b.outy[0].r 0
assert b.outy[1].r 0
assert b.outy[2].r 0
assert b.outy[3].r 0
assert b.outy[4].r 0
system "echo '[] x0 req, give ack'"
set b.outx[0].a 1
cycle
assert b.outx[0].r 0
assert b.outx[1].r 0
assert b.outx[2].r 0
assert b.outy[0].r 0
assert b.outy[1].r 0
assert b.outy[2].r 0
assert b.outy[3].r 0
assert b.outy[4].r 0
system "echo '[] remove acks'"
set b.outx[0].a 0
set b.outy[1].a 0
cycle
assert b.outx[0].r 0
assert b.outx[1].r 0
assert b.outx[2].r 0
assert b.outy[0].r 0
assert b.outy[1].r 0
assert b.outy[2].r 0
assert b.outy[3].r 0
assert b.outy[4].r 0

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//
// Verilog module for: INV_X1<>
//
//
// Verilog module for: A_2P_U_X4<>
//
//
// Verilog module for: INV_X2<>
//
//
// Verilog module for: A_2C1N_RB_X1<>
//
//
// Verilog module for: BUF_X2<>
//
//
// Verilog module for: A_1C1P_X1<>
//
//
// Verilog module for: A_2C1P1N_RB_X1<>
//
//
// Verilog module for: A_3P_U_X4<>
//
//
// Verilog module for: nrn_hs_2d<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0nrn__hs__2d(\in.d.d[0] , \in.a , \outx.d.d[0] , \outx.a , \outy.d.d[0] , \outy.a , reset_B, vdd, vss);
input vdd;
input vss;
input \in.d.d[0] ;
output \in.a ;
output \outx.d.d[0] ;
input \outx.a ;
output \outy.d.d[0] ;
input \outy.a ;
input reset_B;
// -- signals ---
reg \outx.d.d[0] ;
reg \in.a ;
reg _reqB;
reg \outy.d.d[0] ;
wire reset_B;
reg _y_a_B;
wire \outy.a ;
reg _x_a_B;
reg _reset_BX;
wire \in.d.d[0] ;
wire \outx.a ;
reg _en;
reg _req;
// --- instances
INV_X1 \req_inv (.y(_reqB), .a(_req), .vdd(vdd), .vss(vss));
A_2P_U_X4 \pu_y (.p1(_reqB), .p2(\outy.a ), .y(\outy.d.d[0] ), .vdd(vdd), .vss(vss));
INV_X2 \inv_x (.y(_x_a_B), .a(\outx.a ), .vdd(vdd), .vss(vss));
INV_X2 \inv_y (.y(_y_a_B), .a(\outy.a ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X1 \A_ack (.y(\in.a ), .c1(_en), .c2(\in.d.d[0] ), .n1(_req), .pr_B(_reset_BX), .sr_B(_reset_BX), .vdd(vdd), .vss(vss));
BUF_X2 \reset_buf (.y(_reset_BX), .a(reset_B), .vdd(vdd), .vss(vss));
A_1C1P_X1 \A_en (.y(_en), .c1(\in.a ), .p1(_req), .vdd(vdd), .vss(vss));
A_2C1P1N_RB_X1 \A_req (.y(_req), .c1(_en), .c2(_y_a_B), .p1(_x_a_B), .n1(\in.d.d[0] ), .pr_B(_reset_BX), .sr_B(_reset_BX), .vdd(vdd), .vss(vss));
A_3P_U_X4 \pu_x (.p1(\outx.a ), .p2(_reqB), .p3(_y_a_B), .y(\outx.d.d[0] ), .vdd(vdd), .vss(vss));
endmodule
//
// Verilog module for: nrn_hs_2d_inst<>
//
module nrn__hs__2d__inst(\in.d.d[0] , \in.a , \outx.d.d[0] , \outx.a , \outy.d.d[0] , \outy.a , vdd, vss);
input vdd;
input vss;
input \in.d.d[0] ;
output \in.a ;
output \outx.d.d[0] ;
input \outx.a ;
output \outy.d.d[0] ;
input \outy.a ;
// -- signals ---
reg \outx.d.d[0] ;
wire \outy.a ;
wire \in.d.d[0] ;
reg \outy.d.d[0] ;
reg _reset_B;
wire \outx.a ;
reg \in.a ;
// --- instances
_0_0tmpl_0_0dataflow__neuro_0_0nrn__hs__2d \b (.\in.d.d[0] (\in.d.d[0] ), .\in.a (\in.a ), .\outx.d.d[0] (\outx.d.d[0] ), .\outx.a (\outx.a ), .\outy.d.d[0] (\outy.d.d[0] ), .\outy.a (\outy.a ), .reset_B(_reset_B), .vdd(vdd), .vss(vss));
endmodule

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@ -39,12 +39,11 @@ open std::data;
open tmpl::dataflow_neuro;
defproc chip_texel_test (bd<14> in; bd<14> out; Mx1of2<8> reg_data[16];
bool? bd_dly_cfg[4], bd_dly_cfg2[2], loopback_en){
bool? bd_dly_cfg[4], bd_dly_cfg2[2], loopback_en, _reset_B){
bool _reset_B;
prs {
Reset => _reset_B-
}
// prs {
// Reset => _reset_B-
// }
power supply;
supply.vdd = Vdd;
supply.vss = GND;

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