bics/actlib_dataflow_neuro
21
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

added inverters on every 4th synapse targetting line

Browse Source
This commit is contained in:
alexmadison
2022-05-02 15:26:03 +02:00
parent a114505a0b
commit cd445d1736
2 changed files with 29 additions and 21 deletions
Download Patch File Download Diff File Expand all files Collapse all files

12
dataflow_neuro/chips.act
View File

@ -194,11 +194,13 @@ defproc texel_core (avMx1of2<N_IN> in, out;
// Device debug hard-wired safety (reg0, b05 = DEV_DEBUG)
// Stops the possibility of dev_mon being high while some other sig is high.
// Otherwise boom.
// Also the 4th monitor line to each synapse is active LOW, needs inverter.
bool DEV_DEBUG;
pint NSMX4 = N_SYN_MON_X/4; // Self explanatory
sigbuf<std::max(NSMX4,4)> sb_DEV_DEBUG(.in = register.data[0].d[5].t,
.supply = supply);
DEV_DEBUG = sb_DEV_DEBUG.out[0];
INV_X1 syn_targ_set_high_inv[NSMX4];
[NSMX4 >= 1 ->
AND2_X1 ands_devmon[NSMX4];
(i:NSMX4:
@ -207,10 +209,16 @@ defproc texel_core (avMx1of2<N_IN> in, out;
ands_devmon[i].y = syn_mon_x_buf.in[1+i*4];
ands_devmon[i].vdd = supply.vdd;
ands_devmon[i].vss = supply.vss;
syn_targ_set_high_inv[i].a = syn_mon_dec_x.out[3+i*4];
syn_targ_set_high_inv[i].y = syn_mon_x_buf.in[3+i*4];
syn_targ_set_high_inv[i].vdd = supply.vdd;
syn_targ_set_high_inv[i].vss = supply.vss;
)
// Wire up the non-ANDed lines.
// Wire up the remaining lines.
(i:N_SYN_MON_X:
[~(i%4 = 1) ->
[(~(i%4 = 1)) & (~(i%4=3))->
syn_mon_x_buf.in[i] = syn_mon_dec_x.out[i];
]
)