decoder_2d_hs init
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alexmadison
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d10d78347c
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cff6eba344
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@ -134,9 +134,127 @@ namespace tmpl {
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decoder_dualrail<NyC,Ny> d_dr_y(.out = outy, .supply = supply);
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(i:0..NyC-1:d_dr_y.in.d[i] = addr_buf.out.d.d[i+NxC];)
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}
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export template<pint Nx, Ny>
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defproc and_grid(bool! out[Nx*Ny]; bool? inx[Nx], iny[Ny]; power supply) {
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AND2_X1 ands[Nx*Ny];
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(i:0..Nx*Ny-1:ands[i].vss = supply.vss; ands[i].vdd = supply.vdd;)
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(x:0..Nx-1:
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(y:0..Ny-1:
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ands[x + y*Nx].a = inx[x];
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ands[x + y*Nx].b = iny[y];
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ands[x + y*Nx].y = out[x + y*Nx];
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)
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)
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}
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/**
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* 2D decoder which uses synapse handshaking using line pulldowns.
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* Nx is the x size of the decoder array
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* NxC is the number of wires in the x channel.
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* but my guess is that we can't do logs...
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* the req on a1of1 out is the req to each synapse.
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* The ack back from each line should go high when the synapse is charged.
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* N_dly is a hard coded delay of the pull down circuit.
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* It can be set to 0.
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*/
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export template<pint NxC, NyC, Nx, Ny, N_dly>
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defproc decoder_2d_hs (avMx1of2<NxC+NyC> in; a1of1 out[Nx*Ny]; bool? reset_B; power supply) {
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// Buffer to recieve concat(x,y) address packet
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buffer<NxC+NyC> addr_buf(.in = in, .reset_B = reset_B, .supply = supply);
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// Decoder X/Y And trees
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decoder_dualrail<NxC,Nx> d_dr_x(.supply = supply);
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(i:0..NxC-1:d_dr_x.in.d[i] = addr_buf.out.d.d[i];)
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decoder_dualrail<NyC,Ny> d_dr_y(.supply = supply);
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(i:0..NyC-1:d_dr_y.in.d[i] = addr_buf.out.d.d[i+NxC];)
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// Validity
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vtree<NxC> vtree_x (.supply = supply);
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vtree<NyC> vtree_y (.supply = supply);
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(i:0..NxC-1:vtree_x.in.d[i].t = addr_buf.out.d.d[i].t;)
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(i:0..NxC-1:vtree_x.in.d[i].f = addr_buf.out.d.d[i].f;)
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(i:0..NyC-1:vtree_y.in.d[i].t = addr_buf.out.d.d[i+NxC].t;)
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(i:0..NyC-1:vtree_y.in.d[i].f = addr_buf.out.d.d[i+NxC].f;)
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A_2C_B_X1 C2el(.c1 = vtree_x.out, .c2 = vtree_y.out, .y = addr_buf.out.v,
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.vdd = supply.vdd, .vss = supply.vss);
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// and grid for reqs into synapses
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and_grid<Nx, Ny> _and_grid(.inx = d_dr_x.out, .iny = d_dr_y.out, .supply = supply);
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(i:Nx*Ny: out[i].r = _and_grid.out[i];)
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// Acknowledge pull down time
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// Pull UPs on the reqB lines by synapses (easier to invert).
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bool _out_reqsB[Nx], _out_acksB[Nx]; // The vertical output ack lines from each syn.
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PULLDOWN2_X4 req_pulldowns[Nx*Ny];
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pint index;
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(i:Nx:
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(j:Ny:
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index = i + Nx*j;
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req_pulldowns[index].a = out[index].a;
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req_pulldowns[index].b = _out_acksB[i];
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req_pulldowns[index].y = _out_reqsB[i];
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req_pulldowns[index].vss = supply.vss;
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req_pulldowns[index].vdd = supply.vdd;
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)
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)
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// ReqB keep cells
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KEEP_X1 req_keeps[Nx];
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(i:Nx:
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req_keeps[i].y = _out_reqsB[i];
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req_keeps[i].vdd = supply.vdd;
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req_keeps[i].vss = supply.vss;
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)
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// req-ack buffers
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sigbuf<Ny> req_bufs[Nx];
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(i:Nx:
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req_bufs[i].in = _out_reqsB[i];
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req_bufs[i].out[0] = _out_acksB[i]; // DANGER DANGER
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req_bufs[i].supply = supply;
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)
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// Line end pull UPs (triggered once synapse reqs removed)
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delay_fifo<N_dly> pu_dlys[Nx];
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OR2_X1 pu_ORs[Nx];
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PULLUP_X4 pu[Nx]; // TODO probably replace this with variable strength PU
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(i:Nx:
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pu_dlys[i].in = _out_acksB[i];
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pu_dlys[i].supply = supply;
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pu_ORs[i].a = pu_dlys[i].out;
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pu_ORs[i].b = d_dr_x.out[i];
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pu_ORs[i].vdd = supply.vdd;
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pu_ORs[i].vss = supply.vss;
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pu[i].a = pu_ORs[i].y;
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pu[i].y = _out_reqsB[i];
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pu[i].vdd = supply.vdd;
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pu[i].vss = supply.vss;
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)
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// ORtree from all output reqs, back to the buffer ack.
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// This is instead of the ack that came from the delayed validity trees,
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// in decoder_2d_dly.
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ortree<Nx> _ortree(.out = addr_buf.out.a, .supply = supply);
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INV_X1 out_req_invs[Nx];
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(i:Nx:
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out_req_invs[i].a = _out_reqsB[i];
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out_req_invs[i].vdd = supply.vdd;
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out_req_invs[i].vss = supply.vss;
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_ortree.in[i] = out_req_invs[i].y;
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)
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}
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/*
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@ -237,21 +355,6 @@ namespace tmpl {
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}
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export template<pint Nx, Ny>
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defproc and_grid(bool! out[Nx*Ny]; bool? inx[Nx], iny[Ny]; power supply) {
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AND2_X1 ands[Nx*Ny];
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(i:0..Nx*Ny-1:ands[i].vss = supply.vss; ands[i].vdd = supply.vdd;)
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(x:0..Nx-1:
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(y:0..Ny-1:
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ands[x + y*Nx].a = inx[x];
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ands[x + y*Nx].b = iny[y];
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ands[x + y*Nx].y = out[x + y*Nx];
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)
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)
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}
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// Generates the OR-trees required to go from
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// N one-hot inputs to Nc dual rail binary encoding.
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export template<pint Nc, N>
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@ -532,7 +635,7 @@ namespace tmpl {
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export
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defproc line_end_pull_down (bool? in; bool? reset_B; power supply; bool! out)
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defproc nrn_line_end_pull_down (bool? in; bool? reset_B; power supply; bool! out)
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{
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bool _out, __out, nand_out;
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BUF_X1 buf1(.a=in, .y=_out, .vdd=supply.vdd,.vss=supply.vss);
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@ -624,7 +727,7 @@ namespace tmpl {
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delay_fifo<N_dly> dly_y[Ny];
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// Create x line req pull downs
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line_end_pull_down pd_x[Nx];
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nrn_line_end_pull_down pd_x[Nx];
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sigbuf<Nx> rsb_pd_x(.in = reset_B, .supply = supply);
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(i:0..Nx-1:
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dly_x[i].supply = supply;
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@ -637,7 +740,7 @@ namespace tmpl {
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)
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// Create y line req pull downs
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line_end_pull_down pd_y[Ny];
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nrn_line_end_pull_down pd_y[Ny];
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sigbuf<Ny> rsb_pd_y(.in = reset_B, .supply = supply);
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(j:0..Ny-1:
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dly_y[j].supply = supply;
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