texel small testt working
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+128045
-130368
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@@ -0,0 +1,391 @@
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random_seed 0
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initialize
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load-scm "helper.scm"
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random
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set GND 0
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set Vdd 1
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set Reset 1
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mode reset
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cycle
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status U
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watchall
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set c.bd_dly_cfg[0] 1
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set c.bd_dly_cfg[1] 1
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set c.bd_dly_cfg[2] 1
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set c.bd_dly_cfg[3] 1
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set c.bd_dly_cfg2[0] 1
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set c.bd_dly_cfg2[1] 1
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set-bd-channel-neutral "c.in" 14
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set c.out.a 0
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# set c.loopback_en 1
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set c.loopback_en 0
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set Reset 1
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cycle
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mode run
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status X
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system "echo '[] Set reset 0'"
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status X
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set Reset 0
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cycle
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# Reading address 0
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set-bd-data-valid "c.in" 14 8192
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cycle
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set c.in.r 1
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cycle
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assert c.in.a 1
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# Remove input
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set-bd-channel-neutral "c.in" 14
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cycle
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assert c.in.a 0
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# Should first get loopback
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# Receiving output 0 from register 0
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# assert-bd-channel-valid "c.out" 14 8192
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# set c.out.a 1
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# cycle
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# assert-bd-channel-neutral "c.out" 14
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# set c.out.a 0
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# cycle
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# Expect register read packet to arrive
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# Receiving output 0 from register 0
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assert-bd-channel-valid "c.out" 14 0
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set c.out.a 1
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cycle
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assert-bd-channel-neutral "c.out" 14
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set c.out.a 0
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cycle
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# Disable loopback cus it's annoying
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set c.loopback_en 0
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cycle
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# Writing 17 to address 1
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set-bd-data-valid "c.in" 14 12561
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cycle
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set c.in.r 1
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cycle
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assert c.in.a 1
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# Remove input
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set-bd-channel-neutral "c.in" 14
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cycle
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assert c.in.a 0
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# Writing 255 to address 5
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set-bd-data-valid "c.in" 14 16373
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cycle
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set c.in.r 1
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cycle
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assert c.in.a 1
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# Remove input
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set-bd-channel-neutral "c.in" 14
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cycle
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assert c.in.a 0
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# Reading address 1
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system "echo '[] Reading reg 1'"
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set-bd-data-valid "c.in" 14 8193
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cycle
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set c.in.r 1
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cycle
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assert c.in.a 1
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# Remove input
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set-bd-channel-neutral "c.in" 14
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cycle
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assert c.in.a 0
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# Reading address 5
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system "echo '[] Reading reg 5'"
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set-bd-data-valid "c.in" 14 8197
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cycle
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set c.in.r 1
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cycle
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assert c.in.a 1
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# Remove input
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set-bd-channel-neutral "c.in" 14
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cycle
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assert c.in.a 0
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# Receiving output 17 from register 1
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system "echo '[] Receiving 17'"
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assert-bd-channel-valid "c.out" 14 273
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set c.out.a 1
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cycle
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assert-bd-channel-neutral "c.out" 14
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set c.out.a 0
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cycle
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system "echo '[] Receiving 4085'"
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# Receiving output 255 from register 5
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assert-bd-channel-valid "c.out" 14 4085
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set c.out.a 1
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cycle
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assert-bd-channel-neutral "c.out" 14
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set c.out.a 0
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cycle
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# SEND PACKET TO CHANGE TO SYNAPSE HANDSHAKING
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# Writing 255 to address 0
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set-bd-data-valid "c.in" 14 16368
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cycle
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set c.in.r 1
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cycle
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assert c.in.a 1
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# Remove input
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set-bd-channel-neutral "c.in" 14
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cycle
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assert c.in.a 0
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# SPIKES
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# Sending spike to synapse [0,1]
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system "echo '[] Spike'"
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set-bd-data-valid "c.in" 14 2
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cycle
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set c.in.r 1
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cycle
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assert c.in.a 1
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# Remove input
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set-bd-channel-neutral "c.in" 14
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cycle
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assert c.in.a 0
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# Receiving output spike [0,1]
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assert-bd-channel-valid "c.out" 14 2
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set c.out.a 1
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cycle
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assert-bd-channel-neutral "c.out" 14
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set c.out.a 0
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cycle
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# Sending spike to synapse [1,3]
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system "echo '[] Spike'"
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set-bd-data-valid "c.in" 14 7
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cycle
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set c.in.r 1
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cycle
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assert c.in.a 1
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# Remove input
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set-bd-channel-neutral "c.in" 14
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cycle
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assert c.in.a 0
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# Receiving output spike [1,3]
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assert-bd-channel-valid "c.out" 14 7
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set c.out.a 1
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cycle
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assert-bd-channel-neutral "c.out" 14
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set c.out.a 0
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cycle
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# Sending spike to synapse [1,2]
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system "echo '[] Spike'"
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set-bd-data-valid "c.in" 14 5
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cycle
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set c.in.r 1
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cycle
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assert c.in.a 1
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# Remove input
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set-bd-channel-neutral "c.in" 14
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cycle
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assert c.in.a 0
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# Receiving output spike [1,2]
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assert-bd-channel-valid "c.out" 14 5
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set c.out.a 1
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cycle
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assert-bd-channel-neutral "c.out" 14
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set c.out.a 0
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cycle
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# Sending spike to synapse [1,3]
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system "echo '[] Spike'"
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set-bd-data-valid "c.in" 14 7
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cycle
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set c.in.r 1
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cycle
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assert c.in.a 1
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# Remove input
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set-bd-channel-neutral "c.in" 14
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cycle
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assert c.in.a 0
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# Receiving output spike [1,3]
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assert-bd-channel-valid "c.out" 14 7
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set c.out.a 1
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cycle
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assert-bd-channel-neutral "c.out" 14
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set c.out.a 0
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cycle
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# Sending spike to synapse [0,2]
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set-bd-data-valid "c.in" 14 4
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cycle
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set c.in.r 1
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cycle
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assert c.in.a 1
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# Remove input
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set-bd-channel-neutral "c.in" 14
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cycle
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assert c.in.a 0
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# Receiving output spike [0,2]
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assert-bd-channel-valid "c.out" 14 4
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set c.out.a 1
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cycle
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assert-bd-channel-neutral "c.out" 14
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set c.out.a 0
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cycle
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# Sending spike to synapse [0,3]
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set-bd-data-valid "c.in" 14 6
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cycle
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set c.in.r 1
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cycle
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assert c.in.a 1
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# Remove input
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set-bd-channel-neutral "c.in" 14
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cycle
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assert c.in.a 0
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# Receiving output spike [0,3]
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assert-bd-channel-valid "c.out" 14 6
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set c.out.a 1
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cycle
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assert-bd-channel-neutral "c.out" 14
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set c.out.a 0
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cycle
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# Sending spike to synapse [0,1]
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set-bd-data-valid "c.in" 14 2
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cycle
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set c.in.r 1
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cycle
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assert c.in.a 1
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# Remove input
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set-bd-channel-neutral "c.in" 14
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cycle
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assert c.in.a 0
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# Receiving output spike [0,1]
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assert-bd-channel-valid "c.out" 14 2
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set c.out.a 1
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cycle
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assert-bd-channel-neutral "c.out" 14
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set c.out.a 0
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cycle
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# Sending spike to synapse [0,0]
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set-bd-data-valid "c.in" 14 0
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cycle
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set c.in.r 1
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cycle
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assert c.in.a 1
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# Remove input
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set-bd-channel-neutral "c.in" 14
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cycle
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assert c.in.a 0
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# Receiving output spike [0,0]
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assert-bd-channel-valid "c.out" 14 0
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set c.out.a 1
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cycle
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assert-bd-channel-neutral "c.out" 14
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set c.out.a 0
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cycle
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# Sending spike to synapse [0,0]
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set-bd-data-valid "c.in" 14 0
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cycle
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set c.in.r 1
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cycle
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assert c.in.a 1
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# Remove input
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set-bd-channel-neutral "c.in" 14
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cycle
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assert c.in.a 0
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# Receiving output spike [0,0]
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assert-bd-channel-valid "c.out" 14 0
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set c.out.a 1
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cycle
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assert-bd-channel-neutral "c.out" 14
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set c.out.a 0
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cycle
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# Sending spike to synapse [0,3]
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set-bd-data-valid "c.in" 14 6
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cycle
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set c.in.r 1
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cycle
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assert c.in.a 1
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# Remove input
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set-bd-channel-neutral "c.in" 14
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cycle
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assert c.in.a 0
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# Receiving output spike [0,3]
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assert-bd-channel-valid "c.out" 14 6
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set c.out.a 1
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cycle
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assert-bd-channel-neutral "c.out" 14
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set c.out.a 0
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cycle
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+102505
-108310
File diff suppressed because it is too large.
Load diff
+25111
-22043
File diff suppressed because it is too large.
Load diff
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