added sigbuf in chips
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@ -70,69 +70,72 @@ defproc chip_texel (bd<N_IN> in, out;
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power supply;
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bool? reset_B){
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bool _reset_BX;
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BUF_X12 reset_buf(.a = reset_B, .y = _reset_BX, .vdd = supply.vdd, .vss = supply.vss);
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pint index = 0; // Just useful
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bd2qdi<N_IN, N_BD_DLY_CFG, N_BD_DLY_CFG2> _bd2qdi(.in = in, .dly_cfg = bd_dly_cfg, .dly_cfg2 = bd_dly_cfg2,
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.reset_B = reset_B, .supply = supply);
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fifo<N_IN,N_BUFFERS> fifo_in2fork(.in = _bd2qdi.out, .reset_B = reset_B, .supply = supply);
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.reset_B = _reset_BX, .supply = supply);
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fifo<N_IN,N_BUFFERS> fifo_in2fork(.in = _bd2qdi.out, .reset_B = _reset_BX, .supply = supply);
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fork<N_IN> _fork(.in = fifo_in2fork.out, .reset_B = reset_B, .supply = supply);
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fork<N_IN> _fork(.in = fifo_in2fork.out, .reset_B = _reset_BX, .supply = supply);
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// Loopback
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fifo<N_IN,N_BUFFERS> fifo_fork2drop(.in = _fork.out1, .reset_B = reset_B, .supply = supply);
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fifo<N_IN,N_BUFFERS> fifo_fork2drop(.in = _fork.out1, .reset_B = _reset_BX, .supply = supply);
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dropper_static<N_IN, false> _loopback_dropper(.in = fifo_fork2drop.out, .cond = loopback_en,
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.supply = supply);
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// Onwards
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fifo<N_IN,N_BUFFERS> fifo_fork2dmx(.in = _fork.out2, .reset_B = reset_B, .supply = supply);
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demux_bit_msb<N_IN-1> _demux(.in = fifo_fork2dmx.out, .reset_B = reset_B, .supply = supply);
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fifo<N_IN,N_BUFFERS> fifo_fork2dmx(.in = _fork.out2, .reset_B = _reset_BX, .supply = supply);
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demux_bit_msb<N_IN-1> _demux(.in = fifo_fork2dmx.out, .reset_B = _reset_BX, .supply = supply);
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// Register
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fifo<N_IN-1,N_BUFFERS> fifo_dmx2reg(.in = _demux.out2, .reset_B = reset_B, .supply = supply);
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fifo<N_IN-1,N_BUFFERS> fifo_dmx2reg(.in = _demux.out2, .reset_B = _reset_BX, .supply = supply);
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register_wr_array<REG_NCA, REG_NCW, REG_M> register(.in = fifo_dmx2reg.out, .data = reg_data,
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.supply = supply, .reset_B = reset_B);
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fifo<N_IN-2,N_BUFFERS> fifo_reg2mrg(.in = register.out, .reset_B = reset_B, .supply = supply);
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.supply = supply, .reset_B = _reset_BX);
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fifo<N_IN-2,N_BUFFERS> fifo_reg2mrg(.in = register.out, .reset_B = _reset_BX, .supply = supply);
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// Spike Decoder
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pint NC_SYN;
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NC_SYN = NC_SYN_X + NC_SYN_Y;
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slice_data<N_IN-1, 0, NC_SYN> slice_pre_dec(.in = _demux.out1, .supply = supply);
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fifo<NC_SYN,N_BUFFERS> fifo_dmx2dec(.in = slice_pre_dec.out, .reset_B = reset_B, .supply = supply);
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fifo<NC_SYN,N_BUFFERS> fifo_dmx2dec(.in = slice_pre_dec.out, .reset_B = _reset_BX, .supply = supply);
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decoder_2d_hybrid<NC_SYN_X, NC_SYN_Y, N_SYN_X, N_SYN_Y, N_SYN_DLY_CFG> decoder(.in = fifo_dmx2dec.out,
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.out = synapses,
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.hs_en = register.data[0].d[0].t, // Defaults to handshake disable
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.supply = supply, .reset_B = reset_B);
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.supply = supply, .reset_B = _reset_BX);
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(i:N_SYN_DLY_CFG: decoder.dly_cfg[i] = register.data[0].d[1 + i].f;) // Defaults to max delay
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// Neurons + encoder
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pint NC_NRN;
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NC_NRN = NC_NRN_X + NC_NRN_Y;
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nrn_hs_2d_array<N_NRN_X,N_NRN_Y,N_LINE_PD_DLY> nrn_grid(.in = neurons,
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.supply = supply, .reset_B = reset_B);
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.supply = supply, .reset_B = _reset_BX);
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encoder2d_simple<NC_NRN_X, NC_NRN_Y, N_NRN_X, N_NRN_Y> encoder(
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.inx = nrn_grid.outx,
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.iny = nrn_grid.outy,
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.reset_B = reset_B, .supply = supply
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.reset_B = _reset_BX, .supply = supply
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);
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fifo<NC_NRN, N_BUFFERS> fifo_enc2mrg(.in = encoder.out,
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.reset_B = reset_B, .supply = supply);
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.reset_B = _reset_BX, .supply = supply);
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// Merge
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append<NC_NRN, N_IN-NC_NRN, 0> append_enc(.in = fifo_enc2mrg.out, .supply = supply);
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append<N_IN-2, 2, 0> append_reg(.in = fifo_reg2mrg.out, .supply = supply);
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merge<N_IN> merge_enc8reg(.in1 = append_enc.out, .in2 = append_reg.out,
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.supply = supply, .reset_B = reset_B);
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.supply = supply, .reset_B = _reset_BX);
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merge<N_IN> merge_loop8mrg(.in1 = merge_enc8reg.out, .in2 = _loopback_dropper.out,
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.reset_B = reset_B, .supply = supply);
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.reset_B = _reset_BX, .supply = supply);
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// qdi2bd
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fifo<N_IN, N_BUFFERS> fifo_mrg2bd(.in = merge_loop8mrg.out,
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.reset_B = reset_B, .supply = supply);
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.reset_B = _reset_BX, .supply = supply);
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qdi2bd<N_IN, N_BD_DLY_CFG> _qdi2bd(.in = fifo_mrg2bd.out, .out = out, .dly_cfg = bd_dly_cfg,
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.reset_B = reset_B, .supply = supply);
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.reset_B = _reset_BX, .supply = supply);
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