texel small testt working

test/unit_tests/texel_small/run/prsim.in

@@ -0,0 +1,391 @@
+random_seed 0
+initialize
+load-scm "helper.scm"
+random
+set GND 0
+set Vdd 1
+set Reset 1
+
+mode reset
+cycle
+status U
+watchall
+
+
+set c.bd_dly_cfg[0] 1
+set c.bd_dly_cfg[1] 1
+set c.bd_dly_cfg[2] 1
+set c.bd_dly_cfg[3] 1
+
+set c.bd_dly_cfg2[0] 1
+set c.bd_dly_cfg2[1] 1
+
+set-bd-channel-neutral "c.in" 14
+set c.out.a 0
+# set c.loopback_en 1
+set c.loopback_en 0
+set Reset 1
+
+cycle
+
+mode run
+status X
+system "echo '[] Set reset 0'"
+status X
+set Reset 0
+cycle
+
+# Reading address 0
+set-bd-data-valid "c.in" 14 8192
+cycle
+set c.in.r 1
+cycle
+assert c.in.a 1
+
+# Remove input
+set-bd-channel-neutral "c.in" 14
+cycle
+assert c.in.a 0
+
+# Should first get loopback
+# Receiving output 0 from register 0
+# assert-bd-channel-valid "c.out" 14 8192
+# set c.out.a 1
+# cycle
+# assert-bd-channel-neutral "c.out" 14
+# set c.out.a 0
+# cycle
+
+
+# Expect register read packet to arrive
+# Receiving output 0 from register 0
+assert-bd-channel-valid "c.out" 14 0
+set c.out.a 1
+cycle
+assert-bd-channel-neutral "c.out" 14
+set c.out.a 0
+cycle
+
+# Disable loopback cus it's annoying
+set c.loopback_en 0
+cycle
+
+# Writing 17 to address 1
+set-bd-data-valid "c.in" 14 12561
+cycle
+set c.in.r 1
+cycle
+assert c.in.a 1
+
+
+# Remove input
+set-bd-channel-neutral "c.in" 14
+cycle
+assert c.in.a 0
+
+
+# Writing 255 to address 5
+set-bd-data-valid "c.in" 14 16373
+cycle
+set c.in.r 1
+cycle
+assert c.in.a 1
+
+
+# Remove input
+set-bd-channel-neutral "c.in" 14
+cycle
+assert c.in.a 0
+
+# Reading address 1
+system "echo '[] Reading reg 1'"
+set-bd-data-valid "c.in" 14 8193
+cycle
+set c.in.r 1
+cycle
+assert c.in.a 1
+
+
+# Remove input
+set-bd-channel-neutral "c.in" 14
+cycle
+assert c.in.a 0
+
+    
+# Reading address 5
+system "echo '[] Reading reg 5'"
+set-bd-data-valid "c.in" 14 8197
+cycle
+set c.in.r 1
+cycle
+assert c.in.a 1
+
+
+# Remove input
+set-bd-channel-neutral "c.in" 14
+cycle
+assert c.in.a 0
+
+
+# Receiving output 17 from register 1
+system "echo '[] Receiving 17'"
+assert-bd-channel-valid "c.out" 14 273
+set c.out.a 1
+cycle
+assert-bd-channel-neutral "c.out" 14
+set c.out.a 0
+cycle
+
+system "echo '[] Receiving 4085'"
+# Receiving output 255 from register 5
+assert-bd-channel-valid "c.out" 14 4085
+set c.out.a 1
+cycle
+assert-bd-channel-neutral "c.out" 14
+set c.out.a 0
+cycle
+
+
+
+# SEND PACKET TO CHANGE TO SYNAPSE HANDSHAKING
+# Writing 255 to address 0
+set-bd-data-valid "c.in" 14 16368
+cycle
+set c.in.r 1
+cycle
+assert c.in.a 1
+
+# Remove input
+set-bd-channel-neutral "c.in" 14
+cycle
+assert c.in.a 0
+
+
+# SPIKES
+
+
+
+# Sending spike to synapse [0,1]
+system "echo '[] Spike'"
+set-bd-data-valid "c.in" 14 2
+cycle
+set c.in.r 1
+cycle
+assert c.in.a 1
+
+
+# Remove input
+set-bd-channel-neutral "c.in" 14
+cycle
+assert c.in.a 0
+
+    
+# Receiving output spike [0,1]
+assert-bd-channel-valid "c.out" 14 2
+set c.out.a 1
+cycle
+assert-bd-channel-neutral "c.out" 14
+set c.out.a 0
+cycle
+
+# Sending spike to synapse [1,3]
+system "echo '[] Spike'"
+set-bd-data-valid "c.in" 14 7
+cycle
+set c.in.r 1
+cycle
+assert c.in.a 1
+
+
+# Remove input
+set-bd-channel-neutral "c.in" 14
+cycle
+assert c.in.a 0
+
+    
+# Receiving output spike [1,3]
+assert-bd-channel-valid "c.out" 14 7
+set c.out.a 1
+cycle
+assert-bd-channel-neutral "c.out" 14
+set c.out.a 0
+cycle
+
+# Sending spike to synapse [1,2]
+system "echo '[] Spike'"
+set-bd-data-valid "c.in" 14 5
+cycle
+set c.in.r 1
+cycle
+assert c.in.a 1
+
+
+# Remove input
+set-bd-channel-neutral "c.in" 14
+cycle
+assert c.in.a 0
+
+    
+# Receiving output spike [1,2]
+assert-bd-channel-valid "c.out" 14 5
+set c.out.a 1
+cycle
+assert-bd-channel-neutral "c.out" 14
+set c.out.a 0
+cycle
+
+# Sending spike to synapse [1,3]
+system "echo '[] Spike'"
+set-bd-data-valid "c.in" 14 7
+cycle
+set c.in.r 1
+cycle
+assert c.in.a 1
+
+
+# Remove input
+set-bd-channel-neutral "c.in" 14
+cycle
+assert c.in.a 0
+
+    
+# Receiving output spike [1,3]
+assert-bd-channel-valid "c.out" 14 7
+set c.out.a 1
+cycle
+assert-bd-channel-neutral "c.out" 14
+set c.out.a 0
+cycle
+
+# Sending spike to synapse [0,2]
+set-bd-data-valid "c.in" 14 4
+cycle
+set c.in.r 1
+cycle
+assert c.in.a 1
+
+
+# Remove input
+set-bd-channel-neutral "c.in" 14
+cycle
+assert c.in.a 0
+
+    
+# Receiving output spike [0,2]
+assert-bd-channel-valid "c.out" 14 4
+set c.out.a 1
+cycle
+assert-bd-channel-neutral "c.out" 14
+set c.out.a 0
+cycle
+
+# Sending spike to synapse [0,3]
+set-bd-data-valid "c.in" 14 6
+cycle
+set c.in.r 1
+cycle
+assert c.in.a 1
+
+
+# Remove input
+set-bd-channel-neutral "c.in" 14
+cycle
+assert c.in.a 0
+
+    
+# Receiving output spike [0,3]
+assert-bd-channel-valid "c.out" 14 6
+set c.out.a 1
+cycle
+assert-bd-channel-neutral "c.out" 14
+set c.out.a 0
+cycle
+
+# Sending spike to synapse [0,1]
+set-bd-data-valid "c.in" 14 2
+cycle
+set c.in.r 1
+cycle
+assert c.in.a 1
+
+
+# Remove input
+set-bd-channel-neutral "c.in" 14
+cycle
+assert c.in.a 0
+
+    
+# Receiving output spike [0,1]
+assert-bd-channel-valid "c.out" 14 2
+set c.out.a 1
+cycle
+assert-bd-channel-neutral "c.out" 14
+set c.out.a 0
+cycle
+
+# Sending spike to synapse [0,0]
+set-bd-data-valid "c.in" 14 0
+cycle
+set c.in.r 1
+cycle
+assert c.in.a 1
+
+
+# Remove input
+set-bd-channel-neutral "c.in" 14
+cycle
+assert c.in.a 0
+
+    
+# Receiving output spike [0,0]
+assert-bd-channel-valid "c.out" 14 0
+set c.out.a 1
+cycle
+assert-bd-channel-neutral "c.out" 14
+set c.out.a 0
+cycle
+
+# Sending spike to synapse [0,0]
+set-bd-data-valid "c.in" 14 0
+cycle
+set c.in.r 1
+cycle
+assert c.in.a 1
+
+
+# Remove input
+set-bd-channel-neutral "c.in" 14
+cycle
+assert c.in.a 0
+
+    
+# Receiving output spike [0,0]
+assert-bd-channel-valid "c.out" 14 0
+set c.out.a 1
+cycle
+assert-bd-channel-neutral "c.out" 14
+set c.out.a 0
+cycle
+
+# Sending spike to synapse [0,3]
+set-bd-data-valid "c.in" 14 6
+cycle
+set c.in.r 1
+cycle
+assert c.in.a 1
+
+
+# Remove input
+set-bd-channel-neutral "c.in" 14
+cycle
+assert c.in.a 0
+
+    
+# Receiving output spike [0,3]
+assert-bd-channel-valid "c.out" 14 6
+set c.out.a 1
+cycle
+assert-bd-channel-neutral "c.out" 14
+set c.out.a 0
+cycle
+

test/unit_tests/texel_small/test.act

@@ -69,18 +69,22 @@ defproc chip_texel_test (bd<14> in; bd<14> out; Mx1of2<8> reg_data[16];
     pint N_BD_DLY_CFG = 4;
     pint N_BD_DLY_CFG2 = 2;
 
-    pint N_NRN_MON_X = 2;
-    pint N_NRN_MON_Y = 4;
+    pint N_NRN_MON_X = N_NRN_X*2; // [mon,kill]*N
+    pint N_NRN_MON_Y = N_NRN_Y; // [mon]*N
     // pint N_SYN_MON_X = 2;
     // pint N_SYN_MON_Y = 4;
-    pint N_SYN_MON_X = N_SYN_X*4;
-    pint N_SYN_MON_Y = N_SYN_Y;
+    pint N_SYN_MON_X = N_SYN_X*4; // [mon, dev_mon, set, reset]*N
+    pint N_SYN_MON_Y = N_SYN_Y; //  [mon]*N
 
     pint N_MON_AMZO_PER_SYN = 5;
+    pint N_MON_AMZO_PER_NRN = 7;
+
+    pint N_FLAGS_PER_SYN = 5; // Must be at least 3 (since those ones have special safety)
+    pint N_FLAGS_PER_NRN = 7; // And leq than the number of bits in a reg, since have presumed only needs one.
 
     pint N_BUFFERS = 3;
 
-    pint N_LINE_PD_DLY = 0;
+    pint N_LINE_PD_DLY = 3;
     
     pint REG_NCA = 4;
     pint REG_M = 1<<REG_NCA;
@@ -91,7 +95,8 @@ defproc chip_texel_test (bd<14> in; bd<14> out; Mx1of2<8> reg_data[16];
     NC_NRN_X, NC_NRN_Y, NC_SYN_X, NC_SYN_Y,
     N_SYN_DLY_CFG,
     N_NRN_MON_X, N_NRN_MON_Y, N_SYN_MON_X, N_SYN_MON_Y,
-    N_MON_AMZO_PER_SYN,
+    N_MON_AMZO_PER_SYN, N_MON_AMZO_PER_NRN,
+    N_FLAGS_PER_SYN, N_FLAGS_PER_NRN,
     N_BUFFERS,
     N_LINE_PD_DLY,
     N_BD_DLY_CFG, N_BD_DLY_CFG2,

test/unit_tests/texel_small/test.prsim

@@ -11,7 +11,8 @@ set c.bd_dly_cfg2[1] 1
 
 set-bd-channel-neutral "c.in" 14
 set c.out.a 0
-set c.loopback_en 1
+# set c.loopback_en 1
+set c.loopback_en 0
 set Reset 1
 
 cycle
@@ -37,12 +38,12 @@ assert c.in.a 0
 
 # Should first get loopback
 # Receiving output 0 from register 0
-assert-bd-channel-valid "c.out" 14 8192
-set c.out.a 1
-cycle
-assert-bd-channel-neutral "c.out" 14
-set c.out.a 0
-cycle
+# assert-bd-channel-valid "c.out" 14 8192
+# set c.out.a 1
+# cycle
+# assert-bd-channel-neutral "c.out" 14
+# set c.out.a 0
+# cycle
 
 
 # Expect register read packet to arrive
@@ -86,6 +87,7 @@ cycle
 assert c.in.a 0
 
 # Reading address 1
+system "echo '[] Reading reg 1'"
 set-bd-data-valid "c.in" 14 8193
 cycle
 set c.in.r 1
@@ -100,6 +102,7 @@ assert c.in.a 0
 
     
 # Reading address 5
+system "echo '[] Reading reg 5'"
 set-bd-data-valid "c.in" 14 8197
 cycle
 set c.in.r 1
@@ -114,6 +117,7 @@ assert c.in.a 0
 
 
 # Receiving output 17 from register 1
+system "echo '[] Receiving 17'"
 assert-bd-channel-valid "c.out" 14 273
 set c.out.a 1
 cycle
@@ -121,6 +125,7 @@ assert-bd-channel-neutral "c.out" 14
 set c.out.a 0
 cycle
 
+system "echo '[] Receiving 4085'"
 # Receiving output 255 from register 5
 assert-bd-channel-valid "c.out" 14 4085
 set c.out.a 1
@@ -131,9 +136,18 @@ cycle
 
 
 
+# SEND PACKET TO CHANGE TO SYNAPSE HANDSHAKING
+# Writing 255 to address 0
+set-bd-data-valid "c.in" 14 16368
+cycle
+set c.in.r 1
+cycle
+assert c.in.a 1
 
-
-
+# Remove input
+set-bd-channel-neutral "c.in" 14
+cycle
+assert c.in.a 0
 
 
 # SPIKES
@@ -141,6 +155,7 @@ cycle
 
 
 # Sending spike to synapse [0,1]
+system "echo '[] Spike'"
 set-bd-data-valid "c.in" 14 2
 cycle
 set c.in.r 1
@@ -163,6 +178,7 @@ set c.out.a 0
 cycle
 
 # Sending spike to synapse [1,3]
+system "echo '[] Spike'"
 set-bd-data-valid "c.in" 14 7
 cycle
 set c.in.r 1
@@ -185,6 +201,7 @@ set c.out.a 0
 cycle
 
 # Sending spike to synapse [1,2]
+system "echo '[] Spike'"
 set-bd-data-valid "c.in" 14 5
 cycle
 set c.in.r 1
@@ -207,6 +224,7 @@ set c.out.a 0
 cycle
 
 # Sending spike to synapse [1,3]
+system "echo '[] Spike'"
 set-bd-data-valid "c.in" 14 7
 cycle
 set c.in.r 1