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renamed to sadc_encoder

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alexmadison 2022-06-29 13:36:14 +02:00
parent 836e19a72d
commit f488e5dc81
7 changed files with 18607 additions and 0 deletions
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1974
test/unit_tests/sadc_encoder/netlist.v Normal file
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test/unit_tests/sadc_encoder/netlist_clean.v Normal file
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test/unit_tests/sadc_encoder/run/prsim.in Normal file
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random_seed 34
initialize
load-scm "helper.scm"
random
set GND 0
set Vdd 1
set Reset 1
mode reset
cycle
status U
watchall
set c.dly_cfg[0] 1
set c.dly_cfg[1] 1
set c.dly_cfg[2] 1
set c.dly_cfg[3] 1
set c.in[0].r 1
set c.in[1].r 1
set c.in[2].r 1
set c.in[3].r 1
set c.in[4].r 1
set c.in[5].r 1
set c.in[6].r 1
set c.in[7].r 1
set c.in[8].r 1
set c.in[9].r 1
set c.in[10].r 1
set c.in[11].r 1
set c.in[12].r 1
set c.in[13].r 1
set c.in[14].r 1
set c.in[15].r 1
set c.in[16].r 1
set c.in[17].r 1
set c.in[18].r 1
set c.in[19].r 1
set c.in[20].r 1
set c.in[21].r 1
set c.in[22].r 1
set c.in[23].r 1
set c.out.a 0
set Reset 1
cycle
status X
system "echo '[] Set reset 0'"
mode run
set Reset 0
cycle
system "echo '[] Reset finished'"
status X
assert-bd-channel-neutral "c.out" 5
assert c.in[0].a 1
assert c.in[1].a 1
assert c.in[2].a 1
assert c.in[3].a 1
assert c.in[4].a 1
assert c.in[5].a 1
assert c.in[6].a 1
system "echo '[] Spiking 3'"
set c.in[3].r 0
cycle
assert c.in[3].a 0
set c.in[3].r 1
cycle
assert c.in[3].a 1
system "echo '[] Spiking 6'"
set c.in[6].r 0
cycle
assert c.in[6].a 0
set c.in[6].r 1
cycle
assert c.in[6].a 1
system "echo '[] Receive 3'"
assert-bd-channel-valid "c.out" 5 3
set c.out.a 1
cycle
assert-bd-channel-neutral "c.out" 5
set c.out.a 0
cycle
system "echo '[] Receive 6'"
assert-bd-channel-valid "c.out" 5 6
set c.out.a 1
cycle
assert-bd-channel-neutral "c.out" 5
set c.out.a 0
cycle

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test/unit_tests/sadc_encoder/run/prsim.out Normal file
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test/unit_tests/sadc_encoder/run/test.prs Normal file
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test/unit_tests/sadc_encoder/test.act Normal file
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/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/coders.act";
import "../../dataflow_neuro/primitives.act";
import globals;
import std::data;
open std::data;
open tmpl::dataflow_neuro;
pint N = 24;
pint Nc = std::ceil_log2(N);
pint N_BUFFERS = 5;
pint N_BD_DLY_CFG = 4;
defproc sadc_encoder (a1of1 in[N]; bd<Nc> out; bool? dly_cfg[N_BD_DLY_CFG]) {
bool _reset_B;
prs {
Reset => _reset_B-
}
power supply;
supply.vdd = Vdd;
supply.vss = GND;
encoder1d_bd_sadc<Nc, N, N_BUFFERS, N_BD_DLY_CFG> c(.in = in, .out = out, .dly_cfg = dly_cfg,
.reset_B = _reset_B, .supply = supply);
}
// fifo_decoder_neurons_encoder_fifo e;
sadc_encoder c;

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test/unit_tests/sadc_encoder/test.prsim Normal file
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watchall
set c.dly_cfg[0] 1
set c.dly_cfg[1] 1
set c.dly_cfg[2] 1
set c.dly_cfg[3] 1
set c.in[0].r 1
set c.in[1].r 1
set c.in[2].r 1
set c.in[3].r 1
set c.in[4].r 1
set c.in[5].r 1
set c.in[6].r 1
set c.in[7].r 1
set c.in[8].r 1
set c.in[9].r 1
set c.in[10].r 1
set c.in[11].r 1
set c.in[12].r 1
set c.in[13].r 1
set c.in[14].r 1
set c.in[15].r 1
set c.in[16].r 1
set c.in[17].r 1
set c.in[18].r 1
set c.in[19].r 1
set c.in[20].r 1
set c.in[21].r 1
set c.in[22].r 1
set c.in[23].r 1
set c.out.a 0
set Reset 1
cycle
status X
system "echo '[] Set reset 0'"
mode run
set Reset 0
cycle
system "echo '[] Reset finished'"
status X
assert-bd-channel-neutral "c.out" 5
assert c.in[0].a 1
assert c.in[1].a 1
assert c.in[2].a 1
assert c.in[3].a 1
assert c.in[4].a 1
assert c.in[5].a 1
assert c.in[6].a 1
system "echo '[] Spiking 3'"
set c.in[3].r 0
cycle
assert c.in[3].a 0
set c.in[3].r 1
cycle
assert c.in[3].a 1
system "echo '[] Spiking 6'"
set c.in[6].r 0
cycle
assert c.in[6].a 0
set c.in[6].r 1
cycle
assert c.in[6].a 1
system "echo '[] Receive 3'"
assert-bd-channel-valid "c.out" 5 3
set c.out.a 1
cycle
assert-bd-channel-neutral "c.out" 5
set c.out.a 0
cycle
system "echo '[] Receive 6'"
assert-bd-channel-valid "c.out" 5 6
set c.out.a 1
cycle
assert-bd-channel-neutral "c.out" 5
set c.out.a 0
cycle