register rw passed initial tests

dataflow_neuro/registers.act

@@ -414,10 +414,6 @@ defproc registerA_w_array(avMx1of2<NcA + NcW + 1> in; Mx1of2<NcW> data[M];
 
 // BIG TODO
 // I HAVE NOT BOTHERED WITH ANY SIGNAL BUFFERING IN HERE YET
-
-// Input valid tree
-// Note that I may need to check the validity of other downstream stuff,
-// to be ultra careful about delays.
 vtree<NcA + NcW + 1> input_valid(.in = in.d, .out = in.v,
     .supply = supply);
 
@@ -489,8 +485,6 @@ defproc registerA_wr_array(avMx1of2<NcA + NcW + 1> in; Mx1of2<NcW> data[M]; avMx
 // I HAVE NOT BOTHERED WITH ANY SIGNAL BUFFERING IN HERE YET
 
 // Input valid tree
-// Note that I may need to check the validity of other downstream stuff,
-// to be ultra careful about delays.
 vtree<NcA + NcW + 1> input_valid(.in = in.d, .out = in.v,
     .supply = supply);
 
@@ -564,7 +558,7 @@ A_2C_B_X1 read_selectors[M];
 // OrTrees for each output word bit on read
 ortree<M> out_ortrees_t[NcW];
 ortree<M> out_ortrees_f[NcW];
-(i:M:
+(i:NcW:
     out_ortrees_t[i].out = out.d.d[i+NcA].t;
     out_ortrees_f[i].out = out.d.d[i+NcA].f;
 
@@ -579,7 +573,7 @@ AND2_X1 and_reads_f[NcW * M];
 pint index;
 (i:NcW:
     (j:M:
-        index = i * j*NcW;
+        index = i + j*NcW;
 
         and_reads_t[index].a = data[j].d[i].t;
         and_reads_t[index].b = read_selectors[j].y;

test/unit_tests/registerA_wr_array/test.act

@@ -0,0 +1,55 @@
+/*************************************************************************
+ *
+ *  This file is part of ACT dataflow neuro library.
+ * It's the testing facility for cell_lib_std.act
+ *
+ *  Copyright (c) 2022 University of Groningen - Ole Richter  
+ *  Copyright (c) 2022 University of Groningen - Hugh Greatorex
+ *  Copyright (c) 2022 University of Groningen - Michele Mastella
+ *  Copyright (c) 2022 University of Groningen - Madison Cotteret
+ *
+ *  This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
+ *
+ *  You may redistribute and modify this documentation and make products
+ *  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
+ *  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
+ *  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
+ *  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
+ *  for applicable conditions.
+ *
+ *  Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
+ *
+ *  As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
+ *  these sources, You must maintain the Source Location visible in its
+ *  documentation.
+ *
+ **************************************************************************
+ */
+
+import "../../dataflow_neuro/registers.act";
+
+import globals;
+import std::data;
+
+open std::data;
+
+open tmpl::dataflow_neuro;
+
+defproc registerA_wr_array_3x5x8 (avMx1of2<3+5+1> in; Mx1of2<5> data[8]; avMx1of2<8> out){
+    bool _reset_B; 
+    prs {
+        Reset => _reset_B-
+    }
+    power supply;
+    supply.vdd = Vdd;
+    supply.vss = GND;
+
+    // Make a register array with 3 bit address (-> 8 registers), 
+    // each register holding 5 bits.
+    registerA_wr_array<3,5,8> b(.in = in, .data = data, .out = out,
+        .reset_B = _reset_B, .supply = supply);
+}
+
+
+// fifo_decoder_neurons_encoder_fifo e;
+registerA_wr_array_3x5x8 b;

test/unit_tests/registerA_wr_array/test.prsim

@@ -0,0 +1,199 @@
+watchall
+
+set-qdi-channel-neutral "b.in" 9
+set b.out.a 0
+set b.out.v 0
+cycle
+
+
+mode run
+system "echo '[] Set reset 0'"
+status X
+set Reset 0
+cycle
+assert b.in.a 0
+assert b.in.v 0
+
+system "echo '[] Sending packet write 0s to reg0'"
+set-qdi-channel-valid "b.in" 9 256
+cycle
+assert b.in.a 1
+assert b.in.v 1
+assert-var-int "b.data[0]" 5 0
+
+system "echo '[] Removing input'"
+set-qdi-channel-neutral "b.in" 9
+cycle
+assert b.in.a 0
+assert b.in.v 0
+assert-var-int "b.data[0]" 5 0
+
+system "echo '[] Sending packet write 0s to reg0'"
+set-qdi-channel-valid "b.in" 9 256
+cycle
+assert b.in.a 1
+assert b.in.v 1
+assert-var-int "b.data[0]" 5 0
+
+system "echo '[] Removing input'"
+set-qdi-channel-neutral "b.in" 9
+cycle
+assert b.in.a 0
+assert b.in.v 0
+assert-var-int "b.data[0]" 5 0
+
+system "echo '[] Sending packet write 01100=12 to reg0'"
+set-qdi-channel-valid "b.in" 9 352
+cycle
+assert b.in.a 1
+assert b.in.v 1
+assert-var-int "b.data[0]" 5 12
+
+system "echo '[] Removing input'"
+set-qdi-channel-neutral "b.in" 9
+cycle
+assert b.in.a 0
+assert b.in.v 0
+assert-var-int "b.data[0]" 5 12
+
+
+system "echo '[] Sending packet write 0s to reg1'"
+set-qdi-channel-valid "b.in" 9 257
+cycle
+assert b.in.a 1
+assert b.in.v 1
+assert-var-int "b.data[1]" 5 0
+
+system "echo '[] Removing input'"
+set-qdi-channel-neutral "b.in" 9
+cycle
+assert b.in.a 0
+assert b.in.v 0
+
+system "echo '[] Sending packet write 0s to reg2'"
+set-qdi-channel-valid "b.in" 9 258
+cycle
+assert b.in.a 1
+assert b.in.v 1
+assert-var-int "b.data[2]" 5 0
+
+system "echo '[] Removing input'"
+set-qdi-channel-neutral "b.in" 9
+cycle
+assert b.in.a 0
+assert b.in.v 0
+assert-var-int "b.data[2]" 5 0
+
+system "echo '[] Sending packet write 0s to reg3'"
+set-qdi-channel-valid "b.in" 9 259
+cycle
+assert b.in.a 1
+assert b.in.v 1
+
+system "echo '[] Removing input'"
+set-qdi-channel-neutral "b.in" 9
+cycle
+assert b.in.a 0
+assert b.in.v 0
+
+system "echo '[] Sending packet write 0s to reg4'"
+set-qdi-channel-valid "b.in" 9 260
+cycle
+assert b.in.a 1
+assert b.in.v 1
+
+system "echo '[] Removing input'"
+set-qdi-channel-neutral "b.in" 9
+cycle
+assert b.in.a 0
+assert b.in.v 0
+
+system "echo '[] Sending packet write 0s to reg5'"
+set-qdi-channel-valid "b.in" 9 261
+cycle
+assert b.in.a 1
+assert b.in.v 1
+
+system "echo '[] Removing input'"
+set-qdi-channel-neutral "b.in" 9
+cycle
+assert b.in.a 0
+assert b.in.v 0
+
+system "echo '[] Sending packet write 0s to reg6'"
+set-qdi-channel-valid "b.in" 9 262
+cycle
+assert b.in.a 1
+assert b.in.v 1
+
+system "echo '[] Removing input'"
+set-qdi-channel-neutral "b.in" 9
+cycle
+assert b.in.a 0
+assert b.in.v 0
+
+system "echo '[] Sending packet write 0s to reg7'"
+set-qdi-channel-valid "b.in" 9 263
+cycle
+assert b.in.a 1
+assert b.in.v 1
+
+system "echo '[] Removing input'"
+set-qdi-channel-neutral "b.in" 9
+cycle
+assert b.in.a 0
+assert b.in.v 0
+
+assert-var-int "b.data[2]" 5 0
+assert-var-int "b.data[3]" 5 0
+assert-var-int "b.data[4]" 5 0
+assert-var-int "b.data[5]" 5 0
+assert-var-int "b.data[6]" 5 0
+assert-var-int "b.data[7]" 5 0
+
+
+system "echo '[] Reading register 0'"
+set-qdi-channel-valid "b.in" 9 0
+cycle
+assert-qdi-channel-valid "b.out" 8 96
+assert b.in.v 1
+assert b.in.a 0
+
+set b.out.a 1
+set b.out.v 1
+cycle
+assert b.in.a 1
+
+system "echo '[] Removing input'"
+set-qdi-channel-neutral "b.in" 9
+cycle
+assert-qdi-channel-neutral "b.out" 8
+set b.out.a 0
+set b.out.v 0
+cycle
+assert b.in.a 0
+assert b.in.v 0
+
+
+
+system "echo '[] Reading register 1'"
+set-qdi-channel-valid "b.in" 9 1
+cycle
+assert-qdi-channel-valid "b.out" 8 1
+assert b.in.v 1
+assert b.in.a 0
+
+set b.out.a 1
+set b.out.v 1
+cycle
+assert b.in.a 1
+
+system "echo '[] Removing input'"
+set-qdi-channel-neutral "b.in" 9
+cycle
+assert-qdi-channel-neutral "b.out" 8
+set b.out.a 0
+set b.out.v 0
+cycle
+assert b.in.a 0
+assert b.in.v 0