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bics:TexelTapeout

9 Commits
1d542e8a15 ... a130ca59ea

Author SHA1 Message Date
alexmadison
a130ca59ea deleted fifo3 test because it doesnt actually use the fifo object 2023-11-21 12:17:04 +01:00
alexmadison
0a91459073 removed old decoder, only simple now, fixed 8x8 test, deleted other 2 2023-11-21 11:26:04 +01:00
alexmadison
db39324593 fixed encoder2d tests, just changed labels, lowercase d 2023-11-21 10:19:21 +01:00
alexmadison
73acbcbc4f fixed demux_td_sign test and unfucked the sign flipping which shoudl have broken the other version tbh 2023-11-21 10:14:54 +01:00
alexmadison
8b37b91891 removed texel dualcore mapper, never used 2023-11-21 09:54:18 +01:00
alexmadison
200088fb0a removed mapper test, never tested irl 2023-11-21 09:52:18 +01:00
alexmadison
e412faf459 fixed demux td 2 unit test and added note to prims 2023-11-21 09:46:56 +01:00
alexmadison
6eb91b72e0 fixed demux bit 7 test and added note to primitives 2023-11-21 09:35:28 +01:00
alexmadison
822cb58d2c fixed demux_7 test and added comment on demux 2023-11-21 09:25:53 +01:00
19 changed files with 188 additions and 10278 deletions
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232
dataflow_neuro/chips.act
View File

@ -545,238 +545,6 @@ defproc texel_dualcore (bd<N_IN> in, out;
export template<pint N_IN, // Size of input data from outside world
N_NRN_X, N_NRN_Y, N_SYN_X, N_SYN_Y, // Number of neurons / synapses
NC_NRN_X, NC_NRN_Y, NC_SYN_X, NC_SYN_Y,
N_SYN_DLY_CFG,
N_NRN_MON_X, N_NRN_MON_Y, N_SYN_MON_X, N_SYN_MON_Y,
N_MON_AMZO_PER_SYN, N_MON_AMZO_PER_NRN, // Number of signals that each synapse outputs to be monitored.
N_FLAGS_PER_SYN, N_FLAGS_PER_NRN, // Number of signals that each nrn/syn recieves from the register.
N_BUFFERS,
N_LINE_PD_DLY, // Number of dummy delays to add line pull down
N_BD_DLY_CFG, N_BD_DLY_CFG2,
REG_NCA, REG_NCW, REG_M>
defproc texel_dualcore_mapper (bd<N_IN> in, out;
Mx1of2<REG_NCW> c1_reg_data[REG_M];
bool! c1_dec_req_x[N_SYN_X], c1_dec_req_y[N_SYN_Y];
bool? c1_dec_ackB[N_SYN_X];
a1of1 c1_syn_pu[N_SYN_X];
a1of1 c1_enc_inx[N_NRN_X], c1_enc_iny[N_NRN_Y];
a1of1 c1_nrn_pd_x[N_NRN_X], c1_nrn_pd_y[N_NRN_Y];
bool! c1_nrn_mon_x[N_NRN_MON_X], c1_nrn_mon_y[N_NRN_MON_Y];
bool! c1_syn_mon_x[N_SYN_MON_X], c1_syn_mon_y[N_SYN_MON_Y];
bool? c1_syn_mon_AMZI[N_SYN_X * N_MON_AMZO_PER_SYN], c1_nrn_mon_AMZI[N_NRN_X * N_MON_AMZO_PER_NRN];
bool! c1_syn_mon_AMZO[N_MON_AMZO_PER_SYN], c1_nrn_mon_AMZO[N_MON_AMZO_PER_NRN];
bool! c1_syn_flags_EFO[N_FLAGS_PER_SYN], c1_nrn_flags_EFO[N_FLAGS_PER_NRN];
bool! c1_reset_nrn_hs_BO[N_NRN_X], c1_reset_syn_hs_BO[N_SYN_X],
c1_reset_nrn_stge_BO[N_NRN_X], c1_reset_syn_stge_BO[N_SYN_X];
Mx1of2<REG_NCW> c2_reg_data[REG_M];
bool! c2_dec_req_x[N_SYN_X], c2_dec_req_y[N_SYN_Y];
bool? c2_dec_ackB[N_SYN_X];
a1of1 c2_syn_pu[N_SYN_X];
a1of1 c2_enc_inx[N_NRN_X], c2_enc_iny[N_NRN_Y];
a1of1 c2_nrn_pd_x[N_NRN_X], c2_nrn_pd_y[N_NRN_Y];
bool! c2_nrn_mon_x[N_NRN_MON_X], c2_nrn_mon_y[N_NRN_MON_Y];
bool! c2_syn_mon_x[N_SYN_MON_X], c2_syn_mon_y[N_SYN_MON_Y];
bool? c2_syn_mon_AMZI[N_SYN_X * N_MON_AMZO_PER_SYN], c2_nrn_mon_AMZI[N_NRN_X * N_MON_AMZO_PER_NRN];
bool! c2_syn_mon_AMZO[N_MON_AMZO_PER_SYN], c2_nrn_mon_AMZO[N_MON_AMZO_PER_NRN];
bool! c2_syn_flags_EFO[N_FLAGS_PER_SYN], c2_nrn_flags_EFO[N_FLAGS_PER_NRN];
bool! c2_reset_nrn_hs_BO[N_NRN_X], c2_reset_syn_hs_BO[N_SYN_X],
c2_reset_nrn_stge_BO[N_NRN_X], c2_reset_syn_stge_BO[N_SYN_X];
bool? bd_dly_cfg[N_BD_DLY_CFG], bd_dly_cfg2[N_BD_DLY_CFG2];
bool? loopback_en;
power supply;
bool? reset_B, reset_reg_B, reset_syn_stge_BI;
// MAPPER STUFF
bool? mapper_en;
avMx1of2<30> out_sram_wr; // Input packets to go to SRAM (rw word addr)
avMx1of2<8> out_sram_spk; // Spike packets from enc to go to SRAM (core-nrn addr)
avMx1of2<29> in_sram_r; // Readout packets from SRAM
avMx1of2<14> in_sram_spk // Spike packets from SRAM (core-syn addr)
){
// Reset buffers
bool _reset_BX;
BUF_X12 reset_buf(.a = reset_B, .y = _reset_BX, .vdd = supply.vdd, .vss = supply.vss);
bd2qdi<N_IN, N_BD_DLY_CFG, N_BD_DLY_CFG2> _bd2qdi(.in = in, .dly_cfg = bd_dly_cfg, .dly_cfg2 = bd_dly_cfg2,
.reset_B = _reset_BX, .supply = supply);
fifo<N_IN,N_BUFFERS> fifo_in2fork(.in = _bd2qdi.out, .reset_B = _reset_BX, .supply = supply);
fork<N_IN> _fork(.in = fifo_in2fork.out, .reset_B = _reset_BX, .supply = supply);
// Loopback
fifo<N_IN,N_BUFFERS> fifo_fork2drop(.in = _fork.out1, .reset_B = _reset_BX, .supply = supply);
dropper_static<N_IN, false> _loopback_dropper(.in = fifo_fork2drop.out, .cond = loopback_en,
.supply = supply);
fifo<N_IN,N_BUFFERS> fifo_drop2mrg(.in = _loopback_dropper.out, .reset_B = _reset_BX, .supply = supply);
// dmx to SRAM
bool is_to_sram, is_to_cores;
fifo<32, N_BUFFERS> fifo_fork2sramdmx(.in = _fork.out2, .supply = supply, .reset_B = _reset_BX);
demux<32> sram_dmx(.in = fifo_fork2sramdmx.out, .supply = supply, .reset_B = _reset_BX);
sram_dmx.cond.d.d[0].t = is_to_sram;
sram_dmx.cond.d.d[0].f = is_to_cores;
AND2_X1 sram_dmx_and(.a = sram_dmx.in.d.d[30].f, .b = sram_dmx.in.d.d[29].t,
.y = is_to_sram,
.vdd = supply.vdd, .vss = supply.vss);
OR3_X1 sram_dmx_or(.a = sram_dmx.in.d.d[30].t, .b = sram_dmx.in.d.d[30].t, .c = sram_dmx.in.d.d[29].f,
.y = is_to_cores,
.vdd = supply.vdd, .vss = supply.vss);
slice_data<32, 0, 30> pre_sram_slice(.supply = supply);
pre_sram_slice.in.a = sram_dmx.out2.a;
pre_sram_slice.in.v = sram_dmx.out2.v;
(i:29:pre_sram_slice.in.d.d[i] = sram_dmx.out2.d.d[i];)
pre_sram_slice.in.d.d[29] = sram_dmx.out2.d.d[31];
pre_sram_slice.in.d.d[30] = sram_dmx.out2.d.d[30];
pre_sram_slice.in.d.d[31] = sram_dmx.out2.d.d[29];
fifo<30, N_BUFFERS> fifo_out_sram_wr(.in = pre_sram_slice.out, .out = out_sram_wr,
.reset_B = _reset_BX, .supply = supply);
// spikes from sram
// requires weird merging because [core, syny, synx] needs to go to [core, ZEROES, syny, synx]
fifo<14, N_BUFFERS> fifo_in_sram_spk(.in = in_sram_spk, .reset_B = _reset_BX, .supply = supply);
append<14,32,0> sram_spk_in_append(.in = fifo_in_sram_spk.out, .supply = supply);
merge<32> merge_dmx8spk(.in1 = sram_dmx.out1, .reset_B = _reset_BX, .supply = supply);
merge_dmx8spk.in2.a = sram_spk_in_append.out.a;
merge_dmx8spk.in2.v = sram_spk_in_append.out.v;
(i:13: merge_dmx8spk.in2.d.d[i] = sram_spk_in_append.out.d.d[i];)
merge_dmx8spk.in2.d.d[31] = sram_spk_in_append.out.d.d[13];
(i:13..30: merge_dmx8spk.in2.d.d[i] = sram_spk_in_append.out.d.d[i+1];)
// Onwards to core demux
fifo<N_IN,N_BUFFERS> fifo_fork2dmx(.in = merge_dmx8spk.out, .reset_B = _reset_BX, .supply = supply);
demux_bit_msb<N_IN-1> core_dmx(.in = fifo_fork2dmx.out, .reset_B = _reset_BX, .supply = supply);
fifo<N_IN-1,N_BUFFERS> fifo_dmx2core1(.in = core_dmx.out1, .reset_B = _reset_BX, .supply = supply);
fifo<N_IN-1,N_BUFFERS> fifo_dmx2core2(.in = core_dmx.out2, .reset_B = _reset_BX, .supply = supply);
// Cores
texel_core<N_IN-1,N_NRN_X, N_NRN_Y, N_SYN_X, N_SYN_Y,NC_NRN_X, NC_NRN_Y, NC_SYN_X, NC_SYN_Y,N_SYN_DLY_CFG,N_NRN_MON_X, N_NRN_MON_Y, N_SYN_MON_X, N_SYN_MON_Y,N_MON_AMZO_PER_SYN, N_MON_AMZO_PER_NRN,N_FLAGS_PER_SYN, N_FLAGS_PER_NRN,N_BUFFERS,N_LINE_PD_DLY, REG_NCA, REG_NCW, REG_M>
core1(.in = fifo_dmx2core1.out,
.reg_data = c1_reg_data,
// .synapses = c1_synapses,
// .neurons = c1_neurons,
.dec_req_x = c1_dec_req_x, .dec_req_y = c1_dec_req_y,
.dec_ackB = c1_dec_ackB,
.syn_pu = c1_syn_pu,
.enc_inx = c1_enc_inx, .enc_iny = c1_enc_iny,
.nrn_pd_x = c1_nrn_pd_x, .nrn_pd_y = c1_nrn_pd_y,
.nrn_mon_x = c1_nrn_mon_x, .nrn_mon_y = c1_nrn_mon_y,
.syn_mon_x = c1_syn_mon_x, .syn_mon_y = c1_syn_mon_y,
.syn_mon_AMZI = c1_syn_mon_AMZI, .nrn_mon_AMZI = c1_nrn_mon_AMZI,
.syn_mon_AMZO = c1_syn_mon_AMZO, .nrn_mon_AMZO = c1_nrn_mon_AMZO,
.syn_flags_EFO = c1_syn_flags_EFO, .nrn_flags_EFO = c1_nrn_flags_EFO,
.reset_B = _reset_BX, .reset_reg_B = reset_reg_B, .reset_syn_stge_BI = reset_syn_stge_BI,
.reset_syn_hs_BO = c1_reset_syn_hs_BO, .reset_syn_stge_BO = c1_reset_syn_stge_BO,
.reset_nrn_hs_BO = c1_reset_nrn_hs_BO, .reset_nrn_stge_BO = c1_reset_nrn_stge_BO,
.supply = supply
);
texel_core<N_IN-1,N_NRN_X, N_NRN_Y, N_SYN_X, N_SYN_Y,NC_NRN_X, NC_NRN_Y, NC_SYN_X, NC_SYN_Y,N_SYN_DLY_CFG,N_NRN_MON_X, N_NRN_MON_Y, N_SYN_MON_X, N_SYN_MON_Y,N_MON_AMZO_PER_SYN, N_MON_AMZO_PER_NRN,N_FLAGS_PER_SYN, N_FLAGS_PER_NRN,N_BUFFERS,N_LINE_PD_DLY, REG_NCA, REG_NCW, REG_M>
core2(.in = fifo_dmx2core2.out,
.reg_data = c2_reg_data,
// .synapses = c2_synapses,
// .neurons = c2_neurons,
.dec_req_x = c2_dec_req_x, .dec_req_y = c2_dec_req_y,
.dec_ackB = c2_dec_ackB,
.syn_pu = c2_syn_pu,
.enc_inx = c2_enc_inx, .enc_iny = c2_enc_iny,
.nrn_pd_x = c2_nrn_pd_x, .nrn_pd_y = c2_nrn_pd_y,
.nrn_mon_x = c2_nrn_mon_x, .nrn_mon_y = c2_nrn_mon_y,
.syn_mon_x = c2_syn_mon_x, .syn_mon_y = c2_syn_mon_y,
.syn_mon_AMZI = c2_syn_mon_AMZI, .nrn_mon_AMZI = c2_nrn_mon_AMZI,
.syn_mon_AMZO = c2_syn_mon_AMZO, .nrn_mon_AMZO = c2_nrn_mon_AMZO,
.syn_flags_EFO = c2_syn_flags_EFO, .nrn_flags_EFO = c2_nrn_flags_EFO,
.reset_B = _reset_BX, .reset_reg_B = reset_reg_B, .reset_syn_stge_BI = reset_syn_stge_BI,
.reset_syn_hs_BO = c2_reset_syn_hs_BO, .reset_syn_stge_BO = c2_reset_syn_stge_BO,
.reset_nrn_hs_BO = c2_reset_nrn_hs_BO, .reset_nrn_stge_BO = c2_reset_nrn_stge_BO,
.supply = supply
);
fifo<N_IN-1,N_BUFFERS> fifo_core1out(.in = core1.out, .reset_B = _reset_BX, .supply = supply);
fifo<N_IN-1,N_BUFFERS> fifo_core2out(.in = core2.out, .reset_B = _reset_BX, .supply = supply);
// Merge cores
append<N_IN-1, 1, 0> append_core1(.in = fifo_core1out.out, .supply = supply);
append<N_IN-1, 1, 1> append_core2(.in = fifo_core2out.out, .supply = supply);
merge<N_IN> merge_core1x2(.in1 = append_core1.out, .in2 = append_core2.out,
.supply = supply, .reset_B = _reset_BX);
// fork after core merge then go to mapper if its a spike
fifo<32, N_BUFFERS> fifo_core2fork(.in = merge_core1x2.out, .reset_B = _reset_BX, .supply = supply);
fork<32> postcore_fork(.in = fifo_core2fork.out, .reset_B = _reset_BX, .supply = supply);
dropper_static<32, false> sram_dropper(.in = postcore_fork.out1, .cond = mapper_en, .supply = supply);
// Need to have it then drop the spike if its from a register.
demux_td<32, true> drop_if_reg(.in = sram_dropper.out, .reset_B = _reset_BX, .supply = supply); // if cond true, go out on data
drop_if_reg.cond.d.d[0] = sram_dropper.out.d.d[30];
drop_if_reg.token.r = drop_if_reg.token.a;
slice_data<32,0,8> slice_to_sram(.supply = supply);
// And move the msb (core bit) to just after the neuron address...
slice_to_sram.in.a = drop_if_reg.out.a;
slice_to_sram.in.v = drop_if_reg.out.v;
(i:7:slice_to_sram.in.d.d[i] = drop_if_reg.out.d.d[i];)
slice_to_sram.in.d.d[7] = drop_if_reg.out.d.d[31];
(i:7..30: slice_to_sram.in.d.d[i+1] = drop_if_reg.out.d.d[i];)
fifo<8,N_BUFFERS> fifo_out_sram_spk(.in = slice_to_sram.out, .out = out_sram_spk,
.reset_B = _reset_BX, .supply = supply);
// merge from cores and sram read in
fifo<29, N_BUFFERS> fifo_in_sram_r(.in = in_sram_r, .reset_B = _reset_BX, .supply = supply);
fifo<32, N_BUFFERS> fifo_fork2mrg(.in = postcore_fork.out2, .reset_B = _reset_BX, .supply = supply);
append<29,3,2> sram_read_in_append(.in = fifo_in_sram_r.out, .supply = supply);
merge<32> merge_sram8core(.in1 = fifo_fork2mrg.out, .in2 = sram_read_in_append.out,
.reset_B = _reset_BX, .supply = supply);
// Merge cores and loopback
fifo<32, N_BUFFERS> fifo_mrg2mrg(.in = merge_sram8core.out, .reset_B = _reset_BX, .supply = supply);
merge<N_IN> merge_drop8core(.in1 = fifo_mrg2mrg.out, .in2 = fifo_drop2mrg.out,
.reset_B = _reset_BX, .supply = supply);
// qdi2bd
fifo<N_IN, N_BUFFERS> fifo_mrg2bd(.in = merge_drop8core.out,
.reset_B = _reset_BX, .supply = supply);
qdi2bd<N_IN, N_BD_DLY_CFG> _qdi2bd(.in = fifo_mrg2bd.out, .out = out, .dly_cfg = bd_dly_cfg,
.reset_B = _reset_BX, .supply = supply);
}

131
dataflow_neuro/coders.act
View File

@ -754,136 +754,6 @@ defproc decoder_2d_hybrid (avMx1of2<NxC+NyC> in; bool! out_req_x[Nx], out_req_y[
}
export template<pint NxC, NyC, Nx, Ny, ACK_STRENGTH>
defproc encoder2d(a1of1 inx[Nx]; a1of1 iny[Ny]; avMx1of2<(NxC + NyC)> out; power supply; bool reset_B) {
// Reset buffers
pint H = 2*(NxC + NyC); //Reset strength? to be investigated
bool _reset_BX,_reset_BXX[H];
BUF_X4 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
sigbuf<2*(NxC + NyC)> reset_bufarray(.in=_reset_BX, .out=_reset_BXX,.supply=supply);
// Arbiters
a1of1 _arb_out_x, _arb_out_y;
a1of1 _x_temp[Nx],_y_temp[Ny]; // For wiring the reqs to the arbtrees
(i:Nx:
_x_temp[i].r = inx[i].r;
)
(i:Ny:
_y_temp[i].r = iny[i].r;
)
arbtree<Nx> Xarb(.in = _x_temp,.out = _arb_out_x,.supply = supply);
arbtree<Ny> Yarb(.in = _y_temp,.out = _arb_out_y,.supply = supply);
// Sigbufs for strong ackowledge signals from arb_in's
sigbuf_1output<ACK_STRENGTH> x_ack_arb[Nx];
sigbuf_1output<ACK_STRENGTH> y_ack_arb[Ny];
(i:Nx:
x_ack_arb[i].in = _x_temp[i].a;
x_ack_arb[i].out = inx[i].a;
x_ack_arb[i].supply = supply;
)
(i:Ny:
y_ack_arb[i].in = _y_temp[i].a;
y_ack_arb[i].out = iny[i].a;
y_ack_arb[i].supply = supply;
)
// This block checks that the input is valid and that the arbiter made a choice
// Then activates the ack of the arbiter
bool _x_v,_in_x_v,_in_y_v,_x_a_B,_x_a;
A_2C2P_RB_X1 Y_ack_confirm();
Y_ack_confirm.p1 = _x_v;
Y_ack_confirm.p2 =_in_x_v;
Y_ack_confirm.c1 = _arb_out_y.r;
Y_ack_confirm.c2 = _x_a_B;
Y_ack_confirm.y = _arb_out_y.a;
Y_ack_confirm.vdd = supply.vdd;
Y_ack_confirm.vss = supply.vss;
Y_ack_confirm.reset_B = _reset_BX;
// This block checks that the input is valid and that the arbiter made a choice
// Then activates the ack of the arbiter
A_2C_RB_X1 X_ack_confirm();
X_ack_confirm.c1 = _arb_out_x.r;
X_ack_confirm.c2 = _x_a_B;
X_ack_confirm.vdd = supply.vdd;
X_ack_confirm.vss = supply.vss;
X_ack_confirm.pr_B = _reset_BX;
X_ack_confirm.sr_B = _reset_BX;
X_ack_confirm.y = _arb_out_x.a;
// X_req ORtree
bool _x_req_array[Nx], _x_v_B;
(i:Nx:_x_req_array[i] = inx[i].r;)
ortree<Nx> x_req_ortree(.in = _x_req_array, .supply = supply); //todo BUFF
INV_X1 not_x_req_ortree(.a = x_req_ortree.out, .y = _x_v_B);
INV_X1 not_x_req_ortree2(.a = _x_v_B,.y = _x_v);
//X_REQ validation
// bool _x_req_array[Nx],_x_v_B, _en;
// (i:Nx:_x_req_array[i] = x[i].r;)
// ortree x_req_ortree(.in = _x_req_array,.out = _x_v,.supply = supply);
// INV_X1 not_x_req_ortree(.a = _x_v,.y = _x_v_B);
bool _x_a_B2; // sorry
bool _en;
A_1C3P2P2N_R_X1 x_ack();
//branch1
x_ack.p4 = _in_x_v;
x_ack.p5 = _x_v_B;
//branch2
x_ack.p1 = _in_x_v;
x_ack.p2 = _in_y_v;
x_ack.p3 = _x_v;
//
x_ack.c1 = _en;
x_ack.n1 = out.v;
x_ack.n2 = _in_x_v;
//
x_ack.y = _x_a_B2;
//
x_ack.vdd = supply.vdd;
x_ack.vss = supply.vss;
x_ack.pr_B = _reset_BX;
x_ack.sr_B = _reset_BX;
INV_X1 not_x_ack(.a = _x_a_B2, .y = _x_a, .vdd = supply.vdd, .vss = supply.vss);
INV_X1 not_x_ack2(.a = _x_a, .y = _x_a_B, .vdd = supply.vdd, .vss = supply.vss);
A_1C2P_X1 enabling(.p1 = out.a, .p2 = out.v, .c1 = _x_a, .y = _en, .vdd = supply.vdd, .vss = supply.vss);
avMx1of2<(NxC + NyC)> _in_x;
// Encoders
bool x_acks[Nx];
Mx1of2<NxC> x_enc_out;
(i:Nx:x_acks[i] = inx[i].a;)
dualrail_encoder<NxC, Nx> x_encoder(.in = x_acks, .out = x_enc_out, .supply = supply);
bool y_acks[Ny];
Mx1of2<NyC> y_enc_out;
(i:Ny:y_acks[i] = iny[i].a;)
dualrail_encoder<NyC, Ny> y_encoder(.in = y_acks, .out = y_enc_out, .supply = supply);
// Valid trees
vtree<NxC> vtree_x(.in = x_enc_out, .out = _in_x_v, .supply = supply);
vtree<NyC> vtree_y(.in = y_enc_out, .out = _in_y_v, .supply = supply);
// Buffer func thing
Mx1of2<NxC + NyC> into_buffer;
(i:0..NxC-1:into_buffer.d[i] = x_enc_out.d[i];)
(i:0..NyC-1:into_buffer.d[i+NxC] = y_enc_out.d[i];)
AND2_X1 _in_xy_v(.a = _in_x_v, .b = _in_y_v, .vss = supply.vss, .vdd = supply.vdd);
buffer_s_func<NxC + NyC> buf_s_func(.in = into_buffer, .out = out,
.en = _en, .in_v = _in_xy_v.y, .supply = supply, .reset_B = reset_B);
}
export
defproc nrn_line_end_pull_down (bool? in; bool? reset_B; power supply; bool! out)
@ -1133,6 +1003,7 @@ defproc decoder_2d_hybrid (avMx1of2<NxC+NyC> in; bool! out_req_x[Nx], out_req_y[
// WARNUNG WARNUNG WARNUNG //
// @TODO
// This neuron hs design has a fat timing assumption.
// Say that the neuron has sent out both reqs, and is now receiving the acks.
// _x_a_B and _y_a_B are then low, and _req starts to be pulled down to reset the hs.

22
dataflow_neuro/primitives.act
View File

@ -229,7 +229,9 @@ namespace tmpl {
f_buf_func[i].sr_B = _reset_BXX[i];
)
}
// Note that in token false/0 is send on out1, true/1 is send on out2.
// test
export template<pint N>
defproc demux (avMx1of2<N> in; avMx1of2<N> out1; avMx1of2<N> out2; bool? reset_B; avMx1of2<1> cond; power supply) {
//control
@ -237,7 +239,8 @@ namespace tmpl {
OR2_X1 out_or(.a=out1.v, .b=out2.v, .y=_out_v,.vdd=supply.vdd,.vss=supply.vss);
A_3C_RB_X4 inack_ctl(.c1=_en,.c2=_in_c_v_,.c3=_out_v,.y=in.a,.pr_B=_reset_BX,.sr_B=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
cond.a = in.a; // THIS SHOULD BE IMPROVED UPON IN FUTURE VERSIONS
cond.a = in.a; // @TODO THIS SHOULD BE IMPROVED UPON IN FUTURE VERSIONS
// actually it might be fine
cond.v = _in_c_v_;
A_1C1P_X1 en_ctl(.c1=in.a,.p1=_out_v,.y=_en,.vdd=supply.vdd,.vss=supply.vss);
BUF_X1 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
@ -387,9 +390,8 @@ namespace tmpl {
// Demux
export template<pint N; pbool CONDITION_SIGN>
// WARNING WARNING WARNING
// With a False CONDITION_SIGN, this is wrong.
// the c.t/f just need to be swapped, not inverted!!!
// @TODO docs
// also note this is not used in the final texel chip
defproc demux_td (avMx1of2<N> in; avMx1of2<N> out; a1of1 token; bool? reset_B; avMx1of2<1> cond; power supply) {
//control
bool _en, _reset_BX,_reset_BXX[N], _out_v, _in_c_v_, _reset_BXt;
@ -416,10 +418,9 @@ namespace tmpl {
BUF_X1 c_buf_tk(.a=cond.d.d[0].t, .y=_c_tk_buf, .vss = supply.vss, .vdd = supply.vdd);
sigbuf<N> c_buf_d(.in=cond.d.d[0].f, .out=_c_d_buf, .supply=supply);
[] else ->
INV_X1 invout_t(.a = cond.d.d[0].t,.y=cond_inv_t,.vdd = supply.vdd,.vss=supply.vss);
INV_X1 invout_f(.a = cond.d.d[0].f,.y=cond_inv_f,.vdd = supply.vdd,.vss=supply.vss);
BUF_X1 c_buf_tk_inv(.a=cond_inv_t, .y=_c_tk_buf, .vss = supply.vss, .vdd = supply.vdd);
sigbuf<N> c_buf_d_inv(.in=cond_inv_f, .out=_c_d_buf, .supply=supply);
BUF_X1 c_buf_tk(.a=cond.d.d[0].f, .y=_c_tk_buf, .vss = supply.vss, .vdd = supply.vdd);
sigbuf<N> c_buf_d(.in=cond.d.d[0].t, .out=_c_d_buf, .supply=supply);
]
@ -860,7 +861,8 @@ defproc slice_data(avMx1of2<N> in; avMx1of2<std::min(N1,N)-std::max(N0,0)> out;
}
// this is a wrapper for the demux, such that the condition bit is absorbed into the data
// and demux msb is just defaulting it to the msb
export template<pint N; pint CONDITION_BIT>
defproc demux_bit (avMx1of2<N+1> in; avMx1of2<N> out1; avMx1of2<N> out2; bool? reset_B; power supply)
{

9
test/unit_tests/demux_7/test.prsim
View File

@ -23,8 +23,8 @@ cycle
system "echo 'Output neutral checked'"
set my_demux.cond.d.d[0].t 1
set my_demux.cond.d.d[0].f 0
set my_demux.cond.d.d[0].t 0
set my_demux.cond.d.d[0].f 1
set-qdi-channel-valid "my_demux.in" 7 127
cycle
assert my_demux.in.v 1
@ -32,6 +32,7 @@ assert my_demux.in.a 0
assert my_demux.cond.v 1
assert-qdi-channel-valid "my_demux.out1" 7 127
assert-qdi-channel-neutral "my_demux.out2" 7
set my_demux.out1.v 1
cycle
assert my_demux.in.a 1
@ -64,8 +65,8 @@ set my_demux.out2.a 0
set my_demux.out2.v 0
cycle
set my_demux.cond.d.d[0].t 0
set my_demux.cond.d.d[0].f 1
set my_demux.cond.d.d[0].t 1
set my_demux.cond.d.d[0].f 0
set-qdi-channel-valid "my_demux.in" 7 100
cycle
assert my_demux.in.v 1

6
test/unit_tests/demux_bit_7/test.prsim
View File

@ -22,7 +22,7 @@ cycle
system "echo 'Output neutral checked'"
set-qdi-channel-valid "my_demux.in" 8 255
set-qdi-channel-valid "my_demux.in" 8 254
cycle
assert my_demux.in.v 1
assert my_demux.in.a 0
@ -59,12 +59,12 @@ set my_demux.out2.a 0
set my_demux.out2.v 0
cycle
set-qdi-channel-valid "my_demux.in" 8 100
set-qdi-channel-valid "my_demux.in" 8 101
cycle
assert my_demux.in.v 1
assert my_demux.in.a 0
assert-qdi-channel-valid "my_demux.out2" 7 100
assert-qdi-channel-valid "my_demux.out2" 7 50
set my_demux.out2.v 1
cycle
assert my_demux.in.a 1

4
test/unit_tests/demux_td_2/test.act
View File

@ -32,9 +32,9 @@ import globals;
open tmpl::dataflow_neuro;
defproc demux_2 (avMx1of2<2> in; avMx1of2<2> out1; a1of1 token; avMx1of2<1> cond){
defproc demux_2 (avMx1of2<2> in; avMx1of2<2> out; a1of1 token; avMx1of2<1> cond){
demux_td<2, false> my_demux(.in=in, .out1=out1,.token = token, .cond = cond);
demux_td<2, false> my_demux(.in=in, .out=out,.token = token, .cond = cond);
//Low active Reset
bool _reset_B;
prs {

18
test/unit_tests/demux_td_2/test.prsim
View File

@ -1,7 +1,7 @@
watchall
set-qdi-channel-neutral "my_demux.in" 2
set my_demux.out1.a 0
set my_demux.out1.v 0
set my_demux.out.a 0
set my_demux.out.v 0
set my_demux.token.a 0
set my_demux.token.r 0
set my_demux.cond.d.d[0].t 0
@ -15,7 +15,7 @@ system "echo '[]System reset completed'"
status X
mode run
assert-qdi-channel-neutral "my_demux.out1" 2
assert-qdi-channel-neutral "my_demux.out" 2
assert-qdi-channel-neutral "my_demux.in" 2
cycle
@ -28,19 +28,19 @@ cycle
assert my_demux.in.v 1
assert my_demux.in.a 0
assert-qdi-channel-valid "my_demux.out1" 2 3
assert-qdi-channel-valid "my_demux.out" 2 3
assert my_demux.token.a 0
set my_demux.out1.v 1
set my_demux.out.v 1
cycle
assert my_demux.in.a 1
set-qdi-channel-neutral "my_demux.in" 2
cycle
set my_demux.out1.a 1
set my_demux.out.a 1
cycle
set my_demux.out1.v 0
set my_demux.out.v 0
assert my_demux.in.a 1
set-qdi-channel-neutral "my_demux.in" 2
@ -48,8 +48,8 @@ set-qdi-channel-neutral "my_demux.in" 2
system "echo '[]First Cond Checked'"
set my_demux.out1.a 0
set my_demux.out1.v 0
set my_demux.out.a 0
set my_demux.out.v 0
set my_demux.token.a 0
set my_demux.token.r 0
set my_demux.cond.d.d[0].t 0

4
test/unit_tests/demux_td_2_SIGN/test.act
View File

@ -32,9 +32,9 @@ import globals;
open tmpl::dataflow_neuro;
defproc demux_2 (avMx1of2<2> in; avMx1of2<2> out1; a1of1 token; avMx1of2<1> cond){
defproc demux_2 (avMx1of2<2> in; avMx1of2<2> out; a1of1 token; avMx1of2<1> cond){
demux_td<2, true> my_demux(.in=in, .out1=out1,.token = token, .cond = cond);
demux_td<2, true> my_demux(.in=in, .out=out,.token = token, .cond = cond);
//Low active Reset
bool _reset_B;
prs {

26
test/unit_tests/demux_td_2_SIGN/test.prsim
View File

@ -1,7 +1,7 @@
watchall
set-qdi-channel-neutral "my_demux.in" 2
set my_demux.out1.a 0
set my_demux.out1.v 0
set my_demux.out.a 0
set my_demux.out.v 0
set my_demux.token.a 0
set my_demux.token.r 0
set my_demux.cond.d.d[0].t 0
@ -15,7 +15,7 @@ system "echo 'System reset completed'"
status X
mode run
assert-qdi-channel-neutral "my_demux.out1" 2
assert-qdi-channel-neutral "my_demux.out" 2
assert-qdi-channel-neutral "my_demux.in" 2
cycle
@ -28,21 +28,26 @@ cycle
assert my_demux.in.v 1
assert my_demux.in.a 0
assert-qdi-channel-valid "my_demux.out1" 2 3
assert-qdi-channel-valid "my_demux.out" 2 3
assert my_demux.token.a 0
set my_demux.out1.v 1
assert my_demux.token.r 0
set my_demux.out.v 1
cycle
assert my_demux.in.a 1
set-qdi-channel-neutral "my_demux.in" 2
cycle
set my_demux.out1.a 1
set my_demux.out.a 1
cycle
assert-qdi-channel-neutral "my_demux.out" 2
set my_demux.out.a 0
set my_demux.out.v 0
cycle
system "echo 'First Cond Checked'"
set my_demux.out1.a 0
set my_demux.out1.v 0
set my_demux.out.a 0
set my_demux.out.v 0
set my_demux.token.a 0
set my_demux.token.r 0
set my_demux.cond.d.d[0].t 0
@ -58,9 +63,9 @@ cycle
assert my_demux.in.v 1
assert my_demux.in.a 1
assert my_demux.token.r 1
assert-qdi-channel-neutral "my_demux.out" 2
set my_demux.token.a 1
set my_demux.out1.a 1
cycle
assert my_demux.token.r 0
@ -75,6 +80,7 @@ set my_demux.cond.d.d[0].t 0
set my_demux.cond.d.d[0].f 0
cycle
assert my_demux.cond.v 0
assert my_demux.in.a 0

49
test/unit_tests/encoder2D_2x2/test.act
View File

@ -1,49 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/coders.act";
import globals;
import std::data;
open std::data;
open tmpl::dataflow_neuro;
defproc encoder2D_2x2 (a1of1 x[2]; a1of1 y[2]; avMx1of2<2> out){
encoder2D<1, 1, 2, 2, 1> e(.x=x, .y=y, .out=out);
bool _reset_B;
prs {
Reset => _reset_B-
}
e.supply.vss = GND;
e.supply.vdd = Vdd;
e.reset_B = _reset_B;
}
encoder2D_2x2 e;

377
test/unit_tests/encoder2D_2x2/test.prsim
View File

@ -1,377 +0,0 @@
watchall
mode run
system "echo '[] Set Out Ack/Valid Low'"
set e.out.a 0
set e.out.v 0
cycle
system "echo '[] Setting Neuron Req Low'"
set e.y[0].r 0
set e.y[1].r 0
set e.x[0].r 0
set e.x[1].r 0
cycle
# # Slightly confused as to whether Reset should be set to 1 given A_2C_RB_X1 needs active high to change y
# # status X
# # set Reset 1
# # cycle
cycle
set Reset 0
cycle
system "echo '[] Single Neuron Spikes (0,0)'"
set e.y[0].r 1
set e.x[0].r 1
cycle
assert e.e.Yarb.out.r 1
assert e.e.Xarb.out.r 1
assert e.e._x_v 1
system "echo '[] Check Arbiter Acks'"
assert e.e._x_a_B 1
assert e.y[0].a 1
assert e.y[1].a 0
assert e.e.Yarb.out.a 1
assert e.x[0].a 1
assert e.x[1].a 0
assert e.e.Xarb.out.a 1
system "echo '[] Check Encoders'"
assert e.e.y_enc_out.d[0].t 0
assert e.e.y_enc_out.d[0].f 1
assert e.e.x_enc_out.d[0].t 0
assert e.e.x_enc_out.d[0].f 1
system "echo '[] Check Buffer'"
assert e.e._in_x_v 1
assert e.e._in_y_v 1
assert e.e._en 1
assert e.out.d.d[0].t 0
assert e.out.d.d[0].f 1
assert e.out.d.d[1].t 0
assert e.out.d.d[1].f 1
system "echo '[] Finish Neuron Handshake'"
set e.y[0].r 0
set e.x[0].r 0
cycle
assert e.e.Yarb.out.r 0
assert e.e.Xarb.out.r 0
set e.out.a 1
set e.out.v 1
cycle
assert e.e.Yarb.out.a 0
assert e.e.Xarb.out.a 0
assert e.y[0].a 0
assert e.x[0].a 0
set e.out.a 0
set e.out.v 0
cycle
system "echo '[] Neuron (0,0) Encoded'"
system "echo '[] Single Neuron Spikes (1,1)'"
set e.y[1].r 1
set e.x[1].r 1
cycle
assert e.e.Yarb.out.r 1
assert e.e.Xarb.out.r 1
system "echo '[] Check Arbiter Acks'"
assert e.e._x_a_B 1
assert e.y[0].a 0
assert e.y[1].a 1
assert e.e.Yarb.out.a 1
assert e.x[0].a 0
assert e.x[1].a 1
assert e.e.Xarb.out.a 1
system "echo '[] Check Encoders'"
assert e.e.y_enc_out.d[0].t 1
assert e.e.y_enc_out.d[0].f 0
assert e.e.x_enc_out.d[0].t 1
assert e.e.x_enc_out.d[0].f 0
system "echo '[] Check Buffer'"
assert e.e._in_x_v 1
assert e.e._in_y_v 1
assert e.e._en 1
assert e.out.d.d[0].t 1
assert e.out.d.d[0].f 0
assert e.out.d.d[1].t 1
assert e.out.d.d[1].f 0
system "echo '[] Finish Neuron Handshake'"
set e.y[1].r 0
set e.x[1].r 0
cycle
assert e.e.Yarb.out.r 0
assert e.e.Xarb.out.r 0
set e.out.a 1
set e.out.v 1
cycle
assert e.e.Yarb.out.a 0
assert e.e.Xarb.out.a 0
assert e.y[1].a 0
assert e.x[1].a 0
set e.out.a 0
set e.out.v 0
cycle
system "echo '[] Neuron (1,1) Encoded'"
system "echo '[] Neuron Spikes (0,0), (1,0)'"
set e.x[0].r 1
set e.y[0].r 1
set e.x[1].r 1
cycle
assert e.e.Yarb.out.r 1
assert e.e.Xarb.out.r 1
system "echo '[] Check Arbiter Acks (0,0)'"
assert e.e._x_a_B 1
assert e.y[0].a 1
assert e.y[1].a 0
assert e.e.Yarb.out.a 1
assert e.x[0].a 1
assert e.x[1].a 0
assert e.e.Xarb.out.a 1
system "echo '[] Check Encoders'"
assert e.e.y_enc_out.d[0].t 0
assert e.e.y_enc_out.d[0].f 1
assert e.e.x_enc_out.d[0].t 0
assert e.e.x_enc_out.d[0].f 1
system "echo '[] Check Buffer'"
assert e.e._in_x_v 1
assert e.e._in_y_v 1
assert e.e._en 1
assert e.out.d.d[0].t 0
assert e.out.d.d[0].f 1
assert e.out.d.d[1].t 0
assert e.out.d.d[1].f 1
system "echo '[] Finish Neuron Handshake (0,0)'"
set e.x[0].r 0
cycle
set e.out.a 1
set e.out.v 1
cycle
set e.out.a 0
set e.out.v 0
cycle
system "echo '[] Neuron (0,0) Encoded'"
system "echo '[] Check Neuron (1,0) Waiting'"
assert e.e.Yarb.out.r 1
assert e.e.Xarb.out.r 1
system "echo '[] Check Arbiter Acks (1,0)'"
assert e.e._x_a_B 1
assert e.y[0].a 1
assert e.y[1].a 0
assert e.e.Yarb.out.a 1
assert e.x[0].a 0
assert e.x[1].a 1
assert e.e.Xarb.out.a 1
system "echo '[] Check Encoders'"
assert e.e.y_enc_out.d[0].t 0
assert e.e.y_enc_out.d[0].f 1
assert e.e.x_enc_out.d[0].t 1
assert e.e.x_enc_out.d[0].f 0
system "echo '[] Check Buffer'"
assert e.e._in_x_v 1
assert e.e._in_y_v 1
assert e.e._en 1
assert e.out.d.d[0].t 1
assert e.out.d.d[0].f 0
assert e.out.d.d[1].t 0
assert e.out.d.d[1].f 1
system "echo '[] Finish Neuron Handshake (1,0)'"
set e.x[1].r 0
set e.y[0].r 0
cycle
set e.out.a 1
set e.out.v 1
cycle
set e.out.a 0
set e.out.v 0
cycle
system "echo '[] Neuron (1,0) Encoded'"
system "echo '[] Neuron Spikes (1,0), (0,1)'"
set e.x[1].r 1
set e.y[0].r 1
set e.x[0].r 1
set e.y[1].r 1
cycle
assert e.e.Yarb.out.r 1
assert e.e.Xarb.out.r 1
system "echo '[] Check Arbiter Acks (1,0)'"
assert e.e._x_a_B 1
assert e.y[0].a 0
assert e.y[1].a 1
assert e.e.Yarb.out.a 1
assert e.x[0].a 0
assert e.x[1].a 1
assert e.e.Xarb.out.a 1
system "echo '[] Check Encoders'"
assert e.e.y_enc_out.d[0].t 1
assert e.e.y_enc_out.d[0].f 0
assert e.e.x_enc_out.d[0].t 1
assert e.e.x_enc_out.d[0].f 0
system "echo '[] Check Buffer'"
assert e.e._in_x_v 1
assert e.e._in_y_v 1
assert e.e._en 1
assert e.out.d.d[0].t 1
assert e.out.d.d[0].f 0
assert e.out.d.d[1].t 1
assert e.out.d.d[1].f 0
system "echo '[] Finish Neuron Handshake (1,0)'"
set e.x[1].r 0
set e.y[0].r 0
cycle
set e.out.a 1
set e.out.v 1
cycle
set e.out.a 0
set e.out.v 0
cycle
system "echo '[] Neuron (1,0) Encoded'"
system "echo '[] Check Neuron (0,1) Waiting'"
assert e.e.Yarb.out.r 1
assert e.e.Xarb.out.r 1
system "echo '[] Check Arbiter Acks (0,1)'"
assert e.e._x_a_B 1
assert e.y[0].a 0
assert e.y[1].a 1
assert e.e.Yarb.out.a 1
assert e.x[0].a 1
assert e.x[1].a 0
assert e.e.Xarb.out.a 1
system "echo '[] Check Encoders'"
assert e.e.y_enc_out.d[0].t 1
assert e.e.y_enc_out.d[0].f 0
assert e.e.x_enc_out.d[0].t 0
assert e.e.x_enc_out.d[0].f 1
system "echo '[] Check Buffer'"
assert e.e._in_x_v 1
assert e.e._in_y_v 1
assert e.e._en 1
assert e.out.d.d[0].t 0
assert e.out.d.d[0].f 1
assert e.out.d.d[1].t 1
assert e.out.d.d[1].f 0
system "echo '[] Finish Neuron Handshake (1,0)'"
set e.x[0].r 0
set e.y[1].r 0
cycle
set e.out.a 1
set e.out.v 1
cycle
set e.out.a 0
set e.out.v 0
cycle
assert e.e._in_x_v 0
assert e.e._in_y_v 0
assert e.e._x_v 0
system "echo '[] Neuron (1,0) Encoded'"

49
test/unit_tests/encoder2D_8x7/test.act
View File

@ -1,49 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/coders.act";
import globals;
import std::data;
open std::data;
open tmpl::dataflow_neuro;
defproc encoder2D_2x2 (a1of1 x[8]; a1of1 y[7]; avMx1of2<6> out){
encoder2D<3, 3, 8, 7, 1> e(.x=x, .y=y, .out=out);
bool _reset_B;
prs {
Reset => _reset_B-
}
e.supply.vss = GND;
e.supply.vdd = Vdd;
e.reset_B = _reset_B;
}
encoder2D_2x2 e;

246
test/unit_tests/encoder2D_8x7/test.prsim
View File

@ -1,246 +0,0 @@
watchall
mode run
system "echo '[] Set Out Ack/Valid Low'"
set e.out.a 0
set e.out.v 0
cycle
system "echo '[] Setting Neuron Req Low'"
set e.y[0].r 0
set e.y[1].r 0
set e.y[2].r 0
set e.y[3].r 0
set e.y[4].r 0
set e.y[5].r 0
set e.y[6].r 0
# set e.y[7].r 0
set e.x[0].r 0
set e.x[1].r 0
set e.x[2].r 0
set e.x[3].r 0
set e.x[4].r 0
set e.x[5].r 0
set e.x[6].r 0
set e.x[7].r 0
cycle
# # Slightly confused as to whether Reset should be set to 1 given A_2C_RB_X1 needs active high to change y
# # status X
# # set Reset 1
# # cycle
cycle
mode run
status X
status 0
set Reset 0
cycle
system "echo '[] Single Neuron Spikes (2,5), raise y[5].r'"
set e.y[5].r 1
# set e.x[2].r 1
cycle
assert e.e.Yarb.out.r 1
assert e.e.Xarb.out.r 0
assert e.e._x_v 0
system "echo '[] Raise x[2].r'"
# set e.y[5].r 1
set e.x[2].r 1
cycle
assert e.e.Yarb.out.r 1
assert e.e.Xarb.out.r 1
assert e.e._x_v 1
system "echo '[] Check Arbiter Acks'"
assert e.e._x_a_B 1
assert e.y[0].a 0
assert e.y[1].a 0
assert e.y[2].a 0
assert e.y[3].a 0
assert e.y[4].a 0
assert e.y[5].a 1
assert e.y[6].a 0
# assert e.y[7].a 0
assert e.e.Yarb.out.a 1
assert e.x[0].a 0
assert e.x[1].a 0
assert e.x[2].a 1
assert e.x[3].a 0
assert e.x[4].a 0
assert e.x[5].a 0
assert e.x[6].a 0
assert e.x[7].a 0
assert e.e.Xarb.out.a 1
system "echo '[] Check Encoders'"
assert e.e.x_enc_out.d[0].t 0
assert e.e.x_enc_out.d[0].f 1
assert e.e.x_enc_out.d[1].t 1
assert e.e.x_enc_out.d[1].f 0
assert e.e.x_enc_out.d[2].t 0
assert e.e.x_enc_out.d[2].f 1
assert e.e.y_enc_out.d[0].t 1
assert e.e.y_enc_out.d[0].f 0
assert e.e.y_enc_out.d[1].t 0
assert e.e.y_enc_out.d[1].f 1
assert e.e.y_enc_out.d[2].t 1
assert e.e.y_enc_out.d[2].f 0
system "echo '[] Check Buffer'"
assert e.e._in_x_v 1
assert e.e._in_y_v 1
assert e.e._en 1
assert e.out.d.d[0].t 0
assert e.out.d.d[0].f 1
assert e.out.d.d[1].t 1
assert e.out.d.d[1].f 0
assert e.out.d.d[2].t 0
assert e.out.d.d[2].f 1
assert e.out.d.d[3].t 1
assert e.out.d.d[3].f 0
assert e.out.d.d[4].t 0
assert e.out.d.d[4].f 1
assert e.out.d.d[5].t 1
assert e.out.d.d[5].f 0
system "echo '[] Finish Neuron Handshake'"
set e.y[5].r 0
set e.x[2].r 0
cycle
assert e.e.Yarb.out.r 0
assert e.e.Xarb.out.r 0
set e.out.a 1
set e.out.v 1
cycle
assert e.e.Yarb.out.a 0
assert e.e.Xarb.out.a 0
assert e.y[5].a 0
assert e.x[2].a 0
set e.out.a 0
set e.out.v 0
cycle
system "echo '[] Neuron (2,5) Encoded'"
system "echo '[] Single Neuron Spikes (0,0)'"
set e.y[0].r 1
set e.x[0].r 1
cycle
assert e.e.Yarb.out.r 1
assert e.e.Xarb.out.r 1
assert e.e._x_v 1
system "echo '[] Check Arbiter Acks'"
assert e.e._x_a_B 1
assert e.y[0].a 1
assert e.y[1].a 0
assert e.y[2].a 0
assert e.y[3].a 0
assert e.y[4].a 0
assert e.y[5].a 0
assert e.y[6].a 0
# assert e.y[7].a 0
assert e.e.Yarb.out.a 1
assert e.x[0].a 1
assert e.x[1].a 0
assert e.x[2].a 0
assert e.x[3].a 0
assert e.x[4].a 0
assert e.x[5].a 0
assert e.x[6].a 0
assert e.x[7].a 0
assert e.e.Xarb.out.a 1
system "echo '[] Check Encoders'"
assert e.e.y_enc_out.d[0].t 0
assert e.e.y_enc_out.d[0].f 1
assert e.e.y_enc_out.d[1].t 0
assert e.e.y_enc_out.d[1].f 1
assert e.e.y_enc_out.d[2].t 0
assert e.e.y_enc_out.d[2].f 1
assert e.e.x_enc_out.d[0].t 0
assert e.e.x_enc_out.d[0].f 1
assert e.e.x_enc_out.d[1].t 0
assert e.e.x_enc_out.d[1].f 1
assert e.e.x_enc_out.d[2].t 0
assert e.e.x_enc_out.d[2].f 1
system "echo '[] Check Buffer'"
assert e.e._in_x_v 1
assert e.e._in_y_v 1
assert e.e._en 1
assert e.out.d.d[0].t 0
assert e.out.d.d[0].f 1
assert e.out.d.d[1].t 0
assert e.out.d.d[1].f 1
assert e.out.d.d[2].t 0
assert e.out.d.d[2].f 1
assert e.out.d.d[3].t 0
assert e.out.d.d[3].f 1
assert e.out.d.d[4].t 0
assert e.out.d.d[4].f 1
assert e.out.d.d[5].t 0
assert e.out.d.d[5].f 1
system "echo '[] Finish Neuron Handshake'"
set e.y[0].r 0
set e.x[0].r 0
cycle
assert e.e.Yarb.out.r 0
assert e.e.Xarb.out.r 0
set e.out.a 1
set e.out.v 1
cycle
assert e.e.Yarb.out.a 0
assert e.e.Xarb.out.a 0
assert e.y[0].a 0
assert e.x[0].a 0
set e.out.a 0
set e.out.v 0
cycle
system "echo '[] Neuron (0,0) Encoded'"

13
test/unit_tests/encoder2D_8x8/test.act
View File

@ -34,8 +34,14 @@ open std::data;
open tmpl::dataflow_neuro;
defproc encoder2D_2x2 (a1of1 x[8]; a1of1 y[8]; avMx1of2<6> out){
encoder2D<3, 3, 8, 8, 1> e(.x=x, .y=y, .out=out);
defproc encoder2d_2x2 (a1of1 x[8]; a1of1 y[8]; avMx1of2<6> out){
encoder2d_simple<3, 3, 8, 8, 0> e(.inx=x, .iny=y, .out=out);
e.to_pd_x = e.inx;
e.to_pd_y = e.iny;
bool _reset_B;
prs {
Reset => _reset_B-
@ -43,7 +49,6 @@ defproc encoder2D_2x2 (a1of1 x[8]; a1of1 y[8]; avMx1of2<6> out){
e.supply.vss = GND;
e.supply.vdd = Vdd;
e.reset_B = _reset_B;
}
encoder2D_2x2 e;
encoder2d_2x2 e;

266
test/unit_tests/encoder2D_8x8/test.prsim
View File

@ -1,5 +1,5 @@
watchall
mode run
# mode run
system "echo '[] Set Out Ack/Valid Low'"
@ -26,15 +26,10 @@ set e.x[4].r 0
set e.x[5].r 0
set e.x[6].r 0
set e.x[7].r 0
cycle
set Reset 1
# # Slightly confused as to whether Reset should be set to 1 given A_2C_RB_X1 needs active high to change y
# # status X
# # set Reset 1
# # cycle
cycle
mode run
status X
status 0
@ -49,9 +44,13 @@ set e.y[5].r 1
# set e.x[2].r 1
cycle
assert e.e.Yarb.out.r 1
assert e.e.Xarb.out.r 0
assert e.e._x_v 0
assert e.y[5].a 1
system "echo '[] Asserted y[5].a 1'"
# assert e.e.Yarb.out.r 1
# assert e.e.Xarb.out.r 0
# assert e.e._x_v 0
@ -59,14 +58,17 @@ system "echo '[] Raise x[2].r'"
# set e.y[5].r 1
set e.x[2].r 1
cycle
assert e.e.Yarb.out.r 1
assert e.e.Xarb.out.r 1
assert e.e._x_v 1
assert e.x[2].a 1
system "echo '[] Asserted x[2].a 1'"
# assert e.e.Yarb.out.r 1
# assert e.e.Xarb.out.r 1
# assert e.e._x_v 1
system "echo '[] Check Arbiter Acks'"
assert e.e._x_a_B 1
# assert e.e._x_a_B 1
assert e.y[0].a 0
assert e.y[1].a 0
@ -76,7 +78,7 @@ assert e.y[4].a 0
assert e.y[5].a 1
assert e.y[6].a 0
assert e.y[7].a 0
assert e.e.Yarb.out.a 1
# assert e.e.Yarb.out.a 1
assert e.x[0].a 0
@ -87,43 +89,11 @@ assert e.x[4].a 0
assert e.x[5].a 0
assert e.x[6].a 0
assert e.x[7].a 0
assert e.e.Xarb.out.a 1
system "echo '[] Check Encoders'"
assert e.e.x_enc_out.d[0].t 0
assert e.e.x_enc_out.d[0].f 1
assert e.e.x_enc_out.d[1].t 1
assert e.e.x_enc_out.d[1].f 0
assert e.e.x_enc_out.d[2].t 0
assert e.e.x_enc_out.d[2].f 1
assert e.e.y_enc_out.d[0].t 1
assert e.e.y_enc_out.d[0].f 0
assert e.e.y_enc_out.d[1].t 0
assert e.e.y_enc_out.d[1].f 1
assert e.e.y_enc_out.d[2].t 1
assert e.e.y_enc_out.d[2].f 0
system "echo '[] Check Buffer'"
assert e.e._in_x_v 1
assert e.e._in_y_v 1
assert e.e._en 1
assert e.out.d.d[0].t 0
assert e.out.d.d[0].f 1
assert e.out.d.d[1].t 1
assert e.out.d.d[1].f 0
assert e.out.d.d[2].t 0
assert e.out.d.d[2].f 1
assert e.out.d.d[3].t 1
assert e.out.d.d[3].f 0
assert e.out.d.d[4].t 0
assert e.out.d.d[4].f 1
assert e.out.d.d[5].t 1
assert e.out.d.d[5].f 0
# assert e.e.Xarb.out.a 1
assert-qdi-channel-valid "e.out" 6 42
system "echo '[] Asserted output encoding valid 42'"
set e.out.v 1
system "echo '[] Finish Neuron Handshake'"
@ -131,41 +101,7 @@ set e.y[5].r 0
set e.x[2].r 0
cycle
assert e.e.Yarb.out.r 0
assert e.e.Xarb.out.r 0
set e.out.a 1
set e.out.v 1
cycle
assert e.e.Yarb.out.a 0
assert e.e.Xarb.out.a 0
assert e.y[5].a 0
assert e.x[2].a 0
set e.out.a 0
set e.out.v 0
cycle
system "echo '[] Neuron (2,5) Encoded'"
system "echo '[] Single Neuron Spikes (0,0)'"
set e.y[0].r 1
set e.x[0].r 1
cycle
assert e.e.Yarb.out.r 1
assert e.e.Xarb.out.r 1
assert e.e._x_v 1
system "echo '[] Check Arbiter Acks'"
assert e.e._x_a_B 1
assert e.y[0].a 1
assert e.y[0].a 0
assert e.y[1].a 0
assert e.y[2].a 0
assert e.y[3].a 0
@ -173,10 +109,9 @@ assert e.y[4].a 0
assert e.y[5].a 0
assert e.y[6].a 0
assert e.y[7].a 0
assert e.e.Yarb.out.a 1
assert e.x[0].a 1
assert e.x[0].a 0
assert e.x[1].a 0
assert e.x[2].a 0
assert e.x[3].a 0
@ -184,63 +119,120 @@ assert e.x[4].a 0
assert e.x[5].a 0
assert e.x[6].a 0
assert e.x[7].a 0
assert e.e.Xarb.out.a 1
system "echo '[] Check Encoders'"
assert e.e.y_enc_out.d[0].t 0
assert e.e.y_enc_out.d[0].f 1
assert e.e.y_enc_out.d[1].t 0
assert e.e.y_enc_out.d[1].f 1
assert e.e.y_enc_out.d[2].t 0
assert e.e.y_enc_out.d[2].f 1
assert e.e.x_enc_out.d[0].t 0
assert e.e.x_enc_out.d[0].f 1
assert e.e.x_enc_out.d[1].t 0
assert e.e.x_enc_out.d[1].f 1
assert e.e.x_enc_out.d[2].t 0
assert e.e.x_enc_out.d[2].f 1
system "echo '[] Check Buffer'"
assert e.e._in_x_v 1
assert e.e._in_y_v 1
assert e.e._en 1
assert e.out.d.d[0].t 0
assert e.out.d.d[0].f 1
assert e.out.d.d[1].t 0
assert e.out.d.d[1].f 1
assert e.out.d.d[2].t 0
assert e.out.d.d[2].f 1
assert e.out.d.d[3].t 0
assert e.out.d.d[3].f 1
assert e.out.d.d[4].t 0
assert e.out.d.d[4].f 1
assert e.out.d.d[5].t 0
assert e.out.d.d[5].f 1
system "echo '[] Finish Neuron Handshake'"
set e.y[0].r 0
set e.x[0].r 0
cycle
assert e.e.Yarb.out.r 0
assert e.e.Xarb.out.r 0
system "echo '[] Asserted all in acks 0'"
set e.out.a 1
set e.out.v 1
cycle
assert e.e.Yarb.out.a 0
assert e.e.Xarb.out.a 0
assert e.y[0].a 0
assert e.x[0].a 0
assert-qdi-channel-neutral "e.out" 6
set e.out.a 0
set e.out.v 0
cycle
system "echo '[] Neuron (0,0) Encoded'"
system "echo '[] Neuron (2,5) Encoded'"
system "echo '[] Single Neuron Spikes (5,2), raise y[2].r'"
set e.y[2].r 1
# set e.x[2].r 1
cycle
assert e.y[2].a 1
system "echo '[] Asserted y[2].a 1'"
# assert e.e.Yarb.out.r 1
# assert e.e.Xarb.out.r 0
# assert e.e._x_v 0
system "echo '[] Raise x[5].r'"
# set e.y[5].r 1
set e.x[5].r 1
cycle
assert e.x[5].a 1
system "echo '[] Asserted x[5].a 1'"
# assert e.e.Yarb.out.r 1
# assert e.e.Xarb.out.r 1
# assert e.e._x_v 1
system "echo '[] Check Arbiter Acks'"
# assert e.e._x_a_B 1
assert e.y[0].a 0
assert e.y[1].a 0
assert e.y[2].a 1
assert e.y[3].a 0
assert e.y[4].a 0
assert e.y[5].a 0
assert e.y[6].a 0
assert e.y[7].a 0
# assert e.e.Yarb.out.a 1
assert e.x[0].a 0
assert e.x[1].a 0
assert e.x[2].a 0
assert e.x[3].a 0
assert e.x[4].a 0
assert e.x[5].a 1
assert e.x[6].a 0
assert e.x[7].a 0
# assert e.e.Xarb.out.a 1
assert-qdi-channel-valid "e.out" 6 21
system "echo '[] Asserted output encoding valid 21'"
set e.out.v 1
system "echo '[] Finish Neuron Handshake'"
set e.y[2].r 0
set e.x[5].r 0
cycle
assert e.y[0].a 0
assert e.y[1].a 0
assert e.y[2].a 0
assert e.y[3].a 0
assert e.y[4].a 0
assert e.y[5].a 0
assert e.y[6].a 0
assert e.y[7].a 0
assert e.x[0].a 0
assert e.x[1].a 0
assert e.x[2].a 0
assert e.x[3].a 0
assert e.x[4].a 0
assert e.x[5].a 0
assert e.x[6].a 0
assert e.x[7].a 0
system "echo '[] Asserted all in acks 0'"
set e.out.a 1
cycle
assert-qdi-channel-neutral "e.out" 6
set e.out.a 0
set e.out.v 0
cycle
system "echo '[] Neuron (5,2) Encoded'"

9
test/unit_tests/fifo3_8bit/test.act
View File

@ -1,9 +0,0 @@
import tmpl::dataflow_neuro
defproc fifo3_8bit (avMx1of2<8> A; avMx1of2<8> Y)
{
avMx1of2<8> _0to1,_1to2;
buffer<8> buf0 (.in=A, .out=_0to1);
buffer<8> buf1 (.in=_0to1, .out=_1to2);
buffer<8> buf2 (.in=_1to2, .out=Y);
}

39
test/unit_tests/fifo3_8bit/test.prsim
View File

@ -1,39 +0,0 @@
set-channel-neutral "t.A" 8
set t.Y.a 0
cycle
system "echo 'reset completed'"
status X
mode run
cycle
assert t.A.a 0
assert-channel-neutral "t.Y" 8
set-channel-valid "t.A" 8 2
system "echo 'sending first set A'"
cycle
assert t.A.a 1
set-channel-neutral "t.A" 8
cycle
assert t.A.a 0
system "echo 'checking first set'"
assert-channel-valid "t.Y" 8 2
set t.Y.a 1
cycle
assert-channel-neutral "t.Y" 8
set t.Y.a 0
system "echo 'sending second set'"
set-channel-valid "t.A" 8 95
cycle
assert t.A.a 1
set-channel-neutral "t.A" 8
cycle
system "echo 'checking second set'"
assert t.A.a 0
assert-channel-valid "t.Y" 8 95

203
test/unit_tests/texel_dualcore_glue_mapper/test.act
View File

@ -1,203 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/coders.act";
import "../../dataflow_neuro/primitives.act";
import "../../dataflow_neuro/chips.act";
import "../../dataflow_neuro/dummy.act";
import globals;
import std::data;
open std::data;
open tmpl::dataflow_neuro;
pint N_IN = 32;
pint N_NRN_X = 15;
pint N_NRN_Y = 6;
pint NC_NRN_X = 4;
pint NC_NRN_Y = 3;
pint N_SYN_X = 15;
pint N_SYN_Y = 348;
pint NC_SYN_X = 4;
pint NC_SYN_Y = 9;
pint N_SYN_DLY_CFG = 4;
pint N_BD_DLY_CFG = 4;
pint N_BD_DLY_CFG2 = 2;
pint N_NRN_MON_X = N_NRN_X*2; // [mon,kill]*N
pint N_NRN_MON_Y = N_NRN_Y; // [mon]*N
pint N_SYN_MON_X = N_SYN_X*4; // [mon, dev_mon, set, reset]*N
pint N_SYN_MON_Y = N_SYN_Y; // [mon]*N
pint N_MON_AMZO_PER_SYN = 5;
pint N_MON_AMZO_PER_NRN = 3;
pint N_FLAGS_PER_SYN = 5; // Syn: Must be at least 3 (since those ones have special safety)
pint N_FLAGS_PER_NRN = 3; // and leq than the number of bits in a reg, since have presumed only needs one.
pint N_BUFFERS = 3;
pint N_LINE_PD_DLY = 3;
pint REG_NCA = 6;
pint REG_M = 1<<REG_NCA;
pint REG_NCW = 23;
defproc chip_texel_dualcore (bd<N_IN> in, out;
Mx1of2<REG_NCW> c1_reg_data[REG_M];
a1of1 c1_synapses[N_SYN_X * N_SYN_Y];
a1of1 c1_neurons[N_NRN_X * N_NRN_Y];
bool! c1_dec_req_x[N_SYN_X], c1_dec_req_y[N_SYN_Y];
bool? c1_dec_ackB[N_SYN_X];
a1of1 c1_syn_pu[N_SYN_X];
a1of1 c1_enc_inx[N_NRN_X], c1_enc_iny[N_NRN_Y];
a1of1 c1_nrn_pd_x[N_NRN_X], c1_nrn_pd_y[N_NRN_Y];
bool! c1_nrn_mon_x[N_NRN_MON_X], c1_nrn_mon_y[N_NRN_MON_Y];
bool! c1_syn_mon_x[N_SYN_MON_X], c1_syn_mon_y[N_SYN_MON_Y];
bool? c1_syn_mon_AMZI[N_SYN_X * N_MON_AMZO_PER_SYN], c1_nrn_mon_AMZI[N_NRN_X * N_MON_AMZO_PER_NRN];
bool! c1_syn_mon_AMZO[N_MON_AMZO_PER_SYN], c1_nrn_mon_AMZO[N_MON_AMZO_PER_NRN];
bool! c1_syn_flags_EFO[N_FLAGS_PER_SYN], c1_nrn_flags_EFO[N_FLAGS_PER_NRN];
bool! c1_reset_nrn_hs_BO[N_NRN_X], c1_reset_syn_hs_BO[N_SYN_X],
c1_reset_nrn_stge_BO[N_NRN_X], c1_reset_syn_stge_BO[N_SYN_X];
Mx1of2<REG_NCW> c2_reg_data[REG_M];
a1of1 c2_synapses[N_SYN_X * N_SYN_Y];
a1of1 c2_neurons[N_NRN_X * N_NRN_Y];
bool! c2_dec_req_x[N_SYN_X], c2_dec_req_y[N_SYN_Y];
bool? c2_dec_ackB[N_SYN_X];
a1of1 c2_syn_pu[N_SYN_X];
a1of1 c2_enc_inx[N_NRN_X], c2_enc_iny[N_NRN_Y];
a1of1 c2_nrn_pd_x[N_NRN_X], c2_nrn_pd_y[N_NRN_Y];
bool! c2_nrn_mon_x[N_NRN_MON_X], c2_nrn_mon_y[N_NRN_MON_Y];
bool! c2_syn_mon_x[N_SYN_MON_X], c2_syn_mon_y[N_SYN_MON_Y];
bool? c2_syn_mon_AMZI[N_SYN_X * N_MON_AMZO_PER_SYN], c2_nrn_mon_AMZI[N_NRN_X * N_MON_AMZO_PER_NRN];
bool! c2_syn_mon_AMZO[N_MON_AMZO_PER_SYN], c2_nrn_mon_AMZO[N_MON_AMZO_PER_NRN];
bool! c2_syn_flags_EFO[N_FLAGS_PER_SYN], c2_nrn_flags_EFO[N_FLAGS_PER_NRN];
bool! c2_reset_nrn_hs_BO[N_NRN_X], c2_reset_syn_hs_BO[N_SYN_X],
c2_reset_nrn_stge_BO[N_NRN_X], c2_reset_syn_stge_BO[N_SYN_X];
bool! reset_B, reset_reg_B, reset_syn_stge_BI;
bool? bd_dly_cfg[N_BD_DLY_CFG], bd_dly_cfg2[N_BD_DLY_CFG2];
bool? loopback_en;
bool? mapper_en;
avMx1of2<30> out_sram_wr; // Input packets to go to SRAM (rw word addr)
avMx1of2<8> out_sram_spk; // Spike packets from enc to go to SRAM (core-nrn addr)
avMx1of2<29> in_sram_r; // Readout packets from SRAM (data only)
avMx1of2<14> in_sram_spk // Spike packets from SRAM (core-syn addr)
){
bool _reset_B;
prs {
Reset => _reset_B-
}
power supply;
supply.vdd = Vdd;
supply.vss = GND;
texel_dualcore_mapper<N_IN,
N_NRN_X, N_NRN_Y, N_SYN_X, N_SYN_Y,
NC_NRN_X, NC_NRN_Y, NC_SYN_X, NC_SYN_Y,
N_SYN_DLY_CFG,
N_NRN_MON_X, N_NRN_MON_Y, N_SYN_MON_X, N_SYN_MON_Y,
N_MON_AMZO_PER_SYN, N_MON_AMZO_PER_NRN,
N_FLAGS_PER_SYN, N_FLAGS_PER_NRN,
N_BUFFERS,
N_LINE_PD_DLY,
N_BD_DLY_CFG, N_BD_DLY_CFG2,
REG_NCA, REG_NCW, REG_M> c(.in = in, .out = out,
.c1_reg_data = c1_reg_data, .c1_dec_req_x = c1_dec_req_x, .c1_dec_req_y = c1_dec_req_y, .c1_dec_ackB = c1_dec_ackB, .c1_syn_pu = c1_syn_pu, .c1_enc_inx = c1_enc_inx, .c1_enc_iny = c1_enc_iny, .c1_nrn_pd_x = c1_nrn_pd_x, .c1_nrn_pd_y = c1_nrn_pd_y, .c1_nrn_mon_x = c1_nrn_mon_x, .c1_nrn_mon_y = c1_nrn_mon_y, .c1_syn_mon_x = c1_syn_mon_x, .c1_syn_mon_y = c1_syn_mon_y, .c1_syn_mon_AMZI = c1_syn_mon_AMZI, .c1_nrn_mon_AMZI = c1_nrn_mon_AMZI, .c1_syn_mon_AMZO = c1_syn_mon_AMZO, .c1_nrn_mon_AMZO = c1_nrn_mon_AMZO, .c1_syn_flags_EFO = c1_syn_flags_EFO, .c1_nrn_flags_EFO = c1_nrn_flags_EFO, .c1_reset_nrn_hs_BO = c1_reset_nrn_hs_BO, .c1_reset_syn_hs_BO = c1_reset_syn_hs_BO, .c1_reset_nrn_stge_BO = c1_reset_nrn_stge_BO, .c1_reset_syn_stge_BO = c1_reset_syn_stge_BO, .c2_reg_data = c2_reg_data, .c2_dec_req_x = c2_dec_req_x, .c2_dec_req_y = c2_dec_req_y, .c2_dec_ackB = c2_dec_ackB, .c2_syn_pu = c2_syn_pu, .c2_enc_inx = c2_enc_inx, .c2_enc_iny = c2_enc_iny, .c2_nrn_pd_x = c2_nrn_pd_x, .c2_nrn_pd_y = c2_nrn_pd_y, .c2_nrn_mon_x = c2_nrn_mon_x, .c2_nrn_mon_y = c2_nrn_mon_y, .c2_syn_mon_x = c2_syn_mon_x, .c2_syn_mon_y = c2_syn_mon_y, .c2_syn_mon_AMZI = c2_syn_mon_AMZI, .c2_nrn_mon_AMZI = c2_nrn_mon_AMZI, .c2_syn_mon_AMZO = c2_syn_mon_AMZO, .c2_nrn_mon_AMZO = c2_nrn_mon_AMZO, .c2_syn_flags_EFO = c2_syn_flags_EFO, .c2_nrn_flags_EFO = c2_nrn_flags_EFO, .c2_reset_nrn_hs_BO = c2_reset_nrn_hs_BO, .c2_reset_syn_hs_BO = c2_reset_syn_hs_BO, .c2_reset_nrn_stge_BO = c2_reset_nrn_stge_BO, .c2_reset_syn_stge_BO = c2_reset_syn_stge_BO,
.bd_dly_cfg = bd_dly_cfg, .bd_dly_cfg2 = bd_dly_cfg2,
.loopback_en = loopback_en,
.mapper_en = mapper_en,
.out_sram_wr = out_sram_wr, .out_sram_spk = out_sram_spk,
.in_sram_r = in_sram_r, .in_sram_spk = in_sram_spk,
.reset_B = reset_B, .reset_reg_B = reset_reg_B, .reset_syn_stge_BI = reset_syn_stge_BI,
.supply = supply);
pint N_NRN = N_NRN_X * N_NRN_Y;
pint N_SYN_PER_NRN = (N_SYN_X * N_SYN_Y)/N_NRN;
dummy_neuron_core<N_SYN_PER_NRN, N_NRN, N_NRN_X> c1_dummy_neuron_core(.synapses = c1_synapses, .neurons = c1_neurons,
.supply = supply);
dummy_neuron_core<N_SYN_PER_NRN, N_NRN, N_NRN_X> c2_dummy_neuron_core(.synapses = c2_synapses, .neurons = c2_neurons,
.supply = supply);
decoder_2d_synapse_hs<N_SYN_X, N_SYN_Y> c1_syn_grid(
.synapses = c1_synapses,
.in_req_x = c1_dec_req_x, .in_req_y = c1_dec_req_y,
.to_pu = c1_syn_pu,
.out_ackB_decoder = c1_dec_ackB,
.supply = supply);
nrn_hs_2d_array<N_NRN_X,N_NRN_Y> c1_nrn_grid(.in = c1_neurons,
.outx = c1_enc_inx, .outy = c1_enc_iny,
.to_pd_x = c1_nrn_pd_x, .to_pd_y = c1_nrn_pd_y,
.supply = supply, .reset_B = _reset_B);
decoder_2d_synapse_hs<N_SYN_X, N_SYN_Y> c2_syn_grid(
.synapses = c2_synapses,
.in_req_x = c2_dec_req_x, .in_req_y = c2_dec_req_y,
.to_pu = c2_syn_pu,
.out_ackB_decoder = c2_dec_ackB,
.supply = supply);
nrn_hs_2d_array<N_NRN_X,N_NRN_Y> c2_nrn_grid(.in = c2_neurons,
.outx = c2_enc_inx, .outy = c2_enc_iny,
.to_pd_x = c2_nrn_pd_x, .to_pd_y = c2_nrn_pd_y,
.supply = supply, .reset_B = _reset_B);
}
// fifo_decoder_neurons_encoder_fifo e;
chip_texel_dualcore c;

8763
test/unit_tests/texel_dualcore_glue_mapper/test.prsim
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