removed texel dualcore mapper, never used
This commit is contained in:
alexmadison
parent
200088fb0a
commit
8b37b91891
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@ -545,238 +545,6 @@ defproc texel_dualcore (bd<N_IN> in, out;
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export template<pint N_IN, // Size of input data from outside world
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N_NRN_X, N_NRN_Y, N_SYN_X, N_SYN_Y, // Number of neurons / synapses
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NC_NRN_X, NC_NRN_Y, NC_SYN_X, NC_SYN_Y,
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N_SYN_DLY_CFG,
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N_NRN_MON_X, N_NRN_MON_Y, N_SYN_MON_X, N_SYN_MON_Y,
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N_MON_AMZO_PER_SYN, N_MON_AMZO_PER_NRN, // Number of signals that each synapse outputs to be monitored.
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N_FLAGS_PER_SYN, N_FLAGS_PER_NRN, // Number of signals that each nrn/syn recieves from the register.
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N_BUFFERS,
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N_LINE_PD_DLY, // Number of dummy delays to add line pull down
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N_BD_DLY_CFG, N_BD_DLY_CFG2,
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REG_NCA, REG_NCW, REG_M>
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defproc texel_dualcore_mapper (bd<N_IN> in, out;
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Mx1of2<REG_NCW> c1_reg_data[REG_M];
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bool! c1_dec_req_x[N_SYN_X], c1_dec_req_y[N_SYN_Y];
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bool? c1_dec_ackB[N_SYN_X];
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a1of1 c1_syn_pu[N_SYN_X];
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a1of1 c1_enc_inx[N_NRN_X], c1_enc_iny[N_NRN_Y];
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a1of1 c1_nrn_pd_x[N_NRN_X], c1_nrn_pd_y[N_NRN_Y];
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bool! c1_nrn_mon_x[N_NRN_MON_X], c1_nrn_mon_y[N_NRN_MON_Y];
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bool! c1_syn_mon_x[N_SYN_MON_X], c1_syn_mon_y[N_SYN_MON_Y];
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bool? c1_syn_mon_AMZI[N_SYN_X * N_MON_AMZO_PER_SYN], c1_nrn_mon_AMZI[N_NRN_X * N_MON_AMZO_PER_NRN];
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bool! c1_syn_mon_AMZO[N_MON_AMZO_PER_SYN], c1_nrn_mon_AMZO[N_MON_AMZO_PER_NRN];
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bool! c1_syn_flags_EFO[N_FLAGS_PER_SYN], c1_nrn_flags_EFO[N_FLAGS_PER_NRN];
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bool! c1_reset_nrn_hs_BO[N_NRN_X], c1_reset_syn_hs_BO[N_SYN_X],
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c1_reset_nrn_stge_BO[N_NRN_X], c1_reset_syn_stge_BO[N_SYN_X];
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Mx1of2<REG_NCW> c2_reg_data[REG_M];
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bool! c2_dec_req_x[N_SYN_X], c2_dec_req_y[N_SYN_Y];
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bool? c2_dec_ackB[N_SYN_X];
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a1of1 c2_syn_pu[N_SYN_X];
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a1of1 c2_enc_inx[N_NRN_X], c2_enc_iny[N_NRN_Y];
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a1of1 c2_nrn_pd_x[N_NRN_X], c2_nrn_pd_y[N_NRN_Y];
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bool! c2_nrn_mon_x[N_NRN_MON_X], c2_nrn_mon_y[N_NRN_MON_Y];
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bool! c2_syn_mon_x[N_SYN_MON_X], c2_syn_mon_y[N_SYN_MON_Y];
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bool? c2_syn_mon_AMZI[N_SYN_X * N_MON_AMZO_PER_SYN], c2_nrn_mon_AMZI[N_NRN_X * N_MON_AMZO_PER_NRN];
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bool! c2_syn_mon_AMZO[N_MON_AMZO_PER_SYN], c2_nrn_mon_AMZO[N_MON_AMZO_PER_NRN];
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bool! c2_syn_flags_EFO[N_FLAGS_PER_SYN], c2_nrn_flags_EFO[N_FLAGS_PER_NRN];
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bool! c2_reset_nrn_hs_BO[N_NRN_X], c2_reset_syn_hs_BO[N_SYN_X],
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c2_reset_nrn_stge_BO[N_NRN_X], c2_reset_syn_stge_BO[N_SYN_X];
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bool? bd_dly_cfg[N_BD_DLY_CFG], bd_dly_cfg2[N_BD_DLY_CFG2];
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bool? loopback_en;
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power supply;
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bool? reset_B, reset_reg_B, reset_syn_stge_BI;
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// MAPPER STUFF
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bool? mapper_en;
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avMx1of2<30> out_sram_wr; // Input packets to go to SRAM (rw word addr)
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avMx1of2<8> out_sram_spk; // Spike packets from enc to go to SRAM (core-nrn addr)
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avMx1of2<29> in_sram_r; // Readout packets from SRAM
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avMx1of2<14> in_sram_spk // Spike packets from SRAM (core-syn addr)
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){
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// Reset buffers
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bool _reset_BX;
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BUF_X12 reset_buf(.a = reset_B, .y = _reset_BX, .vdd = supply.vdd, .vss = supply.vss);
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bd2qdi<N_IN, N_BD_DLY_CFG, N_BD_DLY_CFG2> _bd2qdi(.in = in, .dly_cfg = bd_dly_cfg, .dly_cfg2 = bd_dly_cfg2,
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.reset_B = _reset_BX, .supply = supply);
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fifo<N_IN,N_BUFFERS> fifo_in2fork(.in = _bd2qdi.out, .reset_B = _reset_BX, .supply = supply);
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fork<N_IN> _fork(.in = fifo_in2fork.out, .reset_B = _reset_BX, .supply = supply);
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// Loopback
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fifo<N_IN,N_BUFFERS> fifo_fork2drop(.in = _fork.out1, .reset_B = _reset_BX, .supply = supply);
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dropper_static<N_IN, false> _loopback_dropper(.in = fifo_fork2drop.out, .cond = loopback_en,
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.supply = supply);
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fifo<N_IN,N_BUFFERS> fifo_drop2mrg(.in = _loopback_dropper.out, .reset_B = _reset_BX, .supply = supply);
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// dmx to SRAM
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bool is_to_sram, is_to_cores;
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fifo<32, N_BUFFERS> fifo_fork2sramdmx(.in = _fork.out2, .supply = supply, .reset_B = _reset_BX);
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demux<32> sram_dmx(.in = fifo_fork2sramdmx.out, .supply = supply, .reset_B = _reset_BX);
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sram_dmx.cond.d.d[0].t = is_to_sram;
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sram_dmx.cond.d.d[0].f = is_to_cores;
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AND2_X1 sram_dmx_and(.a = sram_dmx.in.d.d[30].f, .b = sram_dmx.in.d.d[29].t,
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.y = is_to_sram,
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.vdd = supply.vdd, .vss = supply.vss);
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OR3_X1 sram_dmx_or(.a = sram_dmx.in.d.d[30].t, .b = sram_dmx.in.d.d[30].t, .c = sram_dmx.in.d.d[29].f,
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.y = is_to_cores,
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.vdd = supply.vdd, .vss = supply.vss);
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slice_data<32, 0, 30> pre_sram_slice(.supply = supply);
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pre_sram_slice.in.a = sram_dmx.out2.a;
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pre_sram_slice.in.v = sram_dmx.out2.v;
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(i:29:pre_sram_slice.in.d.d[i] = sram_dmx.out2.d.d[i];)
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pre_sram_slice.in.d.d[29] = sram_dmx.out2.d.d[31];
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pre_sram_slice.in.d.d[30] = sram_dmx.out2.d.d[30];
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pre_sram_slice.in.d.d[31] = sram_dmx.out2.d.d[29];
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fifo<30, N_BUFFERS> fifo_out_sram_wr(.in = pre_sram_slice.out, .out = out_sram_wr,
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.reset_B = _reset_BX, .supply = supply);
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// spikes from sram
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// requires weird merging because [core, syny, synx] needs to go to [core, ZEROES, syny, synx]
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fifo<14, N_BUFFERS> fifo_in_sram_spk(.in = in_sram_spk, .reset_B = _reset_BX, .supply = supply);
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append<14,32,0> sram_spk_in_append(.in = fifo_in_sram_spk.out, .supply = supply);
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merge<32> merge_dmx8spk(.in1 = sram_dmx.out1, .reset_B = _reset_BX, .supply = supply);
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merge_dmx8spk.in2.a = sram_spk_in_append.out.a;
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merge_dmx8spk.in2.v = sram_spk_in_append.out.v;
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(i:13: merge_dmx8spk.in2.d.d[i] = sram_spk_in_append.out.d.d[i];)
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merge_dmx8spk.in2.d.d[31] = sram_spk_in_append.out.d.d[13];
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(i:13..30: merge_dmx8spk.in2.d.d[i] = sram_spk_in_append.out.d.d[i+1];)
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// Onwards to core demux
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fifo<N_IN,N_BUFFERS> fifo_fork2dmx(.in = merge_dmx8spk.out, .reset_B = _reset_BX, .supply = supply);
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demux_bit_msb<N_IN-1> core_dmx(.in = fifo_fork2dmx.out, .reset_B = _reset_BX, .supply = supply);
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fifo<N_IN-1,N_BUFFERS> fifo_dmx2core1(.in = core_dmx.out1, .reset_B = _reset_BX, .supply = supply);
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fifo<N_IN-1,N_BUFFERS> fifo_dmx2core2(.in = core_dmx.out2, .reset_B = _reset_BX, .supply = supply);
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// Cores
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texel_core<N_IN-1,N_NRN_X, N_NRN_Y, N_SYN_X, N_SYN_Y,NC_NRN_X, NC_NRN_Y, NC_SYN_X, NC_SYN_Y,N_SYN_DLY_CFG,N_NRN_MON_X, N_NRN_MON_Y, N_SYN_MON_X, N_SYN_MON_Y,N_MON_AMZO_PER_SYN, N_MON_AMZO_PER_NRN,N_FLAGS_PER_SYN, N_FLAGS_PER_NRN,N_BUFFERS,N_LINE_PD_DLY, REG_NCA, REG_NCW, REG_M>
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core1(.in = fifo_dmx2core1.out,
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.reg_data = c1_reg_data,
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// .synapses = c1_synapses,
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// .neurons = c1_neurons,
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.dec_req_x = c1_dec_req_x, .dec_req_y = c1_dec_req_y,
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.dec_ackB = c1_dec_ackB,
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.syn_pu = c1_syn_pu,
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.enc_inx = c1_enc_inx, .enc_iny = c1_enc_iny,
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.nrn_pd_x = c1_nrn_pd_x, .nrn_pd_y = c1_nrn_pd_y,
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.nrn_mon_x = c1_nrn_mon_x, .nrn_mon_y = c1_nrn_mon_y,
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.syn_mon_x = c1_syn_mon_x, .syn_mon_y = c1_syn_mon_y,
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.syn_mon_AMZI = c1_syn_mon_AMZI, .nrn_mon_AMZI = c1_nrn_mon_AMZI,
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.syn_mon_AMZO = c1_syn_mon_AMZO, .nrn_mon_AMZO = c1_nrn_mon_AMZO,
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.syn_flags_EFO = c1_syn_flags_EFO, .nrn_flags_EFO = c1_nrn_flags_EFO,
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.reset_B = _reset_BX, .reset_reg_B = reset_reg_B, .reset_syn_stge_BI = reset_syn_stge_BI,
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.reset_syn_hs_BO = c1_reset_syn_hs_BO, .reset_syn_stge_BO = c1_reset_syn_stge_BO,
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.reset_nrn_hs_BO = c1_reset_nrn_hs_BO, .reset_nrn_stge_BO = c1_reset_nrn_stge_BO,
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.supply = supply
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);
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texel_core<N_IN-1,N_NRN_X, N_NRN_Y, N_SYN_X, N_SYN_Y,NC_NRN_X, NC_NRN_Y, NC_SYN_X, NC_SYN_Y,N_SYN_DLY_CFG,N_NRN_MON_X, N_NRN_MON_Y, N_SYN_MON_X, N_SYN_MON_Y,N_MON_AMZO_PER_SYN, N_MON_AMZO_PER_NRN,N_FLAGS_PER_SYN, N_FLAGS_PER_NRN,N_BUFFERS,N_LINE_PD_DLY, REG_NCA, REG_NCW, REG_M>
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core2(.in = fifo_dmx2core2.out,
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.reg_data = c2_reg_data,
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// .synapses = c2_synapses,
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// .neurons = c2_neurons,
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.dec_req_x = c2_dec_req_x, .dec_req_y = c2_dec_req_y,
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.dec_ackB = c2_dec_ackB,
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.syn_pu = c2_syn_pu,
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.enc_inx = c2_enc_inx, .enc_iny = c2_enc_iny,
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.nrn_pd_x = c2_nrn_pd_x, .nrn_pd_y = c2_nrn_pd_y,
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.nrn_mon_x = c2_nrn_mon_x, .nrn_mon_y = c2_nrn_mon_y,
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.syn_mon_x = c2_syn_mon_x, .syn_mon_y = c2_syn_mon_y,
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.syn_mon_AMZI = c2_syn_mon_AMZI, .nrn_mon_AMZI = c2_nrn_mon_AMZI,
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.syn_mon_AMZO = c2_syn_mon_AMZO, .nrn_mon_AMZO = c2_nrn_mon_AMZO,
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.syn_flags_EFO = c2_syn_flags_EFO, .nrn_flags_EFO = c2_nrn_flags_EFO,
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.reset_B = _reset_BX, .reset_reg_B = reset_reg_B, .reset_syn_stge_BI = reset_syn_stge_BI,
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.reset_syn_hs_BO = c2_reset_syn_hs_BO, .reset_syn_stge_BO = c2_reset_syn_stge_BO,
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.reset_nrn_hs_BO = c2_reset_nrn_hs_BO, .reset_nrn_stge_BO = c2_reset_nrn_stge_BO,
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.supply = supply
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);
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fifo<N_IN-1,N_BUFFERS> fifo_core1out(.in = core1.out, .reset_B = _reset_BX, .supply = supply);
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fifo<N_IN-1,N_BUFFERS> fifo_core2out(.in = core2.out, .reset_B = _reset_BX, .supply = supply);
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// Merge cores
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append<N_IN-1, 1, 0> append_core1(.in = fifo_core1out.out, .supply = supply);
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append<N_IN-1, 1, 1> append_core2(.in = fifo_core2out.out, .supply = supply);
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merge<N_IN> merge_core1x2(.in1 = append_core1.out, .in2 = append_core2.out,
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.supply = supply, .reset_B = _reset_BX);
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// fork after core merge then go to mapper if its a spike
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fifo<32, N_BUFFERS> fifo_core2fork(.in = merge_core1x2.out, .reset_B = _reset_BX, .supply = supply);
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fork<32> postcore_fork(.in = fifo_core2fork.out, .reset_B = _reset_BX, .supply = supply);
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dropper_static<32, false> sram_dropper(.in = postcore_fork.out1, .cond = mapper_en, .supply = supply);
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// Need to have it then drop the spike if its from a register.
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demux_td<32, true> drop_if_reg(.in = sram_dropper.out, .reset_B = _reset_BX, .supply = supply); // if cond true, go out on data
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drop_if_reg.cond.d.d[0] = sram_dropper.out.d.d[30];
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drop_if_reg.token.r = drop_if_reg.token.a;
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slice_data<32,0,8> slice_to_sram(.supply = supply);
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// And move the msb (core bit) to just after the neuron address...
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slice_to_sram.in.a = drop_if_reg.out.a;
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slice_to_sram.in.v = drop_if_reg.out.v;
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(i:7:slice_to_sram.in.d.d[i] = drop_if_reg.out.d.d[i];)
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slice_to_sram.in.d.d[7] = drop_if_reg.out.d.d[31];
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(i:7..30: slice_to_sram.in.d.d[i+1] = drop_if_reg.out.d.d[i];)
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fifo<8,N_BUFFERS> fifo_out_sram_spk(.in = slice_to_sram.out, .out = out_sram_spk,
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.reset_B = _reset_BX, .supply = supply);
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// merge from cores and sram read in
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fifo<29, N_BUFFERS> fifo_in_sram_r(.in = in_sram_r, .reset_B = _reset_BX, .supply = supply);
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fifo<32, N_BUFFERS> fifo_fork2mrg(.in = postcore_fork.out2, .reset_B = _reset_BX, .supply = supply);
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append<29,3,2> sram_read_in_append(.in = fifo_in_sram_r.out, .supply = supply);
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merge<32> merge_sram8core(.in1 = fifo_fork2mrg.out, .in2 = sram_read_in_append.out,
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.reset_B = _reset_BX, .supply = supply);
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// Merge cores and loopback
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fifo<32, N_BUFFERS> fifo_mrg2mrg(.in = merge_sram8core.out, .reset_B = _reset_BX, .supply = supply);
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merge<N_IN> merge_drop8core(.in1 = fifo_mrg2mrg.out, .in2 = fifo_drop2mrg.out,
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.reset_B = _reset_BX, .supply = supply);
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// qdi2bd
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fifo<N_IN, N_BUFFERS> fifo_mrg2bd(.in = merge_drop8core.out,
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.reset_B = _reset_BX, .supply = supply);
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qdi2bd<N_IN, N_BD_DLY_CFG> _qdi2bd(.in = fifo_mrg2bd.out, .out = out, .dly_cfg = bd_dly_cfg,
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.reset_B = _reset_BX, .supply = supply);
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}
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