dataflow_neuro/interfaces.act

@@ -60,9 +60,9 @@ namespace tmpl {
             sigbuf<N> reset_bufarray(.in=_reset_BX, .out=_reset_BXX, .supply=supply);
 
             // sig buff the req
-			bool _reqX, _reqXX[N+1];
+			bool _reqX, _reqXX[N];
 			BUF_X4 req_buf(.a=_req, .y=_reqX,.vdd=supply.vdd,.vss=supply.vss);
-            sigbuf<N+1> req_bufarray(.in=_reqX, .out=_reqXX, .supply=supply);
+            sigbuf<N> req_bufarray(.in=_reqX, .out=_reqXX, .supply=supply);
 
             // bd2qdi conversion
             // Each line goes to a t pin, its not to a f.
@@ -89,7 +89,7 @@ namespace tmpl {
 
             //control
             bool _en;
-            A_3C_RB_X4 inack_ctl(.c1=_en,.c2=_reqXX[N],.c3=out.v,.y=in.a,.pr_B=_reset_BX,.sr_B=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
+            A_3C_RB_X4 inack_ctl(.c1=_en,.c2=_reqX,.c3=out.v,.y=in.a,.pr_B=_reset_BX,.sr_B=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
             A_1C1P_X1 en_ctl(.c1=in.a,.p1=out.v,.y=_en,.vdd=supply.vdd,.vss=supply.vss);
 
             //function

dataflow_neuro/primitives.act

@@ -286,8 +286,8 @@ namespace tmpl {
                 out1_t_buf_func[i].sr_B = _reset_BXX[i];
                 out1_f_buf_func[i].pr_B = _reset_BXX[i];
                 out1_f_buf_func[i].sr_B = _reset_BXX[i];
-                out1_f_buf_func[i].n2=_c_f_buf[i];
+                out1_f_buf_func[i].n2=_c_t_buf[i];
-                out1_t_buf_func[i].n2=_c_f_buf[i];
+                out1_t_buf_func[i].n2=_c_t_buf[i];
             )
 
             //func buffer out2
@@ -316,8 +316,8 @@ namespace tmpl {
                 out2_t_buf_func[i].sr_B = _reset_BXX[i+N-1];
                 out2_f_buf_func[i].pr_B = _reset_BXX[i+N-1];
                 out2_f_buf_func[i].sr_B = _reset_BXX[i+N-1];
-                out2_f_buf_func[i].n2=_c_t_buf[i];
+                out2_f_buf_func[i].n2=_c_f_buf[i];
-                out2_t_buf_func[i].n2=_c_t_buf[i];
+                out2_t_buf_func[i].n2=_c_f_buf[i];
             )
         }
 
@@ -850,18 +850,14 @@ defproc slice_data(avMx1of2<N> in; avMx1of2<std::min(N1,N)-std::max(N0,0)> out;
     _N1 = std::min(N1,N);
     _N0 = std::max(N0,0);
 
-
+    BUF_X1 ack_buf(.a = out.a, .y = in.a, .vss = supply.vss, .vdd = supply.vdd);
-    // BUF_X1 ack_buf(.a = out.a, .y = in.a, .vss = supply.vss, .vdd = supply.vdd);
 
     vtree<N> in_vt(.in = in.d, .out = in.v, .supply = supply);
     (i:_N1-_N0:
         in.d.d[i + _N0] = out.d.d[i];
     )
 
-    // in.a = out.a;
+    in.a = out.a;
-
-    A_2C_B_X1 Cel(.c1 = out.a, .c2 =in.v, .y = in.a, .vss = supply.vss, .vdd = supply.vdd);
-
 }
 
 

test/unit_tests/chip_nomap/test.act

@@ -39,7 +39,7 @@ open std::data;
 open tmpl::dataflow_neuro;
 
 defproc chip_texel_test (bd<14> in; bd<14> out; Mx1of2<8> reg_data[16];
-    bool? bd_dly_cfg[4], bd_dly_cfg2[2], loopback_en){
+    bool? bd_dly_cfg[4], loopback_en){
 
     bool _reset_B; 
     prs {
@@ -67,7 +67,6 @@ defproc chip_texel_test (bd<14> in; bd<14> out; Mx1of2<8> reg_data[16];
 
     pint N_SYN_DLY_CFG = 4;
     pint N_BD_DLY_CFG = 4;
-    pint N_BD_DLY_CFG2 = 2;
 
     pint N_NRN_MON_X = 2;
     pint N_NRN_MON_Y = 4;
@@ -89,23 +88,12 @@ defproc chip_texel_test (bd<14> in; bd<14> out; Mx1of2<8> reg_data[16];
     N_NRN_MON_X, N_NRN_MON_Y, N_SYN_MON_X, N_SYN_MON_Y,
     N_BUFFERS,
     N_LINE_PD_DLY,
-    N_BD_DLY_CFG, N_BD_DLY_CFG2,
+    N_BD_DLY_CFG,
     REG_NCA, REG_NCW, REG_M> c(.in = in, .out = out, .reg_data = reg_data,
-        .bd_dly_cfg = bd_dly_cfg, .bd_dly_cfg2 = bd_dly_cfg2, .loopback_en = loopback_en,
+        .bd_dly_cfg = bd_dly_cfg, .loopback_en = loopback_en,
         .reset_B = _reset_B, .supply = supply);
 
-    // Spawn in some buffers as a conduit between neurons and synapses.
+    c.synapses = c.neurons; // Connect each synapse hs to a neuron hs
-    pint N_SYNS = N_SYN_X * N_SYN_Y;
-    BUF_X4 syn2nrns_r[N_SYNS];
-    BUF_X4 syn2nrns_a[N_SYNS];
-    (i:N_SYNS:
-        syn2nrns_r[i].a = c.synapses[i].r;
-        syn2nrns_r[i].y = c.neurons[i].r;
-    
-        syn2nrns_a[i].a = c.neurons[i].a;
-        syn2nrns_a[i].y = c.synapses[i].a;
-    )
-    // c.synapses = c.neurons; // Connect each synapse hs to a neuron hs
 
 }
 

test/unit_tests/chip_nomap/test.prsim

@@ -6,10 +6,8 @@ set c.bd_dly_cfg[1] 1
 set c.bd_dly_cfg[2] 1
 set c.bd_dly_cfg[3] 1
 
-set c.bd_dly_cfg2[0] 1
-set c.bd_dly_cfg2[1] 1
-
 set-bd-channel-neutral "c.in" 14
+# set-bd-channel-neutral "c.out" 14
 set c.out.a 0
 set c.loopback_en 1
 set Reset 1
@@ -23,96 +21,6 @@ status X
 set Reset 0
 cycle
 
-# Reading address 0
+set-bd-channel-valid "c.in" 14 16128
-set c.in.d[0] 0
-set c.in.d[1] 0
-set c.in.d[2] 0
-set c.in.d[3] 0
-set c.in.d[4] 0
-set c.in.d[5] 0
-set c.in.d[6] 0
-set c.in.d[7] 0
-set c.in.d[8] 0
-set c.in.d[9] 0
-set c.in.d[10] 0
-set c.in.d[11] 0
-set c.in.d[12] 0
-set c.in.d[13] 1
 cycle
-set c.in.r 1
+assert-bd-channel-valid "c.out" 14 16128
-cycle
-assert c.in.a 1
-
-# Remove input
-set-bd-channel-neutral "c.in" 14
-cycle
-assert c.in.a 0
-
-# Should first get loopback
-assert-bd-channel-valid "c.out" 14 8192
-set c.out.a 1
-cycle
-assert-bd-channel-neutral "c.out" 14
-set c.out.a 0
-cycle
-
-# Expect register read packet to arrive
-assert-bd-channel-valid "c.out" 14 4080
-set c.out.a 1
-cycle
-assert-bd-channel-neutral "c.out" 14
-set c.out.a 0
-cycle
-
-# Disable loopback cus it's annoying
-set c.loopback_en 0
-cycle
-
-# Writing 68 to address 1
-set c.in.d[0] 1
-set c.in.d[1] 0
-set c.in.d[2] 0
-set c.in.d[3] 0
-set c.in.d[4] 0
-set c.in.d[5] 0
-set c.in.d[6] 1
-set c.in.d[7] 0
-set c.in.d[8] 0
-set c.in.d[9] 0
-set c.in.d[10] 1
-set c.in.d[11] 0
-set c.in.d[12] 1
-set c.in.d[13] 1
-cycle
-set c.in.r 1
-cycle
-assert c.in.a 1
-
-# Remove input
-set-bd-channel-neutral "c.in" 14
-cycle
-assert c.in.a 0
-
-
-# Reading address 1
-set c.in.d[0] 1
-set c.in.d[1] 0
-set c.in.d[2] 0
-set c.in.d[3] 0
-set c.in.d[4] 0
-set c.in.d[5] 0
-set c.in.d[6] 0
-set c.in.d[7] 0
-set c.in.d[8] 0
-set c.in.d[9] 0
-set c.in.d[10] 0
-set c.in.d[11] 0
-set c.in.d[12] 0
-set c.in.d[13] 1
-cycle
-set c.in.r 1
-cycle
-assert c.in.a 1
-
-
-assert-bd-channel-valid "c.out" 14 1089