altered dly cfg to use not(t) rather than f

dataflow_neuro/chips.act

@@ -96,7 +96,13 @@ defproc texel_core (avMx1of2<N_IN> in, out;
         .out = synapses,
         .hs_en = register.data[0].d[0].t, // Defaults to handshake disable
         .supply = supply, .reset_B = _reset_BX);
-    (i:N_SYN_DLY_CFG: decoder.dly_cfg[i] = register.data[0].d[1 + i].f;) // Defaults to max delay
+    INV_X1 dly_cfg_inverters[N_SYN_DLY_CFG]; 
+    (i:N_SYN_DLY_CFG:
+        dly_cfg_inverters[i].a = register.data[0].d[1+i].t; // iff t is high, is the delay disabled.
+        dly_cfg_inverters[i].vdd = supply.vdd;
+        dly_cfg_inverters[i].vss = supply.vss;
+        decoder.dly_cfg[i] = dly_cfg_inverters[i].y;
+    ) // This sexy hack means that the inverters are max delay throughout the register flush operations.
 
     // Neurons + encoder
     pint NC_NRN;

dataflow_neuro/coders.act

@@ -86,6 +86,63 @@ defproc decoder_dualrail (Mx1of2<Nc> in; bool? out[N]; power supply) {
 		)
 }
 
+
+/**
+ * Dualrail decoder, but the signals to the decoders are refreshed every 48 gates.
+ * final_refresh is signal at the end of the refresh line.
+ * Is needed for doing validity checking etc, since it is the laggiest signal.
+ */
+export template<pint Nc, N>
+defproc decoder_dualrail_refresh (Mx1of2<Nc> in; bool? out[N]; Mx1of2<Nc> final_refresh; power supply) {
+	// signal buffers
+	pint index;
+	pint NUM_REFRESH = N/(48*2); // x2 bc only half the output bits look for it.
+	BUF_X12 in_tX[Nc*(NUM_REFRESH+1)];
+	BUF_X12 in_fX[Nc*(NUM_REFRESH+1)];
+
+	(i:Nc:
+		// Connect start
+		in_tX[i].a =  in.d[i].t;
+		in_fX[i].a =  in.d[i].f;
+
+		// Connect mid bois
+		(j:NUM_REFRESH:
+			index = i + (1+j)*Nc;
+			in_tX[index].a = in_tX[index-Nc].y;
+		)
+
+		// Connect end
+		in_tX[i+NUM_REFRESH*Nc].y = final_refresh.d[i].t;
+		in_fX[i+NUM_REFRESH*Nc].y = final_refresh.d[i].f;
+	)
+	
+	(i:Nc*(NUM_REFRESH+1):
+		in_tX[i].vdd = supply.vdd;
+		in_tX[i].vss = supply.vss;
+		in_fX[i].vdd = supply.vdd;
+		in_fX[i].vss = supply.vss;
+	)
+
+	// AND trees
+	pint bitval;
+	andtree<Nc> atree[N];
+	(k:0..N-1:atree[k].supply = supply;)
+	(i:0..N-1:
+		(j:0..Nc-1:
+			bitval = (i & ( 1 << j )) >> j; // Get binary digit of integer i, column j
+			[bitval = 1 ->
+				atree[i].in[j] = in_tX[j+(i/96)*Nc].y;
+				// atree[i].in[j] = addr_buf.out.d.d[j].t;
+				[]bitval = 0 ->
+				atree[i].in[j] = in_fX[j+(i/96)*Nc].y;
+				// atree[i].in[j] = addr_buf.out.d.d[j].f;
+				[]bitval >= 2 -> {false : "fuck"};
+				]
+			atree[i].out = out[i];
+			)
+		)
+}
+
 /**
  * Dualrail decoder with buffered outputs.
  * Be careful of out[] indexing.
@@ -110,7 +167,7 @@ defproc decoder_dualrail_x(Mx1of2<Nc> in; bool? out[N]; power supply) {
  */
 export template<pint Nc, N>
 defproc decoder_dualrail_en(Mx1of2<Nc> in; bool? en, out[N]; power supply) {
-	decoder_dualrail<Nc, N> decoder(.in = in, .supply = supply);
+	decoder_dualrail_refresh<Nc, N> decoder(.in = in, .supply = supply);
 
 	sigbuf<N> sb_en(.in = en, .supply = supply);
 	AND2_X1 en_ands[N];
@@ -325,9 +382,9 @@ defproc decoder_2d_hybrid (avMx1of2<NxC+NyC> in; a1of1 out[Nx*Ny]; bool? dly_cfg
 	buffer<NxC+NyC> addr_buf(.in = in, .reset_B = reset_B, .supply = supply);
 
 	// Decoder X/Y And trees
-	decoder_dualrail<NxC,Nx> d_dr_x(.supply = supply);
+	decoder_dualrail_refresh<NxC,Nx> d_dr_x(.supply = supply);
 	(i:0..NxC-1:d_dr_x.in.d[i] = addr_buf.out.d.d[i];)
-	decoder_dualrail<NyC,Ny> d_dr_y(.supply = supply);
+	decoder_dualrail_refresh<NyC,Ny> d_dr_y(.supply = supply);
 	(i:0..NyC-1:d_dr_y.in.d[i] = addr_buf.out.d.d[i+NxC];)
 
 	// sig buf for reqx lines, since they go to synapse pull down gates.
@@ -341,10 +398,10 @@ defproc decoder_2d_hybrid (avMx1of2<NxC+NyC> in; a1of1 out[Nx*Ny]; bool? dly_cfg
 	// Validity 
 	vtree<NxC> vtree_x (.supply = supply);
 	vtree<NyC> vtree_y (.supply = supply);
-	(i:0..NxC-1:vtree_x.in.d[i].t = addr_buf.out.d.d[i].t;)
+	(i:0..NxC-1:vtree_x.in.d[i].t = d_dr_x.final_refresh.d[i].t;)
-	(i:0..NxC-1:vtree_x.in.d[i].f = addr_buf.out.d.d[i].f;)
+	(i:0..NxC-1:vtree_x.in.d[i].f = d_dr_x.final_refresh.d[i].f;)
-	(i:0..NyC-1:vtree_y.in.d[i].t = addr_buf.out.d.d[i+NxC].t;)
+	(i:0..NyC-1:vtree_y.in.d[i].t = d_dr_y.final_refresh.d[i].t;)
-	(i:0..NyC-1:vtree_y.in.d[i].f = addr_buf.out.d.d[i+NxC].f;)
+	(i:0..NyC-1:vtree_y.in.d[i].f = d_dr_y.final_refresh.d[i].f;)
 	A_2C_B_X1 valid_Cel(.c1 = vtree_x.out, .c2 = vtree_y.out, .y = addr_buf.out.v,
 		.vdd = supply.vdd, .vss = supply.vss);
 

test/unit_tests/texel_dualcore/test.act

@@ -42,8 +42,12 @@ open tmpl::dataflow_neuro;
 
 pint N_IN = 32;
 
-pint N_NRN_X = 15;
+// pint N_NRN_X = 15;
-pint N_NRN_Y = 6;
+// pint N_NRN_Y = 6;
+// pint NC_NRN_X = 4;
+// pint NC_NRN_Y = 3;
+pint N_NRN_X = 16;
+pint N_NRN_Y = 8;
 pint NC_NRN_X = 4;
 pint NC_NRN_Y = 3;
 
@@ -51,8 +55,8 @@ pint NC_NRN_Y = 3;
 // pint N_SYN_Y = 348;
 // pint NC_SYN_X = 6;
 // pint NC_SYN_Y = 9;
-pint N_SYN_X = 15;
+pint N_SYN_X = 16;
-pint N_SYN_Y = 6;
+pint N_SYN_Y = 8;
 pint NC_SYN_X = 4;
 pint NC_SYN_Y = 3;
 
@@ -86,10 +90,10 @@ defproc chip_texel_dualcore (bd<N_IN> in, out;
     Mx1of2<REG_NCW> c1_reg_data[REG_M];
     // a1of1 c1_synapses[N_SYN_X * N_SYN_Y];
     // a1of1 c1_neurons[N_NRN_X * N_NRN_Y];
-    bool! c1_syn_r[N_SYN_X * N_SYN_Y];
+    bool c1_syn_r[N_SYN_X * N_SYN_Y];
-    bool? c1_syn_a[N_SYN_X * N_SYN_Y];
+    bool c1_syn_a[N_SYN_X * N_SYN_Y];
-    bool? c1_nrn_r[N_NRN_X * N_NRN_Y];
+    bool c1_nrn_r[N_NRN_X * N_NRN_Y];
-    bool! c1_nrn_a[N_NRN_X * N_NRN_Y];
+    bool c1_nrn_a[N_NRN_X * N_NRN_Y];
     
     bool! c1_nrn_mon_x[N_NRN_MON_X], c1_nrn_mon_y[N_NRN_MON_Y];
     bool! c1_syn_mon_x[N_SYN_MON_X], c1_syn_mon_y[N_SYN_MON_Y];
@@ -100,10 +104,10 @@ defproc chip_texel_dualcore (bd<N_IN> in, out;
     Mx1of2<REG_NCW> c2_reg_data[REG_M];
     // a1of1 c2_synapses[N_SYN_X * N_SYN_Y];
     // a1of1 c2_neurons[N_NRN_X * N_NRN_Y];
-    bool! c2_syn_r[N_SYN_X * N_SYN_Y];
+    bool c2_syn_r[N_SYN_X * N_SYN_Y];
-    bool? c2_syn_a[N_SYN_X * N_SYN_Y];
+    bool c2_syn_a[N_SYN_X * N_SYN_Y];
-    bool? c2_nrn_r[N_NRN_X * N_NRN_Y];
+    bool c2_nrn_r[N_NRN_X * N_NRN_Y];
-    bool! c2_nrn_a[N_NRN_X * N_NRN_Y];
+    bool c2_nrn_a[N_NRN_X * N_NRN_Y];
     
     bool! c2_nrn_mon_x[N_NRN_MON_X], c2_nrn_mon_y[N_NRN_MON_Y];
     bool! c2_syn_mon_x[N_SYN_MON_X], c2_syn_mon_y[N_SYN_MON_Y];
@@ -157,6 +161,21 @@ defproc chip_texel_dualcore (bd<N_IN> in, out;
 
 
 
+    pint N_SYNS = N_SYN_X * N_SYN_Y;
+    BUF_X4 syn2nrns_r[N_SYNS*2];
+    BUF_X4 syn2nrns_a[N_SYNS*2];
+    (i:N_SYNS:
+        syn2nrns_r[i].a = c1_synapses[i].r;
+        syn2nrns_r[i].y = c1_neurons[i].r;
+        syn2nrns_a[i].a = c1_neurons[i].a;
+        syn2nrns_a[i].y = c1_synapses[i].a;
+
+        syn2nrns_r[i+N_SYNS].a = c2_synapses[i].r;
+        syn2nrns_r[i+N_SYNS].y = c2_neurons[i].r;
+        syn2nrns_a[i+N_SYNS].a = c2_neurons[i].a;
+        syn2nrns_a[i+N_SYNS].y = c2_synapses[i].a;
+    )
+
 }