let delay fifos have N= 0, simplified nrn grids thusly

dataflow_neuro/coders.act

@@ -604,23 +604,20 @@ namespace tmpl {
 				)
 			)
 
-			// Hacks to maybe construct some fifos, ignore.
+			// Create delay fifos to emulate the fact that the line pull downs
-			[N_dly >= 1 -> 
+			// are at the end of the line, and thus slow.
-				delay_fifo<N_dly> dly_x[Nx];
+			// Note that if N_dly = 0, delay fifo is just a pipe.
-				delay_fifo<N_dly> dly_y[Ny];	
+			delay_fifo<N_dly> dly_x[Nx];
-			]
+			delay_fifo<N_dly> dly_y[Ny];	
 			
 			// Create x line req pull downs
 			line_end_pull_down pd_x[Nx];
 			sigbuf<Nx> rsb_pd_x(.in = reset_B, .supply = supply);
 			(i:0..Nx-1:
-				[ N_dly = 0 ->
+				dly_x[i].supply = supply;
-					pd_x[i].in = _outx[i].a;
+				dly_x[i].in = _outx[i].a;
-				[] N_dly >= 1 ->
+				pd_x[i].in = dly_x[i].out;
-					dly_x[i].supply = supply;
+				
-					dly_x[i].in = _outx[i].a;
-					pd_x[i].in = dly_x[i].out;
-				]
 				pd_x[i].out = _outx[i].r;
 				pd_x[i].reset_B = rsb_pd_x.out[i];
 				pd_x[i].supply = supply;
@@ -630,13 +627,10 @@ namespace tmpl {
 			line_end_pull_down pd_y[Ny];
 			sigbuf<Ny> rsb_pd_y(.in = reset_B, .supply = supply);
 			(j:0..Ny-1:
-				[ N_dly = 0 ->
+				dly_y[j].supply = supply;
-					pd_y[j].in = _outy[j].a;
+				dly_y[j].in = _outy[j].a;
-				[] N_dly >= 1 ->
+				pd_y[j].in = dly_y[j].out;
-					dly_y[j].supply = supply;
+			
-					dly_y[j].in = _outy[j].a;
-					pd_y[j].in = dly_y[j].out;
-				]
 				pd_y[j].out = _outy[j].r;
 				pd_y[j].reset_B = rsb_pd_y.out[j];
 				pd_y[j].supply = supply;

dataflow_neuro/primitives.act

@@ -690,8 +690,9 @@ namespace tmpl {
         // Is useful for testing purposes.
         // But should probably remove before running innovus etc.
         export template<pint N>
-        defproc delay_fifo (bool! out; bool? in; power supply) {
+        defproc delay_fifo (bool out; bool in; power supply) {
             { N >= 0 : "What?" };
+            [N >= 1 ->
             DLY4_X1 dly[N];
 
             dly[0].vdd = supply.vdd;
@@ -707,6 +708,10 @@ namespace tmpl {
             dly[N-1].vdd = supply.vdd;
             dly[N-1].vss = supply.vss;
             dly[N-1].y = out;
+            [] N = 1 ->
+            in = out;
+            ]
+            
         }
 
 

test/unit_tests/fifo-decoder-neurons-encoder-fifo/test.act

@@ -0,0 +1,99 @@
+/*************************************************************************
+ *
+ *  This file is part of ACT dataflow neuro library.
+ * It's the testing facility for cell_lib_std.act
+ *
+ *  Copyright (c) 2022 University of Groningen - Ole Richter  
+ *  Copyright (c) 2022 University of Groningen - Hugh Greatorex
+ *  Copyright (c) 2022 University of Groningen - Michele Mastella
+ *  Copyright (c) 2022 University of Groningen - Madison Cotteret
+ *
+ *  This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
+ *
+ *  You may redistribute and modify this documentation and make products
+ *  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
+ *  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
+ *  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
+ *  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
+ *  for applicable conditions.
+ *
+ *  Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
+ *
+ *  As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
+ *  these sources, You must maintain the Source Location visible in its
+ *  documentation.
+ *
+ **************************************************************************
+ */
+
+import "../../dataflow_neuro/coders.act";
+import "../../dataflow_neuro/primitives.act";
+
+import globals;
+import std::data;
+
+open std::data;
+
+open tmpl::dataflow_neuro;
+
+defproc fifo_decoder_neurons_encoder_fifo (avMx1of2<7> in; avMx1of2<7> out; bool? dly_cfg[6]){
+    bool _reset_B; 
+    prs {
+        Reset => _reset_B-
+    }
+    power supply;
+    supply.vdd = Vdd;
+    supply.vss = GND;
+
+    pint NxC,NyC,Nx,Ny;
+    NxC = 4;
+    NyC = 3;
+    Nx = 1<<NxC;
+    Ny = 1<<NyC;
+
+    fifo<NxC + NyC,5> fifo_pre(.in = in, .reset_B = _reset_B, .supply = supply);
+    decoder_2d_dly<NxC,NyC,Nx,Ny,6> decoder(.in = fifo_pre.out, .dly_cfg = dly_cfg, 
+        .reset_B = _reset_B, .supply = supply);
+    and_grid<Nx, Ny> _and_grid(.inx = decoder.outx, .iny = decoder.outy, .supply = supply);
+    // Pretend that each "synapse" immediately makes its one neuron "spike".
+    // that is, connect the output of each encoder target to the decoder input.
+    nrn_hs_2D_array<Nx,Ny,16> neuron_grid(.reset_B = _reset_B, .supply = supply);
+    (i:Nx*Ny:
+        // Connect the output bool to the input req of each neuron handshaker
+        // Leave ack dangling.
+        neuron_grid.in[i].r = _and_grid.out[i];
+    )
+
+
+    encoder2D<NxC,NyC,Nx,Ny,4> encoder(.x = neuron_grid.outx, .y = neuron_grid.outy,
+        .reset_B = _reset_B, .supply = supply);
+    fifo<NxC + NyC,5> fifo_post(.in = encoder.out, .out = out, .reset_B = _reset_B, .supply = supply);
+
+}
+
+
+
+// defproc fifo_decoder_and (avMx1of2<7> in; bool! out[8*16]; bool? dly_cfg[6]){
+//     bool _reset_B; 
+//     prs {
+//         Reset => _reset_B-
+//     }
+//     power supply;
+//     supply.vdd = Vdd;
+//     supply.vss = GND;
+
+//     pint NxC,NyC,Nx,Ny;
+//     NxC = 4;
+//     NyC = 3;
+//     Nx = 1<<NxC;
+//     Ny = 1<<NyC;
+
+//     fifo<NxC + NyC,5> fifo_pre(.in = in, .reset_B = _reset_B, .supply = supply);
+//     decoder_2d_dly<NxC,NyC,Nx,Ny,6> decoder(.in = fifo_pre.out, .dly_cfg = dly_cfg, 
+//         .reset_B = _reset_B, .supply = supply);
+//     and_grid<Nx, Ny> _and_grid(.inx = decoder.outx, .iny = decoder.outy, .out = out, .supply = supply);
+//     nrn_hs_2D_array<Nx,Ny,16> nrn_array(.reset_B = _reset_B, .supply = supply);
+// }
+
+// fifo_decoder_neurons_encoder_fifo e;
+fifo_decoder_neurons_encoder_fifo e; 

test/unit_tests/fifo-decoder-neurons-encoder-fifo/test.prsim

@@ -0,0 +1,81 @@
+watchall
+
+set e.out.a 0
+set e.out.v 0
+set-qdi-channel-neutral "e.in" 7
+set Reset 1
+
+set e.dly_cfg[0] 1
+set e.dly_cfg[1] 1
+set e.dly_cfg[2] 1
+set e.dly_cfg[3] 1
+set e.dly_cfg[4] 1
+set e.dly_cfg[5] 1
+
+cycle
+
+
+mode run
+system "echo '[] Set reset 0'"
+status X
+set Reset 0
+cycle
+
+
+
+system "echo '[] Sending in a packet'"
+set-qdi-channel-valid "e.in" 7 75
+cycle
+assert-qdi-channel-valid "e.out" 7 75
+assert e.in.a 1
+assert e.in.v 1
+
+system "echo '[] Removing input'"
+set-qdi-channel-neutral "e.in" 7
+cycle
+assert e.in.a 0
+assert e.in.v 0
+
+system "echo '[] Sending in another packet'"
+set-qdi-channel-valid "e.in" 7 22
+cycle
+# Output is still the first packet
+assert-qdi-channel-valid "e.out" 7 75
+assert e.in.a 1
+assert e.in.v 1
+
+system "echo '[] Removing input'"
+set-qdi-channel-neutral "e.in" 7
+cycle
+assert e.in.a 0
+assert e.in.v 0
+
+system "echo '[] Giving out ack'"
+set e.out.a 1
+set e.out.v 1
+cycle
+assert-qdi-channel-neutral "e.out" 7
+
+system "echo '[] Removing ack'"
+set e.out.a 0
+set e.out.v 0
+cycle
+assert-qdi-channel-valid "e.out" 7 22
+
+system "echo '[] Giving out ack'"
+set e.out.a 1
+set e.out.v 1
+cycle
+assert-qdi-channel-neutral "e.out" 7
+
+system "echo '[] Removing ack'"
+set e.out.a 0
+set e.out.v 0
+cycle
+assert-qdi-channel-neutral "e.out" 7
+
+
+
+
+
+