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82537e07de ... encoder_wi

Author SHA1 Message Date
Michele
97732b2f72 continued handshaking tree, not finished 2022-03-02 18:38:17 +01:00
Michele
9e144e1c17 started arbiter tree 2022-03-02 08:22:56 +01:00
118 changed files with 224 additions and 219560 deletions
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dataflow_neuro/.DS_Store vendored
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93
dataflow_neuro/cell_lib_async.act
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@@ -26,30 +26,6 @@
namespace tmpl {
namespace dataflow_neuro{
export defcell KEEP_X1 (bool y; bool vdd, vss) {
bool _y;
prs{
y => _y-
[weak=1] _y -> y-
[weak=1] ~_y -> y+
}
}
export defcell A_1C2N_RB_X1 (bool! y; bool? c1,n1,n2,pr_B, sr_B; bool vdd, vss) {
bool _y;
prs{
(~c1)|~pr_B -> _y+
c1 & n1 & n2 & sr_B -> _y-
_y => y-
}
sizing {
leak_adjust <- 1;
p_n_mode <- 1;
y {-1}; _y{-1}
}
}
export defcell A_1C1P2N_RB_X1 (bool! y; bool? c1,p1,n1,n2,pr_B, sr_B; bool vdd, vss) {
bool _y;
prs{
@@ -65,22 +41,6 @@ namespace tmpl {
}
}
export defcell A_2C1P1N_RB_X1 (bool! y; bool? c1,c2,p1,n1,pr_B,sr_B; bool vdd, vss) {
bool _y;
prs{
(~p1 & ~c1 & ~c2)|~pr_B -> _y+
c1 & c2 & n1 & sr_B -> _y-
_y => y-
}
sizing {
leak_adjust <- 1;
p_n_mode <- 1;
y {-1}; _y{-1}
}
}
export defcell A_1C1P2N_R_X1 (bool! y; bool? c1,p1,n1,n2,pr_B, sr_B; bool vdd, vss) {
prs{
(~p1 & ~c1)|~pr_B -> y-
@@ -564,59 +524,6 @@ namespace tmpl {
mk_excllo(_y1, _y2)
}
}
export
defproc A_1N_U_X4(bool? a; bool! y; bool? vdd, vss)
{
prs{
[keeper=0] a -> y-
}
}
export
defproc A_2N_U_X4(bool? a, b; bool! y; bool? vdd, vss)
{
prs{
[keeper=0] a & b -> y-
}
}
export
defproc A_1P_U_X4(bool? a; bool! y; bool? vdd, vss)
{
prs{
[keeper=0] ~a -> y+
}
}
export
defproc A_2P_U_X4(bool? a, b; bool! y; bool? vdd, vss)
{
prs{
[keeper=0] ~a & ~b -> y+
}
}
export
defproc PULLDOWN_X4(bool? a; bool! y; bool? vdd, vss) {
A_1N_U_X4 cell(.a = a, .y = y, .vdd = vdd, .vss = vss);
}
export
defproc PULLUP_X4(bool? a; bool! y; bool? vdd, vss) {
A_1P_U_X4 cell(.a = a, .y = y, .vdd = vdd, .vss = vss);
}
defproc A_2C2P_RB_X1(bool! y;bool? c1,c2,p1,p2,reset_B,vdd,vss){
bool _y;
prs{
(~p1 & ~p2 & ~c1 & ~c2)|~reset_B -> _y+
(c1 & c2 & reset_B) -> _y-
_y => y-
}
sizing {leak_adjust <- 1;
p_n_mode <- 1;
y {-1}; _y{-1} }
}
}}

47
dataflow_neuro/cell_lib_std.act
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@@ -102,23 +102,13 @@ namespace tmpl {
/*-- delay cells --*/
// TODO properly
// export defcell DLY4_X1(bool! y; bool? a, vdd, vss)
// {
// bool _y, __y, ___y;
// prs {
// a => _y-
// _y => __y-
// __y => ___y-
// ___y => y-
// }
// }
export defcell DLY4_X1(bool! y; bool? a, vdd, vss)
{
BUF_X1 bufchain[16];
(i:0..14: bufchain[i].y = bufchain[i+1].a;)
bufchain[0].a = a;
bufchain[15].y = y;
bool _y;
prs {
a => _y-
_y => y-
}
}
@@ -282,7 +272,7 @@ namespace tmpl {
export defcell MUX2_X1(bool! y; bool? a, b, s, vdd, vss)
{
// y = !( S ? b : a )
// y = !( S ? a : b )
// Adjusted to fit the XFAB Muxes
bool _s;
bool _y;
@@ -381,31 +371,6 @@ namespace tmpl {
}
sizing { _en{-2}; y{-2,2} }
}
export defproc DFFQ_R_X1 (bool? clk_B, reset_B, d; bool! q,q_B; bool? vdd,vss)
{
bool _clk_B, __clk_B, _mqi,_mqib,_sqi,_sqib;
prs {
// Creating delayed versions of the clock
clk_B => _clk_B-
_clk_B => __clk_B-
(~d & ~_clk_B)|(~reset_B)|(~__clk_B&~_mqi) -> _mqib+
((d & __clk_B)|(_mqi & _clk_B))&reset_B -> _mqib-
_mqib => _mqi-
(~_mqi &~__clk_B)|(~reset_B)|(~_sqi&~_clk_B) -> _sqib+
((_mqi &_clk_B)|(_sqi&__clk_B))&reset_B -> _sqib-
_sqib => _sqi-
_sqib => q-
q => q_B-
}
}
}
}

889
dataflow_neuro/coders.act
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@@ -1,889 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/cell_lib_async.act";
import "../../dataflow_neuro/cell_lib_std.act";
import "../../dataflow_neuro/treegates.act";
import "../../dataflow_neuro/primitives.act";
// import tmpl::dataflow_neuro;
// import tmpl::dataflow_neuro;
import std::channel;
open std::channel;
// import std::func;
open std;
import std::data;
open std::data;
// import dev::channel;
// open dev::channel;
namespace tmpl {
namespace dataflow_neuro {
/**
* Dualrail decoder.
* Nc is the number of dualrail input channels.
* Then builds N output AND gates, connecting to the right input wires.
*/
export template<pint Nc, N>
defproc decoder_dualrail (Mx1of2<Nc> in; bool? out[N]; power supply) {
// signal buffers
sigbuf<N> in_tX[Nc];
sigbuf<N> in_fX[Nc];
(i:Nc:
in_tX[i].supply = supply;
in_tX[i].in = in.d[i].t;
in_fX[i].supply = supply;
in_fX[i].in = in.d[i].f;
)
// AND trees
pint bitval;
andtree<Nc> atree[N];
(k:0..N-1:atree[k].supply = supply;)
(i:0..N-1:
(j:0..Nc-1:
bitval = (i & ( 1 << j )) >> j; // Get binary digit of integer i, column j
[bitval = 1 ->
atree[i].in[j] = in_tX[j].out[i];
// atree[i].in[j] = addr_buf.out.d.d[j].t;
[]bitval = 0 ->
atree[i].in[j] = in_fX[j].out[i];
// atree[i].in[j] = addr_buf.out.d.d[j].f;
[]bitval >= 2 -> {false : "fuck"};
]
atree[i].out = out[i];
)
)
}
/**
* 2D decoder which uses a configurable delay from the VCtrees to buffer ack.
* Nx is the x size of the decoder array
* NxC is the number of wires in the x channel.
* Thus NxC should be something like NxC = ceil(log2(Nx))
* but my guess is that we can't do logs...
* N_dly_cfg is the number of config bits in the ACK delay line,
* with all bits high corresponding to 2**N_dly_cfg -1 DLY4_X1 cells.
*/
export template<pint NxC, NyC, Nx, Ny, N_dly_cfg>
defproc decoder_2d_dly (avMx1of2<NxC+NyC> in; bool? outx[Nx], outy[Ny],
dly_cfg[N_dly_cfg], reset_B; power supply) {
// Buffer to recieve concat(x,y) address packet
buffer<NxC+NyC> addr_buf(.in = in, .reset_B = reset_B, .supply = supply);
// Validity trees
vtree<NxC> vtree_x (.supply = supply);
vtree<NyC> vtree_y (.supply = supply);
(i:0..NxC-1:vtree_x.in.d[i].t = addr_buf.out.d.d[i].t;)
(i:0..NxC-1:vtree_x.in.d[i].f = addr_buf.out.d.d[i].f;)
(i:0..NyC-1:vtree_y.in.d[i].t = addr_buf.out.d.d[i+NxC].t;)
(i:0..NyC-1:vtree_y.in.d[i].f = addr_buf.out.d.d[i+NxC].f;)
// Delay ack line. Ack line is delayed (but not the val)
A_2C_B_X1 C2el(.c1 = vtree_x.out, .c2 = vtree_y.out, .vdd = supply.vdd, .vss = supply.vss);
addr_buf.out.v = C2el.y;
delayprog<N_dly_cfg> dly(.in = C2el.y, .s = dly_cfg, .supply = supply);
dly.out = addr_buf.out.a;
// Decoder X/Y And trees
decoder_dualrail<NxC,Nx> d_dr_x(.out = outx, .supply = supply);
(i:0..NxC-1:d_dr_x.in.d[i] = addr_buf.out.d.d[i];)
decoder_dualrail<NyC,Ny> d_dr_y(.out = outy, .supply = supply);
(i:0..NyC-1:d_dr_y.in.d[i] = addr_buf.out.d.d[i+NxC];)
}
export template<pint Nx, Ny>
defproc and_grid(bool! out[Nx*Ny]; bool? inx[Nx], iny[Ny]; power supply) {
// Buffer inputs
sigbuf<Ny> xbuf[Nx];
sigbuf<Nx> ybuf[Ny];
(i:Nx:
xbuf[i].in = inx[i];
xbuf[i].supply = supply;
)
(i:Ny:
ybuf[i].in = iny[i];
ybuf[i].supply = supply;
)
AND2_X1 ands[Nx*Ny];
(i:0..Nx*Ny-1:ands[i].vss = supply.vss; ands[i].vdd = supply.vdd;)
(x:0..Nx-1:
(y:0..Ny-1:
ands[x + y*Nx].a = xbuf[x].out[y];
ands[x + y*Nx].b = ybuf[y].out[x];
ands[x + y*Nx].y = out[x + y*Nx];
)
)
}
/**
* 2D decoder which uses synapse handshaking using line pulldowns.
* Nx is the x size of the decoder array
* NxC is the number of wires in the x channel.
* but my guess is that we can't do logs...
* the req on a1of1 out is the req to each synapse.
* The ack back from each line should go high when the synapse is charged.
* N_dly is a hard coded delay of the pull down circuit.
* It can be set to 0.
*/
export template<pint NxC, NyC, Nx, Ny>
defproc decoder_2d_hs (avMx1of2<NxC+NyC> in; a1of1 out[Nx*Ny]; bool? reset_B; power supply) {
// Buffer to recieve concat(x,y) address packet
buffer<NxC+NyC> addr_buf(.in = in, .reset_B = reset_B, .supply = supply);
// Decoder X/Y And trees
decoder_dualrail<NxC,Nx> d_dr_x(.supply = supply);
(i:0..NxC-1:d_dr_x.in.d[i] = addr_buf.out.d.d[i];)
decoder_dualrail<NyC,Ny> d_dr_y(.supply = supply);
(i:0..NyC-1:d_dr_y.in.d[i] = addr_buf.out.d.d[i+NxC];)
// sig buf for reqx lines, since they go to synapse pull down gates.
sigbuf<Ny+1> d_dr_xX[Nx];
(i:Nx:
d_dr_xX[i].in = d_dr_x.out[i];
d_dr_xX[i].supply = supply;
)
// Validity
vtree<NxC> vtree_x (.supply = supply);
vtree<NyC> vtree_y (.supply = supply);
(i:0..NxC-1:vtree_x.in.d[i].t = addr_buf.out.d.d[i].t;)
(i:0..NxC-1:vtree_x.in.d[i].f = addr_buf.out.d.d[i].f;)
(i:0..NyC-1:vtree_y.in.d[i].t = addr_buf.out.d.d[i+NxC].t;)
(i:0..NyC-1:vtree_y.in.d[i].f = addr_buf.out.d.d[i+NxC].f;)
A_2C_B_X1 valid_Cel(.c1 = vtree_x.out, .c2 = vtree_y.out, .y = addr_buf.out.v,
.vdd = supply.vdd, .vss = supply.vss);
// and grid for reqs into synapses
and_grid<Nx, Ny> _and_grid(.inx = d_dr_x.out, .iny = d_dr_y.out, .supply = supply);
(i:Nx*Ny: out[i].r = _and_grid.out[i];)
// Acknowledge pull down time
// Pull DOWNs on the ackB lines by synapses (easier to invert).
bool _out_acksB[Nx]; // The vertical output ack lines from each syn.
A_2N_U_X4 ack_pulldowns[Nx*Ny];
pint index;
(i:Nx:
(j:Ny:
index = i + Nx*j;
ack_pulldowns[index].a = out[index].a;
ack_pulldowns[index].b = d_dr_xX[i].out[j];
ack_pulldowns[index].y = _out_acksB[i];
ack_pulldowns[index].vss = supply.vss;
ack_pulldowns[index].vdd = supply.vdd;
)
)
// Line end pull UPs (triggered once reqs removed)
// Use two pullups rather than and-pullup
// bc smaller
// and bc the delay that an AND induces means that the pullup could
// end up fighting a synapse pulldown, as both have the correct req sigs.
A_1P_U_X4 pu[Nx]; // TODO probably replace this with variable strength PU
A_1P_U_X4 pu_reset[Nx];
(i:Nx:
pu[i].a = d_dr_xX[i].out[Ny];
pu[i].y = _out_acksB[i];
pu[i].vdd = supply.vdd;
pu[i].vss = supply.vss;
pu_reset[i].a = reset_B;
pu_reset[i].y = _out_acksB[i];
pu_reset[i].vdd = supply.vdd;
pu_reset[i].vss = supply.vss;
)
// ORtree from all output acks, back to the buffer ack.
// This is instead of the ack that came from the delayed validity trees,
// in decoder_2d_dly.
ortree<Nx> _ortree(.supply = supply);
INV_X1 out_ack_invs[Nx];
(i:Nx:
out_ack_invs[i].a = _out_acksB[i];
out_ack_invs[i].vdd = supply.vdd;
out_ack_invs[i].vss = supply.vss;
_ortree.in[i] = out_ack_invs[i].y;
)
// C element to ensure that the buffer receives an invalid
// _only_ once _both_ ackB has been reset, _and_ its output data
// has been fully invalidated.
// Otherwise run into the issue that ack is removed before data is invalid.
A_2C_B_X1 buf_ack_Cel(.c1 = _ortree.out, .c2 = valid_Cel.y, .y = addr_buf.out.a,
.vdd = supply.vdd, .vss = supply.vss);
}
/**
* 2D decoder which uses either synapse handshaking, or just a delay.
* Controlled by the "hs_en" (handshake_enable) config bit.
* hs_en = 0 -> use delayed version.
* hs_en = 1 -> use synapse handshaking.
* Regardless of which version is used, the final ack going to the buffer
* goes through the prog_delay block.
* Thus, for the handshaking version to be used "correctly",
* dly_cfg should be set to all zeros.
*/
export template<pint NxC, NyC, Nx, Ny, N_dly_cfg>
defproc decoder_2d_hybrid (avMx1of2<NxC+NyC> in; a1of1 out[Nx*Ny]; bool? dly_cfg[N_dly_cfg], hs_en,
reset_B; power supply) {
bool hs_enB;
INV_X4 hs_inv(.a = hs_en, .y = hs_enB, .vdd = supply.vdd, .vss = supply.vss);
// Buffer to recieve concat(x,y) address packet
buffer<NxC+NyC> addr_buf(.in = in, .reset_B = reset_B, .supply = supply);
// Decoder X/Y And trees
decoder_dualrail<NxC,Nx> d_dr_x(.supply = supply);
(i:0..NxC-1:d_dr_x.in.d[i] = addr_buf.out.d.d[i];)
decoder_dualrail<NyC,Ny> d_dr_y(.supply = supply);
(i:0..NyC-1:d_dr_y.in.d[i] = addr_buf.out.d.d[i+NxC];)
// sig buf for reqx lines, since they go to synapse pull down gates.
sigbuf<Ny+1> d_dr_xX[Nx];
(i:Nx:
d_dr_xX[i].in = d_dr_x.out[i];
d_dr_xX[i].supply = supply;
)
// Validity
vtree<NxC> vtree_x (.supply = supply);
vtree<NyC> vtree_y (.supply = supply);
(i:0..NxC-1:vtree_x.in.d[i].t = addr_buf.out.d.d[i].t;)
(i:0..NxC-1:vtree_x.in.d[i].f = addr_buf.out.d.d[i].f;)
(i:0..NyC-1:vtree_y.in.d[i].t = addr_buf.out.d.d[i+NxC].t;)
(i:0..NyC-1:vtree_y.in.d[i].f = addr_buf.out.d.d[i+NxC].f;)
A_2C_B_X1 valid_Cel(.c1 = vtree_x.out, .c2 = vtree_y.out, .y = addr_buf.out.v,
.vdd = supply.vdd, .vss = supply.vss);
// and grid for reqs into synapses
and_grid<Nx, Ny> _and_grid(.inx = d_dr_x.out, .iny = d_dr_y.out, .supply = supply);
(i:Nx*Ny: out[i].r = _and_grid.out[i];)
// Acknowledge pull down time
// Pull DOWNs on the ackB lines by synapses (easier to invert).
bool _out_acksB[Nx]; // The vertical output ack lines from each syn.
A_2N_U_X4 ack_pulldowns[Nx*Ny];
pint index;
(i:Nx:
(j:Ny:
index = i + Nx*j;
ack_pulldowns[index].a = out[index].a;
ack_pulldowns[index].b = d_dr_xX[i].out[j];
ack_pulldowns[index].y = _out_acksB[i];
ack_pulldowns[index].vss = supply.vss;
ack_pulldowns[index].vdd = supply.vdd;
)
)
// Line end pull UPs (triggered once reqs removed)
// Use two pullups rather than and-pullup
// bc smaller
// and bc the delay that an AND induces means that the pullup could
// end up fighting a synapse pulldown, as both have the correct req sigs.
A_2P_U_X4 pu[Nx]; // TODO probably replace this with variable strength PU
A_1P_U_X4 pu_reset[Nx];
(i:Nx:
pu[i].a = d_dr_xX[i].out[Ny];
pu[i].b = hs_enB;
pu[i].y = _out_acksB[i];
pu[i].vdd = supply.vdd;
pu[i].vss = supply.vss;
pu_reset[i].a = reset_B;
pu_reset[i].y = _out_acksB[i];
pu_reset[i].vdd = supply.vdd;
pu_reset[i].vss = supply.vss;
)
// ORtree from all output acks, back to the buffer ack.
// This is instead of the ack that came from the delayed validity trees,
// in decoder_2d_dly.
ortree<Nx> _ortree(.supply = supply);
INV_X1 out_ack_invs[Nx];
(i:Nx:
out_ack_invs[i].a = _out_acksB[i];
out_ack_invs[i].vdd = supply.vdd;
out_ack_invs[i].vss = supply.vss;
_ortree.in[i] = out_ack_invs[i].y;
)
// C element to ensure that the buffer receives an invalid
// _only_ once _both_ ackB has been reset, _and_ its output data
// has been fully invalidated.
// Otherwise run into the issue that ack is removed before data is invalid.
A_2C_B_X1 buf_ack_Cel(.c1 = _ortree.out, .c2 = valid_Cel.y,
.vdd = supply.vdd, .vss = supply.vss);
// Mux to switch between acks from handshake or delay
MUX2_X1 ack_mux(.s = hs_en, .a = valid_Cel.y, .b = buf_ack_Cel.y,
.vdd = supply.vdd, .vss = supply.vss);
// Programmable delay
delayprog<N_dly_cfg> dly(.in = ack_mux.y, .out = addr_buf.out.a, .s = dly_cfg, .supply = supply);
}
/*
* Build an arbiter_handshake tree.
*/
export template<pint N>
defproc arbtree (a1of1 in[N]; a1of1 out; power supply)
{
bool tout;
{ N > 0 : "What?" };
pint i, end, j;
i = 0;
end = N-1;
pint arbCount;
arbCount = 0;
/* Pre"calculate" the number of C cells required, look below if confused */
*[ i != end ->
j = 0;
*[ i <= end ->
j = j + 1;
[i = end ->
i = end+1;
[] i+1 = end ->
i = end+1;
arbCount = arbCount +1;
[] else ->
i = i + 2;
arbCount = arbCount +1;
]
]
/*-- update range that has to be combined --*/
// i = end+1;
end = end+j;
]
/* array that holds ALL the nodes in the completion tree */
a1of1 tmp[end+1];
// Connecting the first nodes to the input
(l:N:
tmp[l] = in[l];
)
/* array to hold the actual C-elments, either A2C or A3C */
[arbCount > 0 ->
arbiter_handshake arbs[arbCount];
]
(h:arbCount:arbs[h].supply = supply;)
/* Reset the variables we just stole lol */
i = 0;
end = N-1;
j = 0;
pint arbIndex = 0;
/* Invariant: i <= end */
*[ i != end ->
/*
* Invariant: tmp[i..end] has the current signals that need to be
* combined together, and "isinv" specifies if they are the inverted
* sense or not
*/
j = 0;
*[ i <= end ->
/*-- there are still signals that need to be combined --*/
j = j + 1;
[ i = end ->
/*-- last piece: pipe input through to next layer --*/
tmp[end+j] = tmp[i];
i = end+1;
[] i+1 = end ->
/*-- last piece: use either a 2 input C-element --*/
arbs[arbIndex].in1 = tmp[i];
arbs[arbIndex].in2 = tmp[i+1];
arbs[arbIndex].out = tmp[end+j];
arbIndex = arbIndex +1;
i = end+1;
[] else ->
/*-- more to come; so use a two input C-element --*/
arbs[arbIndex].in1 = tmp[i];
arbs[arbIndex].in2 = tmp[i+1];
arbs[arbIndex].out = tmp[end+j];
arbIndex = arbIndex +1;
i = i + 2;
]
]
/*-- update range that has to be combined --*/
i = end+1;
end = end+j;
j = 0;
]
out = tmp[end];
}
// Generates the OR-trees required to go from
// N one-hot inputs to Nc dual rail binary encoding.
export template<pint Nc, N>
defproc dualrail_encoder(bool? in[N]; Mx1of2<Nc> out; power supply) {
{N <= 1<<Nc : "Num inputs too wide for encoding channel!"};
// For each output line, need to precalculate how big of an OR tree it needs
// since can't presume that N = 2**Nc
// First version however, just be hella lazy and presume N=2**Nc,
// connect extra nodes to ground (sorry)
pint _N; // N rounded up to a power of 2
_N = (1<<Nc);
ortree<_N/2> ors_t[Nc];
ortree<_N/2> ors_f[Nc];
(i:Nc:ors_t[i].supply = supply; ors_t[i].out = out.d[i].t;)
(i:Nc:ors_f[i].supply = supply; ors_f[i].out = out.d[i].f;)
pint num_connected_t; // Number of guys already connected to the current OR tree
pint num_connected_f;
TIELO_X1 tielo(.vdd = supply.vdd, .vss = supply.vss); // I'm sorry
pint bitval;
(i:0..Nc-1: // For each output line
num_connected_t = 0;
num_connected_f = 0;
(j:0.. _N-1:
bitval = (j & ( 1 << i )) >> i; // Get binary digit of integer j, column i
[bitval = 1 & j <= N-1->
ors_t[i].in[num_connected_t] = in[j];
num_connected_t = num_connected_t + 1;
[] bitval = 0 & j <= N-1->
ors_f[i].in[num_connected_f] = in[j];
num_connected_f = num_connected_f + 1;
[] bitval = 1 & j > N-1->
ors_t[i].in[num_connected_t] = tielo.y;
num_connected_t = num_connected_t + 1;
[] bitval = 0 & j > N-1->
ors_f[i].in[num_connected_f] = tielo.y;
num_connected_f = num_connected_f + 1;
]
)
)
}
/**
* Buffer function code.
* Is the function block ripped from the buffer_s.
* Used in the encoder2d.
*/
export template<pint N>
defproc buffer_s_func (Mx1of2<N> in; avMx1of2<N> out; bool? in_v, en, reset_B; power supply) {
//function
bool _out_a_BX_t[N],_out_a_BX_f[N],_out_a_B,_en_X_t[N],_en_X_f[N], _in_vX, _in_vXX_t[N],_in_vXX_f[N];
A_2C2N_RB_X4 f_buf_func[N];
A_2C2N_RB_X4 t_buf_func[N];
// reset buffers
bool _reset_BX,_reset_BXX[N];
BUF_X1 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
sigbuf<N> reset_bufarray(.in=_reset_BX, .out=_reset_BXX, .supply=supply);
// Enable signal buffers
sigbuf<N> en_buf_t(.in=en, .out=_en_X_t, .supply=supply);
sigbuf<N> en_buf_f(.in=en, .out=_en_X_f, .supply=supply);
// out ack signal buffers
INV_X1 out_a_inv(.a=out.a,.y=_out_a_B, .vss = supply.vss, .vdd = supply.vdd);
sigbuf<N> out_a_B_buf_f(.in=_out_a_B,.out=_out_a_BX_t, .supply=supply);
sigbuf<N> out_a_B_buf_t(.in=_out_a_B,.out=_out_a_BX_f, .supply=supply);
// in val signal buffers
BUF_X4 in_v_prebuf(.a = in_v, .y = _in_vX, .vss = supply.vss, .vdd = supply.vdd);
sigbuf<N> in_v_buf_t(.in=_in_vX, .out=_in_vXX_t, .supply=supply);
sigbuf<N> in_v_buf_f(.in=_in_vX, .out=_in_vXX_f, .supply=supply);
(i:N:
f_buf_func[i].y=out.d.d[i].f;
t_buf_func[i].y=out.d.d[i].t;
f_buf_func[i].c1=_en_X_f[i];
t_buf_func[i].c1=_en_X_t[i];
f_buf_func[i].c2=_out_a_BX_f[i];
t_buf_func[i].c2=_out_a_BX_t[i];
f_buf_func[i].n1=in.d[i].f;
t_buf_func[i].n1=in.d[i].t;
f_buf_func[i].n2=_in_vXX_f[i];
t_buf_func[i].n2=_in_vXX_t[i];
f_buf_func[i].vdd=supply.vdd;
t_buf_func[i].vdd=supply.vdd;
f_buf_func[i].vss=supply.vss;
t_buf_func[i].vss=supply.vss;
t_buf_func[i].pr_B = _reset_BXX[i];
t_buf_func[i].sr_B = _reset_BXX[i];
f_buf_func[i].pr_B = _reset_BXX[i];
f_buf_func[i].sr_B = _reset_BXX[i];
)
}
export template<pint NxC, NyC, Nx, Ny, ACK_STRENGTH>
defproc encoder2D(a1of1 inx[Nx]; a1of1 iny[Ny]; avMx1of2<(NxC + NyC)> out; power supply; bool reset_B) {
// Reset buffers
pint H = 2*(NxC + NyC); //Reset strength? to be investigated
bool _reset_BX,_reset_BXX[H];
BUF_X4 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
sigbuf<2*(NxC + NyC)> reset_bufarray(.in=_reset_BX, .out=_reset_BXX,.supply=supply);
// Arbiters
a1of1 _arb_out_x, _arb_out_y;
a1of1 _x_temp[Nx],_y_temp[Ny]; // For wiring the reqs to the arbtrees
(i:Nx:
_x_temp[i].r = inx[i].r;
)
(i:Ny:
_y_temp[i].r = iny[i].r;
)
arbtree<Nx> Xarb(.in = _x_temp,.out = _arb_out_x,.supply = supply);
arbtree<Ny> Yarb(.in = _y_temp,.out = _arb_out_y,.supply = supply);
// Sigbufs for strong ackowledge signals from arb_in's
sigbuf_1output<ACK_STRENGTH> x_ack_arb[Nx];
sigbuf_1output<ACK_STRENGTH> y_ack_arb[Ny];
(i:Nx:
x_ack_arb[i].in = _x_temp[i].a;
x_ack_arb[i].out = inx[i].a;
x_ack_arb[i].supply = supply;
)
(i:Ny:
y_ack_arb[i].in = _y_temp[i].a;
y_ack_arb[i].out = iny[i].a;
y_ack_arb[i].supply = supply;
)
// This block checks that the input is valid and that the arbiter made a choice
// Then activates the ack of the arbiter
bool _x_v,_in_x_v,_in_y_v,_x_a_B,_x_a;
A_2C2P_RB_X1 Y_ack_confirm();
Y_ack_confirm.p1 = _x_v;
Y_ack_confirm.p2 =_in_x_v;
Y_ack_confirm.c1 = _arb_out_y.r;
Y_ack_confirm.c2 = _x_a_B;
Y_ack_confirm.y = _arb_out_y.a;
Y_ack_confirm.vdd = supply.vdd;
Y_ack_confirm.vss = supply.vss;
Y_ack_confirm.reset_B = _reset_BX;
// This block checks that the input is valid and that the arbiter made a choice
// Then activates the ack of the arbiter
A_2C_RB_X1 X_ack_confirm();
X_ack_confirm.c1 = _arb_out_x.r;
X_ack_confirm.c2 = _x_a_B;
X_ack_confirm.vdd = supply.vdd;
X_ack_confirm.vss = supply.vss;
X_ack_confirm.pr_B = _reset_BX;
X_ack_confirm.sr_B = _reset_BX;
X_ack_confirm.y = _arb_out_x.a;
// X_req ORtree
bool _x_req_array[Nx], _x_v_B;
(i:Nx:_x_req_array[i] = inx[i].r;)
ortree<Nx> x_req_ortree(.in = _x_req_array,.out = _x_v,.supply = supply); //todo BUFF
INV_X1 not_x_req_ortree(.a = _x_v,.y = _x_v_B);
//X_REQ validation
// bool _x_req_array[Nx],_x_v_B, _en;
// (i:Nx:_x_req_array[i] = x[i].r;)
// ortree x_req_ortree(.in = _x_req_array,.out = _x_v,.supply = supply);
// INV_X1 not_x_req_ortree(.a = _x_v,.y = _x_v_B);
bool _en;
A_1C3P2P2N_R_X1 x_ack(); // NEEDS BUFFERING TO X4
//branch1
x_ack.p4 = _in_x_v;
x_ack.p5 = _x_v_B;
//branch2
x_ack.p1 = _in_x_v;
x_ack.p2 = _in_y_v;
x_ack.p3 = _x_v;
//
x_ack.c1 = _en;
x_ack.n1 = out.v;
x_ack.n2 = _in_x_v;
//
x_ack.y = _x_a_B;
//
x_ack.vdd = supply.vdd;
x_ack.vss = supply.vss;
x_ack.pr_B = _reset_BX;
x_ack.sr_B = _reset_BX;
INV_X1 not_x_ack(.a = _x_a_B, .y = _x_a, .vdd = supply.vdd, .vss = supply.vss);
A_1C2P_X1 enabling(.p1 = out.a, .p2 = out.v, .c1 = _x_a, .y = _en, .vdd = supply.vdd, .vss = supply.vss);
avMx1of2<(NxC + NyC)> _in_x;
// Encoders
bool x_acks[Nx];
Mx1of2<NxC> x_enc_out;
(i:Nx:x_acks[i] = inx[i].a;)
dualrail_encoder<NxC, Nx> x_encoder(.in = x_acks, .out = x_enc_out, .supply = supply);
bool y_acks[Ny];
Mx1of2<NyC> y_enc_out;
(i:Ny:y_acks[i] = iny[i].a;)
dualrail_encoder<NyC, Ny> y_encoder(.in = y_acks, .out = y_enc_out, .supply = supply);
// Valid trees
vtree<NxC> vtree_x(.in = x_enc_out, .out = _in_x_v, .supply = supply);
vtree<NyC> vtree_y(.in = y_enc_out, .out = _in_y_v, .supply = supply);
// Buffer func thing
Mx1of2<NxC + NyC> into_buffer;
(i:0..NxC-1:into_buffer.d[i] = x_enc_out.d[i];)
(i:0..NyC-1:into_buffer.d[i+NxC] = y_enc_out.d[i];)
AND2_X1 _in_xy_v(.a = _in_x_v, .b = _in_y_v, .vss = supply.vss, .vdd = supply.vdd);
buffer_s_func<NxC + NyC> buf_s_func(.in = into_buffer, .out = out,
.en = _en, .in_v = _in_xy_v.y, .supply = supply, .reset_B = reset_B);
}
/**
* Neuron handshaking.
* Looks for a rising edge on the neuron req.
* Then performs a 2d handshake out outy then outx.
*/
export
defproc nrn_hs_2D(a1of1 in; a1of1 outx; a1of1 outy; power supply; bool reset_B) {
bool _reset_BX;
BUF_X2 reset_buf(.a = reset_B, .y = _reset_BX, .vdd = supply.vdd, .vss = supply.vss);
bool _en, _req;
// A_1C2N_RB_X1 A_ack(.c1 = _en, .n1 = _req, .n2 = in.r, .y = in.a,
// .pr_B = _reset_BX, .sr_B = _reset_BX, .vss = supply.vss, .vdd = supply.vdd);
// Switched it back
// Because had the problem that if the req was not removed in time,
// it would be recounted as a double spike,
// since in.req is still high after the out has been dealt with.
A_2C1N_RB_X1 A_ack(.c1 = _en, .c2 = in.r, .n1 = _req, .y = in.a,
.pr_B = _reset_BX, .sr_B = _reset_BX, .vss = supply.vss, .vdd = supply.vdd);
A_1C1P_X1 A_en(.p1 = _req, .c1 = in.a, .y = _en,
.vss = supply.vss, .vdd = supply.vdd);
bool _y_a_B, _x_a_B;
INV_X2 inv_x(.a = outx.a, .y = _x_a_B, .vss = supply.vss, .vdd = supply.vdd);
INV_X2 inv_y(.a = outy.a, .y = _y_a_B, .vss = supply.vss, .vdd = supply.vdd);
A_2C1P1N_RB_X1 A_req(.p1 = _x_a_B, .c1 = _en, .c2 = _y_a_B, .n1 = in.r, .y = _req,
.pr_B = _reset_BX, .sr_B = _reset_BX, .vdd = supply.vdd, .vss = supply.vss);
// y_req pull up
NAND2_X1 nand_y(.a = _y_a_B, .b = _req, .vdd = supply.vdd, .vss = supply.vss);
A_1P_U_X4 pu_y(.a = nand_y.y, .y = outy.r, .vdd = supply.vdd, .vss = supply.vss);
// x_req pull up
NAND3_X1 nand_x(.a = _x_a_B, .b = _req, .c = outy.a, .vdd = supply.vdd, .vss = supply.vss);
A_1P_U_X4 pu_x(.a = nand_x.y, .y = outx.r, .vdd = supply.vdd, .vss = supply.vss);
}
export
defproc nrn_line_end_pull_down (bool? in; bool? reset_B; power supply; bool! out)
{
bool _out, __out, nand_out;
BUF_X1 buf1(.a=in, .y=_out, .vdd=supply.vdd,.vss=supply.vss);
BUF_X1 buf2(.a=_out, .y=__out, .vdd=supply.vdd,.vss=supply.vss);
INV_X1 inv(.a = __out, .vdd=supply.vdd,.vss =supply.vss);
NAND2_X1 aenor(.a=inv.y, .b=reset_B, .y = nand_out, .vdd=supply.vdd,.vss=supply.vss);
A_1N_U_X4 pull_down(.a=nand_out, .y=out);
}
/**
* A 2d grid of neuron handshakers.
* Should then slot into the encoder.
* Each neuron has an a1of1 channel (in), which is tripped when a neuron spikes.
* N_dly is number of delay elements to add to line pull down,
* for the purpose of running ACT sims.
* It should probably be set to 0 though.
*/
export template<pint Nx, Ny, N_dly>
defproc nrn_hs_2D_array(a1of1 in[Nx*Ny]; a1of1 outx[Nx], outy[Ny];
power supply; bool reset_B) {
// Make hella signal buffers
sigbuf<Ny> rsbx(.in = reset_B, .supply = supply);
sigbuf<Nx> rsb[Ny]; // ResetSigBuf
(j:Ny:
rsb[j].in = rsbx.out[j];
rsb[j].supply = supply;
)
// Add buffers on output req lines
a1of1 _outx[Nx], _outy[Ny];
BUF_X4 out_req_buf_x[Nx];
(i:Nx:
out_req_buf_x[i].vss = supply.vss;
out_req_buf_x[i].vdd = supply.vdd;
out_req_buf_x[i].a = _outx[i].r;
out_req_buf_x[i].y = outx[i].r;
)
BUF_X4 out_req_buf_y[Ny];
(i:Ny:
out_req_buf_y[i].vss = supply.vss;
out_req_buf_y[i].vdd = supply.vdd;
out_req_buf_y[i].a = _outy[i].r;
out_req_buf_y[i].y = outy[i].r;
)
// Add buffers on output ack lines
// Note that this should be generalised.
// And probably won't even be done by ACT/innovus anwyay
// TODO: do it properly with sigbufs?
BUF_X4 out_ack_buf_x[Nx];
(i:Nx:
out_ack_buf_x[i].vss = supply.vss;
out_ack_buf_x[i].vdd = supply.vdd;
out_ack_buf_x[i].a = outx[i].a;
out_ack_buf_x[i].y = _outx[i].a;
)
BUF_X4 out_ack_buf_y[Ny];
(i:Ny:
out_ack_buf_y[i].vss = supply.vss;
out_ack_buf_y[i].vdd = supply.vdd;
out_ack_buf_y[i].a = outy[i].a;
out_ack_buf_y[i].y = _outy[i].a;
)
// Create handshake grid
pint index;
nrn_hs_2D neurons[Nx*Ny];
(i:0..Nx-1:
(j:0..Ny-1:
index = i + j*Nx;
neurons[index].supply = supply;
neurons[index].reset_B = rsb[j].out[i];
neurons[index].in = in[index];
neurons[index].outx = _outx[i];
neurons[index].outy = _outy[j];
)
)
// Create delay fifos to emulate the fact that the line pull downs
// are at the end of the line, and thus slow.
// Note that if N_dly = 0, delay fifo is just a pipe.
delay_chain<N_dly> dly_x[Nx];
delay_chain<N_dly> dly_y[Ny];
// Create x line req pull downs
nrn_line_end_pull_down pd_x[Nx];
sigbuf<Nx> rsb_pd_x(.in = reset_B, .supply = supply);
(i:0..Nx-1:
dly_x[i].supply = supply;
dly_x[i].in = _outx[i].a;
pd_x[i].in = dly_x[i].out;
pd_x[i].out = _outx[i].r;
pd_x[i].reset_B = rsb_pd_x.out[i];
pd_x[i].supply = supply;
)
// Create y line req pull downs
nrn_line_end_pull_down pd_y[Ny];
sigbuf<Ny> rsb_pd_y(.in = reset_B, .supply = supply);
(j:0..Ny-1:
dly_y[j].supply = supply;
dly_y[j].in = _outy[j].a;
pd_y[j].in = dly_y[j].out;
pd_y[j].out = _outy[j].r;
pd_y[j].reset_B = rsb_pd_y.out[j];
pd_y[j].supply = supply;
)
// Add keeps
KEEP_X1 keep_x[Nx];
(i:Nx:
keep_x[i].vdd = supply.vdd;
keep_x[i].vss = supply.vss;
keep_x[i].y = _outx[i].r;
)
KEEP_X1 keep_y[Ny];
(j:Ny:
keep_y[j].vdd = supply.vdd;
keep_y[j].vss = supply.vss;
keep_y[j].y = _outy[j].r;
)
}
}
}

167
dataflow_neuro/interfaces.act
View File

@@ -1,167 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/cell_lib_async.act";
import "../../dataflow_neuro/cell_lib_std.act";
import "../../dataflow_neuro/treegates.act";
import "../../dataflow_neuro/primitives.act";
import std::channel;
open std::channel;
// import std::func;
open std;
import std::data;
open std::data;
namespace tmpl {
namespace dataflow_neuro {
/**
* Bundled data (non dual rail, with req)
* 2
* quasi delay insensitive channel (dual rail).
* Basically a buffer with a bitwise conversion in front of it.
*/
export template<pint N, N_dly_cfg>
defproc bd2qdi(bd<N> in; avMx1of2<N> out; bool? dly_cfg[N_dly_cfg]; power supply; bool? reset_B) {
// Delay on req_in
bool _req;
delayprog<N_dly_cfg> dly(.in = in.r, .out = _req, .s = dly_cfg, .supply = supply);
// sig buff the reset signal
bool _reset_BX, _reset_BXX[N];
BUF_X4 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
sigbuf<N> reset_bufarray(.in=_reset_BX, .out=_reset_BXX, .supply=supply);
// sig buff the req
bool _reqX, _reqXX[N];
BUF_X4 req_buf(.a=_req, .y=_reqX,.vdd=supply.vdd,.vss=supply.vss);
sigbuf<N> req_bufarray(.in=_reqX, .out=_reqXX, .supply=supply);
// bd2qdi conversion
// Each line goes to a t pin, its not to a f.
bool _inB[N];
INV_X1 input_invs[N];
(i:N:
input_invs[i].a = in.d[i];
input_invs[i].y = _inB[i];
input_invs[i].vss = supply.vss;
input_invs[i].vdd = supply.vdd;
)
// BUFFER
// Basically the buffer_s but with the validity tree ripped out
// and just connected to in_req instead.
// And probably need a delay on the in_ack to ensure en has time to disable
// before the inputs go to another state.
// Actually apparently no: there is a fixed, huge delay, already incurred
// by communicating with pads-> uC -> windows 95 and back again.
// Since the input is never invalid, also need a mechanism
// for the output to become invalid, when an out_ack is received.
//control
bool _en;
A_3C_RB_X4 inack_ctl(.c1=_en,.c2=_reqX,.c3=out.v,.y=in.a,.pr_B=_reset_BX,.sr_B=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
A_1C1P_X1 en_ctl(.c1=in.a,.p1=out.v,.y=_en,.vdd=supply.vdd,.vss=supply.vss);
//function
bool _out_a_BX_t[N],_out_a_BX_f[N],_out_a_B,_en_X_t[N],_en_X_f[N];
A_2C2N_RB_X4 f_buf_func[N];
A_2C2N_RB_X4 t_buf_func[N];
sigbuf<N> en_buf_t(.in=_en, .out=_en_X_t, .supply=supply);
sigbuf<N> en_buf_f(.in=_en, .out=_en_X_f, .supply=supply);
INV_X1 out_a_inv(.a=out.a,.y=_out_a_B, .vss = supply.vss, .vdd = supply.vdd);
sigbuf<N> out_a_B_buf_f(.in=_out_a_B,.out=_out_a_BX_t, .supply=supply);
sigbuf<N> out_a_B_buf_t(.in=_out_a_B,.out=_out_a_BX_f, .supply=supply);
// check if you can also do single var to array connect a=b[N]
// and remove them from the loop
(i:N:
f_buf_func[i].y=out.d.d[i].f;
t_buf_func[i].y=out.d.d[i].t;
f_buf_func[i].c1=_en_X_f[i];
t_buf_func[i].c1=_en_X_t[i];
f_buf_func[i].c2=_out_a_BX_f[i];
t_buf_func[i].c2=_out_a_BX_t[i];
f_buf_func[i].n1=_inB[i];
t_buf_func[i].n1=in.d[i];
f_buf_func[i].n2=_reqXX[i];
t_buf_func[i].n2=_reqXX[i];
f_buf_func[i].vdd=supply.vdd;
t_buf_func[i].vdd=supply.vdd;
f_buf_func[i].vss=supply.vss;
t_buf_func[i].vss=supply.vss;
t_buf_func[i].pr_B = _reset_BXX[i];
t_buf_func[i].sr_B = _reset_BXX[i];
f_buf_func[i].pr_B = _reset_BXX[i];
f_buf_func[i].sr_B = _reset_BXX[i];
)
}
/**
* quasi delay insensitive channel (dual rail).
* 2
* Bundled data (non dual rail, with req)
*/
export template<pint N, N_dly_cfg>
defproc qdi2bd(avMx1of2<N> in; bd<N> out; bool? dly_cfg[N_dly_cfg]; power supply; bool? reset_B) {
// Buffer
buffer<N> buf(.in = in, .supply = supply, .reset_B = reset_B);
buf.out.a = out.a;
// Vtree
vtree<N> out_vtree(.supply = supply);
(i:N:
out_vtree.in.d[i].t = buf.out.d.d[i].t;
out_vtree.in.d[i].f = buf.out.d.d[i].f;
)
buf.out.v = out_vtree.out;
// Delay
delayprog<N_dly_cfg> dly(.in = out_vtree.out, .out = out.r, .s = dly_cfg, .supply = supply);
out_vtree.out = dly.in;
// Wire output data bits to buffer True lines
(i:N:
buf.out.d.d[i].t = out.d[i];
)
}
}
}

248
dataflow_neuro/primitives.act
View File

@@ -127,7 +127,7 @@ namespace tmpl {
A_2C1N_RB_X4 t_buf_func[N];
sigbuf<N> en_buf_t(.in=_en, .out=_en_X_t, .supply=supply);
sigbuf<N> en_buf_f(.in=_en, .out=_en_X_f, .supply=supply);
INV_X1 out_a_inv(.a=out.a,.y=_out_a_B, .vss = supply.vss, .vdd = supply.vdd);
INV_X1 out_a_inv(.a=out.a,.y=_out_a_B);
sigbuf<N> out_a_B_buf_f(.in=_out_a_B,.out=_out_a_BX_t);
sigbuf<N> out_a_B_buf_t(.in=_out_a_B,.out=_out_a_BX_f);
// check if you can also do single var to array connect a=b[N]
@@ -165,7 +165,7 @@ namespace tmpl {
fifo_element[i].supply = supply;
fifo_element[i].reset_B = _reset_BXX[i];
)
fifo_element[M-1].out = out;
fifo_element[N-1].out = out;
// reset buffers
bool _reset_BX;
@@ -204,7 +204,7 @@ namespace tmpl {
A_2C2N_RB_X4 t_buf_func[N];
sigbuf<N> en_buf_t(.in=_en, .out=_en_X_t, .supply=supply);
sigbuf<N> en_buf_f(.in=_en, .out=_en_X_f, .supply=supply);
INV_X1 out_a_inv(.a=out.a,.y=_out_a_B, .vss = supply.vss, .vdd = supply.vdd);
INV_X1 out_a_inv(.a=out.a,.y=_out_a_B);
sigbuf<N> out_a_B_buf_f(.in=_out_a_B,.out=_out_a_BX_t, .supply=supply);
sigbuf<N> out_a_B_buf_t(.in=_out_a_B,.out=_out_a_BX_f, .supply=supply);
// check if you can also do single var to array connect a=b[N]
@@ -238,7 +238,6 @@ namespace tmpl {
OR2_X1 out_or(.a=out1.v, .b=out2.v, .y=_out_v,.vdd=supply.vdd,.vss=supply.vss);
A_3C_RB_X4 inack_ctl(.c1=_en,.c2=_in_c_v_,.c3=_out_v,.y=in.a,.pr_B=_reset_BX,.sr_B=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
cond.a = in.a;
A_1C1P_X1 en_ctl(.c1=in.a,.p1=_out_v,.y=_en,.vdd=supply.vdd,.vss=supply.vss);
BUF_X1 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
sigbuf<2*N> reset_bufarray(.in=_reset_BX, .out=_reset_BXX);
@@ -393,7 +392,7 @@ namespace tmpl {
)
}
// Demux
export template<pint N; pbool CONDITION_SIGN>
defproc demux_td (avMx1of2<N> in; avMx1of2<N> out1; a1of1 token; bool? reset_B; avMx1of2<1> cond; power supply) {
//control
@@ -404,7 +403,7 @@ namespace tmpl {
A_1C1P_X1 en_ctl(.c1=in.a,.p1=_out_v,.y=_en,.vdd=supply.vdd,.vss=supply.vss);
BUF_X1 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
BUF_X1 reset_buf_token(.a=_reset_BX, .y=_reset_BXt,.vdd=supply.vdd,.vss=supply.vss);
sigbuf<N> reset_bufarray(.in=_reset_BX, .out=_reset_BXX, .supply=supply);
sigbuf<N> reset_bufarray(.in=_reset_BX, .out=_reset_BXX);
//validity
bool _in_v, _c_tk_buf, _c_d_buf[N], _c_v, cond_inv_t, cond_inv_f;
@@ -412,13 +411,13 @@ namespace tmpl {
//orientation of condition
[ CONDITION_SIGN ->
BUF_X1 c_buf_tk(.a=cond.d.d[0].t, .y=_c_tk_buf, .vss = supply.vss, .vdd = supply.vdd);
sigbuf<N> c_buf_d(.in=cond.d.d[0].f, .out=_c_d_buf, .supply=supply);
BUF_X1 c_buf_tk(.a=cond.d.d[0].t, .y=_c_tk_buf);
sigbuf<N> c_buf_d(.in=cond.d.d[0].f, .out=_c_d_buf);
[] else ->
INV_X1 invout_t(.a = cond.d.d[0].t,.y=cond_inv_t,.vdd = supply.vdd,.vss=supply.vss);
INV_X1 invout_f(.a = cond.d.d[0].f,.y=cond_inv_f,.vdd = supply.vdd,.vss=supply.vss);
BUF_X1 c_buf_tk_inv(.a=cond_inv_t, .y=_c_tk_buf, .vss = supply.vss, .vdd = supply.vdd);
sigbuf<N> c_buf_d_inv(.in=cond_inv_f, .out=_c_d_buf, .supply=supply);
BUF_X1 c_buf_tk_inv(.a=cond_inv_t, .y=_c_tk_buf);
sigbuf<N> c_buf_d_inv(.in=cond_inv_f, .out=_c_d_buf);
]
@@ -435,9 +434,9 @@ namespace tmpl {
A_2C2N_RB_X4 out1_t_buf_func[N];
sigbuf<N> out1_en_buf_t(.in=_en, .out=_en1_X_t, .supply=supply);
sigbuf<N> out1_en_buf_f(.in=_en, .out=_en1_X_f, .supply=supply);
INV_X1 out1_a_inv(.a=out1.a,.y=_out1_a_B, .vss = supply.vss, .vdd = supply.vdd);
sigbuf<N> out1_a_B_buf_f(.in=_out1_a_B,.out=_out1_a_BX_t, .supply=supply);
sigbuf<N> out1_a_B_buf_t(.in=_out1_a_B,.out=_out1_a_BX_f, .supply=supply);
INV_X1 out1_a_inv(.a=out1.a,.y=_out1_a_B);
sigbuf<N> out1_a_B_buf_f(.in=_out1_a_B,.out=_out1_a_BX_t);
sigbuf<N> out1_a_B_buf_t(.in=_out1_a_B,.out=_out1_a_BX_f);
(i:N:
out1_f_buf_func[i].y=out1.d.d[i].f;
out1_t_buf_func[i].y=out1.d.d[i].t;
@@ -463,8 +462,7 @@ namespace tmpl {
bool token_a_out;
A_2C2N_RB_X4 token_buf;
INV_X1 outt_a_inv(.a=token.a,.y=token_a_out, .vss = supply.vss, .vdd = supply.vdd);
INV_X1 outt_a_inv(.a=token.a,.y=token_a_out);
token_buf.y = token.r;
token_buf.c1 = _en;
@@ -509,8 +507,122 @@ namespace tmpl {
BUF_X1 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
}
// A tree composed by arbiters. The first layer takes N signals
export template<pint N>
defproc arbiter_tree(a1of1 in[N]; a1of1 out; power supply)
{
bool tout;
{ N > 0 : "Invalid N, should be greater than 0" };
/* We calculate here how many arbiters we need to create for the full tree */
pint inputs_in_layer, end, elements_in_layer;
pint odd_element_idx = 0;
pint odd_element_flag = 0;
inputs_in_layer = 0;
end = N-1;
pint element_counter = 0;
// Here we start a for loop to count the elements in the tree
// The loop iterates for every successive layer
// i is the variable used to iterate the inputs,
// j counts the elements in the layer
*[ inputs_in_layer != end ->
elements_in_layer = 0; // At every layer the counter of the elements is resetted
*[ inputs_in_layer < end ->
[ inputs_in_layer + 1 >= end ->
//In this case, the number of input is even: the layer finishes
inputs_in_layer = end;
odd_element_flag = 0;
[] inputs_in_layer + 2 >= end ->
//In this case, we arrived at the last input, this means the inputs are odd
//We need to save the odd input index and move it to the next layer,
//up to when the resulting number is even
odd_element_idx = end;
odd_element_flag = 1;
inputs_in_layer = end;
[] else ->
//If we are not close to the end, analyzes the next two inputs
inputs_in_layer = inputs_in_layer +2;
]
elements_in_layer = elements_in_layer + 1; //At every step the elements count is updated
]
//Move the inputs_in_layer to the next layer
//Increase the end to account for the next layer elements
//If there was an odd element, count it also in the end
inputs_in_layer = end + 1;
end = end + elements_in_layer + odd_element_flag;
element_counter = element_counter + elements_in_layer;
]
{ element_counter = 4 : "Michele you did wrong" };
// Creating the elements of the tree
arbiter_handshake arb_array[element_counter];
(i:element_counter:arb_array[i].supply = supply;)
// These are the wires that connect one element of the tree to the others
a1of1 channels[element_counter*2];
//Connecting the first channels to the inputs
(i:N:channels[i] = in[i];)
channels[element_counter*2-1] = out;
//Now we redo the for loop but here to assign the channels to the elements
odd_element_idx = 0;
odd_element_flag = 0;
inputs_in_layer = 0;
end = N-1;
{ end=4 : "Michele you did wrong" };
// Here we start a for loop to count the elements in the tree
// The loop iterates for every successive layer
// i is the variable used to iterate the inputs,
// j counts the elements in the layer
*[ inputs_in_layer != end ->
elements_in_layer = 0; // At every layer the counter of the elements is resetted
*[ inputs_in_layer < end ->
[ inputs_in_layer + 1 >= end ->
//In this case, the number of input is even: the layer finishes
[ odd_element_flag >= 1 ->
arb_array[elements_in_layer].in1 = channels[inputs_in_layer];
arb_array[elements_in_layer].in2 = channels[odd_element_idx];
[] else ->
arb_array[elements_in_layer].in1 = channels[inputs_in_layer];
arb_array[elements_in_layer].in2 = channels[inputs_in_layer+1];
]
inputs_in_layer = end;
odd_element_flag = 0;
[] inputs_in_layer + 2 >= end ->
//In this case, we arrived at the last input, this means the inputs are odd
//We need to save the odd input index and move it to the next layer,
//up to when the resulting number is even
odd_element_idx = end;
odd_element_flag = 1;
{ end<8 : "Michele you did wrong" };
{ odd_element_idx=4 : "Michele you did wrong" };
arb_array[elements_in_layer].in1 = channels[inputs_in_layer];
arb_array[elements_in_layer].in2 = channels[inputs_in_layer+1];
inputs_in_layer = end;
[] else ->
//If we are not close to the end, analyzes the next two inputs
arb_array[elements_in_layer].in1 = channels[inputs_in_layer];
arb_array[elements_in_layer].in2 = channels[inputs_in_layer+1];
inputs_in_layer = inputs_in_layer +2;
]
elements_in_layer = elements_in_layer + 1; //At every step the elements count is updated
]
//Move the inputs_in_layer to the next layer
//Increase the end to account for the next layer elements
//If there was an odd element, count it also in the end
inputs_in_layer = end + 1;
end = end + elements_in_layer + odd_element_flag;
element_counter = element_counter + elements_in_layer;
]
}
export template<pint N>
defproc merge (avMx1of2<N> in1; avMx1of2<N> in2; avMx1of2<N> out ; bool? reset_B; power supply) {
@@ -624,21 +736,12 @@ namespace tmpl {
// Programmable delay line.
// N is the number of layers,
// the longest layer having 2**N DLY elements
// Circuit for creating delays, there are N delay layers.
// The block has the parameters:
// N -> the number is the number of layers with the longest being 2**N elements
// wl -> word length, length of each word
// N_dly_cfg -> the number of config bits in the ACK delay line
// The block has the pins:
// in -> input data
// out -> output data
// s -> bit word with size N that sets delay configuration. int(s) = number of delays
export template<pint N>
defproc delayprog (bool! out; bool? in, s[N]; power supply)
defproc delayprog (bool! y; bool? a, s[N]; power supply)
{
{ N >= 0 : "What?" };
{ N < 10 : "Delay prog size is given in 2**N. Given N is ridiculous." };
{ N < 9 : "Delay prog size is given in 2**N. Given N is too big." };
AND2_X1 and2[N];
@@ -647,7 +750,7 @@ namespace tmpl {
bool _a[N+1]; // Holds the input to each row
_a[0] = in;
_a[0] = a;
pint i_delay;
i_delay = 0; // Index of the last connected delay element
@@ -660,7 +763,7 @@ namespace tmpl {
// Delays
dly[i_delay].a = and2[i].y;
i_delay = i_delay + 1;
(j:1..(1<<i)-1:
(j:1..i-1:
dly[i_delay].a = dly[i_delay-1].y;
i_delay = i_delay +1;
)
@@ -672,7 +775,7 @@ namespace tmpl {
_a[i+1] = mu2[i].y;
)
out = mu2[N-1].y;
y = mu2[N-1].y;
// Connect everything to vdd/gnd
@@ -684,91 +787,4 @@ namespace tmpl {
(i:N:mu2[i].vss = supply.vss;)
(i:((1<<N)-1):dly[i].vss = supply.vss;)
}
// Non programmable delays
// N is number of delays to have in series (not log!!).
// Is useful for testing purposes.
// But should probably remove before running innovus etc.
export template<pint N>
defproc delay_fifo (bool out; bool in; power supply) {
{ N >= 0 : "What?" };
[N >= 1 ->
DLY4_X1 dly[N];
dly[0].vdd = supply.vdd;
dly[0].vss = supply.vss;
dly[0].a = in;
(i:1..N-1:
dly[i].vdd = supply.vdd;
dly[i].vss = supply.vss;
dly[i].a = dly[i-1].y;
)
dly[N-1].vdd = supply.vdd;
dly[N-1].vss = supply.vss;
dly[N-1].y = out;
[] N = 0 ->
in = out;
]
}
/**
* Appends a hard-coded word "VAL" to an input.
* Works by piping through all sigs, but adding
* some extra sigs when the input is valid.
* N is size of channel to pipe through.
* NVAL is size of word to be put on output.
* VAL is word to be put on output.
* Output looks like
* 0..............N........N+NVAL-1
* --input_data----LSB....MSB
*
*/
export template<pint N, NVAL, VAL>
defproc append (avMx1of2<N> in; avMx1of2<N+NVAL> out; power supply)
{
{ N >= 0 : "What?" };
{ NVAL >= 0 : "What?" };
{ NVAL < 1<<VAL : "VAL too big!" };
// valid tree
vtree<N> in_val(.supply = supply);
(i:N:
in_val.in.d[i].t = in.d.d[i].t;
in_val.in.d[i].f = in.d.d[i].f;
)
// wire through most signals
(i:N:
in.d.d[i].t = out.d.d[i].t;
in.d.d[i].f = out.d.d[i].f;
)
in.a = out.a;
in.v = out.v;
// appender
pint bitval;
sigbuf<NVAL> sb(.in = in_val.out, .supply = supply);
TIELO_X1 tielows[NVAL];
(i:NVAL:tielows[i].vss = supply.vss; tielows[i].vdd = supply.vdd;)
(i:0..NVAL-1:
bitval = (VAL & ( 1 << i )) >> i;
[ bitval = 1 ->
out.d.d[i+N].t = sb.out[i];
out.d.d[i+N].f = tielows[i].y;
[] bitval = 0 ->
out.d.d[i+N].f = sb.out[i];
out.d.d[i+N].t = tielows[i].y;
[] bitval >= 2 -> {false : "fuck"};
]
)
}
}}

258
dataflow_neuro/registers.act
View File

@@ -1,258 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/cell_lib_async.act";
import "../../dataflow_neuro/cell_lib_std.act";
import "../../dataflow_neuro/treegates.act";
import "../../dataflow_neuro/primitives.act";
import "../../dataflow_neuro/coders.act";
// import tmpl::dataflow_neuro;
// import tmpl::dataflow_neuro;
import std::channel;
open std::channel;
namespace tmpl {
namespace dataflow_neuro {
// Circuit for storing registers using AER
// The block has the parameters:
// lognw -> log2(number of words), parameters you can store
// wl -> word length, length of each word
// N_dly_cfg -> the number of config bits in the ACK delay line
// The block has the pins:
// in -> input data,
// - the first bit is write/read_B
// - the next lognw bits describe the location,
// - the last wl the word to write
// data -> the data saved in the flip flop, sized wl x nw
export template<pint lognw,wl,N_dly_cfg>
defproc register_w (avMx1of2<1+lognw+wl> in; d1of<wl> data[1<<lognw]; power supply; bool? reset_B,reset_mem_B,dly_cfg[N_dly_cfg]){
bool _in_v_temp,_in_a_temp,_clock_temp,_clock,_clock_temp_inv;
pint nw = 1<<lognw;
//Validation of the input
vtree<1+lognw+wl> val_input(.in = in.d,.out = _in_v_temp, .supply = supply);
sigbuf_1output<4> val_input_X(.in = _in_v_temp,.out = in.v,.supply = supply);
// Generation of the fake clock pulse (inverted because the ff clocks are low_active)
delayprog<N_dly_cfg> clk_dly(.in = _in_v_temp, .out = _clock_temp,.s = dly_cfg, .supply = supply);
INV_X1 inv_clk(.a = _clock_temp,.y = _clock_temp_inv,.vdd = supply.vdd,.vss = supply.vss);
sigbuf_1output<4> clk_X(.in = _clock_temp,.out = _clock,.supply = supply);
// Sending back to the ackowledge
delayprog<N_dly_cfg> ack_dly(.in = _clock_temp_inv, .out = _in_a_temp,.s = dly_cfg, .supply = supply);
sigbuf_1output<4> ack_input_X(.in = _in_a_temp,.out = in.a,.supply = supply);
//Reset Buffers
bool _reset_BX,_reset_mem_BX,_reset_mem_BXX[nw*wl];
BUF_X1 reset_buf_BX(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
BUF_X1 reset_buf_BXX(.a=reset_mem_B, .y=_reset_mem_BX,.vdd=supply.vdd,.vss=supply.vss);
sigbuf<nw*wl> reset_bufarray(.in=_reset_mem_BX, .out=_reset_mem_BXX,.supply=supply);
// Creating the different flip flop arrays
bool _out_encoder[nw],_clock_word_temp[nw],_clock_word[nw],_clock_buffer_out[nw*wl];
andtree<lognw> atree[nw];
AND2_X1 and_encoder[nw];
sigbuf<wl> clock_buffer[nw];
DFFQ_R_X1 ff[nw*wl];
pint bitval;
(k:nw:atree[k].supply = supply;)
(word_idx:nw:
// Decoding the bit pattern to understand which word we are looking at
(pin_idx:lognw:
bitval = (word_idx & ( 1 << pin_idx )) >> pin_idx; // Get binary digit of integer i, column j
[bitval = 1 ->
atree[word_idx].in[pin_idx] = in.d.d[pin_idx+wl].t;
[] bitval = 0 ->
atree[word_idx].in[pin_idx] = in.d.d[pin_idx+wl].f;
[]bitval >= 2 -> {false : "fuck"};
]
)
// Activating the fake clock for the right word
atree[word_idx].out = _out_encoder[word_idx];
and_encoder[word_idx].a = _out_encoder[word_idx];
and_encoder[word_idx].b = _clock;
and_encoder[word_idx].y = _clock_word_temp[word_idx];
and_encoder[word_idx].vdd = supply.vdd;
and_encoder[word_idx].vss = supply.vss;
clock_buffer[word_idx].in = _clock_word_temp[word_idx];
clock_buffer[word_idx].supply = supply;
// Describing all the FF and their connection
(bit_idx:wl:
ff[bit_idx+word_idx*(wl)].clk_B = clock_buffer[word_idx].out[bit_idx];
ff[bit_idx+word_idx*(wl)].d = in.d.d[bit_idx].t;
ff[bit_idx+word_idx*(wl)].q = data[word_idx].d[bit_idx];
ff[bit_idx+word_idx*(wl)].reset_B = _reset_mem_BXX[bit_idx+word_idx*(wl)];
ff[bit_idx+word_idx*(wl)].vdd = supply.vdd;
ff[bit_idx+word_idx*(wl)].vss = supply.vss;
)
)
}
// Circuit for storing and reading registers using AER
// The block has the parameters:
// lognw -> log2(number of words), parameters you can store
// wl -> word length, length of each word
// N_dly_cfg -> the number of config bits in the ACK delay line
// The block has the pins:
// in -> input data,
// - the MSB is write/read_B
// - the next MSB bits (size lognw) are the location,
// - the LSB (size wl) are the word to write
// out -> in case a reading phase is required, the output is used to show the stored data
// - the MSB bits (size lognw) tell the read register
// - the LSB bits (size wl) tell the word read
// data -> the data saved in the flip flop, sized wl x nw
export template<pint lognw,wl,N_dly_cfg>
defproc register_rw (avMx1of2<1+lognw+wl> in; avMx1of2<lognw+wl> out; d1of<wl> data[1<<lognw]; power supply; bool? reset_B,reset_mem_B,dly_cfg[N_dly_cfg]){
pint nw = 1<<lognw;
bool _in_v_temp,_in_a_temp,_clock_temp,_clock[nw],_clock_temp_inv, _in_a_write, _in_a_read;
//Validation of the input
vtree<1+lognw+wl> val_input(.in = in.d,.out = _in_v_temp, .supply = supply);
sigbuf_1output<12> val_input_X(.in = _in_v_temp,.out = in.v,.supply = supply);
// Acknowledgment
OR2_X1 ack_readwrite(.a = _in_a_write,.b = _in_a_read,.y = _in_a_temp,.vdd = supply.vdd,.vss = supply.vss);
sigbuf_1output<12> ack_input_X(.in = _in_a_temp,.out = in.a,.supply = supply);
// WRITE
// Generation of the fake clock pulse if write is HIGH (inverted because the ff clocks are low_active)
bool _in_v_temp_write;
AND2_X1 clk_switch(.a = _in_v_temp,.b = in.d.d[lognw+wl].f,.y = _in_v_temp_write,.vdd = supply.vdd,.vss = supply.vss);
delayprog<N_dly_cfg> clk_dly(.in = _in_v_temp_write, .out = _clock_temp,.s = dly_cfg, .supply = supply);
INV_X1 inv_clk(.a = _clock_temp,.y = _clock_temp_inv,.vdd = supply.vdd,.vss = supply.vss);
sigbuf<nw> clk_X(.in = _clock_temp_inv, .out = _clock,.supply = supply);
sigbuf<wl> clock_buffer[nw];
bool _clock_word_temp[nw],_clock_word[nw],_clock_buffer_out[nw*wl];
// Sending back to the acknowledge
bool _in_a_write_temp;
delayprog<N_dly_cfg> ack_dly(.in = _clock_temp, .out = _in_a_write_temp,.s = dly_cfg, .supply = supply);
AND2_X1 ack_write_and(.a = in.d.d[lognw+wl].f,.b = _in_a_write_temp,.y = _in_a_write,.vdd = supply.vdd, .vss = supply.vss);
// READ
//Outputing the word to read
AND2_X1 word_to_read[nw];
sigbuf<wl*2> word_to_read_X[nw];
ortree<nw> bitselector_t[wl];
ortree<nw> bitselector_f[wl];
AND2_X1 word_selector_t[nw*wl];
AND2_X1 word_selector_f[nw*wl];
buffer_s<lognw+wl> output_buf(.out = out,.supply = supply, .reset_B = reset_B);
AND2_X1 address_propagator_f[lognw],address_propagator_t[lognw];
// Outputting the address if the read is true
(i:lognw:
address_propagator_t[i].a = in.d.d[lognw+wl].t;
address_propagator_t[i].b = in.d.d[i+wl].t;
address_propagator_t[i].y = output_buf.in.d.d[i+wl].t;
address_propagator_t[i].vdd = supply.vdd;
address_propagator_t[i].vss = supply.vss;
address_propagator_f[i].a = in.d.d[lognw+wl].t;
address_propagator_f[i].b = in.d.d[i+wl].f;
address_propagator_f[i].y = output_buf.in.d.d[i+wl].f;
address_propagator_f[i].vdd = supply.vdd;
address_propagator_f[i].vss = supply.vss;
)
AND2_X1 ack_read_and(.a = in.d.d[lognw+wl].t,.b = output_buf.in.a,.y = _in_a_read,.vdd = supply.vdd, .vss = supply.vss);
//Reset Buffers
bool _reset_BX, _reset_BXX[nw],_reset_mem_BX,_reset_mem_BXX[nw*wl];
BUF_X1 reset_buf_BX(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
BUF_X1 reset_buf_BXX(.a=reset_mem_B, .y=_reset_mem_BX,.vdd=supply.vdd,.vss=supply.vss);
sigbuf<nw*wl> reset_mem_bufarray(.in=_reset_mem_BX, .out=_reset_mem_BXX,.supply=supply);
sigbuf<nw> reset_bufarray(.in=_reset_BX, .out=_reset_BXX,.supply=supply);
//Creating the encoder
andtree<lognw> atree[nw];
OR2_X1 or_encoder[nw];
INV_X1 inv_encoder[nw];
// Creating the different flip flop arrays
bool _out_encoder[nw];
DFFQ_R_X1 ff[nw*wl];
AND2_X1 val_chck[nw*wl];
bool _val_chck_out[nw*wl];
bool _in_v_temp_buf[nw*wl];
sigbuf<nw*wl> v_buf(.in = _in_v_temp,.out = _in_v_temp_buf,.supply = supply);
// For loop for assigning the different components
pint bitval;
(k:nw:atree[k].supply = supply;)
(word_idx:nw:
// Decoding the bit pattern to understand which word we are looking at
(pin_idx:lognw:
bitval = (word_idx & ( 1 << pin_idx )) >> pin_idx; // Get binary digit of integer i, column j
[bitval = 1 ->
atree[word_idx].in[pin_idx] = in.d.d[pin_idx+wl].t;
[] bitval = 0 ->
atree[word_idx].in[pin_idx] = in.d.d[pin_idx+wl].f;
[]bitval >= 2 -> {false : "fuck"};
]
)
// WRITE: Activating the fake clock for the right word
atree[word_idx].out = _out_encoder[word_idx];
inv_encoder[word_idx].a = _out_encoder[word_idx];
inv_encoder[word_idx].y = or_encoder[word_idx].a;
inv_encoder[word_idx].vdd = supply.vdd;
inv_encoder[word_idx].vss = supply.vss;
or_encoder[word_idx].b = _clock[word_idx];
or_encoder[word_idx].y = _clock_word_temp[word_idx];
or_encoder[word_idx].vdd = supply.vdd;
or_encoder[word_idx].vss = supply.vss;
clock_buffer[word_idx].in = _clock_word_temp[word_idx];
clock_buffer[word_idx].supply = supply;
// READ: Selecting the right word to read if read is high
word_to_read[word_idx].a = in.d.d[lognw+wl].t;
word_to_read[word_idx].b = _out_encoder[word_idx];
word_to_read[word_idx].y = word_to_read_X[word_idx].in;
word_to_read[word_idx].vdd = supply.vdd;
word_to_read[word_idx].vss = supply.vss;
word_to_read_X[word_idx].supply = supply;
(bit_idx:wl:
// Describing all the FF and their connection
val_chck[bit_idx].a = _in_v_temp_buf[word_idx+bit_idx];
val_chck[bit_idx].b = in.d.d[bit_idx].t;
val_chck[bit_idx].y = _val_chck_out[bit_idx];
val_chck[bit_idx].vdd = supply.vdd;
val_chck[bit_idx].vss = supply.vss;
ff[bit_idx+word_idx*(wl)].clk_B = clock_buffer[word_idx].out[bit_idx];
ff[bit_idx+word_idx*(wl)].d = in.d.d[bit_idx].t;
ff[bit_idx+word_idx*(wl)].q = data[word_idx].d[bit_idx];
ff[bit_idx+word_idx*(wl)].reset_B = _reset_mem_BXX[bit_idx+word_idx*(wl)];
ff[bit_idx+word_idx*(wl)].vdd = supply.vdd;
ff[bit_idx+word_idx*(wl)].vss = supply.vss;
// READ: creating the selectors for propagating the right word
word_to_read_X[word_idx].out[bit_idx] = word_selector_t[bit_idx+(word_idx*(wl))].a;
word_to_read_X[word_idx].out[bit_idx+wl] = word_selector_f[bit_idx+(word_idx*(wl))].a;
word_selector_t[bit_idx+word_idx*(wl)].b = ff[bit_idx+(word_idx*(wl))].q;
word_selector_t[bit_idx+word_idx*(wl)].y = bitselector_t[bit_idx].in[word_idx];
word_selector_f[bit_idx+word_idx*(wl)].b = ff[bit_idx+(word_idx*(wl))].q_B;
word_selector_f[bit_idx+word_idx*(wl)].y = bitselector_f[bit_idx].in[word_idx];
bitselector_t[bit_idx].out = output_buf.in.d.d[bit_idx].t;
bitselector_f[bit_idx].out = output_buf.in.d.d[bit_idx].f;
bitselector_t[bit_idx].supply = supply;
bitselector_f[bit_idx].supply = supply;
)
)
}
}}

123
dataflow_neuro/treegates.act
View File

@@ -26,7 +26,6 @@
**************************************************************************/
import "../../dataflow_neuro/cell_lib_async.act";
import "../../dataflow_neuro/cell_lib_std.act";
import std::channel;
open std::channel;
namespace tmpl {
@@ -48,9 +47,6 @@ defproc ortree (bool? in[N]; bool! out; power supply)
{ N > 0 : "What?" };
[N = 1 -> BUF_X1 b(.vss=supply.vss, .vdd = supply.vdd, .a = in[0], .y = out);
[] N > 1 ->
pint i, end, j;
i = 0;
end = N-1;
@@ -87,18 +83,18 @@ defproc ortree (bool? in[N]; bool! out; power supply)
/* array to hold the actual C-elments, either A2C or A3C */
[lenTree2Count > 0 ->
OR2_X1 or2s[lenTree2Count];
OR2_X1 C2Els[lenTree2Count];
]
[lenTree3Count > 0 ->
OR3_X1 or3s[lenTree3Count];
OR3_X1 C3Els[lenTree3Count];
]
(h:lenTree2Count:or2s[h].vdd = supply.vdd;)
(h:lenTree3Count:or3s[h].vdd = supply.vdd;)
(h:lenTree2Count:C2Els[h].vdd = supply.vdd;)
(h:lenTree3Count:C3Els[h].vdd = supply.vdd;)
(h:lenTree2Count:or2s[h].vss = supply.vss;)
(h:lenTree3Count:or3s[h].vss = supply.vss;)
(h:lenTree2Count:C2Els[h].vss = supply.vss;)
(h:lenTree3Count:C3Els[h].vss = supply.vss;)
/* Reset the variables we just stole lol */
i = 0;
@@ -121,25 +117,25 @@ defproc ortree (bool? in[N]; bool! out; power supply)
j = j + 1;
[ i+1 >= end ->
/*-- last piece: use either a 2 input C-element --*/
or2s[tree2Index].a = tmp[i];
or2s[tree2Index].b = tmp[i+1];
or2s[tree2Index].y = tmp[end+j];
C2Els[tree2Index].a = tmp[i];
C2Els[tree2Index].b = tmp[i+1];
C2Els[tree2Index].y = tmp[end+j];
tree2Index = tree2Index +1;
i = end;
[] i+2 >= end ->
/*-- last piece: use either a 3 input C-element --*/
or3s[tree3Index].a = tmp[i];
or3s[tree3Index].b = tmp[i+1];
or3s[tree3Index].c = tmp[i+2];
or3s[tree3Index].y = tmp[end+j];
C3Els[tree3Index].a = tmp[i];
C3Els[tree3Index].b = tmp[i+1];
C3Els[tree3Index].c = tmp[i+2];
C3Els[tree3Index].y = tmp[end+j];
tree3Index = tree3Index +1;
i = end;
[] else ->
/*-- more to come; so use a two input C-element --*/
or2s[tree2Index].a = tmp[i];
or2s[tree2Index].b = tmp[i+1];
or2s[tree2Index].y = tmp[end+j];
C2Els[tree2Index].a = tmp[i];
C2Els[tree2Index].b = tmp[i+1];
C2Els[tree2Index].y = tmp[end+j];
tree2Index = tree2Index +1;
i = i + 2;
]
@@ -151,8 +147,6 @@ defproc ortree (bool? in[N]; bool! out; power supply)
]
out = tmp[end];
]
}
export template<pint N>
@@ -162,11 +156,6 @@ defproc andtree (bool? in[N]; bool! out; power supply)
{ N > 0 : "What?" };
[N = 1 -> BUF_X1 b(.vss=supply.vss, .vdd = supply.vdd, .a = in[0], .y = out);
[] N > 1 ->
pint i, end, j;
i = 0;
end = N-1;
@@ -203,18 +192,18 @@ defproc andtree (bool? in[N]; bool! out; power supply)
/* array to hold the actual C-elments, either A2C or A3C */
[lenTree2Count > 0 ->
AND2_X1 and2s[lenTree2Count];
AND2_X1 C2Els[lenTree2Count];
]
[lenTree3Count > 0 ->
AND3_X1 and3s[lenTree3Count];
AND3_X1 C3Els[lenTree3Count];
]
(h:lenTree2Count:and2s[h].vdd = supply.vdd;)
(h:lenTree3Count:and3s[h].vdd = supply.vdd;)
(h:lenTree2Count:C2Els[h].vdd = supply.vdd;)
(h:lenTree3Count:C3Els[h].vdd = supply.vdd;)
(h:lenTree2Count:and2s[h].vss = supply.vss;)
(h:lenTree3Count:and3s[h].vss = supply.vss;)
(h:lenTree2Count:C2Els[h].vss = supply.vss;)
(h:lenTree3Count:C3Els[h].vss = supply.vss;)
/* Reset the variables we just stole lol */
i = 0;
@@ -237,25 +226,25 @@ defproc andtree (bool? in[N]; bool! out; power supply)
j = j + 1;
[ i+1 >= end ->
/*-- last piece: use either a 2 input C-element --*/
and2s[tree2Index].a = tmp[i];
and2s[tree2Index].b = tmp[i+1];
and2s[tree2Index].y = tmp[end+j];
C2Els[tree2Index].a = tmp[i];
C2Els[tree2Index].b = tmp[i+1];
C2Els[tree2Index].y = tmp[end+j];
tree2Index = tree2Index +1;
i = end;
[] i+2 >= end ->
/*-- last piece: use either a 3 input C-element --*/
and3s[tree3Index].a = tmp[i];
and3s[tree3Index].b = tmp[i+1];
and3s[tree3Index].c = tmp[i+2];
and3s[tree3Index].y = tmp[end+j];
C3Els[tree3Index].a = tmp[i];
C3Els[tree3Index].b = tmp[i+1];
C3Els[tree3Index].c = tmp[i+2];
C3Els[tree3Index].y = tmp[end+j];
tree3Index = tree3Index +1;
i = end;
[] else ->
/*-- more to come; so use a two input C-element --*/
and2s[tree2Index].a = tmp[i];
and2s[tree2Index].b = tmp[i+1];
and2s[tree2Index].y = tmp[end+j];
C2Els[tree2Index].a = tmp[i];
C2Els[tree2Index].b = tmp[i+1];
C2Els[tree2Index].y = tmp[end+j];
tree2Index = tree2Index +1;
i = i + 2;
]
@@ -267,8 +256,6 @@ defproc andtree (bool? in[N]; bool! out; power supply)
]
out = tmp[end];
]
}
/*
@@ -282,10 +269,6 @@ defproc ctree (bool? in[N]; bool! out; power supply)
{ N > 0 : "What?" };
bool meaningless_var;
[N = 1 -> BUF_X1 b(.vss=supply.vss, .vdd = supply.vdd, .a = in[0], .y = out);
[] N > 1 ->
pint i, end, j;
i = 0;
end = N-1;
@@ -390,11 +373,6 @@ defproc ctree (bool? in[N]; bool! out; power supply)
out = tmp[end];
]
}
export template<pint N>
@@ -402,16 +380,16 @@ defproc vtree (std::data::Mx1of2?<N> in; bool! out; power supply)
{
// OR layer for making OR between true and false of in (they are then sent to Ctree)
OR2_X1 OR2_tf[N];
ctree<N> ct;
ctree<N> myctree;
(l:N:
OR2_tf[l].a = in.d[l].t;
OR2_tf[l].b = in.d[l].f;
OR2_tf[l].y = ct.in[l];
OR2_tf[l].y = myctree.in[l];
OR2_tf[l].vdd = supply.vdd;
OR2_tf[l].vss = supply.vss;
)
ct.supply = supply;
out = ct.out;
myctree.supply = supply;
out = myctree.out;
}
export template<pint N>
defproc sigbuf (bool? in; bool! out[N]; power supply)
@@ -438,34 +416,5 @@ defproc sigbuf (bool? in; bool! out[N]; power supply)
]
(i:1..N-1:out[i]=out[0];)
}
//Sigbuf in which there is only 1 output. Made for outputs that cannot have multiple wires.
export template<pint N>
defproc sigbuf_1output (bool? in; bool! out; power supply)
{
{ N >= 0 : "sigbuf: parameter error" };
{ N <= 43 : "sigbuf: parameter error, N too big" };
/* -- just use in sized driver here -- */
[ N <= 4 ->
BUF_X1 buf1 (.a = in, .y = out, .vdd = supply.vdd, .vss = supply.vss);
[] N >= 5 & N <= 7 ->
BUF_X2 buf2 (.a = in, .y = out, .vdd = supply.vdd, .vss = supply.vss);
[] N >= 8 & N <= 10 ->
BUF_X3 buf3 (.a = in, .y = out, .vdd = supply.vdd, .vss = supply.vss);
[] N >= 11 & N <= 14 ->
BUF_X4 buf4 (.a = in, .y = out, .vdd = supply.vdd, .vss = supply.vss);
[] N >= 15 & N <= 18 ->
BUF_X6 buf6 (.a = in, .y = out, .vdd = supply.vdd, .vss = supply.vss);
[] N >= 19 & N <= 29 ->
BUF_X8 buf8 (.a = in, .y = out, .vdd = supply.vdd, .vss = supply.vss);
[] N >= 30 & N <= 42 ->
BUF_X12 buf12 (.a = in, .y = out, .vdd = supply.vdd, .vss = supply.vss);
]
}
}}

11
test/prsim_plot.py
View File

@@ -1,4 +1,4 @@
#!/usr/bin/env python3
#!/usr/bin/python3
import sys
import glob
@@ -54,21 +54,17 @@ Use -exclude='regex' to specify signals to exclude (or -ex).""")
raise Exception("Unknown colour given. I cba to code up general colours atm.")
# Check if start time given
t0 = None
for arg in argv:
r = re.findall(r'-t0=(\d+)', arg)
if len(r) >= 1:
print(f"Filtering by start time t0 = {r[0]}")
t0 = int[r[0]]
entries = [e for e in entries if int(e[0]) >= int(r[0])]
# Check if end time given
t1 = None
for arg in argv:
r = re.findall(r'-t1=(\d+)', arg)
if len(r) >= 1:
print(f"Filtering by end time t1 = {r[0]}")
t1 = int[r[0]]
entries = [e for e in entries if int(e[0]) <= int(r[0])]
@@ -119,7 +115,6 @@ Use -exclude='regex' to specify signals to exclude (or -ex).""")
# Get list of all times (after filtering)
times = np.array([int(e[0]) for e in entries])
if not include_all_times: unique_times = np.unique(times)
num_times = unique_times.shape[0]
# Get list of all sigs
sigs = np.array([e[1] for e in entries])
@@ -178,12 +173,8 @@ Use -exclude='regex' to specify signals to exclude (or -ex).""")
# ax.set_ylabel("Signal")
ax.set_yticks([])
# Plot signal names
sig_repeat_period = 20
for sig in unique_sigs:
ax.text(-1, sig_to_index(sig), sig, ha = "right", va = "center", size = 10)
ax.text(num_times, sig_to_index(sig), sig, ha = "left", va = "center", size = 10)
for i in range(num_sigs-1):
ax.axhline(i+0.5, c = "white", lw = 2)

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53
test/unit_tests/append_5_3_2/test.act
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@@ -1,53 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/primitives.act";
import globals;
open tmpl::dataflow_neuro;
defproc append_5_3_2(avMx1of2<5> in; avMx1of2<8> out)
{
bool _reset_B;
prs {
Reset => _reset_B-
}
fifo<5,4> fifo_pre(.in = in, .reset_B = _reset_B);
append<5,3,3> app(.in = fifo_pre.out);
fifo<5+3,4> fifo_post(.in = app.out, .out = out, .reset_B = _reset_B);
app.supply.vdd = Vdd;
app.supply.vss = GND;
fifo_pre.supply.vdd = Vdd;
fifo_pre.supply.vss = GND;
fifo_post.supply.vdd = Vdd;
fifo_post.supply.vss = GND;
}
append_5_3_2 b;

78
test/unit_tests/append_5_3_2/test.prsim
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@@ -1,78 +0,0 @@
watchall
set b.out.a 0
set b.out.v 0
set Reset 0
set-qdi-channel-neutral "b.in" 5
cycle
system "echo '[] set Reset 1'"
set Reset 1
cycle
system "echo '[] set Reset 0'"
set Reset 0
mode run
cycle
status X
assert-qdi-channel-neutral "b.out" 8
assert b.in.a 0
assert b.in.v 0
system "echo '[] sending in a 31'"
set-qdi-channel-valid "b.in" 5 31
cycle
assert-qdi-channel-valid "b.out" 8 127
assert b.in.a 1
assert b.in.v 1
system "echo '[] removing input'"
set-qdi-channel-neutral "b.in" 5
cycle
assert b.in.a 0
assert b.in.v 0
system "echo '[] sending in a 0'"
set-qdi-channel-valid "b.in" 5 0
cycle
# assert-qdi-channel-valid "b.out" 8 96
assert b.in.a 1
assert b.in.v 1
system "echo '[] removing input'"
set-qdi-channel-neutral "b.in" 5
cycle
assert b.in.a 0
assert b.in.v 0
system "echo '[] receiving out ack/val'"
set b.out.a 1
set b.out.v 1
cycle
assert-qdi-channel-neutral "b.out" 8
system "echo '[] removing out ack/val'"
set b.out.a 0
set b.out.v 0
cycle
assert-qdi-channel-valid "b.out" 8 96
system "echo '[] receiving out ack/val'"
set b.out.a 1
set b.out.v 1
cycle
assert-qdi-channel-neutral "b.out" 8
system "echo '[] removing out ack/val'"
set b.out.a 0
set b.out.v 0
cycle
assert-qdi-channel-neutral "b.out" 8

98
test/unit_tests/arbiter_tree_simple_nosim/run/prsim.out
View File

@@ -1,98 +0,0 @@
my_tree.in[4].r my_tree.at_cell.tmp[6].r my_tree.at_cell.arbs[0].arbiter._y1 my_tree.in[2].a my_tree.at_cell.tmp[8].a my_tree.at_cell.arbs[0]._y1_arb my_tree.out.r my_tree.at_cell.tmp[5].a my_tree.at_cell.arbs[2]._y2_arb my_tree.at_cell.arbs[3].ack_cell1._y my_tree.in[0].a my_tree.at_cell.tmp[6].a my_tree.in[4].a my_tree.at_cell.arbs[2].arbiter._y2 my_tree.in[1].a my_tree.out.a my_tree.at_cell.arbs[0].ack_cell1._y my_tree.in[0].r my_tree.at_cell.arbs[3].ack_cell2._y my_tree.in[3].r my_tree.at_cell.tmp[5].r my_tree.in[1].r my_tree.at_cell.arbs[0]._y2_arb my_tree.at_cell.arbs[2].ack_cell2._y my_tree.at_cell.arbs[1]._y1_arb my_tree.at_cell.arbs[1].ack_cell2._y my_tree.in[2].r my_tree.in[3].a my_tree.at_cell.tmp[8].r my_tree.at_cell.arbs[1]._y2_arb my_tree.at_cell.arbs[3]._y1_arb my_tree.at_cell.arbs[3].or_cell._y my_tree.at_cell.arbs[1].arbiter._y2 my_tree.at_cell.arbs[3].arbiter._y2 my_tree.at_cell.arbs[1].ack_cell1._y my_tree.at_cell.arbs[3].arbiter._y1 my_tree.at_cell.arbs[0].ack_cell2._y my_tree.at_cell.arbs[3]._y2_arb my_tree.at_cell.arbs[2].ack_cell1._y my_tree.at_cell.arbs[1].or_cell._y my_tree.at_cell.arbs[2]._y1_arb my_tree.at_cell.arbs[1].arbiter._y1 my_tree.at_cell.arbs[0].or_cell._y my_tree.at_cell.arbs[0].arbiter._y2 my_tree.at_cell.arbs[2].or_cell._y my_tree.at_cell.arbs[2].arbiter._y1
1 my_tree.in[0].r : 0
1 my_tree.out.a : 0
1 my_tree.in[2].r : 0
1 my_tree.in[4].r : 0
1 my_tree.in[1].r : 0
1 my_tree.in[3].r : 0
3 my_tree.at_cell.arbs[3].arbiter._y2 : 1 [by my_tree.in[4].r:=0]
117 my_tree.at_cell.arbs[3]._y2_arb : 0 [by my_tree.at_cell.arbs[3].arbiter._y2:=1]
1138 my_tree.at_cell.arbs[1].arbiter._y2 : 1 [by my_tree.in[3].r:=0]
2864 my_tree.at_cell.arbs[1]._y2_arb : 0 [by my_tree.at_cell.arbs[1].arbiter._y2:=1]
4754 my_tree.at_cell.arbs[0].arbiter._y2 : 1 [by my_tree.in[1].r:=0]
4793 my_tree.at_cell.arbs[0]._y2_arb : 0 [by my_tree.at_cell.arbs[0].arbiter._y2:=1]
7093 my_tree.at_cell.arbs[0].arbiter._y1 : 1 [by my_tree.in[0].r:=0]
7108 my_tree.at_cell.arbs[0]._y1_arb : 0 [by my_tree.at_cell.arbs[0].arbiter._y1:=1]
7599 my_tree.at_cell.arbs[0].or_cell._y : 1 [by my_tree.at_cell.arbs[0]._y1_arb:=0]
7612 my_tree.at_cell.tmp[5].r : 0 [by my_tree.at_cell.arbs[0].or_cell._y:=1]
7652 my_tree.at_cell.arbs[2].arbiter._y1 : 1 [by my_tree.at_cell.tmp[5].r:=0]
8067 my_tree.at_cell.arbs[2]._y1_arb : 0 [by my_tree.at_cell.arbs[2].arbiter._y1:=1]
10468 my_tree.at_cell.arbs[1].arbiter._y1 : 1 [by my_tree.in[2].r:=0]
10488 my_tree.at_cell.arbs[1]._y1_arb : 0 [by my_tree.at_cell.arbs[1].arbiter._y1:=1]
16549 my_tree.at_cell.arbs[1].or_cell._y : 1 [by my_tree.at_cell.arbs[1]._y1_arb:=0]
16596 my_tree.at_cell.tmp[6].r : 0 [by my_tree.at_cell.arbs[1].or_cell._y:=1]
16612 my_tree.at_cell.arbs[2].arbiter._y2 : 1 [by my_tree.at_cell.tmp[6].r:=0]
60710 my_tree.at_cell.arbs[2]._y2_arb : 0 [by my_tree.at_cell.arbs[2].arbiter._y2:=1]
65483 my_tree.at_cell.arbs[3].ack_cell2._y : 1 [by my_tree.at_cell.arbs[3]._y2_arb:=0]
65487 my_tree.in[4].a : 0 [by my_tree.at_cell.arbs[3].ack_cell2._y:=1]
74434 my_tree.at_cell.arbs[2].or_cell._y : 1 [by my_tree.at_cell.arbs[2]._y2_arb:=0]
83563 my_tree.at_cell.tmp[8].r : 0 [by my_tree.at_cell.arbs[2].or_cell._y:=1]
83578 my_tree.at_cell.arbs[3].arbiter._y1 : 1 [by my_tree.at_cell.tmp[8].r:=0]
126826 my_tree.at_cell.arbs[3]._y1_arb : 0 [by my_tree.at_cell.arbs[3].arbiter._y1:=1]
126881 my_tree.at_cell.arbs[3].or_cell._y : 1 [by my_tree.at_cell.arbs[3]._y1_arb:=0]
163757 my_tree.at_cell.arbs[3].ack_cell1._y : 1 [by my_tree.at_cell.arbs[3]._y1_arb:=0]
178534 my_tree.out.r : 0 [by my_tree.at_cell.arbs[3].or_cell._y:=1]
193537 my_tree.at_cell.tmp[8].a : 0 [by my_tree.at_cell.arbs[3].ack_cell1._y:=1]
207386 my_tree.at_cell.arbs[2].ack_cell2._y : 1 [by my_tree.at_cell.tmp[8].a:=0]
218349 my_tree.at_cell.arbs[2].ack_cell1._y : 1 [by my_tree.at_cell.tmp[8].a:=0]
218771 my_tree.at_cell.tmp[5].a : 0 [by my_tree.at_cell.arbs[2].ack_cell1._y:=1]
218772 my_tree.at_cell.arbs[0].ack_cell1._y : 1 [by my_tree.at_cell.tmp[5].a:=0]
218773 my_tree.in[0].a : 0 [by my_tree.at_cell.arbs[0].ack_cell1._y:=1]
221729 my_tree.at_cell.tmp[6].a : 0 [by my_tree.at_cell.arbs[2].ack_cell2._y:=1]
222011 my_tree.at_cell.arbs[1].ack_cell1._y : 1 [by my_tree.at_cell.tmp[6].a:=0]
222779 my_tree.in[2].a : 0 [by my_tree.at_cell.arbs[1].ack_cell1._y:=1]
241934 my_tree.at_cell.arbs[1].ack_cell2._y : 1 [by my_tree.at_cell.tmp[6].a:=0]
241937 my_tree.in[3].a : 0 [by my_tree.at_cell.arbs[1].ack_cell2._y:=1]
267485 my_tree.at_cell.arbs[0].ack_cell2._y : 1 [by my_tree.at_cell.tmp[5].a:=0]
289926 my_tree.in[1].a : 0 [by my_tree.at_cell.arbs[0].ack_cell2._y:=1]
-------------------------------------------------
[0] System initialized
289926 Reset : 0
290477 my_tree._reset_B : 1 [by Reset:=0]
-------------------------------------------------
[1] System reset completed
290477 my_tree.in[0].r : 1
290477 my_tree.in[4].r : 1
290477 my_tree.in[2].r : 1
291431 my_tree.at_cell.arbs[3].arbiter._y2 : 0 [by my_tree.in[4].r:=1]
291548 my_tree.at_cell.arbs[0].arbiter._y1 : 0 [by my_tree.in[0].r:=1]
291558 my_tree.at_cell.arbs[1].arbiter._y1 : 0 [by my_tree.in[2].r:=1]
291576 my_tree.at_cell.arbs[1]._y1_arb : 1 [by my_tree.at_cell.arbs[1].arbiter._y1:=0]
292530 my_tree.at_cell.arbs[0]._y1_arb : 1 [by my_tree.at_cell.arbs[0].arbiter._y1:=0]
295589 my_tree.at_cell.arbs[1].or_cell._y : 0 [by my_tree.at_cell.arbs[1]._y1_arb:=1]
296533 my_tree.at_cell.arbs[0].or_cell._y : 0 [by my_tree.at_cell.arbs[0]._y1_arb:=1]
318117 my_tree.at_cell.tmp[5].r : 1 [by my_tree.at_cell.arbs[0].or_cell._y:=0]
322877 my_tree.at_cell.arbs[2].arbiter._y1 : 0 [by my_tree.at_cell.tmp[5].r:=1]
323379 my_tree.at_cell.arbs[2]._y1_arb : 1 [by my_tree.at_cell.arbs[2].arbiter._y1:=0]
323582 my_tree.at_cell.arbs[2].or_cell._y : 0 [by my_tree.at_cell.arbs[2]._y1_arb:=1]
325436 my_tree.at_cell.tmp[8].r : 1 [by my_tree.at_cell.arbs[2].or_cell._y:=0]
340490 my_tree.at_cell.tmp[6].r : 1 [by my_tree.at_cell.arbs[1].or_cell._y:=0]
345901 my_tree.at_cell.arbs[3]._y2_arb : 1 [by my_tree.at_cell.arbs[3].arbiter._y2:=0]
346040 my_tree.at_cell.arbs[3].or_cell._y : 0 [by my_tree.at_cell.arbs[3]._y2_arb:=1]
382386 my_tree.out.r : 1 [by my_tree.at_cell.arbs[3].or_cell._y:=0]
382386 my_tree.out.a : 1
382455 my_tree.at_cell.arbs[3].ack_cell2._y : 0 [by my_tree.out.a:=1]
382466 my_tree.in[4].a : 1 [by my_tree.at_cell.arbs[3].ack_cell2._y:=0]
-------------------------------------------------
[2] Number 4 was chosen, move to the next one
382466 my_tree.in[4].r : 0
434252 my_tree.at_cell.arbs[3].arbiter._y2 : 1 [by my_tree.in[4].r:=0]
434267 my_tree.at_cell.arbs[3]._y2_arb : 0 [by my_tree.at_cell.arbs[3].arbiter._y2:=1]
434268 my_tree.at_cell.arbs[3].or_cell._y : 1 [by my_tree.at_cell.arbs[3]._y2_arb:=0]
434305 my_tree.out.r : 0 [by my_tree.at_cell.arbs[3].or_cell._y:=1]
434456 my_tree.at_cell.arbs[3].arbiter._y1 : 0 [by my_tree.at_cell.arbs[3].arbiter._y2:=1]
434456 my_tree.out.a : 0
435195 my_tree.at_cell.arbs[3].ack_cell2._y : 1 [by my_tree.out.a:=0]
435307 my_tree.in[4].a : 0 [by my_tree.at_cell.arbs[3].ack_cell2._y:=1]
482819 my_tree.at_cell.arbs[3]._y1_arb : 1 [by my_tree.in[4].a:=0]
482859 my_tree.at_cell.arbs[3].or_cell._y : 0 [by my_tree.at_cell.arbs[3]._y1_arb:=1]
483116 my_tree.out.r : 1 [by my_tree.at_cell.arbs[3].or_cell._y:=0]
483116 my_tree.out.a : 1
483203 my_tree.at_cell.arbs[3].ack_cell1._y : 0 [by my_tree.out.a:=1]
483497 my_tree.at_cell.tmp[8].a : 1 [by my_tree.at_cell.arbs[3].ack_cell1._y:=0]
483498 my_tree.at_cell.arbs[2].ack_cell1._y : 0 [by my_tree.at_cell.tmp[8].a:=1]
485304 my_tree.at_cell.tmp[5].a : 1 [by my_tree.at_cell.arbs[2].ack_cell1._y:=0]
487311 my_tree.at_cell.arbs[0].ack_cell1._y : 0 [by my_tree.at_cell.tmp[5].a:=1]
488520 my_tree.in[0].a : 1 [by my_tree.at_cell.arbs[0].ack_cell1._y:=0]
-------------------------------------------------
[2] Number 0 was chosen, finish test

325
test/unit_tests/arbiter_tree_simple_nosim/run/test.prs
View File

@@ -1,325 +0,0 @@
= "GND" "GND"
= "Vdd" "Vdd"
= "Reset" "Reset"
"Reset"->"my_tree._reset_B"-
~("Reset")->"my_tree._reset_B"+
= "my_tree.at_cell.arbs[0].in1.d.d[0]" "my_tree.at_cell.arbs[0].in1.r"
= "my_tree.at_cell.arbs[0].in1.a" "my_tree.at_cell.arbs[0].arbiter.d"
= "my_tree.at_cell.arbs[0].in1.a" "my_tree.at_cell.arbs[0].ack_cell1.y"
= "my_tree.at_cell.arbs[0].in1.d.d[0]" "my_tree.at_cell.arbs[0].arbiter.a"
= "my_tree.at_cell.arbs[0].in1.d.d[0]" "my_tree.at_cell.arbs[0].in1.r"
~"my_tree.at_cell.arbs[0].ack_cell1.c1"&~"my_tree.at_cell.arbs[0].ack_cell1.c2"->"my_tree.at_cell.arbs[0].ack_cell1._y"+
"my_tree.at_cell.arbs[0].ack_cell1.c1"&"my_tree.at_cell.arbs[0].ack_cell1.c2"->"my_tree.at_cell.arbs[0].ack_cell1._y"-
"my_tree.at_cell.arbs[0].ack_cell1._y"->"my_tree.at_cell.arbs[0].ack_cell1.y"-
~("my_tree.at_cell.arbs[0].ack_cell1._y")->"my_tree.at_cell.arbs[0].ack_cell1.y"+
= "my_tree.at_cell.arbs[0].in2.d.d[0]" "my_tree.at_cell.arbs[0].in2.r"
= "my_tree.at_cell.arbs[0].in2.a" "my_tree.at_cell.arbs[0].arbiter.c"
= "my_tree.at_cell.arbs[0].in2.a" "my_tree.at_cell.arbs[0].ack_cell2.y"
= "my_tree.at_cell.arbs[0].in2.d.d[0]" "my_tree.at_cell.arbs[0].arbiter.b"
= "my_tree.at_cell.arbs[0].in2.d.d[0]" "my_tree.at_cell.arbs[0].in2.r"
= "my_tree.at_cell.arbs[0].supply.vdd" "my_tree.at_cell.arbs[0].arbiter.vdd"
= "my_tree.at_cell.arbs[0].supply.vdd" "my_tree.at_cell.arbs[0].or_cell.vdd"
= "my_tree.at_cell.arbs[0].supply.vdd" "my_tree.at_cell.arbs[0].ack_cell2.vdd"
= "my_tree.at_cell.arbs[0].supply.vdd" "my_tree.at_cell.arbs[0].ack_cell1.vdd"
= "my_tree.at_cell.arbs[0].supply.vss" "my_tree.at_cell.arbs[0].arbiter.vss"
= "my_tree.at_cell.arbs[0].supply.vss" "my_tree.at_cell.arbs[0].or_cell.vss"
= "my_tree.at_cell.arbs[0].supply.vss" "my_tree.at_cell.arbs[0].ack_cell2.vss"
= "my_tree.at_cell.arbs[0].supply.vss" "my_tree.at_cell.arbs[0].ack_cell1.vss"
"my_tree.at_cell.arbs[0].arbiter.a"&"my_tree.at_cell.arbs[0].arbiter._y2"->"my_tree.at_cell.arbs[0].arbiter._y1"-
~"my_tree.at_cell.arbs[0].arbiter.a"|~"my_tree.at_cell.arbs[0].arbiter._y2"->"my_tree.at_cell.arbs[0].arbiter._y1"+
"my_tree.at_cell.arbs[0].arbiter.b"&"my_tree.at_cell.arbs[0].arbiter._y1"->"my_tree.at_cell.arbs[0].arbiter._y2"-
~"my_tree.at_cell.arbs[0].arbiter.b"|~"my_tree.at_cell.arbs[0].arbiter._y1"->"my_tree.at_cell.arbs[0].arbiter._y2"+
"my_tree.at_cell.arbs[0].arbiter._y1"|"my_tree.at_cell.arbs[0].arbiter.c"->"my_tree.at_cell.arbs[0].arbiter.y1"-
~("my_tree.at_cell.arbs[0].arbiter._y1"|"my_tree.at_cell.arbs[0].arbiter.c")->"my_tree.at_cell.arbs[0].arbiter.y1"+
"my_tree.at_cell.arbs[0].arbiter._y2"|"my_tree.at_cell.arbs[0].arbiter.d"->"my_tree.at_cell.arbs[0].arbiter.y2"-
~("my_tree.at_cell.arbs[0].arbiter._y2"|"my_tree.at_cell.arbs[0].arbiter.d")->"my_tree.at_cell.arbs[0].arbiter.y2"+
mk_excllo("my_tree.at_cell.arbs[0].arbiter._y1","my_tree.at_cell.arbs[0].arbiter._y2")
= "my_tree.at_cell.arbs[0]._y1_arb" "my_tree.at_cell.arbs[0].arbiter.y1"
= "my_tree.at_cell.arbs[0]._y1_arb" "my_tree.at_cell.arbs[0].or_cell.a"
= "my_tree.at_cell.arbs[0]._y1_arb" "my_tree.at_cell.arbs[0].ack_cell1.c2"
~"my_tree.at_cell.arbs[0].ack_cell2.c1"&~"my_tree.at_cell.arbs[0].ack_cell2.c2"->"my_tree.at_cell.arbs[0].ack_cell2._y"+
"my_tree.at_cell.arbs[0].ack_cell2.c1"&"my_tree.at_cell.arbs[0].ack_cell2.c2"->"my_tree.at_cell.arbs[0].ack_cell2._y"-
"my_tree.at_cell.arbs[0].ack_cell2._y"->"my_tree.at_cell.arbs[0].ack_cell2.y"-
~("my_tree.at_cell.arbs[0].ack_cell2._y")->"my_tree.at_cell.arbs[0].ack_cell2.y"+
"my_tree.at_cell.arbs[0].or_cell.a"|"my_tree.at_cell.arbs[0].or_cell.b"->"my_tree.at_cell.arbs[0].or_cell._y"-
~("my_tree.at_cell.arbs[0].or_cell.a"|"my_tree.at_cell.arbs[0].or_cell.b")->"my_tree.at_cell.arbs[0].or_cell._y"+
"my_tree.at_cell.arbs[0].or_cell._y"->"my_tree.at_cell.arbs[0].or_cell.y"-
~("my_tree.at_cell.arbs[0].or_cell._y")->"my_tree.at_cell.arbs[0].or_cell.y"+
= "my_tree.at_cell.arbs[0].out.d.d[0]" "my_tree.at_cell.arbs[0].out.r"
= "my_tree.at_cell.arbs[0].out.a" "my_tree.at_cell.arbs[0].ack_cell2.c1"
= "my_tree.at_cell.arbs[0].out.a" "my_tree.at_cell.arbs[0].ack_cell1.c1"
= "my_tree.at_cell.arbs[0].out.d.d[0]" "my_tree.at_cell.arbs[0].or_cell.y"
= "my_tree.at_cell.arbs[0].out.d.d[0]" "my_tree.at_cell.arbs[0].out.r"
= "my_tree.at_cell.arbs[0]._y2_arb" "my_tree.at_cell.arbs[0].arbiter.y2"
= "my_tree.at_cell.arbs[0]._y2_arb" "my_tree.at_cell.arbs[0].or_cell.b"
= "my_tree.at_cell.arbs[0]._y2_arb" "my_tree.at_cell.arbs[0].ack_cell2.c2"
= "my_tree.at_cell.arbs[1].in1.d.d[0]" "my_tree.at_cell.arbs[1].in1.r"
= "my_tree.at_cell.arbs[1].in1.a" "my_tree.at_cell.arbs[1].arbiter.d"
= "my_tree.at_cell.arbs[1].in1.a" "my_tree.at_cell.arbs[1].ack_cell1.y"
= "my_tree.at_cell.arbs[1].in1.d.d[0]" "my_tree.at_cell.arbs[1].arbiter.a"
= "my_tree.at_cell.arbs[1].in1.d.d[0]" "my_tree.at_cell.arbs[1].in1.r"
~"my_tree.at_cell.arbs[1].ack_cell1.c1"&~"my_tree.at_cell.arbs[1].ack_cell1.c2"->"my_tree.at_cell.arbs[1].ack_cell1._y"+
"my_tree.at_cell.arbs[1].ack_cell1.c1"&"my_tree.at_cell.arbs[1].ack_cell1.c2"->"my_tree.at_cell.arbs[1].ack_cell1._y"-
"my_tree.at_cell.arbs[1].ack_cell1._y"->"my_tree.at_cell.arbs[1].ack_cell1.y"-
~("my_tree.at_cell.arbs[1].ack_cell1._y")->"my_tree.at_cell.arbs[1].ack_cell1.y"+
= "my_tree.at_cell.arbs[1].in2.d.d[0]" "my_tree.at_cell.arbs[1].in2.r"
= "my_tree.at_cell.arbs[1].in2.a" "my_tree.at_cell.arbs[1].arbiter.c"
= "my_tree.at_cell.arbs[1].in2.a" "my_tree.at_cell.arbs[1].ack_cell2.y"
= "my_tree.at_cell.arbs[1].in2.d.d[0]" "my_tree.at_cell.arbs[1].arbiter.b"
= "my_tree.at_cell.arbs[1].in2.d.d[0]" "my_tree.at_cell.arbs[1].in2.r"
= "my_tree.at_cell.arbs[1].supply.vdd" "my_tree.at_cell.arbs[1].arbiter.vdd"
= "my_tree.at_cell.arbs[1].supply.vdd" "my_tree.at_cell.arbs[1].or_cell.vdd"
= "my_tree.at_cell.arbs[1].supply.vdd" "my_tree.at_cell.arbs[1].ack_cell2.vdd"
= "my_tree.at_cell.arbs[1].supply.vdd" "my_tree.at_cell.arbs[1].ack_cell1.vdd"
= "my_tree.at_cell.arbs[1].supply.vss" "my_tree.at_cell.arbs[1].arbiter.vss"
= "my_tree.at_cell.arbs[1].supply.vss" "my_tree.at_cell.arbs[1].or_cell.vss"
= "my_tree.at_cell.arbs[1].supply.vss" "my_tree.at_cell.arbs[1].ack_cell2.vss"
= "my_tree.at_cell.arbs[1].supply.vss" "my_tree.at_cell.arbs[1].ack_cell1.vss"
"my_tree.at_cell.arbs[1].arbiter.a"&"my_tree.at_cell.arbs[1].arbiter._y2"->"my_tree.at_cell.arbs[1].arbiter._y1"-
~"my_tree.at_cell.arbs[1].arbiter.a"|~"my_tree.at_cell.arbs[1].arbiter._y2"->"my_tree.at_cell.arbs[1].arbiter._y1"+
"my_tree.at_cell.arbs[1].arbiter.b"&"my_tree.at_cell.arbs[1].arbiter._y1"->"my_tree.at_cell.arbs[1].arbiter._y2"-
~"my_tree.at_cell.arbs[1].arbiter.b"|~"my_tree.at_cell.arbs[1].arbiter._y1"->"my_tree.at_cell.arbs[1].arbiter._y2"+
"my_tree.at_cell.arbs[1].arbiter._y1"|"my_tree.at_cell.arbs[1].arbiter.c"->"my_tree.at_cell.arbs[1].arbiter.y1"-
~("my_tree.at_cell.arbs[1].arbiter._y1"|"my_tree.at_cell.arbs[1].arbiter.c")->"my_tree.at_cell.arbs[1].arbiter.y1"+
"my_tree.at_cell.arbs[1].arbiter._y2"|"my_tree.at_cell.arbs[1].arbiter.d"->"my_tree.at_cell.arbs[1].arbiter.y2"-
~("my_tree.at_cell.arbs[1].arbiter._y2"|"my_tree.at_cell.arbs[1].arbiter.d")->"my_tree.at_cell.arbs[1].arbiter.y2"+
mk_excllo("my_tree.at_cell.arbs[1].arbiter._y1","my_tree.at_cell.arbs[1].arbiter._y2")
= "my_tree.at_cell.arbs[1]._y1_arb" "my_tree.at_cell.arbs[1].arbiter.y1"
= "my_tree.at_cell.arbs[1]._y1_arb" "my_tree.at_cell.arbs[1].or_cell.a"
= "my_tree.at_cell.arbs[1]._y1_arb" "my_tree.at_cell.arbs[1].ack_cell1.c2"
~"my_tree.at_cell.arbs[1].ack_cell2.c1"&~"my_tree.at_cell.arbs[1].ack_cell2.c2"->"my_tree.at_cell.arbs[1].ack_cell2._y"+
"my_tree.at_cell.arbs[1].ack_cell2.c1"&"my_tree.at_cell.arbs[1].ack_cell2.c2"->"my_tree.at_cell.arbs[1].ack_cell2._y"-
"my_tree.at_cell.arbs[1].ack_cell2._y"->"my_tree.at_cell.arbs[1].ack_cell2.y"-
~("my_tree.at_cell.arbs[1].ack_cell2._y")->"my_tree.at_cell.arbs[1].ack_cell2.y"+
"my_tree.at_cell.arbs[1].or_cell.a"|"my_tree.at_cell.arbs[1].or_cell.b"->"my_tree.at_cell.arbs[1].or_cell._y"-
~("my_tree.at_cell.arbs[1].or_cell.a"|"my_tree.at_cell.arbs[1].or_cell.b")->"my_tree.at_cell.arbs[1].or_cell._y"+
"my_tree.at_cell.arbs[1].or_cell._y"->"my_tree.at_cell.arbs[1].or_cell.y"-
~("my_tree.at_cell.arbs[1].or_cell._y")->"my_tree.at_cell.arbs[1].or_cell.y"+
= "my_tree.at_cell.arbs[1].out.d.d[0]" "my_tree.at_cell.arbs[1].out.r"
= "my_tree.at_cell.arbs[1].out.a" "my_tree.at_cell.arbs[1].ack_cell2.c1"
= "my_tree.at_cell.arbs[1].out.a" "my_tree.at_cell.arbs[1].ack_cell1.c1"
= "my_tree.at_cell.arbs[1].out.d.d[0]" "my_tree.at_cell.arbs[1].or_cell.y"
= "my_tree.at_cell.arbs[1].out.d.d[0]" "my_tree.at_cell.arbs[1].out.r"
= "my_tree.at_cell.arbs[1]._y2_arb" "my_tree.at_cell.arbs[1].arbiter.y2"
= "my_tree.at_cell.arbs[1]._y2_arb" "my_tree.at_cell.arbs[1].or_cell.b"
= "my_tree.at_cell.arbs[1]._y2_arb" "my_tree.at_cell.arbs[1].ack_cell2.c2"
= "my_tree.at_cell.arbs[2].in1.d.d[0]" "my_tree.at_cell.arbs[2].in1.r"
= "my_tree.at_cell.arbs[2].in1.a" "my_tree.at_cell.arbs[2].arbiter.d"
= "my_tree.at_cell.arbs[2].in1.a" "my_tree.at_cell.arbs[2].ack_cell1.y"
= "my_tree.at_cell.arbs[2].in1.d.d[0]" "my_tree.at_cell.arbs[2].arbiter.a"
= "my_tree.at_cell.arbs[2].in1.d.d[0]" "my_tree.at_cell.arbs[2].in1.r"
~"my_tree.at_cell.arbs[2].ack_cell1.c1"&~"my_tree.at_cell.arbs[2].ack_cell1.c2"->"my_tree.at_cell.arbs[2].ack_cell1._y"+
"my_tree.at_cell.arbs[2].ack_cell1.c1"&"my_tree.at_cell.arbs[2].ack_cell1.c2"->"my_tree.at_cell.arbs[2].ack_cell1._y"-
"my_tree.at_cell.arbs[2].ack_cell1._y"->"my_tree.at_cell.arbs[2].ack_cell1.y"-
~("my_tree.at_cell.arbs[2].ack_cell1._y")->"my_tree.at_cell.arbs[2].ack_cell1.y"+
= "my_tree.at_cell.arbs[2].in2.d.d[0]" "my_tree.at_cell.arbs[2].in2.r"
= "my_tree.at_cell.arbs[2].in2.a" "my_tree.at_cell.arbs[2].arbiter.c"
= "my_tree.at_cell.arbs[2].in2.a" "my_tree.at_cell.arbs[2].ack_cell2.y"
= "my_tree.at_cell.arbs[2].in2.d.d[0]" "my_tree.at_cell.arbs[2].arbiter.b"
= "my_tree.at_cell.arbs[2].in2.d.d[0]" "my_tree.at_cell.arbs[2].in2.r"
= "my_tree.at_cell.arbs[2].supply.vdd" "my_tree.at_cell.arbs[2].arbiter.vdd"
= "my_tree.at_cell.arbs[2].supply.vdd" "my_tree.at_cell.arbs[2].or_cell.vdd"
= "my_tree.at_cell.arbs[2].supply.vdd" "my_tree.at_cell.arbs[2].ack_cell2.vdd"
= "my_tree.at_cell.arbs[2].supply.vdd" "my_tree.at_cell.arbs[2].ack_cell1.vdd"
= "my_tree.at_cell.arbs[2].supply.vss" "my_tree.at_cell.arbs[2].arbiter.vss"
= "my_tree.at_cell.arbs[2].supply.vss" "my_tree.at_cell.arbs[2].or_cell.vss"
= "my_tree.at_cell.arbs[2].supply.vss" "my_tree.at_cell.arbs[2].ack_cell2.vss"
= "my_tree.at_cell.arbs[2].supply.vss" "my_tree.at_cell.arbs[2].ack_cell1.vss"
"my_tree.at_cell.arbs[2].arbiter.a"&"my_tree.at_cell.arbs[2].arbiter._y2"->"my_tree.at_cell.arbs[2].arbiter._y1"-
~"my_tree.at_cell.arbs[2].arbiter.a"|~"my_tree.at_cell.arbs[2].arbiter._y2"->"my_tree.at_cell.arbs[2].arbiter._y1"+
"my_tree.at_cell.arbs[2].arbiter.b"&"my_tree.at_cell.arbs[2].arbiter._y1"->"my_tree.at_cell.arbs[2].arbiter._y2"-
~"my_tree.at_cell.arbs[2].arbiter.b"|~"my_tree.at_cell.arbs[2].arbiter._y1"->"my_tree.at_cell.arbs[2].arbiter._y2"+
"my_tree.at_cell.arbs[2].arbiter._y1"|"my_tree.at_cell.arbs[2].arbiter.c"->"my_tree.at_cell.arbs[2].arbiter.y1"-
~("my_tree.at_cell.arbs[2].arbiter._y1"|"my_tree.at_cell.arbs[2].arbiter.c")->"my_tree.at_cell.arbs[2].arbiter.y1"+
"my_tree.at_cell.arbs[2].arbiter._y2"|"my_tree.at_cell.arbs[2].arbiter.d"->"my_tree.at_cell.arbs[2].arbiter.y2"-
~("my_tree.at_cell.arbs[2].arbiter._y2"|"my_tree.at_cell.arbs[2].arbiter.d")->"my_tree.at_cell.arbs[2].arbiter.y2"+
mk_excllo("my_tree.at_cell.arbs[2].arbiter._y1","my_tree.at_cell.arbs[2].arbiter._y2")
= "my_tree.at_cell.arbs[2]._y1_arb" "my_tree.at_cell.arbs[2].arbiter.y1"
= "my_tree.at_cell.arbs[2]._y1_arb" "my_tree.at_cell.arbs[2].or_cell.a"
= "my_tree.at_cell.arbs[2]._y1_arb" "my_tree.at_cell.arbs[2].ack_cell1.c2"
~"my_tree.at_cell.arbs[2].ack_cell2.c1"&~"my_tree.at_cell.arbs[2].ack_cell2.c2"->"my_tree.at_cell.arbs[2].ack_cell2._y"+
"my_tree.at_cell.arbs[2].ack_cell2.c1"&"my_tree.at_cell.arbs[2].ack_cell2.c2"->"my_tree.at_cell.arbs[2].ack_cell2._y"-
"my_tree.at_cell.arbs[2].ack_cell2._y"->"my_tree.at_cell.arbs[2].ack_cell2.y"-
~("my_tree.at_cell.arbs[2].ack_cell2._y")->"my_tree.at_cell.arbs[2].ack_cell2.y"+
"my_tree.at_cell.arbs[2].or_cell.a"|"my_tree.at_cell.arbs[2].or_cell.b"->"my_tree.at_cell.arbs[2].or_cell._y"-
~("my_tree.at_cell.arbs[2].or_cell.a"|"my_tree.at_cell.arbs[2].or_cell.b")->"my_tree.at_cell.arbs[2].or_cell._y"+
"my_tree.at_cell.arbs[2].or_cell._y"->"my_tree.at_cell.arbs[2].or_cell.y"-
~("my_tree.at_cell.arbs[2].or_cell._y")->"my_tree.at_cell.arbs[2].or_cell.y"+
= "my_tree.at_cell.arbs[2].out.d.d[0]" "my_tree.at_cell.arbs[2].out.r"
= "my_tree.at_cell.arbs[2].out.a" "my_tree.at_cell.arbs[2].ack_cell2.c1"
= "my_tree.at_cell.arbs[2].out.a" "my_tree.at_cell.arbs[2].ack_cell1.c1"
= "my_tree.at_cell.arbs[2].out.d.d[0]" "my_tree.at_cell.arbs[2].or_cell.y"
= "my_tree.at_cell.arbs[2].out.d.d[0]" "my_tree.at_cell.arbs[2].out.r"
= "my_tree.at_cell.arbs[2]._y2_arb" "my_tree.at_cell.arbs[2].arbiter.y2"
= "my_tree.at_cell.arbs[2]._y2_arb" "my_tree.at_cell.arbs[2].or_cell.b"
= "my_tree.at_cell.arbs[2]._y2_arb" "my_tree.at_cell.arbs[2].ack_cell2.c2"
= "my_tree.at_cell.arbs[3].in1.d.d[0]" "my_tree.at_cell.arbs[3].in1.r"
= "my_tree.at_cell.arbs[3].in1.a" "my_tree.at_cell.arbs[3].arbiter.d"
= "my_tree.at_cell.arbs[3].in1.a" "my_tree.at_cell.arbs[3].ack_cell1.y"
= "my_tree.at_cell.arbs[3].in1.d.d[0]" "my_tree.at_cell.arbs[3].arbiter.a"
= "my_tree.at_cell.arbs[3].in1.d.d[0]" "my_tree.at_cell.arbs[3].in1.r"
~"my_tree.at_cell.arbs[3].ack_cell1.c1"&~"my_tree.at_cell.arbs[3].ack_cell1.c2"->"my_tree.at_cell.arbs[3].ack_cell1._y"+
"my_tree.at_cell.arbs[3].ack_cell1.c1"&"my_tree.at_cell.arbs[3].ack_cell1.c2"->"my_tree.at_cell.arbs[3].ack_cell1._y"-
"my_tree.at_cell.arbs[3].ack_cell1._y"->"my_tree.at_cell.arbs[3].ack_cell1.y"-
~("my_tree.at_cell.arbs[3].ack_cell1._y")->"my_tree.at_cell.arbs[3].ack_cell1.y"+
= "my_tree.at_cell.arbs[3].in2.d.d[0]" "my_tree.at_cell.arbs[3].in2.r"
= "my_tree.at_cell.arbs[3].in2.a" "my_tree.at_cell.arbs[3].arbiter.c"
= "my_tree.at_cell.arbs[3].in2.a" "my_tree.at_cell.arbs[3].ack_cell2.y"
= "my_tree.at_cell.arbs[3].in2.d.d[0]" "my_tree.at_cell.arbs[3].arbiter.b"
= "my_tree.at_cell.arbs[3].in2.d.d[0]" "my_tree.at_cell.arbs[3].in2.r"
= "my_tree.at_cell.arbs[3].supply.vdd" "my_tree.at_cell.arbs[3].arbiter.vdd"
= "my_tree.at_cell.arbs[3].supply.vdd" "my_tree.at_cell.arbs[3].or_cell.vdd"
= "my_tree.at_cell.arbs[3].supply.vdd" "my_tree.at_cell.arbs[3].ack_cell2.vdd"
= "my_tree.at_cell.arbs[3].supply.vdd" "my_tree.at_cell.arbs[3].ack_cell1.vdd"
= "my_tree.at_cell.arbs[3].supply.vss" "my_tree.at_cell.arbs[3].arbiter.vss"
= "my_tree.at_cell.arbs[3].supply.vss" "my_tree.at_cell.arbs[3].or_cell.vss"
= "my_tree.at_cell.arbs[3].supply.vss" "my_tree.at_cell.arbs[3].ack_cell2.vss"
= "my_tree.at_cell.arbs[3].supply.vss" "my_tree.at_cell.arbs[3].ack_cell1.vss"
"my_tree.at_cell.arbs[3].arbiter.a"&"my_tree.at_cell.arbs[3].arbiter._y2"->"my_tree.at_cell.arbs[3].arbiter._y1"-
~"my_tree.at_cell.arbs[3].arbiter.a"|~"my_tree.at_cell.arbs[3].arbiter._y2"->"my_tree.at_cell.arbs[3].arbiter._y1"+
"my_tree.at_cell.arbs[3].arbiter.b"&"my_tree.at_cell.arbs[3].arbiter._y1"->"my_tree.at_cell.arbs[3].arbiter._y2"-
~"my_tree.at_cell.arbs[3].arbiter.b"|~"my_tree.at_cell.arbs[3].arbiter._y1"->"my_tree.at_cell.arbs[3].arbiter._y2"+
"my_tree.at_cell.arbs[3].arbiter._y1"|"my_tree.at_cell.arbs[3].arbiter.c"->"my_tree.at_cell.arbs[3].arbiter.y1"-
~("my_tree.at_cell.arbs[3].arbiter._y1"|"my_tree.at_cell.arbs[3].arbiter.c")->"my_tree.at_cell.arbs[3].arbiter.y1"+
"my_tree.at_cell.arbs[3].arbiter._y2"|"my_tree.at_cell.arbs[3].arbiter.d"->"my_tree.at_cell.arbs[3].arbiter.y2"-
~("my_tree.at_cell.arbs[3].arbiter._y2"|"my_tree.at_cell.arbs[3].arbiter.d")->"my_tree.at_cell.arbs[3].arbiter.y2"+
mk_excllo("my_tree.at_cell.arbs[3].arbiter._y1","my_tree.at_cell.arbs[3].arbiter._y2")
= "my_tree.at_cell.arbs[3]._y1_arb" "my_tree.at_cell.arbs[3].arbiter.y1"
= "my_tree.at_cell.arbs[3]._y1_arb" "my_tree.at_cell.arbs[3].or_cell.a"
= "my_tree.at_cell.arbs[3]._y1_arb" "my_tree.at_cell.arbs[3].ack_cell1.c2"
~"my_tree.at_cell.arbs[3].ack_cell2.c1"&~"my_tree.at_cell.arbs[3].ack_cell2.c2"->"my_tree.at_cell.arbs[3].ack_cell2._y"+
"my_tree.at_cell.arbs[3].ack_cell2.c1"&"my_tree.at_cell.arbs[3].ack_cell2.c2"->"my_tree.at_cell.arbs[3].ack_cell2._y"-
"my_tree.at_cell.arbs[3].ack_cell2._y"->"my_tree.at_cell.arbs[3].ack_cell2.y"-
~("my_tree.at_cell.arbs[3].ack_cell2._y")->"my_tree.at_cell.arbs[3].ack_cell2.y"+
"my_tree.at_cell.arbs[3].or_cell.a"|"my_tree.at_cell.arbs[3].or_cell.b"->"my_tree.at_cell.arbs[3].or_cell._y"-
~("my_tree.at_cell.arbs[3].or_cell.a"|"my_tree.at_cell.arbs[3].or_cell.b")->"my_tree.at_cell.arbs[3].or_cell._y"+
"my_tree.at_cell.arbs[3].or_cell._y"->"my_tree.at_cell.arbs[3].or_cell.y"-
~("my_tree.at_cell.arbs[3].or_cell._y")->"my_tree.at_cell.arbs[3].or_cell.y"+
= "my_tree.at_cell.arbs[3].out.d.d[0]" "my_tree.at_cell.arbs[3].out.r"
= "my_tree.at_cell.arbs[3].out.a" "my_tree.at_cell.arbs[3].ack_cell2.c1"
= "my_tree.at_cell.arbs[3].out.a" "my_tree.at_cell.arbs[3].ack_cell1.c1"
= "my_tree.at_cell.arbs[3].out.d.d[0]" "my_tree.at_cell.arbs[3].or_cell.y"
= "my_tree.at_cell.arbs[3].out.d.d[0]" "my_tree.at_cell.arbs[3].out.r"
= "my_tree.at_cell.arbs[3]._y2_arb" "my_tree.at_cell.arbs[3].arbiter.y2"
= "my_tree.at_cell.arbs[3]._y2_arb" "my_tree.at_cell.arbs[3].or_cell.b"
= "my_tree.at_cell.arbs[3]._y2_arb" "my_tree.at_cell.arbs[3].ack_cell2.c2"
= "my_tree.at_cell.tmp[5].d.d[0]" "my_tree.at_cell.tmp[5].r"
= "my_tree.at_cell.tmp[6].d.d[0]" "my_tree.at_cell.tmp[6].r"
= "my_tree.at_cell.tmp[8].d.d[0]" "my_tree.at_cell.tmp[8].r"
= "my_tree.at_cell.tmp[5].r" "my_tree.at_cell.arbs[2].in1.r"
= "my_tree.at_cell.tmp[5].a" "my_tree.at_cell.arbs[2].in1.a"
= "my_tree.at_cell.tmp[5].d.d[0]" "my_tree.at_cell.arbs[2].in1.d.d[0]"
= "my_tree.at_cell.tmp[5].r" "my_tree.at_cell.arbs[0].out.r"
= "my_tree.at_cell.tmp[5].a" "my_tree.at_cell.arbs[0].out.a"
= "my_tree.at_cell.tmp[5].d.d[0]" "my_tree.at_cell.arbs[0].out.d.d[0]"
= "my_tree.at_cell.tmp[6].r" "my_tree.at_cell.arbs[2].in2.r"
= "my_tree.at_cell.tmp[6].a" "my_tree.at_cell.arbs[2].in2.a"
= "my_tree.at_cell.tmp[6].d.d[0]" "my_tree.at_cell.arbs[2].in2.d.d[0]"
= "my_tree.at_cell.tmp[6].r" "my_tree.at_cell.arbs[1].out.r"
= "my_tree.at_cell.tmp[6].a" "my_tree.at_cell.arbs[1].out.a"
= "my_tree.at_cell.tmp[6].d.d[0]" "my_tree.at_cell.arbs[1].out.d.d[0]"
= "my_tree.at_cell.tmp[8].r" "my_tree.at_cell.arbs[3].in1.r"
= "my_tree.at_cell.tmp[8].a" "my_tree.at_cell.arbs[3].in1.a"
= "my_tree.at_cell.tmp[8].d.d[0]" "my_tree.at_cell.arbs[3].in1.d.d[0]"
= "my_tree.at_cell.tmp[8].r" "my_tree.at_cell.arbs[2].out.r"
= "my_tree.at_cell.tmp[8].a" "my_tree.at_cell.arbs[2].out.a"
= "my_tree.at_cell.tmp[8].d.d[0]" "my_tree.at_cell.arbs[2].out.d.d[0]"
= "my_tree.at_cell.tmp[8].d.d[0]" "my_tree.at_cell.tmp[8].r"
= "my_tree.at_cell.tmp[6].d.d[0]" "my_tree.at_cell.tmp[6].r"
= "my_tree.at_cell.tmp[5].d.d[0]" "my_tree.at_cell.tmp[5].r"
= "my_tree.at_cell.supply.vss" "my_tree.at_cell.arbs[3].supply.vss"
= "my_tree.at_cell.supply.vdd" "my_tree.at_cell.arbs[3].supply.vdd"
= "my_tree.at_cell.supply.vss" "my_tree.at_cell.arbs[2].supply.vss"
= "my_tree.at_cell.supply.vdd" "my_tree.at_cell.arbs[2].supply.vdd"
= "my_tree.at_cell.supply.vss" "my_tree.at_cell.arbs[1].supply.vss"
= "my_tree.at_cell.supply.vdd" "my_tree.at_cell.arbs[1].supply.vdd"
= "my_tree.at_cell.supply.vss" "my_tree.at_cell.arbs[0].supply.vss"
= "my_tree.at_cell.supply.vdd" "my_tree.at_cell.arbs[0].supply.vdd"
= "my_tree.at_cell.in[0].d.d[0]" "my_tree.at_cell.in[0].r"
= "my_tree.at_cell.in[1].d.d[0]" "my_tree.at_cell.in[1].r"
= "my_tree.at_cell.in[2].d.d[0]" "my_tree.at_cell.in[2].r"
= "my_tree.at_cell.in[3].d.d[0]" "my_tree.at_cell.in[3].r"
= "my_tree.at_cell.in[4].d.d[0]" "my_tree.at_cell.in[4].r"
= "my_tree.at_cell.in[0].r" "my_tree.at_cell.arbs[0].in1.r"
= "my_tree.at_cell.in[0].a" "my_tree.at_cell.arbs[0].in1.a"
= "my_tree.at_cell.in[0].d.d[0]" "my_tree.at_cell.arbs[0].in1.d.d[0]"
= "my_tree.at_cell.in[0].r" "my_tree.at_cell.tmp[0].r"
= "my_tree.at_cell.in[0].a" "my_tree.at_cell.tmp[0].a"
= "my_tree.at_cell.in[0].d.d[0]" "my_tree.at_cell.tmp[0].d.d[0]"
= "my_tree.at_cell.in[1].r" "my_tree.at_cell.arbs[0].in2.r"
= "my_tree.at_cell.in[1].a" "my_tree.at_cell.arbs[0].in2.a"
= "my_tree.at_cell.in[1].d.d[0]" "my_tree.at_cell.arbs[0].in2.d.d[0]"
= "my_tree.at_cell.in[1].r" "my_tree.at_cell.tmp[1].r"
= "my_tree.at_cell.in[1].a" "my_tree.at_cell.tmp[1].a"
= "my_tree.at_cell.in[1].d.d[0]" "my_tree.at_cell.tmp[1].d.d[0]"
= "my_tree.at_cell.in[2].r" "my_tree.at_cell.arbs[1].in1.r"
= "my_tree.at_cell.in[2].a" "my_tree.at_cell.arbs[1].in1.a"
= "my_tree.at_cell.in[2].d.d[0]" "my_tree.at_cell.arbs[1].in1.d.d[0]"
= "my_tree.at_cell.in[2].r" "my_tree.at_cell.tmp[2].r"
= "my_tree.at_cell.in[2].a" "my_tree.at_cell.tmp[2].a"
= "my_tree.at_cell.in[2].d.d[0]" "my_tree.at_cell.tmp[2].d.d[0]"
= "my_tree.at_cell.in[3].r" "my_tree.at_cell.arbs[1].in2.r"
= "my_tree.at_cell.in[3].a" "my_tree.at_cell.arbs[1].in2.a"
= "my_tree.at_cell.in[3].d.d[0]" "my_tree.at_cell.arbs[1].in2.d.d[0]"
= "my_tree.at_cell.in[3].r" "my_tree.at_cell.tmp[3].r"
= "my_tree.at_cell.in[3].a" "my_tree.at_cell.tmp[3].a"
= "my_tree.at_cell.in[3].d.d[0]" "my_tree.at_cell.tmp[3].d.d[0]"
= "my_tree.at_cell.in[4].r" "my_tree.at_cell.arbs[3].in2.r"
= "my_tree.at_cell.in[4].a" "my_tree.at_cell.arbs[3].in2.a"
= "my_tree.at_cell.in[4].d.d[0]" "my_tree.at_cell.arbs[3].in2.d.d[0]"
= "my_tree.at_cell.in[4].r" "my_tree.at_cell.tmp[9].r"
= "my_tree.at_cell.in[4].a" "my_tree.at_cell.tmp[9].a"
= "my_tree.at_cell.in[4].d.d[0]" "my_tree.at_cell.tmp[9].d.d[0]"
= "my_tree.at_cell.in[4].r" "my_tree.at_cell.tmp[7].r"
= "my_tree.at_cell.in[4].a" "my_tree.at_cell.tmp[7].a"
= "my_tree.at_cell.in[4].d.d[0]" "my_tree.at_cell.tmp[7].d.d[0]"
= "my_tree.at_cell.in[4].r" "my_tree.at_cell.tmp[4].r"
= "my_tree.at_cell.in[4].a" "my_tree.at_cell.tmp[4].a"
= "my_tree.at_cell.in[4].d.d[0]" "my_tree.at_cell.tmp[4].d.d[0]"
= "my_tree.at_cell.in[4].d.d[0]" "my_tree.at_cell.in[4].r"
= "my_tree.at_cell.in[3].d.d[0]" "my_tree.at_cell.in[3].r"
= "my_tree.at_cell.in[2].d.d[0]" "my_tree.at_cell.in[2].r"
= "my_tree.at_cell.in[1].d.d[0]" "my_tree.at_cell.in[1].r"
= "my_tree.at_cell.in[0].d.d[0]" "my_tree.at_cell.in[0].r"
= "my_tree.at_cell.out.d.d[0]" "my_tree.at_cell.out.r"
= "my_tree.at_cell.out.r" "my_tree.at_cell.arbs[3].out.r"
= "my_tree.at_cell.out.a" "my_tree.at_cell.arbs[3].out.a"
= "my_tree.at_cell.out.d.d[0]" "my_tree.at_cell.arbs[3].out.d.d[0]"
= "my_tree.at_cell.out.r" "my_tree.at_cell.tmp[10].r"
= "my_tree.at_cell.out.a" "my_tree.at_cell.tmp[10].a"
= "my_tree.at_cell.out.d.d[0]" "my_tree.at_cell.tmp[10].d.d[0]"
= "my_tree.at_cell.out.d.d[0]" "my_tree.at_cell.out.r"
= "my_tree._supply.vss" "my_tree.at_cell.supply.vss"
= "my_tree._supply.vdd" "my_tree.at_cell.supply.vdd"
= "Vdd" "my_tree._supply.vdd"
= "GND" "my_tree._supply.vss"
= "my_tree.out.d.d[0]" "my_tree.out.r"
= "my_tree.out.r" "my_tree.at_cell.out.r"
= "my_tree.out.a" "my_tree.at_cell.out.a"
= "my_tree.out.d.d[0]" "my_tree.at_cell.out.d.d[0]"
= "my_tree.out.d.d[0]" "my_tree.out.r"
= "my_tree.in[0].d.d[0]" "my_tree.in[0].r"
= "my_tree.in[1].d.d[0]" "my_tree.in[1].r"
= "my_tree.in[2].d.d[0]" "my_tree.in[2].r"
= "my_tree.in[3].d.d[0]" "my_tree.in[3].r"
= "my_tree.in[4].d.d[0]" "my_tree.in[4].r"
= "my_tree.in[0].r" "my_tree.at_cell.in[0].r"
= "my_tree.in[1].r" "my_tree.at_cell.in[1].r"
= "my_tree.in[2].r" "my_tree.at_cell.in[2].r"
= "my_tree.in[3].r" "my_tree.at_cell.in[3].r"
= "my_tree.in[4].r" "my_tree.at_cell.in[4].r"
= "my_tree.in[0].a" "my_tree.at_cell.in[0].a"
= "my_tree.in[1].a" "my_tree.at_cell.in[1].a"
= "my_tree.in[2].a" "my_tree.at_cell.in[2].a"
= "my_tree.in[3].a" "my_tree.at_cell.in[3].a"
= "my_tree.in[4].a" "my_tree.at_cell.in[4].a"
= "my_tree.in[0].d.d[0]" "my_tree.at_cell.in[0].d.d[0]"
= "my_tree.in[1].d.d[0]" "my_tree.at_cell.in[1].d.d[0]"
= "my_tree.in[2].d.d[0]" "my_tree.at_cell.in[2].d.d[0]"
= "my_tree.in[3].d.d[0]" "my_tree.at_cell.in[3].d.d[0]"
= "my_tree.in[4].d.d[0]" "my_tree.at_cell.in[4].d.d[0]"
= "my_tree.in[4].d.d[0]" "my_tree.in[4].r"
= "my_tree.in[3].d.d[0]" "my_tree.in[3].r"
= "my_tree.in[2].d.d[0]" "my_tree.in[2].r"
= "my_tree.in[1].d.d[0]" "my_tree.in[1].r"
= "my_tree.in[0].d.d[0]" "my_tree.in[0].r"

55
test/unit_tests/arbiter_tree_simple_nosim/test.act
View File

@@ -1,55 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/primitives.act";
import "../../dataflow_neuro/coders.act";
import globals;
open tmpl::dataflow_neuro;
defproc arbiter_treee (a1of1 in[5]; a1of1 out)
{
//Low active Reset
bool _reset_B;
prs {
Reset => _reset_B-
}
power _supply;
_supply.vdd = Vdd;
_supply.vss = GND;
arbtree<5> at_cell(.in=in, .out = out);
at_cell.supply = _supply;
}
arbiter_treee my_tree;

52
test/unit_tests/arbiter_tree_simple_nosim/test.prsim
View File

@@ -1,52 +0,0 @@
watchall
set my_tree.in[0].r 0
set my_tree.in[1].r 0
set my_tree.in[2].r 0
set my_tree.in[3].r 0
set my_tree.in[4].r 0
set my_tree.out.a 0
cycle
assert my_tree.in[0].a 0
assert my_tree.in[1].a 0
assert my_tree.in[2].a 0
assert my_tree.in[3].a 0
assert my_tree.in[4].a 0
assert my_tree.out.r 0
system "echo '-------------------------------------------------'"
system "echo '[0] System initialized'"
set Reset 0
cycle
system "echo '-------------------------------------------------'"
system "echo '[1] System reset completed'"
set my_tree.in[0].r 1
set my_tree.in[2].r 1
set my_tree.in[4].r 1
cycle
assert my_tree.out.r 1
set my_tree.out.a 1
cycle
assert my_tree.in[4].a 1
set my_tree.in[4].r 0
system "echo '-------------------------------------------------'"
system "echo '[2] Number 4 was chosen, move to the next one'"
cycle
assert my_tree.out.r 0
set my_tree.out.a 0
cycle
assert my_tree.in[4].a 0
assert my_tree.out.r 1
set my_tree.out.a 1
cycle
assert my_tree.in[0].a 1
system "echo '-------------------------------------------------'"
system "echo '[2] Number 0 was chosen, finish test'"

232
test/unit_tests/arbiter_tree_test/run/prsim.out
View File

@@ -1,232 +0,0 @@
my_tree.in[1].r my_tree.at_cell.tmp[8].a my_tree.in[3].r my_tree.at_cell.tmp[5].a my_tree.at_cell.arbs[3].ack_cell1._y my_tree.fifo_to_tree[2].fifo_element[1]._out_a_B my_tree._in[1].a my_tree.fifo_to_tree[3].fifo_element[1]._out_a_B my_tree._in[3].a my_tree.fifo_to_tree[0].fifo_element[1]._out_a_B my_tree._in[2].a my_tree.at_cell.arbs[2].ack_cell2._y my_tree.at_cell.arbs[1].ack_cell2._y my_tree._in[4].a my_tree.out.a my_tree._in[0].a my_tree.at_cell.arbs[1].ack_cell1._y my_tree.at_cell.tmp[6].a my_tree.in[2].r my_tree.in[4].r my_tree.at_cell.arbs[2].ack_cell1._y my_tree.in[0].r my_tree.fifo_to_tree[1].fifo_element[1]._out_a_B my_tree.fifo_to_tree[4].fifo_element[1]._out_a_B my_tree.at_cell.arbs[0].ack_cell1._y my_tree.at_cell.arbs[3].ack_cell2._y my_tree.at_cell.arbs[0].ack_cell2._y
217204 my_tree.in[0].r : 0
217204 my_tree.out.a : 0
217204 my_tree.in[4].r : 0
217204 my_tree.in[2].r : 0
217204 my_tree.in[1].r : 0
217204 my_tree.in[3].r : 0
217205 my_tree.at_cell.arbs[3].ack_cell2._y : 1 [by my_tree.out.a:=0]
217216 my_tree._in[4].a : 0 [by my_tree.at_cell.arbs[3].ack_cell2._y:=1]
217586 my_tree.fifo_to_tree[4].fifo_element[1]._out_a_B : 1 [by my_tree._in[4].a:=0]
217752 my_tree.at_cell.arbs[3].ack_cell1._y : 1 [by my_tree.out.a:=0]
217819 my_tree.at_cell.tmp[8].a : 0 [by my_tree.at_cell.arbs[3].ack_cell1._y:=1]
217835 my_tree.at_cell.arbs[2].ack_cell1._y : 1 [by my_tree.at_cell.tmp[8].a:=0]
220460 my_tree.at_cell.arbs[2].ack_cell2._y : 1 [by my_tree.at_cell.tmp[8].a:=0]
220988 my_tree.at_cell.tmp[6].a : 0 [by my_tree.at_cell.arbs[2].ack_cell2._y:=1]
222397 my_tree.at_cell.tmp[5].a : 0 [by my_tree.at_cell.arbs[2].ack_cell1._y:=1]
223423 my_tree.at_cell.arbs[1].ack_cell2._y : 1 [by my_tree.at_cell.tmp[6].a:=0]
223425 my_tree._in[3].a : 0 [by my_tree.at_cell.arbs[1].ack_cell2._y:=1]
235438 my_tree.at_cell.arbs[0].ack_cell1._y : 1 [by my_tree.at_cell.tmp[5].a:=0]
235441 my_tree._in[0].a : 0 [by my_tree.at_cell.arbs[0].ack_cell1._y:=1]
235470 my_tree.fifo_to_tree[0].fifo_element[1]._out_a_B : 1 [by my_tree._in[0].a:=0]
246322 my_tree.at_cell.arbs[0].ack_cell2._y : 1 [by my_tree.at_cell.tmp[5].a:=0]
246639 my_tree._in[1].a : 0 [by my_tree.at_cell.arbs[0].ack_cell2._y:=1]
247868 my_tree.at_cell.arbs[1].ack_cell1._y : 1 [by my_tree.at_cell.tmp[6].a:=0]
248021 my_tree._in[2].a : 0 [by my_tree.at_cell.arbs[1].ack_cell1._y:=1]
248065 my_tree.fifo_to_tree[2].fifo_element[1]._out_a_B : 1 [by my_tree._in[2].a:=0]
248240 my_tree.fifo_to_tree[1].fifo_element[1]._out_a_B : 1 [by my_tree._in[1].a:=0]
284383 my_tree.fifo_to_tree[3].fifo_element[1]._out_a_B : 1 [by my_tree._in[3].a:=0]
-------------------------------------------------
[0] System initialized
284383 Reset : 0
287144 my_tree._reset_B : 1 [by Reset:=0]
287145 my_tree.fifo_to_tree[3].reset_buf._y : 0 [by my_tree._reset_B:=1]
287145 my_tree.fifo_to_tree[0].reset_buf._y : 0 [by my_tree._reset_B:=1]
287166 my_tree.fifo_to_tree[1].reset_buf._y : 0 [by my_tree._reset_B:=1]
287325 my_tree.fifo_to_tree[1]._reset_BX : 1 [by my_tree.fifo_to_tree[1].reset_buf._y:=0]
287361 my_tree.fifo_to_tree[2].reset_buf._y : 0 [by my_tree._reset_B:=1]
288648 my_tree.fifo_to_tree[2]._reset_BX : 1 [by my_tree.fifo_to_tree[2].reset_buf._y:=0]
288726 my_tree.fifo_to_tree[3]._reset_BX : 1 [by my_tree.fifo_to_tree[3].reset_buf._y:=0]
288871 my_tree.fifo_to_tree[3].reset_bufarray.buf1._y : 0 [by my_tree.fifo_to_tree[3]._reset_BX:=1]
290880 my_tree.fifo_to_tree[2].reset_bufarray.buf1._y : 0 [by my_tree.fifo_to_tree[2]._reset_BX:=1]
291703 my_tree.fifo_to_tree[3]._reset_BXX[0] : 1 [by my_tree.fifo_to_tree[3].reset_bufarray.buf1._y:=0]
291704 my_tree.fifo_to_tree[3].fifo_element[0].reset_buf._y : 0 [by my_tree.fifo_to_tree[3]._reset_BXX[0]:=1]
291866 my_tree.fifo_to_tree[3].fifo_element[0]._reset_BX : 1 [by my_tree.fifo_to_tree[3].fifo_element[0].reset_buf._y:=0]
296490 my_tree.fifo_to_tree[0]._reset_BX : 1 [by my_tree.fifo_to_tree[0].reset_buf._y:=0]
297234 my_tree.fifo_to_tree[2]._reset_BXX[0] : 1 [by my_tree.fifo_to_tree[2].reset_bufarray.buf1._y:=0]
297241 my_tree.fifo_to_tree[2].fifo_element[1].reset_buf._y : 0 [by my_tree.fifo_to_tree[2]._reset_BXX[0]:=1]
297248 my_tree.fifo_to_tree[2].fifo_element[0].reset_buf._y : 0 [by my_tree.fifo_to_tree[2]._reset_BXX[0]:=1]
297401 my_tree.fifo_to_tree[2].fifo_element[1]._reset_BX : 1 [by my_tree.fifo_to_tree[2].fifo_element[1].reset_buf._y:=0]
300827 my_tree.fifo_to_tree[4].reset_buf._y : 0 [by my_tree._reset_B:=1]
300828 my_tree.fifo_to_tree[4]._reset_BX : 1 [by my_tree.fifo_to_tree[4].reset_buf._y:=0]
300829 my_tree.fifo_to_tree[4].reset_bufarray.buf1._y : 0 [by my_tree.fifo_to_tree[4]._reset_BX:=1]
300830 my_tree.fifo_to_tree[4]._reset_BXX[0] : 1 [by my_tree.fifo_to_tree[4].reset_bufarray.buf1._y:=0]
301017 my_tree.fifo_to_tree[4].fifo_element[1].reset_buf._y : 0 [by my_tree.fifo_to_tree[4]._reset_BXX[0]:=1]
301018 my_tree.fifo_to_tree[4].fifo_element[1]._reset_BX : 1 [by my_tree.fifo_to_tree[4].fifo_element[1].reset_buf._y:=0]
303073 my_tree.fifo_to_tree[4].fifo_element[0].reset_buf._y : 0 [by my_tree.fifo_to_tree[4]._reset_BXX[0]:=1]
303859 my_tree.fifo_to_tree[0].reset_bufarray.buf1._y : 0 [by my_tree.fifo_to_tree[0]._reset_BX:=1]
307001 my_tree.fifo_to_tree[1].reset_bufarray.buf1._y : 0 [by my_tree.fifo_to_tree[1]._reset_BX:=1]
307002 my_tree.fifo_to_tree[1]._reset_BXX[0] : 1 [by my_tree.fifo_to_tree[1].reset_bufarray.buf1._y:=0]
307007 my_tree.fifo_to_tree[1].fifo_element[1].reset_buf._y : 0 [by my_tree.fifo_to_tree[1]._reset_BXX[0]:=1]
307255 my_tree.fifo_to_tree[4].fifo_element[0]._reset_BX : 1 [by my_tree.fifo_to_tree[4].fifo_element[0].reset_buf._y:=0]
307855 my_tree.fifo_to_tree[1].fifo_element[0].reset_buf._y : 0 [by my_tree.fifo_to_tree[1]._reset_BXX[0]:=1]
307856 my_tree.fifo_to_tree[1].fifo_element[0]._reset_BX : 1 [by my_tree.fifo_to_tree[1].fifo_element[0].reset_buf._y:=0]
307898 my_tree.fifo_to_tree[1].fifo_element[1]._reset_BX : 1 [by my_tree.fifo_to_tree[1].fifo_element[1].reset_buf._y:=0]
318805 my_tree.fifo_to_tree[2].fifo_element[0]._reset_BX : 1 [by my_tree.fifo_to_tree[2].fifo_element[0].reset_buf._y:=0]
330987 my_tree.fifo_to_tree[3].fifo_element[1].reset_buf._y : 0 [by my_tree.fifo_to_tree[3]._reset_BXX[0]:=1]
331004 my_tree.fifo_to_tree[3].fifo_element[1]._reset_BX : 1 [by my_tree.fifo_to_tree[3].fifo_element[1].reset_buf._y:=0]
338641 my_tree.fifo_to_tree[0]._reset_BXX[0] : 1 [by my_tree.fifo_to_tree[0].reset_bufarray.buf1._y:=0]
341214 my_tree.fifo_to_tree[0].fifo_element[0].reset_buf._y : 0 [by my_tree.fifo_to_tree[0]._reset_BXX[0]:=1]
341217 my_tree.fifo_to_tree[0].fifo_element[0]._reset_BX : 1 [by my_tree.fifo_to_tree[0].fifo_element[0].reset_buf._y:=0]
347002 my_tree.fifo_to_tree[0].fifo_element[1].reset_buf._y : 0 [by my_tree.fifo_to_tree[0]._reset_BXX[0]:=1]
347943 my_tree.fifo_to_tree[0].fifo_element[1]._reset_BX : 1 [by my_tree.fifo_to_tree[0].fifo_element[1].reset_buf._y:=0]
-------------------------------------------------
[1] System reset completed
347943 my_tree.in[0].r : 1
347943 my_tree.in[4].r : 1
347943 my_tree.in[2].r : 1
347944 my_tree.fifo_to_tree[4].fifo_element[0].buf_func._y : 0 [by my_tree.in[4].r:=1]
347985 my_tree.fifo_to_tree[2].fifo_element[0].buf_func._y : 0 [by my_tree.in[2].r:=1]
350761 my_tree.fifo_to_tree[4].fifo_element[1].in.r : 1 [by my_tree.fifo_to_tree[4].fifo_element[0].buf_func._y:=0]
350856 my_tree.fifo_to_tree[4].fifo_element[1].buf_func._y : 0 [by my_tree.fifo_to_tree[4].fifo_element[1].in.r:=1]
350864 my_tree._in[4].r : 1 [by my_tree.fifo_to_tree[4].fifo_element[1].buf_func._y:=0]
350898 my_tree.at_cell.arbs[3].arbiter._y2 : 0 [by my_tree._in[4].r:=1]
351096 my_tree.fifo_to_tree[4].fifo_element[0].inack_ctl._y : 0 [by my_tree.fifo_to_tree[4].fifo_element[1].in.r:=1]
351100 my_tree.in[4].a : 1 [by my_tree.fifo_to_tree[4].fifo_element[0].inack_ctl._y:=0]
351816 my_tree.at_cell.arbs[3]._y2_arb : 1 [by my_tree.at_cell.arbs[3].arbiter._y2:=0]
354214 my_tree.at_cell.arbs[3].or_cell._y : 0 [by my_tree.at_cell.arbs[3]._y2_arb:=1]
357429 my_tree.out.r : 1 [by my_tree.at_cell.arbs[3].or_cell._y:=0]
361718 my_tree.fifo_to_tree[2].fifo_element[1].in.r : 1 [by my_tree.fifo_to_tree[2].fifo_element[0].buf_func._y:=0]
361766 my_tree.fifo_to_tree[2].fifo_element[0].inack_ctl._y : 0 [by my_tree.fifo_to_tree[2].fifo_element[1].in.r:=1]
361769 my_tree.in[2].a : 1 [by my_tree.fifo_to_tree[2].fifo_element[0].inack_ctl._y:=0]
361947 my_tree.fifo_to_tree[2].fifo_element[0]._en : 0 [by my_tree.in[2].a:=1]
364751 my_tree.fifo_to_tree[4].fifo_element[1].inack_ctl._y : 0 [by my_tree._in[4].r:=1]
385728 my_tree.fifo_to_tree[4].fifo_element[1].in.a : 1 [by my_tree.fifo_to_tree[4].fifo_element[1].inack_ctl._y:=0]
391679 my_tree.fifo_to_tree[4].fifo_element[0]._out_a_B : 0 [by my_tree.fifo_to_tree[4].fifo_element[1].in.a:=1]
397478 my_tree.fifo_to_tree[4].fifo_element[0]._en : 0 [by my_tree.in[4].a:=1]
397627 my_tree.fifo_to_tree[4].fifo_element[1]._en : 0 [by my_tree.fifo_to_tree[4].fifo_element[1].in.a:=1]
406905 my_tree.fifo_to_tree[0].fifo_element[0].buf_func._y : 0 [by my_tree.in[0].r:=1]
407732 my_tree.fifo_to_tree[0].fifo_element[1].in.r : 1 [by my_tree.fifo_to_tree[0].fifo_element[0].buf_func._y:=0]
407905 my_tree.fifo_to_tree[0].fifo_element[1].buf_func._y : 0 [by my_tree.fifo_to_tree[0].fifo_element[1].in.r:=1]
407906 my_tree._in[0].r : 1 [by my_tree.fifo_to_tree[0].fifo_element[1].buf_func._y:=0]
407910 my_tree.fifo_to_tree[0].fifo_element[1].inack_ctl._y : 0 [by my_tree._in[0].r:=1]
407916 my_tree.fifo_to_tree[0].fifo_element[0].inack_ctl._y : 0 [by my_tree.fifo_to_tree[0].fifo_element[1].in.r:=1]
407979 my_tree.at_cell.arbs[0].arbiter._y1 : 0 [by my_tree._in[0].r:=1]
408012 my_tree.in[0].a : 1 [by my_tree.fifo_to_tree[0].fifo_element[0].inack_ctl._y:=0]
408013 my_tree.fifo_to_tree[0].fifo_element[0]._en : 0 [by my_tree.in[0].a:=1]
408115 my_tree.at_cell.arbs[0]._y1_arb : 1 [by my_tree.at_cell.arbs[0].arbiter._y1:=0]
408837 my_tree.fifo_to_tree[2].fifo_element[1].buf_func._y : 0 [by my_tree.fifo_to_tree[2].fifo_element[1].in.r:=1]
409078 my_tree._in[2].r : 1 [by my_tree.fifo_to_tree[2].fifo_element[1].buf_func._y:=0]
409090 my_tree.fifo_to_tree[2].fifo_element[1].inack_ctl._y : 0 [by my_tree._in[2].r:=1]
412990 my_tree.fifo_to_tree[2].fifo_element[1].in.a : 1 [by my_tree.fifo_to_tree[2].fifo_element[1].inack_ctl._y:=0]
412991 my_tree.fifo_to_tree[2].fifo_element[0]._out_a_B : 0 [by my_tree.fifo_to_tree[2].fifo_element[1].in.a:=1]
413037 my_tree.at_cell.arbs[1].arbiter._y1 : 0 [by my_tree._in[2].r:=1]
413047 my_tree.fifo_to_tree[2].fifo_element[0].buf_func._y : 1 [by my_tree.fifo_to_tree[2].fifo_element[0]._out_a_B:=0]
413048 my_tree.fifo_to_tree[2].fifo_element[1].in.r : 0 [by my_tree.fifo_to_tree[2].fifo_element[0].buf_func._y:=1]
414019 my_tree.fifo_to_tree[2].fifo_element[1]._en : 0 [by my_tree.fifo_to_tree[2].fifo_element[1].in.a:=1]
414056 my_tree.fifo_to_tree[2].fifo_element[1].inack_ctl._y : 1 [by my_tree.fifo_to_tree[2].fifo_element[1]._en:=0]
427161 my_tree.at_cell.arbs[0].or_cell._y : 0 [by my_tree.at_cell.arbs[0]._y1_arb:=1]
427162 my_tree.at_cell.tmp[5].r : 1 [by my_tree.at_cell.arbs[0].or_cell._y:=0]
430726 my_tree.at_cell.arbs[2].arbiter._y1 : 0 [by my_tree.at_cell.tmp[5].r:=1]
432418 my_tree.at_cell.arbs[2]._y1_arb : 1 [by my_tree.at_cell.arbs[2].arbiter._y1:=0]
432431 my_tree.at_cell.arbs[2].or_cell._y : 0 [by my_tree.at_cell.arbs[2]._y1_arb:=1]
436963 my_tree.fifo_to_tree[4].fifo_element[0].buf_func._y : 1 [by my_tree.fifo_to_tree[4].fifo_element[0]._en:=0]
437320 my_tree.fifo_to_tree[4].fifo_element[1].in.r : 0 [by my_tree.fifo_to_tree[4].fifo_element[0].buf_func._y:=1]
437345 my_tree.fifo_to_tree[4].fifo_element[1].inack_ctl._y : 1 [by my_tree.fifo_to_tree[4].fifo_element[1].in.r:=0]
437366 my_tree.fifo_to_tree[4].fifo_element[1].in.a : 0 [by my_tree.fifo_to_tree[4].fifo_element[1].inack_ctl._y:=1]
437367 my_tree.fifo_to_tree[4].fifo_element[0]._out_a_B : 1 [by my_tree.fifo_to_tree[4].fifo_element[1].in.a:=0]
437431 my_tree.fifo_to_tree[2].fifo_element[1].in.a : 0 [by my_tree.fifo_to_tree[2].fifo_element[1].inack_ctl._y:=1]
445198 my_tree.fifo_to_tree[0].fifo_element[1].in.a : 1 [by my_tree.fifo_to_tree[0].fifo_element[1].inack_ctl._y:=0]
445199 my_tree.fifo_to_tree[0].fifo_element[1]._en : 0 [by my_tree.fifo_to_tree[0].fifo_element[1].in.a:=1]
445199 my_tree.fifo_to_tree[0].fifo_element[0]._out_a_B : 0 [by my_tree.fifo_to_tree[0].fifo_element[1].in.a:=1]
445360 my_tree.fifo_to_tree[0].fifo_element[0].buf_func._y : 1 [by my_tree.fifo_to_tree[0].fifo_element[0]._out_a_B:=0]
446397 my_tree.fifo_to_tree[0].fifo_element[1].in.r : 0 [by my_tree.fifo_to_tree[0].fifo_element[0].buf_func._y:=1]
446402 my_tree.fifo_to_tree[0].fifo_element[1].inack_ctl._y : 1 [by my_tree.fifo_to_tree[0].fifo_element[1].in.r:=0]
446983 my_tree.fifo_to_tree[0].fifo_element[1].in.a : 0 [by my_tree.fifo_to_tree[0].fifo_element[1].inack_ctl._y:=1]
447079 my_tree.fifo_to_tree[2].fifo_element[0]._out_a_B : 1 [by my_tree.fifo_to_tree[2].fifo_element[1].in.a:=0]
447391 my_tree.fifo_to_tree[0].fifo_element[0]._out_a_B : 1 [by my_tree.fifo_to_tree[0].fifo_element[1].in.a:=0]
449415 my_tree.at_cell.tmp[8].r : 1 [by my_tree.at_cell.arbs[2].or_cell._y:=0]
458043 my_tree.at_cell.arbs[1]._y1_arb : 1 [by my_tree.at_cell.arbs[1].arbiter._y1:=0]
458054 my_tree.at_cell.arbs[1].or_cell._y : 0 [by my_tree.at_cell.arbs[1]._y1_arb:=1]
459101 my_tree.at_cell.tmp[6].r : 1 [by my_tree.at_cell.arbs[1].or_cell._y:=0]
459101 my_tree.out.a : 1
459115 my_tree.at_cell.arbs[3].ack_cell2._y : 0 [by my_tree.out.a:=1]
459133 my_tree._in[4].a : 1 [by my_tree.at_cell.arbs[3].ack_cell2._y:=0]
459137 my_tree.fifo_to_tree[4].fifo_element[1]._out_a_B : 0 [by my_tree._in[4].a:=1]
459241 my_tree.fifo_to_tree[4].fifo_element[1].buf_func._y : 1 [by my_tree.fifo_to_tree[4].fifo_element[1]._out_a_B:=0]
490685 my_tree._in[4].r : 0 [by my_tree.fifo_to_tree[4].fifo_element[1].buf_func._y:=1]
491889 my_tree.at_cell.arbs[3].arbiter._y2 : 1 [by my_tree._in[4].r:=0]
492117 my_tree.at_cell.arbs[3].arbiter._y1 : 0 [by my_tree.at_cell.arbs[3].arbiter._y2:=1]
492732 my_tree.at_cell.arbs[3]._y2_arb : 0 [by my_tree.at_cell.arbs[3].arbiter._y2:=1]
494191 my_tree.at_cell.arbs[3].or_cell._y : 1 [by my_tree.at_cell.arbs[3]._y2_arb:=0]
494261 my_tree.out.r : 0 [by my_tree.at_cell.arbs[3].or_cell._y:=1]
499140 my_tree.fifo_to_tree[4].fifo_element[1]._en : 1 [by my_tree._in[4].r:=0]
499140 my_tree.out.a : 0
549562 my_tree.at_cell.arbs[3].ack_cell2._y : 1 [by my_tree.out.a:=0]
549573 my_tree._in[4].a : 0 [by my_tree.at_cell.arbs[3].ack_cell2._y:=1]
549576 my_tree.at_cell.arbs[3]._y1_arb : 1 [by my_tree._in[4].a:=0]
549627 my_tree.fifo_to_tree[4].fifo_element[1]._out_a_B : 1 [by my_tree._in[4].a:=0]
550724 my_tree.at_cell.arbs[3].or_cell._y : 0 [by my_tree.at_cell.arbs[3]._y1_arb:=1]
551885 my_tree.out.r : 1 [by my_tree.at_cell.arbs[3].or_cell._y:=0]
551885 my_tree.out.a : 1
560537 my_tree.at_cell.arbs[3].ack_cell1._y : 0 [by my_tree.out.a:=1]
560618 my_tree.at_cell.tmp[8].a : 1 [by my_tree.at_cell.arbs[3].ack_cell1._y:=0]
571695 my_tree.at_cell.arbs[2].ack_cell1._y : 0 [by my_tree.at_cell.tmp[8].a:=1]
589678 my_tree.at_cell.tmp[5].a : 1 [by my_tree.at_cell.arbs[2].ack_cell1._y:=0]
589770 my_tree.at_cell.arbs[0].ack_cell1._y : 0 [by my_tree.at_cell.tmp[5].a:=1]
598081 my_tree._in[0].a : 1 [by my_tree.at_cell.arbs[0].ack_cell1._y:=0]
599825 my_tree.fifo_to_tree[0].fifo_element[1]._out_a_B : 0 [by my_tree._in[0].a:=1]
600438 my_tree.fifo_to_tree[0].fifo_element[1].buf_func._y : 1 [by my_tree.fifo_to_tree[0].fifo_element[1]._out_a_B:=0]
614460 my_tree._in[0].r : 0 [by my_tree.fifo_to_tree[0].fifo_element[1].buf_func._y:=1]
614505 my_tree.at_cell.arbs[0].arbiter._y1 : 1 [by my_tree._in[0].r:=0]
615457 my_tree.fifo_to_tree[0].fifo_element[1]._en : 1 [by my_tree._in[0].r:=0]
616154 my_tree.at_cell.arbs[0]._y1_arb : 0 [by my_tree.at_cell.arbs[0].arbiter._y1:=1]
616679 my_tree.at_cell.arbs[0].or_cell._y : 1 [by my_tree.at_cell.arbs[0]._y1_arb:=0]
617579 my_tree.at_cell.tmp[5].r : 0 [by my_tree.at_cell.arbs[0].or_cell._y:=1]
617631 my_tree.at_cell.arbs[2].arbiter._y1 : 1 [by my_tree.at_cell.tmp[5].r:=0]
617638 my_tree.at_cell.arbs[2].arbiter._y2 : 0 [by my_tree.at_cell.arbs[2].arbiter._y1:=1]
633243 my_tree.at_cell.arbs[2]._y1_arb : 0 [by my_tree.at_cell.arbs[2].arbiter._y1:=1]
639710 my_tree.at_cell.arbs[2].or_cell._y : 1 [by my_tree.at_cell.arbs[2]._y1_arb:=0]
639712 my_tree.at_cell.tmp[8].r : 0 [by my_tree.at_cell.arbs[2].or_cell._y:=1]
640066 my_tree.at_cell.arbs[3].arbiter._y1 : 1 [by my_tree.at_cell.tmp[8].r:=0]
640199 my_tree.at_cell.arbs[3]._y1_arb : 0 [by my_tree.at_cell.arbs[3].arbiter._y1:=1]
640200 my_tree.at_cell.arbs[3].or_cell._y : 1 [by my_tree.at_cell.arbs[3]._y1_arb:=0]
640204 my_tree.out.r : 0 [by my_tree.at_cell.arbs[3].or_cell._y:=1]
640204 my_tree.out.a : 0
640750 my_tree.at_cell.arbs[3].ack_cell1._y : 1 [by my_tree.out.a:=0]
686313 my_tree.at_cell.tmp[8].a : 0 [by my_tree.at_cell.arbs[3].ack_cell1._y:=1]
686314 my_tree.at_cell.arbs[2].ack_cell1._y : 1 [by my_tree.at_cell.tmp[8].a:=0]
698692 my_tree.at_cell.tmp[5].a : 0 [by my_tree.at_cell.arbs[2].ack_cell1._y:=1]
698771 my_tree.at_cell.arbs[2]._y2_arb : 1 [by my_tree.at_cell.tmp[5].a:=0]
698859 my_tree.at_cell.arbs[2].or_cell._y : 0 [by my_tree.at_cell.arbs[2]._y2_arb:=1]
701125 my_tree.at_cell.arbs[0].ack_cell1._y : 1 [by my_tree.at_cell.tmp[5].a:=0]
706641 my_tree.at_cell.tmp[8].r : 1 [by my_tree.at_cell.arbs[2].or_cell._y:=0]
706700 my_tree.at_cell.arbs[3].arbiter._y1 : 0 [by my_tree.at_cell.tmp[8].r:=1]
706730 my_tree.at_cell.arbs[3]._y1_arb : 1 [by my_tree.at_cell.arbs[3].arbiter._y1:=0]
708197 my_tree.at_cell.arbs[3].or_cell._y : 0 [by my_tree.at_cell.arbs[3]._y1_arb:=1]
729452 my_tree._in[0].a : 0 [by my_tree.at_cell.arbs[0].ack_cell1._y:=1]
748836 my_tree.fifo_to_tree[0].fifo_element[1]._out_a_B : 1 [by my_tree._in[0].a:=0]
767701 my_tree.out.r : 1 [by my_tree.at_cell.arbs[3].or_cell._y:=0]
767701 my_tree.out.a : 1
768386 my_tree.at_cell.arbs[3].ack_cell1._y : 0 [by my_tree.out.a:=1]
785101 my_tree.at_cell.tmp[8].a : 1 [by my_tree.at_cell.arbs[3].ack_cell1._y:=0]
785228 my_tree.at_cell.arbs[2].ack_cell2._y : 0 [by my_tree.at_cell.tmp[8].a:=1]
785397 my_tree.at_cell.tmp[6].a : 1 [by my_tree.at_cell.arbs[2].ack_cell2._y:=0]
785440 my_tree.at_cell.arbs[1].ack_cell1._y : 0 [by my_tree.at_cell.tmp[6].a:=1]
785452 my_tree._in[2].a : 1 [by my_tree.at_cell.arbs[1].ack_cell1._y:=0]
786731 my_tree.fifo_to_tree[2].fifo_element[1]._out_a_B : 0 [by my_tree._in[2].a:=1]
786964 my_tree.fifo_to_tree[2].fifo_element[1].buf_func._y : 1 [by my_tree.fifo_to_tree[2].fifo_element[1]._out_a_B:=0]
786967 my_tree._in[2].r : 0 [by my_tree.fifo_to_tree[2].fifo_element[1].buf_func._y:=1]
786968 my_tree.fifo_to_tree[2].fifo_element[1]._en : 1 [by my_tree._in[2].r:=0]
787005 my_tree.at_cell.arbs[1].arbiter._y1 : 1 [by my_tree._in[2].r:=0]
799757 my_tree.at_cell.arbs[1]._y1_arb : 0 [by my_tree.at_cell.arbs[1].arbiter._y1:=1]
799849 my_tree.at_cell.arbs[1].or_cell._y : 1 [by my_tree.at_cell.arbs[1]._y1_arb:=0]
802576 my_tree.at_cell.tmp[6].r : 0 [by my_tree.at_cell.arbs[1].or_cell._y:=1]
802578 my_tree.at_cell.arbs[2].arbiter._y2 : 1 [by my_tree.at_cell.tmp[6].r:=0]
802579 my_tree.at_cell.arbs[2]._y2_arb : 0 [by my_tree.at_cell.arbs[2].arbiter._y2:=1]
804080 my_tree.at_cell.arbs[2].or_cell._y : 1 [by my_tree.at_cell.arbs[2]._y2_arb:=0]
804082 my_tree.at_cell.tmp[8].r : 0 [by my_tree.at_cell.arbs[2].or_cell._y:=1]
804100 my_tree.at_cell.arbs[3].arbiter._y1 : 1 [by my_tree.at_cell.tmp[8].r:=0]
804219 my_tree.at_cell.arbs[3]._y1_arb : 0 [by my_tree.at_cell.arbs[3].arbiter._y1:=1]
809939 my_tree.at_cell.arbs[3].or_cell._y : 1 [by my_tree.at_cell.arbs[3]._y1_arb:=0]
809947 my_tree.out.r : 0 [by my_tree.at_cell.arbs[3].or_cell._y:=1]
809947 my_tree.out.a : 0
810001 my_tree.at_cell.arbs[3].ack_cell1._y : 1 [by my_tree.out.a:=0]
860539 my_tree.at_cell.tmp[8].a : 0 [by my_tree.at_cell.arbs[3].ack_cell1._y:=1]
860544 my_tree.at_cell.arbs[2].ack_cell2._y : 1 [by my_tree.at_cell.tmp[8].a:=0]
861611 my_tree.at_cell.tmp[6].a : 0 [by my_tree.at_cell.arbs[2].ack_cell2._y:=1]
861612 my_tree.at_cell.arbs[1].ack_cell1._y : 1 [by my_tree.at_cell.tmp[6].a:=0]
861750 my_tree._in[2].a : 0 [by my_tree.at_cell.arbs[1].ack_cell1._y:=1]
861751 my_tree.fifo_to_tree[2].fifo_element[1]._out_a_B : 1 [by my_tree._in[2].a:=0]
-------------------------------------------------
[3] Sent three inputs, received 3 outputs

1085
test/unit_tests/arbiter_tree_test/run/test.prs
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64
test/unit_tests/arbiter_tree_test/test.act
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@@ -1,64 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/primitives.act";
import "../../dataflow_neuro/coders.act";
import globals;
open tmpl::dataflow_neuro;
defproc arbiter_treee (a1of1 in[5]; a1of1 out)
{
//Low active Reset
bool _reset_B;
prs {
Reset => _reset_B-
}
a1of1 _in[5];
power _supply;
_supply.vdd = Vdd;
_supply.vss = GND;
fifo_t<2> fifo_to_tree[5];
(i:5:
fifo_to_tree[i].in = in[i];
fifo_to_tree[i].out = _in[i];
fifo_to_tree[i].supply = _supply;
fifo_to_tree[i].reset_B = _reset_B;
)
arbtree<5> at_cell(.in=_in, .out = out);
at_cell.supply = _supply;
}
arbiter_treee my_tree;

63
test/unit_tests/arbiter_tree_test/test.prsim
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@@ -1,63 +0,0 @@
watchall
set my_tree.in[0].r 0
set my_tree.in[1].r 0
set my_tree.in[2].r 0
set my_tree.in[3].r 0
set my_tree.in[4].r 0
set my_tree.out.a 0
cycle
assert my_tree.in[0].a 0
assert my_tree.in[1].a 0
assert my_tree.in[2].a 0
assert my_tree.in[3].a 0
assert my_tree.in[4].a 0
assert my_tree.out.r 0
system "echo '-------------------------------------------------'"
system "echo '[0] System initialized'"
set Reset 0
cycle
system "echo '-------------------------------------------------'"
system "echo '[1] System reset completed'"
set my_tree.in[0].r 1
set my_tree.in[2].r 1
set my_tree.in[4].r 1
cycle
assert my_tree.out.r 1
set my_tree.out.a 1
cycle
assert my_tree.out.r 0
set my_tree.out.a 0
cycle
assert my_tree.out.r 1
set my_tree.out.a 1
cycle
assert my_tree.out.r 0
set my_tree.out.a 0
cycle
assert my_tree.out.r 1
set my_tree.out.a 1
cycle
assert my_tree.out.r 0
set my_tree.out.a 0
cycle
system "echo '-------------------------------------------------'"
system "echo '[3] Sent three inputs, received 3 outputs'"

BIN
test/unit_tests/arbtree_5/.DS_Store vendored
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85
test/unit_tests/arbtree_5/run/prsim.out
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t.in[0] t.out t.in[2] t.in[3] t.at.tmp[6] t.at.tmp[5] t.at.tmp[8] t.in[4] t.at.arbs[1]._y t.in[1] t.at.arbs[2]._y t.at.arbs[3]._y t.at.arbs[0]._y
0
1
0 t.in[0] : 0
0 t.in[4] : 0
0 t.in[3] : 0
0 t.in[2] : 0
0 t.in[1] : 0
1 t.at.arbs[1]._y : 1 [by t.in[2]:=0]
7092 t.at.arbs[0]._y : 1 [by t.in[1]:=0]
7094 t.at.tmp[5] : 0 [by t.at.arbs[0]._y:=1]
10468 t.at.tmp[6] : 0 [by t.at.arbs[1]._y:=1]
15221 t.at.arbs[2]._y : 1 [by t.at.tmp[6]:=0]
16358 t.at.tmp[8] : 0 [by t.at.arbs[2]._y:=1]
16472 t.at.arbs[3]._y : 1 [by t.at.tmp[8]:=0]
81838 t.out : 0 [by t.at.arbs[3]._y:=1]
[] setting all low
[] setting bit 0 high
81838 t.in[0] : 1
83564 t.at.arbs[0]._y : 0 [by t.in[0]:=1]
83603 t.at.tmp[5] : 1 [by t.at.arbs[0]._y:=0]
83618 t.at.arbs[2]._y : 0 [by t.at.tmp[5]:=1]
84109 t.at.tmp[8] : 1 [by t.at.arbs[2]._y:=0]
84122 t.at.arbs[3]._y : 0 [by t.at.tmp[8]:=1]
84162 t.out : 1 [by t.at.arbs[3]._y:=0]
[] setting all low
84162 t.in[0] : 0
84577 t.at.arbs[0]._y : 1 [by t.in[0]:=0]
84597 t.at.tmp[5] : 0 [by t.at.arbs[0]._y:=1]
90658 t.at.arbs[2]._y : 1 [by t.at.tmp[5]:=0]
90705 t.at.tmp[8] : 0 [by t.at.arbs[2]._y:=1]
90721 t.at.arbs[3]._y : 1 [by t.at.tmp[8]:=0]
134819 t.out : 0 [by t.at.arbs[3]._y:=1]
[] setting bit 1 high
134819 t.in[1] : 1
148543 t.at.arbs[0]._y : 0 [by t.in[1]:=1]
148547 t.at.tmp[5] : 1 [by t.at.arbs[0]._y:=0]
157676 t.at.arbs[2]._y : 0 [by t.at.tmp[5]:=1]
157691 t.at.tmp[8] : 1 [by t.at.arbs[2]._y:=0]
200939 t.at.arbs[3]._y : 0 [by t.at.tmp[8]:=1]
237870 t.out : 1 [by t.at.arbs[3]._y:=0]
[] setting all low
237870 t.in[1] : 0
237925 t.at.arbs[0]._y : 1 [by t.in[1]:=0]
289578 t.at.tmp[5] : 0 [by t.at.arbs[0]._y:=1]
319358 t.at.arbs[2]._y : 1 [by t.at.tmp[5]:=0]
333207 t.at.tmp[8] : 0 [by t.at.arbs[2]._y:=1]
358019 t.at.arbs[3]._y : 1 [by t.at.tmp[8]:=0]
372362 t.out : 0 [by t.at.arbs[3]._y:=1]
[] setting bit 2 high
372362 t.in[2] : 1
372784 t.at.arbs[1]._y : 0 [by t.in[2]:=1]
421498 t.at.tmp[6] : 1 [by t.at.arbs[1]._y:=0]
421499 t.at.arbs[2]._y : 0 [by t.at.tmp[6]:=1]
421500 t.at.tmp[8] : 1 [by t.at.arbs[2]._y:=0]
441705 t.at.arbs[3]._y : 0 [by t.at.tmp[8]:=1]
441987 t.out : 1 [by t.at.arbs[3]._y:=0]
[] setting all low
441987 t.in[2] : 0
442755 t.at.arbs[1]._y : 1 [by t.in[2]:=0]
442758 t.at.tmp[6] : 0 [by t.at.arbs[1]._y:=1]
465199 t.at.arbs[2]._y : 1 [by t.at.tmp[6]:=0]
465750 t.at.tmp[8] : 0 [by t.at.arbs[2]._y:=1]
466821 t.at.arbs[3]._y : 1 [by t.at.tmp[8]:=0]
467775 t.out : 0 [by t.at.arbs[3]._y:=1]
[] setting bit 3 high
467775 t.in[3] : 1
468856 t.at.arbs[1]._y : 0 [by t.in[3]:=1]
523326 t.at.tmp[6] : 1 [by t.at.arbs[1]._y:=0]
524308 t.at.arbs[2]._y : 0 [by t.at.tmp[6]:=1]
524326 t.at.tmp[8] : 1 [by t.at.arbs[2]._y:=0]
528339 t.at.arbs[3]._y : 0 [by t.at.tmp[8]:=1]
532342 t.out : 1 [by t.at.arbs[3]._y:=0]
[] setting all low
532342 t.in[3] : 0
577243 t.at.arbs[1]._y : 1 [by t.in[3]:=0]
598827 t.at.tmp[6] : 0 [by t.at.arbs[1]._y:=1]
603587 t.at.arbs[2]._y : 1 [by t.at.tmp[6]:=0]
604089 t.at.tmp[8] : 0 [by t.at.arbs[2]._y:=1]
604292 t.at.arbs[3]._y : 1 [by t.at.tmp[8]:=0]
606146 t.out : 0 [by t.at.arbs[3]._y:=1]
[] setting bit 4 high
606146 t.in[4] : 1
606285 t.at.arbs[3]._y : 0 [by t.in[4]:=1]
642631 t.out : 1 [by t.at.arbs[3]._y:=0]

BIN
test/unit_tests/arbtree_5/run/prsim.pdf
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55
test/unit_tests/arbtree_5/run/test.prs
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@@ -1,55 +0,0 @@
= "GND" "GND"
= "Vdd" "Vdd"
= "Reset" "Reset"
"t.at.arbs[0].a"|"t.at.arbs[0].b"->"t.at.arbs[0]._y"-
~("t.at.arbs[0].a"|"t.at.arbs[0].b")->"t.at.arbs[0]._y"+
"t.at.arbs[0]._y"->"t.at.arbs[0].y"-
~("t.at.arbs[0]._y")->"t.at.arbs[0].y"+
"t.at.arbs[1].a"|"t.at.arbs[1].b"->"t.at.arbs[1]._y"-
~("t.at.arbs[1].a"|"t.at.arbs[1].b")->"t.at.arbs[1]._y"+
"t.at.arbs[1]._y"->"t.at.arbs[1].y"-
~("t.at.arbs[1]._y")->"t.at.arbs[1].y"+
"t.at.arbs[2].a"|"t.at.arbs[2].b"->"t.at.arbs[2]._y"-
~("t.at.arbs[2].a"|"t.at.arbs[2].b")->"t.at.arbs[2]._y"+
"t.at.arbs[2]._y"->"t.at.arbs[2].y"-
~("t.at.arbs[2]._y")->"t.at.arbs[2].y"+
"t.at.arbs[3].a"|"t.at.arbs[3].b"->"t.at.arbs[3]._y"-
~("t.at.arbs[3].a"|"t.at.arbs[3].b")->"t.at.arbs[3]._y"+
"t.at.arbs[3]._y"->"t.at.arbs[3].y"-
~("t.at.arbs[3]._y")->"t.at.arbs[3].y"+
= "t.at.tmp[5]" "t.at.arbs[2].a"
= "t.at.tmp[5]" "t.at.arbs[0].y"
= "t.at.tmp[6]" "t.at.arbs[2].b"
= "t.at.tmp[6]" "t.at.arbs[1].y"
= "t.at.tmp[8]" "t.at.arbs[3].a"
= "t.at.tmp[8]" "t.at.arbs[2].y"
= "t.at.supply.vdd" "t.at.arbs[3].vdd"
= "t.at.supply.vdd" "t.at.arbs[2].vdd"
= "t.at.supply.vdd" "t.at.arbs[1].vdd"
= "t.at.supply.vdd" "t.at.arbs[0].vdd"
= "t.at.supply.vss" "t.at.arbs[3].vss"
= "t.at.supply.vss" "t.at.arbs[2].vss"
= "t.at.supply.vss" "t.at.arbs[1].vss"
= "t.at.supply.vss" "t.at.arbs[0].vss"
= "t.at.in[0]" "t.at.arbs[0].a"
= "t.at.in[0]" "t.at.tmp[0]"
= "t.at.in[1]" "t.at.arbs[0].b"
= "t.at.in[1]" "t.at.tmp[1]"
= "t.at.in[2]" "t.at.arbs[1].a"
= "t.at.in[2]" "t.at.tmp[2]"
= "t.at.in[3]" "t.at.arbs[1].b"
= "t.at.in[3]" "t.at.tmp[3]"
= "t.at.in[4]" "t.at.arbs[3].b"
= "t.at.in[4]" "t.at.tmp[9]"
= "t.at.in[4]" "t.at.tmp[7]"
= "t.at.in[4]" "t.at.tmp[4]"
= "t.at.out" "t.at.arbs[3].y"
= "t.at.out" "t.at.tmp[10]"
= "Vdd" "t.at.supply.vdd"
= "GND" "t.at.supply.vss"
= "t.out" "t.at.out"
= "t.in[0]" "t.at.in[0]"
= "t.in[1]" "t.at.in[1]"
= "t.in[2]" "t.at.in[2]"
= "t.in[3]" "t.at.in[3]"
= "t.in[4]" "t.at.in[4]"

41
test/unit_tests/arbtree_5/test.act
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@@ -1,41 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/treegates.act";
import globals;
open tmpl::dataflow_neuro;
defproc arbtree_5 (bool? in[5]; bool! out){
arbtree<5> at(.in=in, .out=out);
at.supply.vss = GND;
at.supply.vdd = Vdd;
}
arbtree_5 t;

88
test/unit_tests/arbtree_5/test.prsim
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@@ -1,88 +0,0 @@
watchall
system "echo '0'"
set t.in[0] 0
set t.in[1] 0
set t.in[2] 0
set t.in[3] 0
set t.in[4] 0
system "echo '1'"
cycle
mode run
# assert t.out 0
system "echo '[] setting all low'"
set t.in[0] 0
set t.in[1] 0
set t.in[2] 0
set t.in[3] 0
set t.in[4] 0
cycle
system "echo '[] setting bit 0 high'"
set t.in[0] 1
cycle
system "echo '[] setting all low'"
set t.in[0] 0
set t.in[1] 0
set t.in[2] 0
set t.in[3] 0
set t.in[4] 0
cycle
system "echo '[] setting bit 1 high'"
set t.in[0] 0
set t.in[1] 1
cycle
system "echo '[] setting all low'"
set t.in[0] 0
set t.in[1] 0
set t.in[2] 0
set t.in[3] 0
set t.in[4] 0
cycle
system "echo '[] setting bit 2 high'"
set t.in[1] 0
set t.in[2] 1
cycle
system "echo '[] setting all low'"
set t.in[0] 0
set t.in[1] 0
set t.in[2] 0
set t.in[3] 0
set t.in[4] 0
cycle
system "echo '[] setting bit 3 high'"
set t.in[2] 0
set t.in[3] 1
cycle
system "echo '[] setting all low'"
set t.in[0] 0
set t.in[1] 0
set t.in[2] 0
set t.in[3] 0
set t.in[4] 0
cycle
system "echo '[] setting bit 4 high'"
set t.in[3] 0
set t.in[4] 1
cycle

615
test/unit_tests/bd2qdi_5/run/prsim.out
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@@ -1,615 +0,0 @@
b.b._out_a_BX_f[0] b.b.dly.dly[5].__y b.b.dly.mu2[0]._s b.b._inB[1] b.b.dly.dly[9].__y b.in.r b.b._inB[4] b.b.dly.dly[6].y b.in.d[1] b.b.dly.dly[3].a b.in.d[4] b.b.dly.dly[11].__y b.b._reqX b.b._en_X_f[0] b.b.dly.dly[13].y b.b.dly.dly[4]._y b.dly_cfg[3] b.in.d[2] b.b.dly.dly[11].y b.b.dly.dly[0].a b.b._en_X_t[0] b.b.dly.mu2[3].b b.dly_cfg[2] b.b._out_a_BX_t[0] b.b._reqXX[0] b.out.v b.b.dly.dly[7].___y b.b._out_a_B b.b._inB[2] b.b._inB[0] b.b.dly._a[1] b.dly_cfg[1] b.b.dly.dly[8].__y b.b.dly.dly[4].___y b.in.d[0] b.b.dly.dly[8]._y b.b.dly.dly[0].__y b.dly_cfg[0] b.b.dly.dly[7].a b.b.req_buf._y b.b.dly.dly[8].y b.b.en_buf_f.buf2._y b.b.dly.dly[10].y b.b.dly.dly[3].___y b.b.dly.mu2[1]._y b.b.dly.dly[5].y b.b.dly._a[2] b.b.dly.dly[6]._y b.b.dly.mu2[3]._s b.b.dly.dly[7].y b.b.en_buf_t.buf2._y b.b._en b.b.dly._a[3] b.b.dly.dly[1].___y b.out.a b.in.d[3] b.b.dly.dly[2]._y b.b.dly.dly[7].__y b.b._req b.b.dly.dly[12].___y b.b.dly.dly[12].y b.b.dly.dly[8].___y b.b.dly.dly[1].a b.b.dly.dly[9].___y b.b.dly.dly[3].y b.b.dly.dly[2].y b.b.dly.dly[14].___y b.b._inB[3] b.b.dly.mu2[0]._y b.b.dly.dly[6].___y b.b.dly.and2[0]._y b.b.dly.dly[3]._y b.b.dly.dly[10].__y b.b.out_a_B_buf_t.buf2._y b.b.dly.mu2[3]._y b.b.req_bufarray.buf2._y b.b.dly.dly[5]._y b.b.dly.mu2[1]._s b.b.dly.dly[4].y b.b.dly.dly[1]._y b.b.dly.and2[3]._y b.b.dly.dly[13].___y b.b.dly.dly[0]._y b.b.dly.dly[11]._y b.b.dly.dly[14].__y b.b.dly.dly[1].__y b.b.dly.mu2[2]._y b.b.dly.and2[1]._y b.b.out_a_B_buf_f.buf2._y b.b.dly.dly[9].y b.b.dly.dly[0].___y b.b.dly.dly[7]._y b.b.dly.dly[13]._y b.b.dly.dly[4].__y b.b.dly.and2[2]._y b.b.dly.dly[12].__y b.b.dly.dly[11].___y b.b.dly.dly[1].y b.b.dly.dly[12]._y b.b.dly.dly[2].__y b.b.dly.dly[14]._y b.b.dly.dly[5].___y b.b.dly.dly[2].___y b.b.dly.dly[0].y b.b.dly.dly[3].__y b.b.dly.mu2[2]._s b.b.dly.dly[13].__y b.b.dly.dly[10].___y b.b.dly.dly[9]._y b.b.dly.dly[6].__y b.b.dly.dly[10]._y
87848 b.out.a : 0
87848 Reset : 0
87848 b.in.r : 0
87848 b.dly_cfg[3] : 1
87848 b.dly_cfg[2] : 1
87848 b.in.d[4] : 0
87848 b.out.v : 0
87848 b.dly_cfg[1] : 1
87848 b.in.d[3] : 1
87848 b.in.d[2] : 0
87848 b.dly_cfg[0] : 1
87848 b.in.d[1] : 0
87848 b.in.d[0] : 1
87849 b.b.dly.mu2[1]._s : 0 [by b.dly_cfg[1]:=1]
87849 b.b._inB[3] : 0 [by b.in.d[3]:=1]
87851 b.b._inB[0] : 0 [by b.in.d[0]:=1]
88130 b.b.dly.mu2[0]._s : 0 [by b.dly_cfg[0]:=1]
88270 b.b._inB[4] : 1 [by b.in.d[4]:=0]
88616 b.b._inB[1] : 1 [by b.in.d[1]:=0]
101697 b.b.dly.and2[0]._y : 1 [by b.in.r:=0]
102191 b.b.dly.mu2[2]._s : 0 [by b.dly_cfg[2]:=1]
108053 b.b._inB[2] : 1 [by b.in.d[2]:=0]
112660 b.b.dly.mu2[3]._s : 0 [by b.dly_cfg[3]:=1]
117628 b._reset_B : 1 [by Reset:=0]
118179 b.b.reset_buf._y : 0 [by b._reset_B:=1]
119250 b.b._reset_BX : 1 [by b.b.reset_buf._y:=0]
120204 b.b.reset_bufarray.buf2._y : 0 [by b.b._reset_BX:=1]
121285 b.b._reset_BXX[0] : 1 [by b.b.reset_bufarray.buf2._y:=0]
121303 b.b.f_buf_func[4]._y : X [by b.b._reset_BXX[0]:=1]
122267 b.b.f_buf_func[2]._y : X [by b.b._reset_BXX[0]:=1]
124138 b.b.dly.dly[0].a : 0 [by b.b.dly.and2[0]._y:=1]
125288 b.b.t_buf_func[3]._y : X [by b.b._reset_BXX[0]:=1]
125298 b.b.t_buf_func[0]._y : X [by b.b._reset_BXX[0]:=1]
125501 b.b.t_buf_func[0].y : X [by b.b.t_buf_func[0]._y:=X]
125790 b.b.t_buf_func[3].y : X [by b.b.t_buf_func[3]._y:=X]
128898 b.b.dly.dly[0]._y : 1 [by b.b.dly.dly[0].a:=0]
130752 b.b.dly.dly[0].__y : 0 [by b.b.dly.dly[0]._y:=1]
130891 b.b.dly.dly[0].___y : 1 [by b.b.dly.dly[0].__y:=0]
136562 b.b._en : 1 [by b.out.v:=0]
136573 b.b.en_buf_t.buf2._y : 0 [by b.b._en:=1]
136631 b.b.en_buf_f.buf2._y : 0 [by b.b._en:=1]
136835 b.b._en_X_f[0] : 1 [by b.b.en_buf_f.buf2._y:=0]
139501 b.b._out_a_B : 1 [by b.out.a:=0]
139502 b.b.out_a_B_buf_f.buf2._y : 0 [by b.b._out_a_B:=1]
139516 b.b.out_a_B_buf_t.buf2._y : 0 [by b.b._out_a_B:=1]
139539 b.b._out_a_BX_t[0] : 1 [by b.b.out_a_B_buf_f.buf2._y:=0]
140255 b.b._out_a_BX_f[0] : 1 [by b.b.out_a_B_buf_t.buf2._y:=0]
143851 b.b.f_buf_func[2].y : X [by b.b.f_buf_func[2]._y:=X]
166204 b.b.f_buf_func[4].y : X [by b.b.f_buf_func[4]._y:=X]
167237 b.b.dly.dly[0].y : 0 [by b.b.dly.dly[0].___y:=1]
167349 b.b.dly.mu2[0]._y : 1 [by b.b.dly.dly[0].y:=0]
175755 b.b.f_buf_func[1]._y : X [by b.b._reset_BXX[0]:=1]
175795 b.b.f_buf_func[1].y : X [by b.b.f_buf_func[1]._y:=X]
188359 b.b._en_X_t[0] : 1 [by b.b.en_buf_t.buf2._y:=0]
214861 b.b.dly._a[1] : 0 [by b.b.dly.mu2[0]._y:=1]
215118 b.b.dly.and2[1]._y : 1 [by b.b.dly._a[1]:=0]
215205 b.b.dly.dly[1].a : 0 [by b.b.dly.and2[1]._y:=1]
215499 b.b.dly.dly[1]._y : 1 [by b.b.dly.dly[1].a:=0]
215500 b.b.dly.dly[1].__y : 0 [by b.b.dly.dly[1]._y:=1]
217306 b.b.dly.dly[1].___y : 1 [by b.b.dly.dly[1].__y:=0]
219313 b.b.dly.dly[1].y : 0 [by b.b.dly.dly[1].___y:=1]
220522 b.b.dly.dly[2]._y : 1 [by b.b.dly.dly[1].y:=0]
221112 b.b.dly.dly[2].__y : 0 [by b.b.dly.dly[2]._y:=1]
221290 b.b.dly.dly[2].___y : 1 [by b.b.dly.dly[2].__y:=0]
222093 b.b.dly.dly[2].y : 0 [by b.b.dly.dly[2].___y:=1]
222257 b.b.dly.mu2[1]._y : 1 [by b.b.dly.dly[2].y:=0]
224452 b.b.dly._a[2] : 0 [by b.b.dly.mu2[1]._y:=1]
224474 b.b.dly.and2[2]._y : 1 [by b.b.dly._a[2]:=0]
225321 b.b.dly.dly[3].a : 0 [by b.b.dly.and2[2]._y:=1]
255449 b.b.dly.dly[3]._y : 1 [by b.b.dly.dly[3].a:=0]
255582 b.b.dly.dly[3].__y : 0 [by b.b.dly.dly[3]._y:=1]
271244 b.b.dly.dly[3].___y : 1 [by b.b.dly.dly[3].__y:=0]
271603 b.b.dly.dly[3].y : 0 [by b.b.dly.dly[3].___y:=1]
285719 b.b.dly.dly[4]._y : 1 [by b.b.dly.dly[3].y:=0]
285940 b.b.dly.dly[4].__y : 0 [by b.b.dly.dly[4]._y:=1]
285947 b.b.dly.dly[4].___y : 1 [by b.b.dly.dly[4].__y:=0]
285977 b.b.dly.dly[4].y : 0 [by b.b.dly.dly[4].___y:=1]
292690 b.b.dly.dly[5]._y : 1 [by b.b.dly.dly[4].y:=0]
350151 b.b.dly.dly[5].__y : 0 [by b.b.dly.dly[5]._y:=1]
350242 b.b.dly.dly[5].___y : 1 [by b.b.dly.dly[5].__y:=0]
352431 b.b.dly.dly[5].y : 0 [by b.b.dly.dly[5].___y:=1]
352438 b.b.dly.dly[6]._y : 1 [by b.b.dly.dly[5].y:=0]
355225 b.b.dly.dly[6].__y : 0 [by b.b.dly.dly[6]._y:=1]
355331 b.b.dly.dly[6].___y : 1 [by b.b.dly.dly[6].__y:=0]
355409 b.b.dly.dly[6].y : 0 [by b.b.dly.dly[6].___y:=1]
355684 b.b.dly.mu2[2]._y : 1 [by b.b.dly.dly[6].y:=0]
374680 b.b.dly._a[3] : 0 [by b.b.dly.mu2[2]._y:=1]
375135 b.b.dly.and2[3]._y : 1 [by b.b.dly._a[3]:=0]
375147 b.b.dly.dly[7].a : 0 [by b.b.dly.and2[3]._y:=1]
375551 b.b.dly.dly[7]._y : 1 [by b.b.dly.dly[7].a:=0]
375563 b.b.dly.dly[7].__y : 0 [by b.b.dly.dly[7]._y:=1]
381479 b.b.dly.dly[7].___y : 1 [by b.b.dly.dly[7].__y:=0]
385755 b.b.dly.dly[7].y : 0 [by b.b.dly.dly[7].___y:=1]
388654 b.b.dly.dly[8]._y : 1 [by b.b.dly.dly[7].y:=0]
392949 b.b.dly.dly[8].__y : 0 [by b.b.dly.dly[8]._y:=1]
392951 b.b.dly.dly[8].___y : 1 [by b.b.dly.dly[8].__y:=0]
397486 b.b.dly.dly[8].y : 0 [by b.b.dly.dly[8].___y:=1]
398735 b.b.dly.dly[9]._y : 1 [by b.b.dly.dly[8].y:=0]
402234 b.b.dly.dly[9].__y : 0 [by b.b.dly.dly[9]._y:=1]
402400 b.b.dly.dly[9].___y : 1 [by b.b.dly.dly[9].__y:=0]
402475 b.b.dly.dly[9].y : 0 [by b.b.dly.dly[9].___y:=1]
402820 b.b.dly.dly[10]._y : 1 [by b.b.dly.dly[9].y:=0]
402958 b.b.dly.dly[10].__y : 0 [by b.b.dly.dly[10]._y:=1]
408221 b.b.dly.dly[10].___y : 1 [by b.b.dly.dly[10].__y:=0]
408223 b.b.dly.dly[10].y : 0 [by b.b.dly.dly[10].___y:=1]
452140 b.b.dly.dly[11]._y : 1 [by b.b.dly.dly[10].y:=0]
452141 b.b.dly.dly[11].__y : 0 [by b.b.dly.dly[11]._y:=1]
452689 b.b.dly.dly[11].___y : 1 [by b.b.dly.dly[11].__y:=0]
452700 b.b.dly.dly[11].y : 0 [by b.b.dly.dly[11].___y:=1]
453070 b.b.dly.dly[12]._y : 1 [by b.b.dly.dly[11].y:=0]
453137 b.b.dly.dly[12].__y : 0 [by b.b.dly.dly[12]._y:=1]
455778 b.b.dly.dly[12].___y : 1 [by b.b.dly.dly[12].__y:=0]
455794 b.b.dly.dly[12].y : 0 [by b.b.dly.dly[12].___y:=1]
460356 b.b.dly.dly[13]._y : 1 [by b.b.dly.dly[12].y:=0]
460884 b.b.dly.dly[13].__y : 0 [by b.b.dly.dly[13]._y:=1]
463319 b.b.dly.dly[13].___y : 1 [by b.b.dly.dly[13].__y:=0]
490199 b.b.dly.dly[13].y : 0 [by b.b.dly.dly[13].___y:=1]
514124 b.b.dly.dly[14]._y : 1 [by b.b.dly.dly[13].y:=0]
527165 b.b.dly.dly[14].__y : 0 [by b.b.dly.dly[14]._y:=1]
527167 b.b.dly.dly[14].___y : 1 [by b.b.dly.dly[14].__y:=0]
588125 b.b.dly.mu2[3].b : 0 [by b.b.dly.dly[14].___y:=1]
588128 b.b.dly.mu2[3]._y : 1 [by b.b.dly.mu2[3].b:=0]
588157 b.b._req : 0 [by b.b.dly.mu2[3]._y:=1]
588474 b.b.req_buf._y : 1 [by b.b._req:=0]
590075 b.b._reqX : 0 [by b.b.req_buf._y:=1]
590228 b.b.req_bufarray.buf2._y : 1 [by b.b._reqX:=0]
590272 b.b._reqXX[0] : 0 [by b.b.req_bufarray.buf2._y:=1]
[] set Reset 1
590272 Reset : 1
593033 b._reset_B : 0 [by Reset:=1]
606716 b.b.reset_buf._y : 1 [by b._reset_B:=0]
606717 b.b._reset_BX : 0 [by b.b.reset_buf._y:=1]
606934 b.b.reset_bufarray.buf2._y : 1 [by b.b._reset_BX:=0]
606956 b.b._reset_BXX[0] : 0 [by b.b.reset_bufarray.buf2._y:=1]
606957 b.b.f_buf_func[1]._y : 1 [by b.b._reset_BXX[0]:=0]
607115 b.b.t_buf_func[0]._y : 1 [by b.b._reset_BXX[0]:=0]
608244 b.b.f_buf_func[1].y : 0 [by b.b.f_buf_func[1]._y:=1]
608537 b.b.f_buf_func[2]._y : 1 [by b.b._reset_BXX[0]:=0]
608682 b.b.f_buf_func[2].y : 0 [by b.b.f_buf_func[2]._y:=1]
609347 b.b.t_buf_func[0].y : 0 [by b.b.t_buf_func[0]._y:=1]
616301 b.b.f_buf_func[4]._y : 1 [by b.b._reset_BXX[0]:=0]
619133 b.b.f_buf_func[4].y : 0 [by b.b.f_buf_func[4]._y:=1]
626632 b.b.t_buf_func[3]._y : 1 [by b.b._reset_BXX[0]:=0]
632986 b.b.t_buf_func[3].y : 0 [by b.b.t_buf_func[3]._y:=1]
[] set Reset 0
632986 Reset : 0
632987 b._reset_B : 1 [by Reset:=0]
672271 b.b.reset_buf._y : 0 [by b._reset_B:=1]
672433 b.b._reset_BX : 1 [by b.b.reset_buf._y:=0]
679802 b.b.reset_bufarray.buf2._y : 0 [by b.b._reset_BX:=1]
679816 b.b._reset_BXX[0] : 1 [by b.b.reset_bufarray.buf2._y:=0]
[] Reset finished, setting data
679816 b.in.d[0] : 0
679816 b.in.d[4] : 1
679816 b.in.d[2] : 1
679816 b.in.d[1] : 1
679816 b.in.d[3] : 0
679817 b.b._inB[1] : 0 [by b.in.d[1]:=1]
679817 b.b._inB[3] : 1 [by b.in.d[3]:=0]
679823 b.b._inB[0] : 1 [by b.in.d[0]:=0]
679976 b.b._inB[4] : 0 [by b.in.d[4]:=1]
701373 b.b._inB[2] : 0 [by b.in.d[2]:=1]
[] Reset finished, setting req 1
701373 b.in.r : 1
701374 b.b.dly.and2[0]._y : 0 [by b.in.r:=1]
703617 b.b.dly.dly[0].a : 1 [by b.b.dly.and2[0]._y:=0]
703804 b.b.dly.dly[0]._y : 0 [by b.b.dly.dly[0].a:=1]
703805 b.b.dly.dly[0].__y : 1 [by b.b.dly.dly[0]._y:=0]
707987 b.b.dly.dly[0].___y : 0 [by b.b.dly.dly[0].__y:=1]
742769 b.b.dly.dly[0].y : 1 [by b.b.dly.dly[0].___y:=0]
742770 b.b.dly.mu2[0]._y : 0 [by b.b.dly.dly[0].y:=1]
743623 b.b.dly._a[1] : 1 [by b.b.dly.mu2[0]._y:=0]
743628 b.b.dly.and2[1]._y : 0 [by b.b.dly._a[1]:=1]
744519 b.b.dly.dly[1].a : 1 [by b.b.dly.and2[1]._y:=0]
744520 b.b.dly.dly[1]._y : 0 [by b.b.dly.dly[1].a:=1]
744537 b.b.dly.dly[1].__y : 1 [by b.b.dly.dly[1]._y:=0]
747110 b.b.dly.dly[1].___y : 0 [by b.b.dly.dly[1].__y:=1]
755471 b.b.dly.dly[1].y : 1 [by b.b.dly.dly[1].___y:=0]
755474 b.b.dly.dly[2]._y : 0 [by b.b.dly.dly[1].y:=1]
756415 b.b.dly.dly[2].__y : 1 [by b.b.dly.dly[2]._y:=0]
815377 b.b.dly.dly[2].___y : 0 [by b.b.dly.dly[2].__y:=1]
815378 b.b.dly.dly[2].y : 1 [by b.b.dly.dly[2].___y:=0]
815420 b.b.dly.mu2[1]._y : 0 [by b.b.dly.dly[2].y:=1]
818237 b.b.dly._a[2] : 1 [by b.b.dly.mu2[1]._y:=0]
831970 b.b.dly.and2[2]._y : 0 [by b.b.dly._a[2]:=1]
832065 b.b.dly.dly[3].a : 1 [by b.b.dly.and2[2]._y:=0]
832400 b.b.dly.dly[3]._y : 0 [by b.b.dly.dly[3].a:=1]
832408 b.b.dly.dly[3].__y : 1 [by b.b.dly.dly[3]._y:=0]
832442 b.b.dly.dly[3].___y : 0 [by b.b.dly.dly[3].__y:=1]
846329 b.b.dly.dly[3].y : 1 [by b.b.dly.dly[3].___y:=0]
847247 b.b.dly.dly[4]._y : 0 [by b.b.dly.dly[3].y:=1]
847251 b.b.dly.dly[4].__y : 1 [by b.b.dly.dly[4]._y:=0]
893629 b.b.dly.dly[4].___y : 0 [by b.b.dly.dly[4].__y:=1]
896027 b.b.dly.dly[4].y : 1 [by b.b.dly.dly[4].___y:=0]
899242 b.b.dly.dly[5]._y : 0 [by b.b.dly.dly[4].y:=1]
946361 b.b.dly.dly[5].__y : 1 [by b.b.dly.dly[5]._y:=0]
946409 b.b.dly.dly[5].___y : 0 [by b.b.dly.dly[5].__y:=1]
946412 b.b.dly.dly[5].y : 1 [by b.b.dly.dly[5].___y:=0]
946590 b.b.dly.dly[6]._y : 0 [by b.b.dly.dly[5].y:=1]
967567 b.b.dly.dly[6].__y : 1 [by b.b.dly.dly[6]._y:=0]
979466 b.b.dly.dly[6].___y : 0 [by b.b.dly.dly[6].__y:=1]
985417 b.b.dly.dly[6].y : 1 [by b.b.dly.dly[6].___y:=0]
1024902 b.b.dly.mu2[2]._y : 0 [by b.b.dly.dly[6].y:=1]
1025729 b.b.dly._a[3] : 1 [by b.b.dly.mu2[2]._y:=0]
1025902 b.b.dly.and2[3]._y : 0 [by b.b.dly._a[3]:=1]
1026086 b.b.dly.dly[7].a : 1 [by b.b.dly.and2[3]._y:=0]
1026087 b.b.dly.dly[7]._y : 0 [by b.b.dly.dly[7].a:=1]
1026160 b.b.dly.dly[7].__y : 1 [by b.b.dly.dly[7]._y:=0]
1026164 b.b.dly.dly[7].___y : 0 [by b.b.dly.dly[7].__y:=1]
1063452 b.b.dly.dly[7].y : 1 [by b.b.dly.dly[7].___y:=0]
1063548 b.b.dly.dly[8]._y : 0 [by b.b.dly.dly[7].y:=1]
1063684 b.b.dly.dly[8].__y : 1 [by b.b.dly.dly[8]._y:=0]
1063685 b.b.dly.dly[8].___y : 0 [by b.b.dly.dly[8].__y:=1]
1082731 b.b.dly.dly[8].y : 1 [by b.b.dly.dly[8].___y:=0]
1082972 b.b.dly.dly[9]._y : 0 [by b.b.dly.dly[8].y:=1]
1086931 b.b.dly.dly[9].__y : 1 [by b.b.dly.dly[9]._y:=0]
1086943 b.b.dly.dly[9].___y : 0 [by b.b.dly.dly[9].__y:=1]
1090843 b.b.dly.dly[9].y : 1 [by b.b.dly.dly[9].___y:=0]
1091872 b.b.dly.dly[10]._y : 0 [by b.b.dly.dly[9].y:=1]
1091873 b.b.dly.dly[10].__y : 1 [by b.b.dly.dly[10]._y:=0]
1091929 b.b.dly.dly[10].___y : 0 [by b.b.dly.dly[10].__y:=1]
1136935 b.b.dly.dly[10].y : 1 [by b.b.dly.dly[10].___y:=0]
1136936 b.b.dly.dly[11]._y : 0 [by b.b.dly.dly[10].y:=1]
1136973 b.b.dly.dly[11].__y : 1 [by b.b.dly.dly[11]._y:=0]
1160348 b.b.dly.dly[11].___y : 0 [by b.b.dly.dly[11].__y:=1]
1160349 b.b.dly.dly[11].y : 1 [by b.b.dly.dly[11].___y:=0]
1163913 b.b.dly.dly[12]._y : 0 [by b.b.dly.dly[11].y:=1]
1165605 b.b.dly.dly[12].__y : 1 [by b.b.dly.dly[12]._y:=0]
1165618 b.b.dly.dly[12].___y : 0 [by b.b.dly.dly[12].__y:=1]
1182602 b.b.dly.dly[12].y : 1 [by b.b.dly.dly[12].___y:=0]
1182959 b.b.dly.dly[13]._y : 0 [by b.b.dly.dly[12].y:=1]
1182984 b.b.dly.dly[13].__y : 1 [by b.b.dly.dly[13]._y:=0]
1183005 b.b.dly.dly[13].___y : 0 [by b.b.dly.dly[13].__y:=1]
1183006 b.b.dly.dly[13].y : 1 [by b.b.dly.dly[13].___y:=0]
1192654 b.b.dly.dly[14]._y : 0 [by b.b.dly.dly[13].y:=1]
1192655 b.b.dly.dly[14].__y : 1 [by b.b.dly.dly[14]._y:=0]
1192656 b.b.dly.dly[14].___y : 0 [by b.b.dly.dly[14].__y:=1]
1192817 b.b.dly.mu2[3].b : 1 [by b.b.dly.dly[14].___y:=0]
1193854 b.b.dly.mu2[3]._y : 0 [by b.b.dly.mu2[3].b:=1]
1193859 b.b._req : 1 [by b.b.dly.mu2[3]._y:=0]
1194440 b.b.req_buf._y : 0 [by b.b._req:=1]
1194848 b.b._reqX : 1 [by b.b.req_buf._y:=0]
1194859 b.b.req_bufarray.buf2._y : 0 [by b.b._reqX:=1]
1195906 b.b._reqXX[0] : 1 [by b.b.req_bufarray.buf2._y:=0]
1195910 b.b.t_buf_func[1]._y : 0 [by b.b._reqXX[0]:=1]
1195920 b.b.f_buf_func[0]._y : 0 [by b.b._reqXX[0]:=1]
1195924 b.b.f_buf_func[3]._y : 0 [by b.b._reqXX[0]:=1]
1196010 b.b.t_buf_func[2]._y : 0 [by b.b._reqXX[0]:=1]
1196152 b.b.f_buf_func[3].y : 1 [by b.b.f_buf_func[3]._y:=0]
1196853 b.b.t_buf_func[2].y : 1 [by b.b.t_buf_func[2]._y:=0]
1197114 b.b.t_buf_func[1].y : 1 [by b.b.t_buf_func[1]._y:=0]
1204375 b.b.f_buf_func[0].y : 1 [by b.b.f_buf_func[0]._y:=0]
1227350 b.b.t_buf_func[4]._y : 0 [by b.b._reqXX[0]:=1]
1228809 b.b.t_buf_func[4].y : 1 [by b.b.t_buf_func[4]._y:=0]
[] Receiving val out
1228809 b.out.v : 1
1228879 b.b.inack_ctl._y : 0 [by b.out.v:=1]
1279301 b.in.a : 1 [by b.b.inack_ctl._y:=0]
1279312 b.b._en : 0 [by b.in.a:=1]
1279315 b.b.en_buf_f.buf2._y : 1 [by b.b._en:=0]
1279366 b.b.en_buf_t.buf2._y : 1 [by b.b._en:=0]
1280463 b.b._en_X_f[0] : 0 [by b.b.en_buf_f.buf2._y:=1]
1280527 b.b._en_X_t[0] : 0 [by b.b.en_buf_t.buf2._y:=1]
[] Changing some input data
1280527 b.in.d[0] : 1
1289179 b.b._inB[0] : 0 [by b.in.d[0]:=1]
[] Removing req
[] Changing more data
1289179 b.in.r : 0
1289179 b.in.d[4] : 0
1289260 b.b.dly.and2[0]._y : 1 [by b.in.r:=0]
1300256 b.b._inB[4] : 1 [by b.in.d[4]:=0]
1307243 b.b.dly.dly[0].a : 0 [by b.b.dly.and2[0]._y:=1]
1307335 b.b.dly.dly[0]._y : 1 [by b.b.dly.dly[0].a:=0]
1315646 b.b.dly.dly[0].__y : 0 [by b.b.dly.dly[0]._y:=1]
1317390 b.b.dly.dly[0].___y : 1 [by b.b.dly.dly[0].__y:=0]
1318003 b.b.dly.dly[0].y : 0 [by b.b.dly.dly[0].___y:=1]
1332025 b.b.dly.mu2[0]._y : 1 [by b.b.dly.dly[0].y:=0]
1332070 b.b.dly._a[1] : 0 [by b.b.dly.mu2[0]._y:=1]
1333067 b.b.dly.and2[1]._y : 1 [by b.b.dly._a[1]:=0]
1334716 b.b.dly.dly[1].a : 0 [by b.b.dly.and2[1]._y:=1]
1335241 b.b.dly.dly[1]._y : 1 [by b.b.dly.dly[1].a:=0]
1336141 b.b.dly.dly[1].__y : 0 [by b.b.dly.dly[1]._y:=1]
1336193 b.b.dly.dly[1].___y : 1 [by b.b.dly.dly[1].__y:=0]
1336200 b.b.dly.dly[1].y : 0 [by b.b.dly.dly[1].___y:=1]
1351812 b.b.dly.dly[2]._y : 1 [by b.b.dly.dly[1].y:=0]
1358279 b.b.dly.dly[2].__y : 0 [by b.b.dly.dly[2]._y:=1]
1358281 b.b.dly.dly[2].___y : 1 [by b.b.dly.dly[2].__y:=0]
1358635 b.b.dly.dly[2].y : 0 [by b.b.dly.dly[2].___y:=1]
1358768 b.b.dly.mu2[1]._y : 1 [by b.b.dly.dly[2].y:=0]
1358769 b.b.dly._a[2] : 0 [by b.b.dly.mu2[1]._y:=1]
1358773 b.b.dly.and2[2]._y : 1 [by b.b.dly._a[2]:=0]
1359319 b.b.dly.dly[3].a : 0 [by b.b.dly.and2[2]._y:=1]
1404882 b.b.dly.dly[3]._y : 1 [by b.b.dly.dly[3].a:=0]
1404883 b.b.dly.dly[3].__y : 0 [by b.b.dly.dly[3]._y:=1]
1417261 b.b.dly.dly[3].___y : 1 [by b.b.dly.dly[3].__y:=0]
1417340 b.b.dly.dly[3].y : 0 [by b.b.dly.dly[3].___y:=1]
1419773 b.b.dly.dly[4]._y : 1 [by b.b.dly.dly[3].y:=0]
1419861 b.b.dly.dly[4].__y : 0 [by b.b.dly.dly[4]._y:=1]
1427643 b.b.dly.dly[4].___y : 1 [by b.b.dly.dly[4].__y:=0]
1455970 b.b.dly.dly[4].y : 0 [by b.b.dly.dly[4].___y:=1]
1456029 b.b.dly.dly[5]._y : 1 [by b.b.dly.dly[4].y:=0]
1456059 b.b.dly.dly[5].__y : 0 [by b.b.dly.dly[5]._y:=1]
1457526 b.b.dly.dly[5].___y : 1 [by b.b.dly.dly[5].__y:=0]
1517030 b.b.dly.dly[5].y : 0 [by b.b.dly.dly[5].___y:=1]
1536414 b.b.dly.dly[6]._y : 1 [by b.b.dly.dly[5].y:=0]
1537099 b.b.dly.dly[6].__y : 0 [by b.b.dly.dly[6]._y:=1]
1553814 b.b.dly.dly[6].___y : 1 [by b.b.dly.dly[6].__y:=0]
1553941 b.b.dly.dly[6].y : 0 [by b.b.dly.dly[6].___y:=1]
1554110 b.b.dly.mu2[2]._y : 1 [by b.b.dly.dly[6].y:=0]
1554153 b.b.dly._a[3] : 0 [by b.b.dly.mu2[2]._y:=1]
1554165 b.b.dly.and2[3]._y : 1 [by b.b.dly._a[3]:=0]
1555444 b.b.dly.dly[7].a : 0 [by b.b.dly.and2[3]._y:=1]
1555677 b.b.dly.dly[7]._y : 1 [by b.b.dly.dly[7].a:=0]
1555680 b.b.dly.dly[7].__y : 0 [by b.b.dly.dly[7]._y:=1]
1555718 b.b.dly.dly[7].___y : 1 [by b.b.dly.dly[7].__y:=0]
1555719 b.b.dly.dly[7].y : 0 [by b.b.dly.dly[7].___y:=1]
1568471 b.b.dly.dly[8]._y : 1 [by b.b.dly.dly[7].y:=0]
1568563 b.b.dly.dly[8].__y : 0 [by b.b.dly.dly[8]._y:=1]
1571290 b.b.dly.dly[8].___y : 1 [by b.b.dly.dly[8].__y:=0]
1571292 b.b.dly.dly[8].y : 0 [by b.b.dly.dly[8].___y:=1]
1571293 b.b.dly.dly[9]._y : 1 [by b.b.dly.dly[8].y:=0]
1572794 b.b.dly.dly[9].__y : 0 [by b.b.dly.dly[9]._y:=1]
1572796 b.b.dly.dly[9].___y : 1 [by b.b.dly.dly[9].__y:=0]
1572814 b.b.dly.dly[9].y : 0 [by b.b.dly.dly[9].___y:=1]
1572933 b.b.dly.dly[10]._y : 1 [by b.b.dly.dly[9].y:=0]
1578653 b.b.dly.dly[10].__y : 0 [by b.b.dly.dly[10]._y:=1]
1578661 b.b.dly.dly[10].___y : 1 [by b.b.dly.dly[10].__y:=0]
1578715 b.b.dly.dly[10].y : 0 [by b.b.dly.dly[10].___y:=1]
1629253 b.b.dly.dly[11]._y : 1 [by b.b.dly.dly[10].y:=0]
1629258 b.b.dly.dly[11].__y : 0 [by b.b.dly.dly[11]._y:=1]
1630325 b.b.dly.dly[11].___y : 1 [by b.b.dly.dly[11].__y:=0]
1630326 b.b.dly.dly[11].y : 0 [by b.b.dly.dly[11].___y:=1]
1630464 b.b.dly.dly[12]._y : 1 [by b.b.dly.dly[11].y:=0]
1630465 b.b.dly.dly[12].__y : 0 [by b.b.dly.dly[12]._y:=1]
1630529 b.b.dly.dly[12].___y : 1 [by b.b.dly.dly[12].__y:=0]
1630652 b.b.dly.dly[12].y : 0 [by b.b.dly.dly[12].___y:=1]
1630654 b.b.dly.dly[13]._y : 1 [by b.b.dly.dly[12].y:=0]
1630691 b.b.dly.dly[13].__y : 0 [by b.b.dly.dly[13]._y:=1]
1630834 b.b.dly.dly[13].___y : 1 [by b.b.dly.dly[13].__y:=0]
1630885 b.b.dly.dly[13].y : 0 [by b.b.dly.dly[13].___y:=1]
1631327 b.b.dly.dly[14]._y : 1 [by b.b.dly.dly[13].y:=0]
1631338 b.b.dly.dly[14].__y : 0 [by b.b.dly.dly[14]._y:=1]
1631339 b.b.dly.dly[14].___y : 1 [by b.b.dly.dly[14].__y:=0]
1631348 b.b.dly.mu2[3].b : 0 [by b.b.dly.dly[14].___y:=1]
1631373 b.b.dly.mu2[3]._y : 1 [by b.b.dly.mu2[3].b:=0]
1641626 b.b._req : 0 [by b.b.dly.mu2[3]._y:=1]
1645147 b.b.req_buf._y : 1 [by b.b._req:=0]
1645292 b.b._reqX : 0 [by b.b.req_buf._y:=1]
1661460 b.b.req_bufarray.buf2._y : 1 [by b.b._reqX:=0]
1661690 b.b._reqXX[0] : 0 [by b.b.req_bufarray.buf2._y:=1]
[] Receiving ack out
1661690 b.out.a : 1
1662381 b.b._out_a_B : 0 [by b.out.a:=1]
1662395 b.b.out_a_B_buf_t.buf2._y : 1 [by b.b._out_a_B:=0]
1663924 b.b.out_a_B_buf_f.buf2._y : 1 [by b.b._out_a_B:=0]
1664006 b.b._out_a_BX_f[0] : 0 [by b.b.out_a_B_buf_t.buf2._y:=1]
1664007 b.b.f_buf_func[3]._y : 1 [by b.b._out_a_BX_f[0]:=0]
1664008 b.b.f_buf_func[3].y : 0 [by b.b.f_buf_func[3]._y:=1]
1664017 b.b.f_buf_func[0]._y : 1 [by b.b._out_a_BX_f[0]:=0]
1670518 b.b.f_buf_func[0].y : 0 [by b.b.f_buf_func[0]._y:=1]
1681436 b.b._out_a_BX_t[0] : 0 [by b.b.out_a_B_buf_f.buf2._y:=1]
1681568 b.b.t_buf_func[4]._y : 1 [by b.b._out_a_BX_t[0]:=0]
1681569 b.b.t_buf_func[4].y : 0 [by b.b.t_buf_func[4]._y:=1]
1682075 b.b.t_buf_func[1]._y : 1 [by b.b._out_a_BX_t[0]:=0]
1682092 b.b.t_buf_func[1].y : 0 [by b.b.t_buf_func[1]._y:=1]
1683229 b.b.t_buf_func[2]._y : 1 [by b.b._out_a_BX_t[0]:=0]
1683381 b.b.t_buf_func[2].y : 0 [by b.b.t_buf_func[2]._y:=1]
1683381 b.out.v : 0
1686364 b.b.inack_ctl._y : 1 [by b.out.v:=0]
1686367 b.in.a : 0 [by b.b.inack_ctl._y:=1]
1686791 b.b._en : 1 [by b.in.a:=0]
1686797 b.b.en_buf_f.buf2._y : 0 [by b.b._en:=1]
1689258 b.b._en_X_f[0] : 1 [by b.b.en_buf_f.buf2._y:=0]
1689379 b.b.en_buf_t.buf2._y : 0 [by b.b._en:=1]
1690209 b.b._en_X_t[0] : 1 [by b.b.en_buf_t.buf2._y:=0]
[] Set ack out 0
1690209 b.out.a : 0
1713141 b.b._out_a_B : 1 [by b.out.a:=0]
1713143 b.b.out_a_B_buf_t.buf2._y : 0 [by b.b._out_a_B:=1]
1713335 b.b.out_a_B_buf_f.buf2._y : 0 [by b.b._out_a_B:=1]
1713473 b.b._out_a_BX_t[0] : 1 [by b.b.out_a_B_buf_f.buf2._y:=0]
1713746 b.b._out_a_BX_f[0] : 1 [by b.b.out_a_B_buf_t.buf2._y:=0]
[] Again!!! setting data
1713746 b.in.d[0] : 0
1713746 b.in.d[2] : 0
1713746 b.in.d[1] : 0
1713763 b.b._inB[2] : 1 [by b.in.d[2]:=0]
1713763 b.b._inB[0] : 1 [by b.in.d[0]:=0]
1714172 b.b._inB[1] : 1 [by b.in.d[1]:=0]
[] Again!!! setting req 1
1714172 b.in.r : 1
1714173 b.b.dly.and2[0]._y : 0 [by b.in.r:=1]
1714174 b.b.dly.dly[0].a : 1 [by b.b.dly.and2[0]._y:=0]
1715200 b.b.dly.dly[0]._y : 0 [by b.b.dly.dly[0].a:=1]
1715201 b.b.dly.dly[0].__y : 1 [by b.b.dly.dly[0]._y:=0]
1715220 b.b.dly.dly[0].___y : 0 [by b.b.dly.dly[0].__y:=1]
1715388 b.b.dly.dly[0].y : 1 [by b.b.dly.dly[0].___y:=0]
1715927 b.b.dly.mu2[0]._y : 0 [by b.b.dly.dly[0].y:=1]
1716088 b.b.dly._a[1] : 1 [by b.b.dly.mu2[0]._y:=0]
1716261 b.b.dly.and2[1]._y : 0 [by b.b.dly._a[1]:=1]
1718808 b.b.dly.dly[1].a : 1 [by b.b.dly.and2[1]._y:=0]
1733869 b.b.dly.dly[1]._y : 0 [by b.b.dly.dly[1].a:=1]
1733870 b.b.dly.dly[1].__y : 1 [by b.b.dly.dly[1]._y:=0]
1733871 b.b.dly.dly[1].___y : 0 [by b.b.dly.dly[1].__y:=1]
1734261 b.b.dly.dly[1].y : 1 [by b.b.dly.dly[1].___y:=0]
1734468 b.b.dly.dly[2]._y : 0 [by b.b.dly.dly[1].y:=1]
1735301 b.b.dly.dly[2].__y : 1 [by b.b.dly.dly[2]._y:=0]
1735329 b.b.dly.dly[2].___y : 0 [by b.b.dly.dly[2].__y:=1]
1735336 b.b.dly.dly[2].y : 1 [by b.b.dly.dly[2].___y:=0]
1735750 b.b.dly.mu2[1]._y : 0 [by b.b.dly.dly[2].y:=1]
1735754 b.b.dly._a[2] : 1 [by b.b.dly.mu2[1]._y:=0]
1737533 b.b.dly.and2[2]._y : 0 [by b.b.dly._a[2]:=1]
1760407 b.b.dly.dly[3].a : 1 [by b.b.dly.and2[2]._y:=0]
1760573 b.b.dly.dly[3]._y : 0 [by b.b.dly.dly[3].a:=1]
1800443 b.b.dly.dly[3].__y : 1 [by b.b.dly.dly[3]._y:=0]
1809088 b.b.dly.dly[3].___y : 0 [by b.b.dly.dly[3].__y:=1]
1810021 b.b.dly.dly[3].y : 1 [by b.b.dly.dly[3].___y:=0]
1810877 b.b.dly.dly[4]._y : 0 [by b.b.dly.dly[3].y:=1]
1811016 b.b.dly.dly[4].__y : 1 [by b.b.dly.dly[4]._y:=0]
1837225 b.b.dly.dly[4].___y : 0 [by b.b.dly.dly[4].__y:=1]
1837420 b.b.dly.dly[4].y : 1 [by b.b.dly.dly[4].___y:=0]
1837422 b.b.dly.dly[5]._y : 0 [by b.b.dly.dly[4].y:=1]
1890871 b.b.dly.dly[5].__y : 1 [by b.b.dly.dly[5]._y:=0]
1890877 b.b.dly.dly[5].___y : 0 [by b.b.dly.dly[5].__y:=1]
1891131 b.b.dly.dly[5].y : 1 [by b.b.dly.dly[5].___y:=0]
1891139 b.b.dly.dly[6]._y : 0 [by b.b.dly.dly[5].y:=1]
1891140 b.b.dly.dly[6].__y : 1 [by b.b.dly.dly[6]._y:=0]
1891146 b.b.dly.dly[6].___y : 0 [by b.b.dly.dly[6].__y:=1]
1942182 b.b.dly.dly[6].y : 1 [by b.b.dly.dly[6].___y:=0]
1945272 b.b.dly.mu2[2]._y : 0 [by b.b.dly.dly[6].y:=1]
1945498 b.b.dly._a[3] : 1 [by b.b.dly.mu2[2]._y:=0]
1946317 b.b.dly.and2[3]._y : 0 [by b.b.dly._a[3]:=1]
1946318 b.b.dly.dly[7].a : 1 [by b.b.dly.and2[3]._y:=0]
1946324 b.b.dly.dly[7]._y : 0 [by b.b.dly.dly[7].a:=1]
1946326 b.b.dly.dly[7].__y : 1 [by b.b.dly.dly[7]._y:=0]
1949888 b.b.dly.dly[7].___y : 0 [by b.b.dly.dly[7].__y:=1]
1949903 b.b.dly.dly[7].y : 1 [by b.b.dly.dly[7].___y:=0]
1970704 b.b.dly.dly[8]._y : 0 [by b.b.dly.dly[7].y:=1]
1970811 b.b.dly.dly[8].__y : 1 [by b.b.dly.dly[8]._y:=0]
1970904 b.b.dly.dly[8].___y : 0 [by b.b.dly.dly[8].__y:=1]
1972556 b.b.dly.dly[8].y : 1 [by b.b.dly.dly[8].___y:=0]
1976495 b.b.dly.dly[9]._y : 0 [by b.b.dly.dly[8].y:=1]
1977253 b.b.dly.dly[9].__y : 1 [by b.b.dly.dly[9]._y:=0]
1979876 b.b.dly.dly[9].___y : 0 [by b.b.dly.dly[9].__y:=1]
1980592 b.b.dly.dly[9].y : 1 [by b.b.dly.dly[9].___y:=0]
1980593 b.b.dly.dly[10]._y : 0 [by b.b.dly.dly[9].y:=1]
1982333 b.b.dly.dly[10].__y : 1 [by b.b.dly.dly[10]._y:=0]
1982334 b.b.dly.dly[10].___y : 0 [by b.b.dly.dly[10].__y:=1]
1994486 b.b.dly.dly[10].y : 1 [by b.b.dly.dly[10].___y:=0]
2022685 b.b.dly.dly[11]._y : 0 [by b.b.dly.dly[10].y:=1]
2022686 b.b.dly.dly[11].__y : 1 [by b.b.dly.dly[11]._y:=0]
2022692 b.b.dly.dly[11].___y : 0 [by b.b.dly.dly[11].__y:=1]
2022693 b.b.dly.dly[11].y : 1 [by b.b.dly.dly[11].___y:=0]
2062182 b.b.dly.dly[12]._y : 0 [by b.b.dly.dly[11].y:=1]
2083781 b.b.dly.dly[12].__y : 1 [by b.b.dly.dly[12]._y:=0]
2083803 b.b.dly.dly[12].___y : 0 [by b.b.dly.dly[12].__y:=1]
2106311 b.b.dly.dly[12].y : 1 [by b.b.dly.dly[12].___y:=0]
2106318 b.b.dly.dly[13]._y : 0 [by b.b.dly.dly[12].y:=1]
2106383 b.b.dly.dly[13].__y : 1 [by b.b.dly.dly[13]._y:=0]
2106396 b.b.dly.dly[13].___y : 0 [by b.b.dly.dly[13].__y:=1]
2107520 b.b.dly.dly[13].y : 1 [by b.b.dly.dly[13].___y:=0]
2107624 b.b.dly.dly[14]._y : 0 [by b.b.dly.dly[13].y:=1]
2107665 b.b.dly.dly[14].__y : 1 [by b.b.dly.dly[14]._y:=0]
2107666 b.b.dly.dly[14].___y : 0 [by b.b.dly.dly[14].__y:=1]
2107667 b.b.dly.mu2[3].b : 1 [by b.b.dly.dly[14].___y:=0]
2172045 b.b.dly.mu2[3]._y : 0 [by b.b.dly.mu2[3].b:=1]
2185217 b.b._req : 1 [by b.b.dly.mu2[3]._y:=0]
2185218 b.b.req_buf._y : 0 [by b.b._req:=1]
2205043 b.b._reqX : 1 [by b.b.req_buf._y:=0]
2208179 b.b.req_bufarray.buf2._y : 0 [by b.b._reqX:=1]
2209005 b.b._reqXX[0] : 1 [by b.b.req_bufarray.buf2._y:=0]
2209063 b.b.f_buf_func[2]._y : 0 [by b.b._reqXX[0]:=1]
2210838 b.b.f_buf_func[0]._y : 0 [by b.b._reqXX[0]:=1]
2210852 b.b.f_buf_func[0].y : 1 [by b.b.f_buf_func[0]._y:=0]
2211448 b.b.f_buf_func[3]._y : 0 [by b.b._reqXX[0]:=1]
2211804 b.b.f_buf_func[3].y : 1 [by b.b.f_buf_func[3]._y:=0]
2225553 b.b.f_buf_func[1]._y : 0 [by b.b._reqXX[0]:=1]
2225778 b.b.f_buf_func[4]._y : 0 [by b.b._reqXX[0]:=1]
2225883 b.b.f_buf_func[4].y : 1 [by b.b.f_buf_func[4]._y:=0]
2246262 b.b.f_buf_func[2].y : 1 [by b.b.f_buf_func[2]._y:=0]
2261391 b.b.f_buf_func[1].y : 1 [by b.b.f_buf_func[1]._y:=0]
[] Receiving val out
2261391 b.out.v : 1
2261500 b.b.inack_ctl._y : 0 [by b.out.v:=1]
2261501 b.in.a : 1 [by b.b.inack_ctl._y:=0]
2261510 b.b._en : 0 [by b.in.a:=1]
2261511 b.b.en_buf_t.buf2._y : 1 [by b.b._en:=0]
2297905 b.b._en_X_t[0] : 0 [by b.b.en_buf_t.buf2._y:=1]
2299463 b.b.en_buf_f.buf2._y : 1 [by b.b._en:=0]
2299464 b.b._en_X_f[0] : 0 [by b.b.en_buf_f.buf2._y:=1]
[] Changing some input data
2299464 b.in.d[0] : 1
2299464 b.in.d[2] : 1
2299464 b.in.d[1] : 1
2300214 b.b._inB[1] : 0 [by b.in.d[1]:=1]
2302553 b.b._inB[0] : 0 [by b.in.d[0]:=1]
2348190 b.b._inB[2] : 0 [by b.in.d[2]:=1]
[] Removing req
[] Changing more data
2348190 b.in.r : 0
2354945 b.b.dly.and2[0]._y : 1 [by b.in.r:=0]
2354996 b.b.dly.dly[0].a : 0 [by b.b.dly.and2[0]._y:=1]
2355006 b.b.dly.dly[0]._y : 1 [by b.b.dly.dly[0].a:=0]
2355326 b.b.dly.dly[0].__y : 0 [by b.b.dly.dly[0]._y:=1]
2362908 b.b.dly.dly[0].___y : 1 [by b.b.dly.dly[0].__y:=0]
2362909 b.b.dly.dly[0].y : 0 [by b.b.dly.dly[0].___y:=1]
2362910 b.b.dly.mu2[0]._y : 1 [by b.b.dly.dly[0].y:=0]
2364640 b.b.dly._a[1] : 0 [by b.b.dly.mu2[0]._y:=1]
2366327 b.b.dly.and2[1]._y : 1 [by b.b.dly._a[1]:=0]
2366342 b.b.dly.dly[1].a : 0 [by b.b.dly.and2[1]._y:=1]
2390616 b.b.dly.dly[1]._y : 1 [by b.b.dly.dly[1].a:=0]
2391070 b.b.dly.dly[1].__y : 0 [by b.b.dly.dly[1]._y:=1]
2391386 b.b.dly.dly[1].___y : 1 [by b.b.dly.dly[1].__y:=0]
2391387 b.b.dly.dly[1].y : 0 [by b.b.dly.dly[1].___y:=1]
2391770 b.b.dly.dly[2]._y : 1 [by b.b.dly.dly[1].y:=0]
2399233 b.b.dly.dly[2].__y : 0 [by b.b.dly.dly[2]._y:=1]
2399253 b.b.dly.dly[2].___y : 1 [by b.b.dly.dly[2].__y:=0]
2400576 b.b.dly.dly[2].y : 0 [by b.b.dly.dly[2].___y:=1]
2400663 b.b.dly.mu2[1]._y : 1 [by b.b.dly.dly[2].y:=0]
2407385 b.b.dly._a[2] : 0 [by b.b.dly.mu2[1]._y:=1]
2407397 b.b.dly.and2[2]._y : 1 [by b.b.dly._a[2]:=0]
2407542 b.b.dly.dly[3].a : 0 [by b.b.dly.and2[2]._y:=1]
2408443 b.b.dly.dly[3]._y : 1 [by b.b.dly.dly[3].a:=0]
2409792 b.b.dly.dly[3].__y : 0 [by b.b.dly.dly[3]._y:=1]
2410011 b.b.dly.dly[3].___y : 1 [by b.b.dly.dly[3].__y:=0]
2418342 b.b.dly.dly[3].y : 0 [by b.b.dly.dly[3].___y:=1]
2449923 b.b.dly.dly[4]._y : 1 [by b.b.dly.dly[3].y:=0]
2449941 b.b.dly.dly[4].__y : 0 [by b.b.dly.dly[4]._y:=1]
2452135 b.b.dly.dly[4].___y : 1 [by b.b.dly.dly[4].__y:=0]
2490107 b.b.dly.dly[4].y : 0 [by b.b.dly.dly[4].___y:=1]
2490227 b.b.dly.dly[5]._y : 1 [by b.b.dly.dly[4].y:=0]
2496542 b.b.dly.dly[5].__y : 0 [by b.b.dly.dly[5]._y:=1]
2498606 b.b.dly.dly[5].___y : 1 [by b.b.dly.dly[5].__y:=0]
2499198 b.b.dly.dly[5].y : 0 [by b.b.dly.dly[5].___y:=1]
2499205 b.b.dly.dly[6]._y : 1 [by b.b.dly.dly[5].y:=0]
2499206 b.b.dly.dly[6].__y : 0 [by b.b.dly.dly[6]._y:=1]
2499330 b.b.dly.dly[6].___y : 1 [by b.b.dly.dly[6].__y:=0]
2505260 b.b.dly.dly[6].y : 0 [by b.b.dly.dly[6].___y:=1]
2506312 b.b.dly.mu2[2]._y : 1 [by b.b.dly.dly[6].y:=0]
2506672 b.b.dly._a[3] : 0 [by b.b.dly.mu2[2]._y:=1]
2516866 b.b.dly.and2[3]._y : 1 [by b.b.dly._a[3]:=0]
2517963 b.b.dly.dly[7].a : 0 [by b.b.dly.and2[3]._y:=1]
2537855 b.b.dly.dly[7]._y : 1 [by b.b.dly.dly[7].a:=0]
2537859 b.b.dly.dly[7].__y : 0 [by b.b.dly.dly[7]._y:=1]
2549523 b.b.dly.dly[7].___y : 1 [by b.b.dly.dly[7].__y:=0]
2587442 b.b.dly.dly[7].y : 0 [by b.b.dly.dly[7].___y:=1]
2605103 b.b.dly.dly[8]._y : 1 [by b.b.dly.dly[7].y:=0]
2608484 b.b.dly.dly[8].__y : 0 [by b.b.dly.dly[8]._y:=1]
2608740 b.b.dly.dly[8].___y : 1 [by b.b.dly.dly[8].__y:=0]
2623670 b.b.dly.dly[8].y : 0 [by b.b.dly.dly[8].___y:=1]
2623707 b.b.dly.dly[9]._y : 1 [by b.b.dly.dly[8].y:=0]
2623719 b.b.dly.dly[9].__y : 0 [by b.b.dly.dly[9]._y:=1]
2623728 b.b.dly.dly[9].___y : 1 [by b.b.dly.dly[9].__y:=0]
2624155 b.b.dly.dly[9].y : 0 [by b.b.dly.dly[9].___y:=1]
2624397 b.b.dly.dly[10]._y : 1 [by b.b.dly.dly[9].y:=0]
2625232 b.b.dly.dly[10].__y : 0 [by b.b.dly.dly[10]._y:=1]
2671968 b.b.dly.dly[10].___y : 1 [by b.b.dly.dly[10].__y:=0]
2673528 b.b.dly.dly[10].y : 0 [by b.b.dly.dly[10].___y:=1]
2710621 b.b.dly.dly[11]._y : 1 [by b.b.dly.dly[10].y:=0]
2710881 b.b.dly.dly[11].__y : 0 [by b.b.dly.dly[11]._y:=1]
2719869 b.b.dly.dly[11].___y : 1 [by b.b.dly.dly[11].__y:=0]
2719870 b.b.dly.dly[11].y : 0 [by b.b.dly.dly[11].___y:=1]
2755920 b.b.dly.dly[12]._y : 1 [by b.b.dly.dly[11].y:=0]
2756304 b.b.dly.dly[12].__y : 0 [by b.b.dly.dly[12]._y:=1]
2756323 b.b.dly.dly[12].___y : 1 [by b.b.dly.dly[12].__y:=0]
2756332 b.b.dly.dly[12].y : 0 [by b.b.dly.dly[12].___y:=1]
2778286 b.b.dly.dly[13]._y : 1 [by b.b.dly.dly[12].y:=0]
2778474 b.b.dly.dly[13].__y : 0 [by b.b.dly.dly[13]._y:=1]
2824250 b.b.dly.dly[13].___y : 1 [by b.b.dly.dly[13].__y:=0]
2827850 b.b.dly.dly[13].y : 0 [by b.b.dly.dly[13].___y:=1]
2827998 b.b.dly.dly[14]._y : 1 [by b.b.dly.dly[13].y:=0]
2846875 b.b.dly.dly[14].__y : 0 [by b.b.dly.dly[14]._y:=1]
2846890 b.b.dly.dly[14].___y : 1 [by b.b.dly.dly[14].__y:=0]
2857499 b.b.dly.mu2[3].b : 0 [by b.b.dly.dly[14].___y:=1]
2858386 b.b.dly.mu2[3]._y : 1 [by b.b.dly.mu2[3].b:=0]
2866368 b.b._req : 0 [by b.b.dly.mu2[3]._y:=1]
2866369 b.b.req_buf._y : 1 [by b.b._req:=0]
2873095 b.b._reqX : 0 [by b.b.req_buf._y:=1]
2873460 b.b.req_bufarray.buf2._y : 1 [by b.b._reqX:=0]
2882418 b.b._reqXX[0] : 0 [by b.b.req_bufarray.buf2._y:=1]
[] Receiving ack out
2882418 b.out.a : 1
2883802 b.b._out_a_B : 0 [by b.out.a:=1]
2883823 b.b.out_a_B_buf_t.buf2._y : 1 [by b.b._out_a_B:=0]
2883826 b.b._out_a_BX_f[0] : 0 [by b.b.out_a_B_buf_t.buf2._y:=1]
2883828 b.b.f_buf_func[3]._y : 1 [by b.b._out_a_BX_f[0]:=0]
2883829 b.b.f_buf_func[4]._y : 1 [by b.b._out_a_BX_f[0]:=0]
2883829 b.b.f_buf_func[3].y : 0 [by b.b.f_buf_func[3]._y:=1]
2883843 b.b.out_a_B_buf_f.buf2._y : 1 [by b.b._out_a_B:=0]
2884408 b.b.f_buf_func[2]._y : 1 [by b.b._out_a_BX_f[0]:=0]
2885268 b.b.f_buf_func[2].y : 0 [by b.b.f_buf_func[2]._y:=1]
2885703 b.b.f_buf_func[0]._y : 1 [by b.b._out_a_BX_f[0]:=0]
2885704 b.b.f_buf_func[0].y : 0 [by b.b.f_buf_func[0]._y:=1]
2887281 b.b.f_buf_func[4].y : 0 [by b.b.f_buf_func[4]._y:=1]
2890976 b.b._out_a_BX_t[0] : 0 [by b.b.out_a_B_buf_f.buf2._y:=1]
2893335 b.b.f_buf_func[1]._y : 1 [by b.b._out_a_BX_f[0]:=0]
2893410 b.b.f_buf_func[1].y : 0 [by b.b.f_buf_func[1]._y:=1]
2893410 b.out.v : 0
2921361 b.b.inack_ctl._y : 1 [by b.out.v:=0]
2921435 b.in.a : 0 [by b.b.inack_ctl._y:=1]
2923705 b.b._en : 1 [by b.in.a:=0]
2923803 b.b.en_buf_f.buf2._y : 0 [by b.b._en:=1]
2929476 b.b.en_buf_t.buf2._y : 0 [by b.b._en:=1]
2933329 b.b._en_X_t[0] : 1 [by b.b.en_buf_t.buf2._y:=0]
2955531 b.b._en_X_f[0] : 1 [by b.b.en_buf_f.buf2._y:=0]
[] Set ack out 0
2955531 b.out.a : 0
2961672 b.b._out_a_B : 1 [by b.out.a:=0]
2961676 b.b.out_a_B_buf_f.buf2._y : 0 [by b.b._out_a_B:=1]
2961681 b.b._out_a_BX_t[0] : 1 [by b.b.out_a_B_buf_f.buf2._y:=0]
2964032 b.b.out_a_B_buf_t.buf2._y : 0 [by b.b._out_a_B:=1]
2964323 b.b._out_a_BX_f[0] : 1 [by b.b.out_a_B_buf_t.buf2._y:=0]

731
test/unit_tests/bd2qdi_5/run/test.prs
View File

@@ -1,731 +0,0 @@
= "GND" "GND"
= "Vdd" "Vdd"
= "Reset" "Reset"
"Reset"->"b._reset_B"-
~("Reset")->"b._reset_B"+
"b.b.reset_bufarray.buf2.a"->"b.b.reset_bufarray.buf2._y"-
~("b.b.reset_bufarray.buf2.a")->"b.b.reset_bufarray.buf2._y"+
"b.b.reset_bufarray.buf2._y"->"b.b.reset_bufarray.buf2.y"-
~("b.b.reset_bufarray.buf2._y")->"b.b.reset_bufarray.buf2.y"+
= "b.b.reset_bufarray.supply.vdd" "b.b.reset_bufarray.buf2.vdd"
= "b.b.reset_bufarray.supply.vss" "b.b.reset_bufarray.buf2.vss"
= "b.b.reset_bufarray.out[0]" "b.b.reset_bufarray.out[4]"
= "b.b.reset_bufarray.out[0]" "b.b.reset_bufarray.out[3]"
= "b.b.reset_bufarray.out[0]" "b.b.reset_bufarray.out[2]"
= "b.b.reset_bufarray.out[0]" "b.b.reset_bufarray.out[1]"
= "b.b.reset_bufarray.out[0]" "b.b.reset_bufarray.buf2.y"
= "b.b.reset_bufarray.in" "b.b.reset_bufarray.buf2.a"
~"b.b.inack_ctl.c1"&~"b.b.inack_ctl.c2"&~"b.b.inack_ctl.c3"|~"b.b.inack_ctl.pr_B"->"b.b.inack_ctl._y"+
"b.b.inack_ctl.c1"&"b.b.inack_ctl.c2"&"b.b.inack_ctl.c3"&"b.b.inack_ctl.sr_B"->"b.b.inack_ctl._y"-
"b.b.inack_ctl._y"->"b.b.inack_ctl.y"-
~("b.b.inack_ctl._y")->"b.b.inack_ctl.y"+
"b.b.dly.and2[0].a"&"b.b.dly.and2[0].b"->"b.b.dly.and2[0]._y"-
~("b.b.dly.and2[0].a"&"b.b.dly.and2[0].b")->"b.b.dly.and2[0]._y"+
"b.b.dly.and2[0]._y"->"b.b.dly.and2[0].y"-
~("b.b.dly.and2[0]._y")->"b.b.dly.and2[0].y"+
"b.b.dly.and2[1].a"&"b.b.dly.and2[1].b"->"b.b.dly.and2[1]._y"-
~("b.b.dly.and2[1].a"&"b.b.dly.and2[1].b")->"b.b.dly.and2[1]._y"+
"b.b.dly.and2[1]._y"->"b.b.dly.and2[1].y"-
~("b.b.dly.and2[1]._y")->"b.b.dly.and2[1].y"+
"b.b.dly.and2[2].a"&"b.b.dly.and2[2].b"->"b.b.dly.and2[2]._y"-
~("b.b.dly.and2[2].a"&"b.b.dly.and2[2].b")->"b.b.dly.and2[2]._y"+
"b.b.dly.and2[2]._y"->"b.b.dly.and2[2].y"-
~("b.b.dly.and2[2]._y")->"b.b.dly.and2[2].y"+
"b.b.dly.and2[3].a"&"b.b.dly.and2[3].b"->"b.b.dly.and2[3]._y"-
~("b.b.dly.and2[3].a"&"b.b.dly.and2[3].b")->"b.b.dly.and2[3]._y"+
"b.b.dly.and2[3]._y"->"b.b.dly.and2[3].y"-
~("b.b.dly.and2[3]._y")->"b.b.dly.and2[3].y"+
= "b.b.dly.s[0]" "b.b.dly.mu2[0].s"
= "b.b.dly.s[0]" "b.b.dly.and2[0].b"
= "b.b.dly.s[1]" "b.b.dly.mu2[1].s"
= "b.b.dly.s[1]" "b.b.dly.and2[1].b"
= "b.b.dly.s[2]" "b.b.dly.mu2[2].s"
= "b.b.dly.s[2]" "b.b.dly.and2[2].b"
= "b.b.dly.s[3]" "b.b.dly.mu2[3].s"
= "b.b.dly.s[3]" "b.b.dly.and2[3].b"
= "b.b.dly.supply.vdd" "b.b.dly.dly[14].vdd"
= "b.b.dly.supply.vdd" "b.b.dly.dly[13].vdd"
= "b.b.dly.supply.vdd" "b.b.dly.dly[12].vdd"
= "b.b.dly.supply.vdd" "b.b.dly.dly[11].vdd"
= "b.b.dly.supply.vdd" "b.b.dly.dly[10].vdd"
= "b.b.dly.supply.vdd" "b.b.dly.dly[9].vdd"
= "b.b.dly.supply.vdd" "b.b.dly.dly[8].vdd"
= "b.b.dly.supply.vdd" "b.b.dly.dly[7].vdd"
= "b.b.dly.supply.vdd" "b.b.dly.dly[6].vdd"
= "b.b.dly.supply.vdd" "b.b.dly.dly[5].vdd"
= "b.b.dly.supply.vdd" "b.b.dly.dly[4].vdd"
= "b.b.dly.supply.vdd" "b.b.dly.dly[3].vdd"
= "b.b.dly.supply.vdd" "b.b.dly.dly[2].vdd"
= "b.b.dly.supply.vdd" "b.b.dly.dly[1].vdd"
= "b.b.dly.supply.vdd" "b.b.dly.dly[0].vdd"
= "b.b.dly.supply.vdd" "b.b.dly.mu2[3].vdd"
= "b.b.dly.supply.vdd" "b.b.dly.mu2[2].vdd"
= "b.b.dly.supply.vdd" "b.b.dly.mu2[1].vdd"
= "b.b.dly.supply.vdd" "b.b.dly.mu2[0].vdd"
= "b.b.dly.supply.vdd" "b.b.dly.and2[3].vdd"
= "b.b.dly.supply.vdd" "b.b.dly.and2[2].vdd"
= "b.b.dly.supply.vdd" "b.b.dly.and2[1].vdd"
= "b.b.dly.supply.vdd" "b.b.dly.and2[0].vdd"
= "b.b.dly.supply.vss" "b.b.dly.dly[14].vss"
= "b.b.dly.supply.vss" "b.b.dly.dly[13].vss"
= "b.b.dly.supply.vss" "b.b.dly.dly[12].vss"
= "b.b.dly.supply.vss" "b.b.dly.dly[11].vss"
= "b.b.dly.supply.vss" "b.b.dly.dly[10].vss"
= "b.b.dly.supply.vss" "b.b.dly.dly[9].vss"
= "b.b.dly.supply.vss" "b.b.dly.dly[8].vss"
= "b.b.dly.supply.vss" "b.b.dly.dly[7].vss"
= "b.b.dly.supply.vss" "b.b.dly.dly[6].vss"
= "b.b.dly.supply.vss" "b.b.dly.dly[5].vss"
= "b.b.dly.supply.vss" "b.b.dly.dly[4].vss"
= "b.b.dly.supply.vss" "b.b.dly.dly[3].vss"
= "b.b.dly.supply.vss" "b.b.dly.dly[2].vss"
= "b.b.dly.supply.vss" "b.b.dly.dly[1].vss"
= "b.b.dly.supply.vss" "b.b.dly.dly[0].vss"
= "b.b.dly.supply.vss" "b.b.dly.mu2[3].vss"
= "b.b.dly.supply.vss" "b.b.dly.mu2[2].vss"
= "b.b.dly.supply.vss" "b.b.dly.mu2[1].vss"
= "b.b.dly.supply.vss" "b.b.dly.mu2[0].vss"
= "b.b.dly.supply.vss" "b.b.dly.and2[3].vss"
= "b.b.dly.supply.vss" "b.b.dly.and2[2].vss"
= "b.b.dly.supply.vss" "b.b.dly.and2[1].vss"
= "b.b.dly.supply.vss" "b.b.dly.and2[0].vss"
"b.b.dly.mu2[0].s"->"b.b.dly.mu2[0]._s"-
~("b.b.dly.mu2[0].s")->"b.b.dly.mu2[0]._s"+
~"b.b.dly.mu2[0].a"&~"b.b.dly.mu2[0].s"|~"b.b.dly.mu2[0].b"&~"b.b.dly.mu2[0]._s"->"b.b.dly.mu2[0]._y"+
"b.b.dly.mu2[0].a"&"b.b.dly.mu2[0]._s"|"b.b.dly.mu2[0].b"&"b.b.dly.mu2[0].s"->"b.b.dly.mu2[0]._y"-
"b.b.dly.mu2[0]._y"->"b.b.dly.mu2[0].y"-
~("b.b.dly.mu2[0]._y")->"b.b.dly.mu2[0].y"+
"b.b.dly.mu2[1].s"->"b.b.dly.mu2[1]._s"-
~("b.b.dly.mu2[1].s")->"b.b.dly.mu2[1]._s"+
~"b.b.dly.mu2[1].a"&~"b.b.dly.mu2[1].s"|~"b.b.dly.mu2[1].b"&~"b.b.dly.mu2[1]._s"->"b.b.dly.mu2[1]._y"+
"b.b.dly.mu2[1].a"&"b.b.dly.mu2[1]._s"|"b.b.dly.mu2[1].b"&"b.b.dly.mu2[1].s"->"b.b.dly.mu2[1]._y"-
"b.b.dly.mu2[1]._y"->"b.b.dly.mu2[1].y"-
~("b.b.dly.mu2[1]._y")->"b.b.dly.mu2[1].y"+
"b.b.dly.mu2[2].s"->"b.b.dly.mu2[2]._s"-
~("b.b.dly.mu2[2].s")->"b.b.dly.mu2[2]._s"+
~"b.b.dly.mu2[2].a"&~"b.b.dly.mu2[2].s"|~"b.b.dly.mu2[2].b"&~"b.b.dly.mu2[2]._s"->"b.b.dly.mu2[2]._y"+
"b.b.dly.mu2[2].a"&"b.b.dly.mu2[2]._s"|"b.b.dly.mu2[2].b"&"b.b.dly.mu2[2].s"->"b.b.dly.mu2[2]._y"-
"b.b.dly.mu2[2]._y"->"b.b.dly.mu2[2].y"-
~("b.b.dly.mu2[2]._y")->"b.b.dly.mu2[2].y"+
"b.b.dly.mu2[3].s"->"b.b.dly.mu2[3]._s"-
~("b.b.dly.mu2[3].s")->"b.b.dly.mu2[3]._s"+
~"b.b.dly.mu2[3].a"&~"b.b.dly.mu2[3].s"|~"b.b.dly.mu2[3].b"&~"b.b.dly.mu2[3]._s"->"b.b.dly.mu2[3]._y"+
"b.b.dly.mu2[3].a"&"b.b.dly.mu2[3]._s"|"b.b.dly.mu2[3].b"&"b.b.dly.mu2[3].s"->"b.b.dly.mu2[3]._y"-
"b.b.dly.mu2[3]._y"->"b.b.dly.mu2[3].y"-
~("b.b.dly.mu2[3]._y")->"b.b.dly.mu2[3].y"+
"b.b.dly.dly[0].a"->"b.b.dly.dly[0]._y"-
~("b.b.dly.dly[0].a")->"b.b.dly.dly[0]._y"+
"b.b.dly.dly[0]._y"->"b.b.dly.dly[0].__y"-
~("b.b.dly.dly[0]._y")->"b.b.dly.dly[0].__y"+
"b.b.dly.dly[0].__y"->"b.b.dly.dly[0].___y"-
~("b.b.dly.dly[0].__y")->"b.b.dly.dly[0].___y"+
"b.b.dly.dly[0].___y"->"b.b.dly.dly[0].y"-
~("b.b.dly.dly[0].___y")->"b.b.dly.dly[0].y"+
"b.b.dly.dly[1].a"->"b.b.dly.dly[1]._y"-
~("b.b.dly.dly[1].a")->"b.b.dly.dly[1]._y"+
"b.b.dly.dly[1]._y"->"b.b.dly.dly[1].__y"-
~("b.b.dly.dly[1]._y")->"b.b.dly.dly[1].__y"+
"b.b.dly.dly[1].__y"->"b.b.dly.dly[1].___y"-
~("b.b.dly.dly[1].__y")->"b.b.dly.dly[1].___y"+
"b.b.dly.dly[1].___y"->"b.b.dly.dly[1].y"-
~("b.b.dly.dly[1].___y")->"b.b.dly.dly[1].y"+
"b.b.dly.dly[2].a"->"b.b.dly.dly[2]._y"-
~("b.b.dly.dly[2].a")->"b.b.dly.dly[2]._y"+
"b.b.dly.dly[2]._y"->"b.b.dly.dly[2].__y"-
~("b.b.dly.dly[2]._y")->"b.b.dly.dly[2].__y"+
"b.b.dly.dly[2].__y"->"b.b.dly.dly[2].___y"-
~("b.b.dly.dly[2].__y")->"b.b.dly.dly[2].___y"+
"b.b.dly.dly[2].___y"->"b.b.dly.dly[2].y"-
~("b.b.dly.dly[2].___y")->"b.b.dly.dly[2].y"+
"b.b.dly.dly[3].a"->"b.b.dly.dly[3]._y"-
~("b.b.dly.dly[3].a")->"b.b.dly.dly[3]._y"+
"b.b.dly.dly[3]._y"->"b.b.dly.dly[3].__y"-
~("b.b.dly.dly[3]._y")->"b.b.dly.dly[3].__y"+
"b.b.dly.dly[3].__y"->"b.b.dly.dly[3].___y"-
~("b.b.dly.dly[3].__y")->"b.b.dly.dly[3].___y"+
"b.b.dly.dly[3].___y"->"b.b.dly.dly[3].y"-
~("b.b.dly.dly[3].___y")->"b.b.dly.dly[3].y"+
"b.b.dly.dly[4].a"->"b.b.dly.dly[4]._y"-
~("b.b.dly.dly[4].a")->"b.b.dly.dly[4]._y"+
"b.b.dly.dly[4]._y"->"b.b.dly.dly[4].__y"-
~("b.b.dly.dly[4]._y")->"b.b.dly.dly[4].__y"+
"b.b.dly.dly[4].__y"->"b.b.dly.dly[4].___y"-
~("b.b.dly.dly[4].__y")->"b.b.dly.dly[4].___y"+
"b.b.dly.dly[4].___y"->"b.b.dly.dly[4].y"-
~("b.b.dly.dly[4].___y")->"b.b.dly.dly[4].y"+
"b.b.dly.dly[5].a"->"b.b.dly.dly[5]._y"-
~("b.b.dly.dly[5].a")->"b.b.dly.dly[5]._y"+
"b.b.dly.dly[5]._y"->"b.b.dly.dly[5].__y"-
~("b.b.dly.dly[5]._y")->"b.b.dly.dly[5].__y"+
"b.b.dly.dly[5].__y"->"b.b.dly.dly[5].___y"-
~("b.b.dly.dly[5].__y")->"b.b.dly.dly[5].___y"+
"b.b.dly.dly[5].___y"->"b.b.dly.dly[5].y"-
~("b.b.dly.dly[5].___y")->"b.b.dly.dly[5].y"+
"b.b.dly.dly[6].a"->"b.b.dly.dly[6]._y"-
~("b.b.dly.dly[6].a")->"b.b.dly.dly[6]._y"+
"b.b.dly.dly[6]._y"->"b.b.dly.dly[6].__y"-
~("b.b.dly.dly[6]._y")->"b.b.dly.dly[6].__y"+
"b.b.dly.dly[6].__y"->"b.b.dly.dly[6].___y"-
~("b.b.dly.dly[6].__y")->"b.b.dly.dly[6].___y"+
"b.b.dly.dly[6].___y"->"b.b.dly.dly[6].y"-
~("b.b.dly.dly[6].___y")->"b.b.dly.dly[6].y"+
"b.b.dly.dly[7].a"->"b.b.dly.dly[7]._y"-
~("b.b.dly.dly[7].a")->"b.b.dly.dly[7]._y"+
"b.b.dly.dly[7]._y"->"b.b.dly.dly[7].__y"-
~("b.b.dly.dly[7]._y")->"b.b.dly.dly[7].__y"+
"b.b.dly.dly[7].__y"->"b.b.dly.dly[7].___y"-
~("b.b.dly.dly[7].__y")->"b.b.dly.dly[7].___y"+
"b.b.dly.dly[7].___y"->"b.b.dly.dly[7].y"-
~("b.b.dly.dly[7].___y")->"b.b.dly.dly[7].y"+
"b.b.dly.dly[8].a"->"b.b.dly.dly[8]._y"-
~("b.b.dly.dly[8].a")->"b.b.dly.dly[8]._y"+
"b.b.dly.dly[8]._y"->"b.b.dly.dly[8].__y"-
~("b.b.dly.dly[8]._y")->"b.b.dly.dly[8].__y"+
"b.b.dly.dly[8].__y"->"b.b.dly.dly[8].___y"-
~("b.b.dly.dly[8].__y")->"b.b.dly.dly[8].___y"+
"b.b.dly.dly[8].___y"->"b.b.dly.dly[8].y"-
~("b.b.dly.dly[8].___y")->"b.b.dly.dly[8].y"+
"b.b.dly.dly[9].a"->"b.b.dly.dly[9]._y"-
~("b.b.dly.dly[9].a")->"b.b.dly.dly[9]._y"+
"b.b.dly.dly[9]._y"->"b.b.dly.dly[9].__y"-
~("b.b.dly.dly[9]._y")->"b.b.dly.dly[9].__y"+
"b.b.dly.dly[9].__y"->"b.b.dly.dly[9].___y"-
~("b.b.dly.dly[9].__y")->"b.b.dly.dly[9].___y"+
"b.b.dly.dly[9].___y"->"b.b.dly.dly[9].y"-
~("b.b.dly.dly[9].___y")->"b.b.dly.dly[9].y"+
"b.b.dly.dly[10].a"->"b.b.dly.dly[10]._y"-
~("b.b.dly.dly[10].a")->"b.b.dly.dly[10]._y"+
"b.b.dly.dly[10]._y"->"b.b.dly.dly[10].__y"-
~("b.b.dly.dly[10]._y")->"b.b.dly.dly[10].__y"+
"b.b.dly.dly[10].__y"->"b.b.dly.dly[10].___y"-
~("b.b.dly.dly[10].__y")->"b.b.dly.dly[10].___y"+
"b.b.dly.dly[10].___y"->"b.b.dly.dly[10].y"-
~("b.b.dly.dly[10].___y")->"b.b.dly.dly[10].y"+
"b.b.dly.dly[11].a"->"b.b.dly.dly[11]._y"-
~("b.b.dly.dly[11].a")->"b.b.dly.dly[11]._y"+
"b.b.dly.dly[11]._y"->"b.b.dly.dly[11].__y"-
~("b.b.dly.dly[11]._y")->"b.b.dly.dly[11].__y"+
"b.b.dly.dly[11].__y"->"b.b.dly.dly[11].___y"-
~("b.b.dly.dly[11].__y")->"b.b.dly.dly[11].___y"+
"b.b.dly.dly[11].___y"->"b.b.dly.dly[11].y"-
~("b.b.dly.dly[11].___y")->"b.b.dly.dly[11].y"+
"b.b.dly.dly[12].a"->"b.b.dly.dly[12]._y"-
~("b.b.dly.dly[12].a")->"b.b.dly.dly[12]._y"+
"b.b.dly.dly[12]._y"->"b.b.dly.dly[12].__y"-
~("b.b.dly.dly[12]._y")->"b.b.dly.dly[12].__y"+
"b.b.dly.dly[12].__y"->"b.b.dly.dly[12].___y"-
~("b.b.dly.dly[12].__y")->"b.b.dly.dly[12].___y"+
"b.b.dly.dly[12].___y"->"b.b.dly.dly[12].y"-
~("b.b.dly.dly[12].___y")->"b.b.dly.dly[12].y"+
"b.b.dly.dly[13].a"->"b.b.dly.dly[13]._y"-
~("b.b.dly.dly[13].a")->"b.b.dly.dly[13]._y"+
"b.b.dly.dly[13]._y"->"b.b.dly.dly[13].__y"-
~("b.b.dly.dly[13]._y")->"b.b.dly.dly[13].__y"+
"b.b.dly.dly[13].__y"->"b.b.dly.dly[13].___y"-
~("b.b.dly.dly[13].__y")->"b.b.dly.dly[13].___y"+
"b.b.dly.dly[13].___y"->"b.b.dly.dly[13].y"-
~("b.b.dly.dly[13].___y")->"b.b.dly.dly[13].y"+
"b.b.dly.dly[14].a"->"b.b.dly.dly[14]._y"-
~("b.b.dly.dly[14].a")->"b.b.dly.dly[14]._y"+
"b.b.dly.dly[14]._y"->"b.b.dly.dly[14].__y"-
~("b.b.dly.dly[14]._y")->"b.b.dly.dly[14].__y"+
"b.b.dly.dly[14].__y"->"b.b.dly.dly[14].___y"-
~("b.b.dly.dly[14].__y")->"b.b.dly.dly[14].___y"+
"b.b.dly.dly[14].___y"->"b.b.dly.dly[14].y"-
~("b.b.dly.dly[14].___y")->"b.b.dly.dly[14].y"+
= "b.b.dly.dly[14].y" "b.b.dly.mu2[3].b"
= "b.b.dly.dly[14].a" "b.b.dly.dly[13].y"
= "b.b.dly.dly[13].a" "b.b.dly.dly[12].y"
= "b.b.dly.dly[12].a" "b.b.dly.dly[11].y"
= "b.b.dly.dly[11].a" "b.b.dly.dly[10].y"
= "b.b.dly.dly[10].a" "b.b.dly.dly[9].y"
= "b.b.dly.dly[9].a" "b.b.dly.dly[8].y"
= "b.b.dly.dly[8].a" "b.b.dly.dly[7].y"
= "b.b.dly.dly[7].a" "b.b.dly.and2[3].y"
= "b.b.dly.dly[6].y" "b.b.dly.mu2[2].b"
= "b.b.dly.dly[6].a" "b.b.dly.dly[5].y"
= "b.b.dly.dly[5].a" "b.b.dly.dly[4].y"
= "b.b.dly.dly[4].a" "b.b.dly.dly[3].y"
= "b.b.dly.dly[3].a" "b.b.dly.and2[2].y"
= "b.b.dly.dly[2].y" "b.b.dly.mu2[1].b"
= "b.b.dly.dly[2].a" "b.b.dly.dly[1].y"
= "b.b.dly.dly[1].a" "b.b.dly.and2[1].y"
= "b.b.dly.dly[0].y" "b.b.dly.mu2[0].b"
= "b.b.dly.dly[0].a" "b.b.dly.and2[0].y"
= "b.b.dly._a[1]" "b.b.dly.mu2[1].a"
= "b.b.dly._a[1]" "b.b.dly.and2[1].a"
= "b.b.dly._a[1]" "b.b.dly.mu2[0].y"
= "b.b.dly._a[2]" "b.b.dly.mu2[2].a"
= "b.b.dly._a[2]" "b.b.dly.and2[2].a"
= "b.b.dly._a[2]" "b.b.dly.mu2[1].y"
= "b.b.dly._a[3]" "b.b.dly.mu2[3].a"
= "b.b.dly._a[3]" "b.b.dly.and2[3].a"
= "b.b.dly._a[3]" "b.b.dly.mu2[2].y"
= "b.b.dly.out" "b.b.dly.mu2[3].y"
= "b.b.dly.out" "b.b.dly._a[4]"
= "b.b.dly.in" "b.b.dly.mu2[0].a"
= "b.b.dly.in" "b.b.dly.and2[0].a"
= "b.b.dly.in" "b.b.dly._a[0]"
= "b.b._out_a_BX_f[0]" "b.b.out_a_B_buf_t.out[0]"
= "b.b._out_a_BX_f[1]" "b.b.out_a_B_buf_t.out[1]"
= "b.b._out_a_BX_f[2]" "b.b.out_a_B_buf_t.out[2]"
= "b.b._out_a_BX_f[3]" "b.b.out_a_B_buf_t.out[3]"
= "b.b._out_a_BX_f[4]" "b.b.out_a_B_buf_t.out[4]"
= "b.b._out_a_BX_f[0]" "b.b.f_buf_func[4].c2"
= "b.b._out_a_BX_f[0]" "b.b.f_buf_func[3].c2"
= "b.b._out_a_BX_f[0]" "b.b.f_buf_func[2].c2"
= "b.b._out_a_BX_f[0]" "b.b.f_buf_func[1].c2"
= "b.b._out_a_BX_f[0]" "b.b.f_buf_func[0].c2"
= "b.b._out_a_BX_f[0]" "b.b._out_a_BX_f[4]"
= "b.b._out_a_BX_f[0]" "b.b._out_a_BX_f[3]"
= "b.b._out_a_BX_f[0]" "b.b._out_a_BX_f[2]"
= "b.b._out_a_BX_f[0]" "b.b._out_a_BX_f[1]"
"b.b.out_a_inv.a"->"b.b.out_a_inv.y"-
~("b.b.out_a_inv.a")->"b.b.out_a_inv.y"+
= "b.b._en" "b.b.en_buf_f.in"
= "b.b._en" "b.b.en_buf_t.in"
= "b.b._en" "b.b.en_ctl.y"
= "b.b._en" "b.b.inack_ctl.c1"
timing("b.b.in.a"-,"b.b.in.d[0]","b.b.in.r"+)
timing("b.b.in.a"-,"b.b.in.d[1]","b.b.in.r"+)
timing("b.b.in.a"-,"b.b.in.d[2]","b.b.in.r"+)
timing("b.b.in.a"-,"b.b.in.d[3]","b.b.in.r"+)
timing("b.b.in.a"-,"b.b.in.d[4]","b.b.in.r"+)
= "b.b.in.r" "b.b.dly.in"
= "b.b.in.a" "b.b.en_ctl.c1"
= "b.b.in.a" "b.b.inack_ctl.y"
= "b.b.in.d[0]" "b.b.t_buf_func[0].n1"
= "b.b.in.d[0]" "b.b.input_invs[0].a"
= "b.b.in.d[1]" "b.b.t_buf_func[1].n1"
= "b.b.in.d[1]" "b.b.input_invs[1].a"
= "b.b.in.d[2]" "b.b.t_buf_func[2].n1"
= "b.b.in.d[2]" "b.b.input_invs[2].a"
= "b.b.in.d[3]" "b.b.t_buf_func[3].n1"
= "b.b.in.d[3]" "b.b.input_invs[3].a"
= "b.b.in.d[4]" "b.b.t_buf_func[4].n1"
= "b.b.in.d[4]" "b.b.input_invs[4].a"
= "b.b._inB[0]" "b.b.f_buf_func[0].n1"
= "b.b._inB[0]" "b.b.input_invs[0].y"
= "b.b._inB[1]" "b.b.f_buf_func[1].n1"
= "b.b._inB[1]" "b.b.input_invs[1].y"
= "b.b._inB[2]" "b.b.f_buf_func[2].n1"
= "b.b._inB[2]" "b.b.input_invs[2].y"
= "b.b._inB[3]" "b.b.f_buf_func[3].n1"
= "b.b._inB[3]" "b.b.input_invs[3].y"
= "b.b._inB[4]" "b.b.f_buf_func[4].n1"
= "b.b._inB[4]" "b.b.input_invs[4].y"
"b.b.reset_buf.a"->"b.b.reset_buf._y"-
~("b.b.reset_buf.a")->"b.b.reset_buf._y"+
"b.b.reset_buf._y"->"b.b.reset_buf.y"-
~("b.b.reset_buf._y")->"b.b.reset_buf.y"+
= "b.b._reset_BX" "b.b.inack_ctl.sr_B"
= "b.b._reset_BX" "b.b.inack_ctl.pr_B"
= "b.b._reset_BX" "b.b.reset_bufarray.in"
= "b.b._reset_BX" "b.b.reset_buf.y"
= "b.b.reset_B" "b.b.reset_buf.a"
= "b.b._out_a_BX_t[0]" "b.b.out_a_B_buf_f.out[0]"
= "b.b._out_a_BX_t[1]" "b.b.out_a_B_buf_f.out[1]"
= "b.b._out_a_BX_t[2]" "b.b.out_a_B_buf_f.out[2]"
= "b.b._out_a_BX_t[3]" "b.b.out_a_B_buf_f.out[3]"
= "b.b._out_a_BX_t[4]" "b.b.out_a_B_buf_f.out[4]"
= "b.b._out_a_BX_t[0]" "b.b.t_buf_func[4].c2"
= "b.b._out_a_BX_t[0]" "b.b.t_buf_func[3].c2"
= "b.b._out_a_BX_t[0]" "b.b.t_buf_func[2].c2"
= "b.b._out_a_BX_t[0]" "b.b.t_buf_func[1].c2"
= "b.b._out_a_BX_t[0]" "b.b.t_buf_func[0].c2"
= "b.b._out_a_BX_t[0]" "b.b._out_a_BX_t[4]"
= "b.b._out_a_BX_t[0]" "b.b._out_a_BX_t[3]"
= "b.b._out_a_BX_t[0]" "b.b._out_a_BX_t[2]"
= "b.b._out_a_BX_t[0]" "b.b._out_a_BX_t[1]"
= "b.b._reset_BXX[0]" "b.b.reset_bufarray.out[0]"
= "b.b._reset_BXX[1]" "b.b.reset_bufarray.out[1]"
= "b.b._reset_BXX[2]" "b.b.reset_bufarray.out[2]"
= "b.b._reset_BXX[3]" "b.b.reset_bufarray.out[3]"
= "b.b._reset_BXX[4]" "b.b.reset_bufarray.out[4]"
= "b.b._reset_BXX[0]" "b.b.f_buf_func[4].sr_B"
= "b.b._reset_BXX[0]" "b.b.f_buf_func[4].pr_B"
= "b.b._reset_BXX[0]" "b.b.t_buf_func[4].sr_B"
= "b.b._reset_BXX[0]" "b.b.t_buf_func[4].pr_B"
= "b.b._reset_BXX[0]" "b.b.f_buf_func[3].sr_B"
= "b.b._reset_BXX[0]" "b.b.f_buf_func[3].pr_B"
= "b.b._reset_BXX[0]" "b.b.t_buf_func[3].sr_B"
= "b.b._reset_BXX[0]" "b.b.t_buf_func[3].pr_B"
= "b.b._reset_BXX[0]" "b.b.f_buf_func[2].sr_B"
= "b.b._reset_BXX[0]" "b.b.f_buf_func[2].pr_B"
= "b.b._reset_BXX[0]" "b.b.t_buf_func[2].sr_B"
= "b.b._reset_BXX[0]" "b.b.t_buf_func[2].pr_B"
= "b.b._reset_BXX[0]" "b.b.f_buf_func[1].sr_B"
= "b.b._reset_BXX[0]" "b.b.f_buf_func[1].pr_B"
= "b.b._reset_BXX[0]" "b.b.t_buf_func[1].sr_B"
= "b.b._reset_BXX[0]" "b.b.t_buf_func[1].pr_B"
= "b.b._reset_BXX[0]" "b.b.f_buf_func[0].sr_B"
= "b.b._reset_BXX[0]" "b.b.f_buf_func[0].pr_B"
= "b.b._reset_BXX[0]" "b.b.t_buf_func[0].sr_B"
= "b.b._reset_BXX[0]" "b.b.t_buf_func[0].pr_B"
= "b.b._reset_BXX[0]" "b.b._reset_BXX[4]"
= "b.b._reset_BXX[0]" "b.b._reset_BXX[3]"
= "b.b._reset_BXX[0]" "b.b._reset_BXX[2]"
= "b.b._reset_BXX[0]" "b.b._reset_BXX[1]"
"b.b.en_buf_f.buf2.a"->"b.b.en_buf_f.buf2._y"-
~("b.b.en_buf_f.buf2.a")->"b.b.en_buf_f.buf2._y"+
"b.b.en_buf_f.buf2._y"->"b.b.en_buf_f.buf2.y"-
~("b.b.en_buf_f.buf2._y")->"b.b.en_buf_f.buf2.y"+
= "b.b.en_buf_f.supply.vdd" "b.b.en_buf_f.buf2.vdd"
= "b.b.en_buf_f.supply.vss" "b.b.en_buf_f.buf2.vss"
= "b.b.en_buf_f.out[0]" "b.b.en_buf_f.out[4]"
= "b.b.en_buf_f.out[0]" "b.b.en_buf_f.out[3]"
= "b.b.en_buf_f.out[0]" "b.b.en_buf_f.out[2]"
= "b.b.en_buf_f.out[0]" "b.b.en_buf_f.out[1]"
= "b.b.en_buf_f.out[0]" "b.b.en_buf_f.buf2.y"
= "b.b.en_buf_f.in" "b.b.en_buf_f.buf2.a"
"b.b.input_invs[0].a"->"b.b.input_invs[0].y"-
~("b.b.input_invs[0].a")->"b.b.input_invs[0].y"+
"b.b.input_invs[1].a"->"b.b.input_invs[1].y"-
~("b.b.input_invs[1].a")->"b.b.input_invs[1].y"+
"b.b.input_invs[2].a"->"b.b.input_invs[2].y"-
~("b.b.input_invs[2].a")->"b.b.input_invs[2].y"+
"b.b.input_invs[3].a"->"b.b.input_invs[3].y"-
~("b.b.input_invs[3].a")->"b.b.input_invs[3].y"+
"b.b.input_invs[4].a"->"b.b.input_invs[4].y"-
~("b.b.input_invs[4].a")->"b.b.input_invs[4].y"+
"b.b.out_a_B_buf_t.buf2.a"->"b.b.out_a_B_buf_t.buf2._y"-
~("b.b.out_a_B_buf_t.buf2.a")->"b.b.out_a_B_buf_t.buf2._y"+
"b.b.out_a_B_buf_t.buf2._y"->"b.b.out_a_B_buf_t.buf2.y"-
~("b.b.out_a_B_buf_t.buf2._y")->"b.b.out_a_B_buf_t.buf2.y"+
= "b.b.out_a_B_buf_t.supply.vdd" "b.b.out_a_B_buf_t.buf2.vdd"
= "b.b.out_a_B_buf_t.supply.vss" "b.b.out_a_B_buf_t.buf2.vss"
= "b.b.out_a_B_buf_t.out[0]" "b.b.out_a_B_buf_t.out[4]"
= "b.b.out_a_B_buf_t.out[0]" "b.b.out_a_B_buf_t.out[3]"
= "b.b.out_a_B_buf_t.out[0]" "b.b.out_a_B_buf_t.out[2]"
= "b.b.out_a_B_buf_t.out[0]" "b.b.out_a_B_buf_t.out[1]"
= "b.b.out_a_B_buf_t.out[0]" "b.b.out_a_B_buf_t.buf2.y"
= "b.b.out_a_B_buf_t.in" "b.b.out_a_B_buf_t.buf2.a"
= "b.b._en_X_f[0]" "b.b.en_buf_f.out[0]"
= "b.b._en_X_f[1]" "b.b.en_buf_f.out[1]"
= "b.b._en_X_f[2]" "b.b.en_buf_f.out[2]"
= "b.b._en_X_f[3]" "b.b.en_buf_f.out[3]"
= "b.b._en_X_f[4]" "b.b.en_buf_f.out[4]"
= "b.b._en_X_f[0]" "b.b.f_buf_func[4].c1"
= "b.b._en_X_f[0]" "b.b.f_buf_func[3].c1"
= "b.b._en_X_f[0]" "b.b.f_buf_func[2].c1"
= "b.b._en_X_f[0]" "b.b.f_buf_func[1].c1"
= "b.b._en_X_f[0]" "b.b.f_buf_func[0].c1"
= "b.b._en_X_f[0]" "b.b._en_X_f[4]"
= "b.b._en_X_f[0]" "b.b._en_X_f[3]"
= "b.b._en_X_f[0]" "b.b._en_X_f[2]"
= "b.b._en_X_f[0]" "b.b._en_X_f[1]"
= "b.b.dly_cfg[0]" "b.b.dly.s[0]"
= "b.b.dly_cfg[1]" "b.b.dly.s[1]"
= "b.b.dly_cfg[2]" "b.b.dly.s[2]"
= "b.b.dly_cfg[3]" "b.b.dly.s[3]"
= "b.b.supply.vss" "b.b.out_a_B_buf_t.supply.vss"
= "b.b.supply.vdd" "b.b.out_a_B_buf_t.supply.vdd"
= "b.b.supply.vss" "b.b.out_a_B_buf_f.supply.vss"
= "b.b.supply.vdd" "b.b.out_a_B_buf_f.supply.vdd"
= "b.b.supply.vss" "b.b.en_buf_f.supply.vss"
= "b.b.supply.vdd" "b.b.en_buf_f.supply.vdd"
= "b.b.supply.vss" "b.b.en_buf_t.supply.vss"
= "b.b.supply.vdd" "b.b.en_buf_t.supply.vdd"
= "b.b.supply.vss" "b.b.req_bufarray.supply.vss"
= "b.b.supply.vdd" "b.b.req_bufarray.supply.vdd"
= "b.b.supply.vss" "b.b.reset_bufarray.supply.vss"
= "b.b.supply.vdd" "b.b.reset_bufarray.supply.vdd"
= "b.b.supply.vss" "b.b.dly.supply.vss"
= "b.b.supply.vdd" "b.b.dly.supply.vdd"
= "b.b.supply.vdd" "b.b.t_buf_func[4].vdd"
= "b.b.supply.vdd" "b.b.f_buf_func[4].vdd"
= "b.b.supply.vdd" "b.b.t_buf_func[3].vdd"
= "b.b.supply.vdd" "b.b.f_buf_func[3].vdd"
= "b.b.supply.vdd" "b.b.t_buf_func[2].vdd"
= "b.b.supply.vdd" "b.b.f_buf_func[2].vdd"
= "b.b.supply.vdd" "b.b.t_buf_func[1].vdd"
= "b.b.supply.vdd" "b.b.f_buf_func[1].vdd"
= "b.b.supply.vdd" "b.b.t_buf_func[0].vdd"
= "b.b.supply.vdd" "b.b.f_buf_func[0].vdd"
= "b.b.supply.vdd" "b.b.out_a_inv.vdd"
= "b.b.supply.vdd" "b.b.en_ctl.vdd"
= "b.b.supply.vdd" "b.b.inack_ctl.vdd"
= "b.b.supply.vdd" "b.b.input_invs[4].vdd"
= "b.b.supply.vdd" "b.b.input_invs[3].vdd"
= "b.b.supply.vdd" "b.b.input_invs[2].vdd"
= "b.b.supply.vdd" "b.b.input_invs[1].vdd"
= "b.b.supply.vdd" "b.b.input_invs[0].vdd"
= "b.b.supply.vdd" "b.b.req_buf.vdd"
= "b.b.supply.vdd" "b.b.reset_buf.vdd"
= "b.b.supply.vss" "b.b.t_buf_func[4].vss"
= "b.b.supply.vss" "b.b.f_buf_func[4].vss"
= "b.b.supply.vss" "b.b.t_buf_func[3].vss"
= "b.b.supply.vss" "b.b.f_buf_func[3].vss"
= "b.b.supply.vss" "b.b.t_buf_func[2].vss"
= "b.b.supply.vss" "b.b.f_buf_func[2].vss"
= "b.b.supply.vss" "b.b.t_buf_func[1].vss"
= "b.b.supply.vss" "b.b.f_buf_func[1].vss"
= "b.b.supply.vss" "b.b.t_buf_func[0].vss"
= "b.b.supply.vss" "b.b.f_buf_func[0].vss"
= "b.b.supply.vss" "b.b.out_a_inv.vss"
= "b.b.supply.vss" "b.b.en_ctl.vss"
= "b.b.supply.vss" "b.b.inack_ctl.vss"
= "b.b.supply.vss" "b.b.input_invs[4].vss"
= "b.b.supply.vss" "b.b.input_invs[3].vss"
= "b.b.supply.vss" "b.b.input_invs[2].vss"
= "b.b.supply.vss" "b.b.input_invs[1].vss"
= "b.b.supply.vss" "b.b.input_invs[0].vss"
= "b.b.supply.vss" "b.b.req_buf.vss"
= "b.b.supply.vss" "b.b.reset_buf.vss"
~"b.b.en_ctl.p1"&~"b.b.en_ctl.c1"->"b.b.en_ctl.y"+
"b.b.en_ctl.c1"->"b.b.en_ctl.y"-
"b.b.out_a_B_buf_f.buf2.a"->"b.b.out_a_B_buf_f.buf2._y"-
~("b.b.out_a_B_buf_f.buf2.a")->"b.b.out_a_B_buf_f.buf2._y"+
"b.b.out_a_B_buf_f.buf2._y"->"b.b.out_a_B_buf_f.buf2.y"-
~("b.b.out_a_B_buf_f.buf2._y")->"b.b.out_a_B_buf_f.buf2.y"+
= "b.b.out_a_B_buf_f.supply.vdd" "b.b.out_a_B_buf_f.buf2.vdd"
= "b.b.out_a_B_buf_f.supply.vss" "b.b.out_a_B_buf_f.buf2.vss"
= "b.b.out_a_B_buf_f.out[0]" "b.b.out_a_B_buf_f.out[4]"
= "b.b.out_a_B_buf_f.out[0]" "b.b.out_a_B_buf_f.out[3]"
= "b.b.out_a_B_buf_f.out[0]" "b.b.out_a_B_buf_f.out[2]"
= "b.b.out_a_B_buf_f.out[0]" "b.b.out_a_B_buf_f.out[1]"
= "b.b.out_a_B_buf_f.out[0]" "b.b.out_a_B_buf_f.buf2.y"
= "b.b.out_a_B_buf_f.in" "b.b.out_a_B_buf_f.buf2.a"
= "b.b.out.d.d[0].d[0]" "b.b.out.d.d[0].f"
= "b.b.out.d.d[0].d[1]" "b.b.out.d.d[0].t"
= "b.b.out.d.d[1].d[0]" "b.b.out.d.d[1].f"
= "b.b.out.d.d[1].d[1]" "b.b.out.d.d[1].t"
= "b.b.out.d.d[2].d[0]" "b.b.out.d.d[2].f"
= "b.b.out.d.d[2].d[1]" "b.b.out.d.d[2].t"
= "b.b.out.d.d[3].d[0]" "b.b.out.d.d[3].f"
= "b.b.out.d.d[3].d[1]" "b.b.out.d.d[3].t"
= "b.b.out.d.d[4].d[0]" "b.b.out.d.d[4].f"
= "b.b.out.d.d[4].d[1]" "b.b.out.d.d[4].t"
= "b.b.out.d.d[4].d[0]" "b.b.out.d.d[4].f"
= "b.b.out.d.d[4].d[1]" "b.b.out.d.d[4].t"
= "b.b.out.d.d[3].d[0]" "b.b.out.d.d[3].f"
= "b.b.out.d.d[3].d[1]" "b.b.out.d.d[3].t"
= "b.b.out.d.d[2].d[0]" "b.b.out.d.d[2].f"
= "b.b.out.d.d[2].d[1]" "b.b.out.d.d[2].t"
= "b.b.out.d.d[1].d[0]" "b.b.out.d.d[1].f"
= "b.b.out.d.d[1].d[1]" "b.b.out.d.d[1].t"
= "b.b.out.d.d[0].d[0]" "b.b.out.d.d[0].f"
= "b.b.out.d.d[0].d[1]" "b.b.out.d.d[0].t"
= "b.b.out.d.d[4].d[0]" "b.b.out.d.d[4].f"
= "b.b.out.d.d[4].d[1]" "b.b.out.d.d[4].t"
= "b.b.out.d.d[3].d[0]" "b.b.out.d.d[3].f"
= "b.b.out.d.d[3].d[1]" "b.b.out.d.d[3].t"
= "b.b.out.d.d[2].d[0]" "b.b.out.d.d[2].f"
= "b.b.out.d.d[2].d[1]" "b.b.out.d.d[2].t"
= "b.b.out.d.d[1].d[0]" "b.b.out.d.d[1].f"
= "b.b.out.d.d[1].d[1]" "b.b.out.d.d[1].t"
= "b.b.out.d.d[0].d[0]" "b.b.out.d.d[0].f"
= "b.b.out.d.d[0].d[1]" "b.b.out.d.d[0].t"
= "b.b.out.a" "b.b.out_a_inv.a"
= "b.b.out.v" "b.b.en_ctl.p1"
= "b.b.out.v" "b.b.inack_ctl.c3"
= "b.b.out.d.d[4].d[0]" "b.b.f_buf_func[4].y"
= "b.b.out.d.d[4].d[0]" "b.b.out.d.d[4].f"
= "b.b.out.d.d[4].d[1]" "b.b.t_buf_func[4].y"
= "b.b.out.d.d[4].d[1]" "b.b.out.d.d[4].t"
= "b.b.out.d.d[3].d[0]" "b.b.f_buf_func[3].y"
= "b.b.out.d.d[3].d[0]" "b.b.out.d.d[3].f"
= "b.b.out.d.d[3].d[1]" "b.b.t_buf_func[3].y"
= "b.b.out.d.d[3].d[1]" "b.b.out.d.d[3].t"
= "b.b.out.d.d[2].d[0]" "b.b.f_buf_func[2].y"
= "b.b.out.d.d[2].d[0]" "b.b.out.d.d[2].f"
= "b.b.out.d.d[2].d[1]" "b.b.t_buf_func[2].y"
= "b.b.out.d.d[2].d[1]" "b.b.out.d.d[2].t"
= "b.b.out.d.d[1].d[0]" "b.b.f_buf_func[1].y"
= "b.b.out.d.d[1].d[0]" "b.b.out.d.d[1].f"
= "b.b.out.d.d[1].d[1]" "b.b.t_buf_func[1].y"
= "b.b.out.d.d[1].d[1]" "b.b.out.d.d[1].t"
= "b.b.out.d.d[0].d[0]" "b.b.f_buf_func[0].y"
= "b.b.out.d.d[0].d[0]" "b.b.out.d.d[0].f"
= "b.b.out.d.d[0].d[1]" "b.b.t_buf_func[0].y"
= "b.b.out.d.d[0].d[1]" "b.b.out.d.d[0].t"
= "b.b._reqXX[0]" "b.b.req_bufarray.out[0]"
= "b.b._reqXX[1]" "b.b.req_bufarray.out[1]"
= "b.b._reqXX[2]" "b.b.req_bufarray.out[2]"
= "b.b._reqXX[3]" "b.b.req_bufarray.out[3]"
= "b.b._reqXX[4]" "b.b.req_bufarray.out[4]"
= "b.b._reqXX[0]" "b.b.t_buf_func[4].n2"
= "b.b._reqXX[0]" "b.b.f_buf_func[4].n2"
= "b.b._reqXX[0]" "b.b.t_buf_func[3].n2"
= "b.b._reqXX[0]" "b.b.f_buf_func[3].n2"
= "b.b._reqXX[0]" "b.b.t_buf_func[2].n2"
= "b.b._reqXX[0]" "b.b.f_buf_func[2].n2"
= "b.b._reqXX[0]" "b.b.t_buf_func[1].n2"
= "b.b._reqXX[0]" "b.b.f_buf_func[1].n2"
= "b.b._reqXX[0]" "b.b.t_buf_func[0].n2"
= "b.b._reqXX[0]" "b.b.f_buf_func[0].n2"
= "b.b._reqXX[0]" "b.b._reqXX[4]"
= "b.b._reqXX[0]" "b.b._reqXX[3]"
= "b.b._reqXX[0]" "b.b._reqXX[2]"
= "b.b._reqXX[0]" "b.b._reqXX[1]"
= "b.b._req" "b.b.req_buf.a"
= "b.b._req" "b.b.dly.out"
"b.b.req_bufarray.buf2.a"->"b.b.req_bufarray.buf2._y"-
~("b.b.req_bufarray.buf2.a")->"b.b.req_bufarray.buf2._y"+
"b.b.req_bufarray.buf2._y"->"b.b.req_bufarray.buf2.y"-
~("b.b.req_bufarray.buf2._y")->"b.b.req_bufarray.buf2.y"+
= "b.b.req_bufarray.supply.vdd" "b.b.req_bufarray.buf2.vdd"
= "b.b.req_bufarray.supply.vss" "b.b.req_bufarray.buf2.vss"
= "b.b.req_bufarray.out[0]" "b.b.req_bufarray.out[4]"
= "b.b.req_bufarray.out[0]" "b.b.req_bufarray.out[3]"
= "b.b.req_bufarray.out[0]" "b.b.req_bufarray.out[2]"
= "b.b.req_bufarray.out[0]" "b.b.req_bufarray.out[1]"
= "b.b.req_bufarray.out[0]" "b.b.req_bufarray.buf2.y"
= "b.b.req_bufarray.in" "b.b.req_bufarray.buf2.a"
= "b.b._reqX" "b.b.inack_ctl.c2"
= "b.b._reqX" "b.b.req_bufarray.in"
= "b.b._reqX" "b.b.req_buf.y"
= "b.b._out_a_B" "b.b.out_a_B_buf_t.in"
= "b.b._out_a_B" "b.b.out_a_B_buf_f.in"
= "b.b._out_a_B" "b.b.out_a_inv.y"
"b.b.en_buf_t.buf2.a"->"b.b.en_buf_t.buf2._y"-
~("b.b.en_buf_t.buf2.a")->"b.b.en_buf_t.buf2._y"+
"b.b.en_buf_t.buf2._y"->"b.b.en_buf_t.buf2.y"-
~("b.b.en_buf_t.buf2._y")->"b.b.en_buf_t.buf2.y"+
= "b.b.en_buf_t.supply.vdd" "b.b.en_buf_t.buf2.vdd"
= "b.b.en_buf_t.supply.vss" "b.b.en_buf_t.buf2.vss"
= "b.b.en_buf_t.out[0]" "b.b.en_buf_t.out[4]"
= "b.b.en_buf_t.out[0]" "b.b.en_buf_t.out[3]"
= "b.b.en_buf_t.out[0]" "b.b.en_buf_t.out[2]"
= "b.b.en_buf_t.out[0]" "b.b.en_buf_t.out[1]"
= "b.b.en_buf_t.out[0]" "b.b.en_buf_t.buf2.y"
= "b.b.en_buf_t.in" "b.b.en_buf_t.buf2.a"
"b.b.req_buf.a"->"b.b.req_buf._y"-
~("b.b.req_buf.a")->"b.b.req_buf._y"+
"b.b.req_buf._y"->"b.b.req_buf.y"-
~("b.b.req_buf._y")->"b.b.req_buf.y"+
= "b.b._en_X_t[0]" "b.b.en_buf_t.out[0]"
= "b.b._en_X_t[1]" "b.b.en_buf_t.out[1]"
= "b.b._en_X_t[2]" "b.b.en_buf_t.out[2]"
= "b.b._en_X_t[3]" "b.b.en_buf_t.out[3]"
= "b.b._en_X_t[4]" "b.b.en_buf_t.out[4]"
= "b.b._en_X_t[0]" "b.b.t_buf_func[4].c1"
= "b.b._en_X_t[0]" "b.b.t_buf_func[3].c1"
= "b.b._en_X_t[0]" "b.b.t_buf_func[2].c1"
= "b.b._en_X_t[0]" "b.b.t_buf_func[1].c1"
= "b.b._en_X_t[0]" "b.b.t_buf_func[0].c1"
= "b.b._en_X_t[0]" "b.b._en_X_t[4]"
= "b.b._en_X_t[0]" "b.b._en_X_t[3]"
= "b.b._en_X_t[0]" "b.b._en_X_t[2]"
= "b.b._en_X_t[0]" "b.b._en_X_t[1]"
~"b.b.f_buf_func[0].c1"&~"b.b.f_buf_func[0].c2"|~"b.b.f_buf_func[0].pr_B"->"b.b.f_buf_func[0]._y"+
"b.b.f_buf_func[0].c1"&"b.b.f_buf_func[0].c2"&"b.b.f_buf_func[0].n1"&"b.b.f_buf_func[0].n2"&"b.b.f_buf_func[0].sr_B"->"b.b.f_buf_func[0]._y"-
"b.b.f_buf_func[0]._y"->"b.b.f_buf_func[0].y"-
~("b.b.f_buf_func[0]._y")->"b.b.f_buf_func[0].y"+
~"b.b.f_buf_func[1].c1"&~"b.b.f_buf_func[1].c2"|~"b.b.f_buf_func[1].pr_B"->"b.b.f_buf_func[1]._y"+
"b.b.f_buf_func[1].c1"&"b.b.f_buf_func[1].c2"&"b.b.f_buf_func[1].n1"&"b.b.f_buf_func[1].n2"&"b.b.f_buf_func[1].sr_B"->"b.b.f_buf_func[1]._y"-
"b.b.f_buf_func[1]._y"->"b.b.f_buf_func[1].y"-
~("b.b.f_buf_func[1]._y")->"b.b.f_buf_func[1].y"+
~"b.b.f_buf_func[2].c1"&~"b.b.f_buf_func[2].c2"|~"b.b.f_buf_func[2].pr_B"->"b.b.f_buf_func[2]._y"+
"b.b.f_buf_func[2].c1"&"b.b.f_buf_func[2].c2"&"b.b.f_buf_func[2].n1"&"b.b.f_buf_func[2].n2"&"b.b.f_buf_func[2].sr_B"->"b.b.f_buf_func[2]._y"-
"b.b.f_buf_func[2]._y"->"b.b.f_buf_func[2].y"-
~("b.b.f_buf_func[2]._y")->"b.b.f_buf_func[2].y"+
~"b.b.f_buf_func[3].c1"&~"b.b.f_buf_func[3].c2"|~"b.b.f_buf_func[3].pr_B"->"b.b.f_buf_func[3]._y"+
"b.b.f_buf_func[3].c1"&"b.b.f_buf_func[3].c2"&"b.b.f_buf_func[3].n1"&"b.b.f_buf_func[3].n2"&"b.b.f_buf_func[3].sr_B"->"b.b.f_buf_func[3]._y"-
"b.b.f_buf_func[3]._y"->"b.b.f_buf_func[3].y"-
~("b.b.f_buf_func[3]._y")->"b.b.f_buf_func[3].y"+
~"b.b.f_buf_func[4].c1"&~"b.b.f_buf_func[4].c2"|~"b.b.f_buf_func[4].pr_B"->"b.b.f_buf_func[4]._y"+
"b.b.f_buf_func[4].c1"&"b.b.f_buf_func[4].c2"&"b.b.f_buf_func[4].n1"&"b.b.f_buf_func[4].n2"&"b.b.f_buf_func[4].sr_B"->"b.b.f_buf_func[4]._y"-
"b.b.f_buf_func[4]._y"->"b.b.f_buf_func[4].y"-
~("b.b.f_buf_func[4]._y")->"b.b.f_buf_func[4].y"+
~"b.b.t_buf_func[0].c1"&~"b.b.t_buf_func[0].c2"|~"b.b.t_buf_func[0].pr_B"->"b.b.t_buf_func[0]._y"+
"b.b.t_buf_func[0].c1"&"b.b.t_buf_func[0].c2"&"b.b.t_buf_func[0].n1"&"b.b.t_buf_func[0].n2"&"b.b.t_buf_func[0].sr_B"->"b.b.t_buf_func[0]._y"-
"b.b.t_buf_func[0]._y"->"b.b.t_buf_func[0].y"-
~("b.b.t_buf_func[0]._y")->"b.b.t_buf_func[0].y"+
~"b.b.t_buf_func[1].c1"&~"b.b.t_buf_func[1].c2"|~"b.b.t_buf_func[1].pr_B"->"b.b.t_buf_func[1]._y"+
"b.b.t_buf_func[1].c1"&"b.b.t_buf_func[1].c2"&"b.b.t_buf_func[1].n1"&"b.b.t_buf_func[1].n2"&"b.b.t_buf_func[1].sr_B"->"b.b.t_buf_func[1]._y"-
"b.b.t_buf_func[1]._y"->"b.b.t_buf_func[1].y"-
~("b.b.t_buf_func[1]._y")->"b.b.t_buf_func[1].y"+
~"b.b.t_buf_func[2].c1"&~"b.b.t_buf_func[2].c2"|~"b.b.t_buf_func[2].pr_B"->"b.b.t_buf_func[2]._y"+
"b.b.t_buf_func[2].c1"&"b.b.t_buf_func[2].c2"&"b.b.t_buf_func[2].n1"&"b.b.t_buf_func[2].n2"&"b.b.t_buf_func[2].sr_B"->"b.b.t_buf_func[2]._y"-
"b.b.t_buf_func[2]._y"->"b.b.t_buf_func[2].y"-
~("b.b.t_buf_func[2]._y")->"b.b.t_buf_func[2].y"+
~"b.b.t_buf_func[3].c1"&~"b.b.t_buf_func[3].c2"|~"b.b.t_buf_func[3].pr_B"->"b.b.t_buf_func[3]._y"+
"b.b.t_buf_func[3].c1"&"b.b.t_buf_func[3].c2"&"b.b.t_buf_func[3].n1"&"b.b.t_buf_func[3].n2"&"b.b.t_buf_func[3].sr_B"->"b.b.t_buf_func[3]._y"-
"b.b.t_buf_func[3]._y"->"b.b.t_buf_func[3].y"-
~("b.b.t_buf_func[3]._y")->"b.b.t_buf_func[3].y"+
~"b.b.t_buf_func[4].c1"&~"b.b.t_buf_func[4].c2"|~"b.b.t_buf_func[4].pr_B"->"b.b.t_buf_func[4]._y"+
"b.b.t_buf_func[4].c1"&"b.b.t_buf_func[4].c2"&"b.b.t_buf_func[4].n1"&"b.b.t_buf_func[4].n2"&"b.b.t_buf_func[4].sr_B"->"b.b.t_buf_func[4]._y"-
"b.b.t_buf_func[4]._y"->"b.b.t_buf_func[4].y"-
~("b.b.t_buf_func[4]._y")->"b.b.t_buf_func[4].y"+
= "Vdd" "b.b.supply.vdd"
= "GND" "b.b.supply.vss"
= "b._reset_B" "b.b.reset_B"
= "b.dly_cfg[0]" "b.b.dly_cfg[0]"
= "b.dly_cfg[1]" "b.b.dly_cfg[1]"
= "b.dly_cfg[2]" "b.b.dly_cfg[2]"
= "b.dly_cfg[3]" "b.b.dly_cfg[3]"
= "b.out.d.d[0].d[0]" "b.out.d.d[0].f"
= "b.out.d.d[0].d[1]" "b.out.d.d[0].t"
= "b.out.d.d[1].d[0]" "b.out.d.d[1].f"
= "b.out.d.d[1].d[1]" "b.out.d.d[1].t"
= "b.out.d.d[2].d[0]" "b.out.d.d[2].f"
= "b.out.d.d[2].d[1]" "b.out.d.d[2].t"
= "b.out.d.d[3].d[0]" "b.out.d.d[3].f"
= "b.out.d.d[3].d[1]" "b.out.d.d[3].t"
= "b.out.d.d[4].d[0]" "b.out.d.d[4].f"
= "b.out.d.d[4].d[1]" "b.out.d.d[4].t"
= "b.out.d.d[4].d[0]" "b.out.d.d[4].f"
= "b.out.d.d[4].d[1]" "b.out.d.d[4].t"
= "b.out.d.d[3].d[0]" "b.out.d.d[3].f"
= "b.out.d.d[3].d[1]" "b.out.d.d[3].t"
= "b.out.d.d[2].d[0]" "b.out.d.d[2].f"
= "b.out.d.d[2].d[1]" "b.out.d.d[2].t"
= "b.out.d.d[1].d[0]" "b.out.d.d[1].f"
= "b.out.d.d[1].d[1]" "b.out.d.d[1].t"
= "b.out.d.d[0].d[0]" "b.out.d.d[0].f"
= "b.out.d.d[0].d[1]" "b.out.d.d[0].t"
= "b.out.d.d[4].d[0]" "b.out.d.d[4].f"
= "b.out.d.d[4].d[1]" "b.out.d.d[4].t"
= "b.out.d.d[3].d[0]" "b.out.d.d[3].f"
= "b.out.d.d[3].d[1]" "b.out.d.d[3].t"
= "b.out.d.d[2].d[0]" "b.out.d.d[2].f"
= "b.out.d.d[2].d[1]" "b.out.d.d[2].t"
= "b.out.d.d[1].d[0]" "b.out.d.d[1].f"
= "b.out.d.d[1].d[1]" "b.out.d.d[1].t"
= "b.out.d.d[0].d[0]" "b.out.d.d[0].f"
= "b.out.d.d[0].d[1]" "b.out.d.d[0].t"
= "b.out.v" "b.b.out.v"
= "b.out.a" "b.b.out.a"
= "b.out.d.d[0].f" "b.b.out.d.d[0].f"
= "b.out.d.d[0].t" "b.b.out.d.d[0].t"
= "b.out.d.d[0].d[0]" "b.b.out.d.d[0].d[0]"
= "b.out.d.d[0].d[1]" "b.b.out.d.d[0].d[1]"
= "b.out.d.d[1].f" "b.b.out.d.d[1].f"
= "b.out.d.d[1].t" "b.b.out.d.d[1].t"
= "b.out.d.d[1].d[0]" "b.b.out.d.d[1].d[0]"
= "b.out.d.d[1].d[1]" "b.b.out.d.d[1].d[1]"
= "b.out.d.d[2].f" "b.b.out.d.d[2].f"
= "b.out.d.d[2].t" "b.b.out.d.d[2].t"
= "b.out.d.d[2].d[0]" "b.b.out.d.d[2].d[0]"
= "b.out.d.d[2].d[1]" "b.b.out.d.d[2].d[1]"
= "b.out.d.d[3].f" "b.b.out.d.d[3].f"
= "b.out.d.d[3].t" "b.b.out.d.d[3].t"
= "b.out.d.d[3].d[0]" "b.b.out.d.d[3].d[0]"
= "b.out.d.d[3].d[1]" "b.b.out.d.d[3].d[1]"
= "b.out.d.d[4].f" "b.b.out.d.d[4].f"
= "b.out.d.d[4].t" "b.b.out.d.d[4].t"
= "b.out.d.d[4].d[0]" "b.b.out.d.d[4].d[0]"
= "b.out.d.d[4].d[1]" "b.b.out.d.d[4].d[1]"
= "b.out.d.d[4].d[0]" "b.out.d.d[4].f"
= "b.out.d.d[4].d[1]" "b.out.d.d[4].t"
= "b.out.d.d[3].d[0]" "b.out.d.d[3].f"
= "b.out.d.d[3].d[1]" "b.out.d.d[3].t"
= "b.out.d.d[2].d[0]" "b.out.d.d[2].f"
= "b.out.d.d[2].d[1]" "b.out.d.d[2].t"
= "b.out.d.d[1].d[0]" "b.out.d.d[1].f"
= "b.out.d.d[1].d[1]" "b.out.d.d[1].t"
= "b.out.d.d[0].d[0]" "b.out.d.d[0].f"
= "b.out.d.d[0].d[1]" "b.out.d.d[0].t"
timing("b.in.a"-,"b.in.d[0]","b.in.r"+)
timing("b.in.a"-,"b.in.d[1]","b.in.r"+)
timing("b.in.a"-,"b.in.d[2]","b.in.r"+)
timing("b.in.a"-,"b.in.d[3]","b.in.r"+)
timing("b.in.a"-,"b.in.d[4]","b.in.r"+)
= "b.in.a" "b.b.in.a"
= "b.in.r" "b.b.in.r"
= "b.in.d[0]" "b.b.in.d[0]"
= "b.in.d[1]" "b.b.in.d[1]"
= "b.in.d[2]" "b.b.in.d[2]"
= "b.in.d[3]" "b.b.in.d[3]"
= "b.in.d[4]" "b.b.in.d[4]"

45
test/unit_tests/bd2qdi_5/test.act
View File

@@ -1,45 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/interfaces.act";
import globals;
open tmpl::dataflow_neuro;
defproc bd2qdi_5(bd<5> in; avMx1of2<5> out; bool? dly_cfg[4])
{
bool _reset_B;
prs {
Reset => _reset_B-
}
bd2qdi<5,4> b(.in = in, .out = out, .reset_B = _reset_B, .dly_cfg = dly_cfg);
b.supply.vdd = Vdd;
b.supply.vss = GND;
}
bd2qdi_5 b;

137
test/unit_tests/bd2qdi_5/test.prsim
View File

@@ -1,137 +0,0 @@
watchall
set b.out.a 0
set b.out.v 0
set b.in.r 0
set b.dly_cfg[0] 1
set b.dly_cfg[1] 1
set b.dly_cfg[2] 1
set b.dly_cfg[3] 1
set b.in.d[0] 1
set b.in.d[1] 0
set b.in.d[2] 0
set b.in.d[3] 1
set b.in.d[4] 0
set Reset 0
cycle
system "echo '[] set Reset 1'"
set Reset 1
cycle
system "echo '[] set Reset 0'"
set Reset 0
mode run
cycle
status X
assert-qdi-channel-neutral "b.out" 5
assert b.in.a 0
system "echo '[] Reset finished, setting data'"
set b.in.d[0] 0
set b.in.d[1] 1
set b.in.d[2] 1
set b.in.d[3] 0
set b.in.d[4] 1
cycle
system "echo '[] Reset finished, setting req 1'"
set b.in.r 1
cycle
assert-qdi-channel-valid "b.out" 5 22
system "echo '[] Receiving val out'"
set b.out.v 1
# set b.out.a 1
cycle
assert-qdi-channel-valid "b.out" 5 22
assert b.in.a 1
system "echo '[] Changing some input data'"
set b.in.d[0] 1
set b.in.d[1] 1
set b.in.d[2] 1
cycle
system "echo '[] Removing req'"
set b.in.r 0
system "echo '[] Changing more data'"
set b.in.d[3] 0
set b.in.d[4] 0
cycle
assert-qdi-channel-valid "b.out" 5 22
system "echo '[] Receiving ack out'"
set b.out.a 1
cycle
assert-qdi-channel-neutral "b.out" 5
set b.out.v 0
cycle
assert b.in.a 0
system "echo '[] Set ack out 0'"
set b.out.a 0
cycle
assert-qdi-channel-neutral "b.out" 5
assert b.in.a 0
system "echo '[] Again!!! setting data'"
set b.in.d[0] 0
set b.in.d[1] 0
set b.in.d[2] 0
set b.in.d[3] 0
set b.in.d[4] 0
cycle
system "echo '[] Again!!! setting req 1'"
set b.in.r 1
cycle
assert-qdi-channel-valid "b.out" 5 0
system "echo '[] Receiving val out'"
set b.out.v 1
# set b.out.a 1
cycle
assert-qdi-channel-valid "b.out" 5 0
assert b.in.a 1
system "echo '[] Changing some input data'"
set b.in.d[0] 1
set b.in.d[1] 1
set b.in.d[2] 1
cycle
system "echo '[] Removing req'"
set b.in.r 0
system "echo '[] Changing more data'"
set b.in.d[3] 0
set b.in.d[4] 0
cycle
assert-qdi-channel-valid "b.out" 5 0
system "echo '[] Receiving ack out'"
set b.out.a 1
cycle
assert-qdi-channel-neutral "b.out" 5
set b.out.v 0
cycle
assert b.in.a 0
system "echo '[] Set ack out 0'"
set b.out.a 0
cycle
assert-qdi-channel-neutral "b.out" 5
assert b.in.a 0

685
test/unit_tests/buf_15.v
View File

@@ -1,685 +0,0 @@
//
// Verilog module for: BUF_X6<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0BUF__X6(y, a);
output y;
input a;
// -- signals ---
reg y;
wire a;
reg _y;
// --- instances
endmodule
//
// Verilog module for: sigbuf<15>
//
module _0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4(in, \out[0] );
input in;
output \out[0] ;
// -- signals ---
wire in;
reg \out[0] ;
// --- instances
_0_0tmpl_0_0dataflow__neuro_0_0BUF__X6 \buf6 (.y(\out[0] ), .a(in));
endmodule
//
// Verilog module for: A_3C_RB_X4<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0A__3C__RB__X4(y, c1, c2, c3, pr_B, sr_B);
output y;
input c1;
input c2;
input c3;
input pr_B;
input sr_B;
// -- signals ---
wire sr_B;
wire pr_B;
wire c3;
wire c1;
reg _y;
reg y;
wire c2;
// --- instances
endmodule
//
// Verilog module for: BUF_X4<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0BUF__X4(y, a);
output y;
input a;
// -- signals ---
reg _y;
wire a;
reg y;
// --- instances
endmodule
//
// Verilog module for: INV_X1<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0INV__X1(y, a);
output y;
input a;
// -- signals ---
reg y;
wire a;
// --- instances
endmodule
//
// Verilog module for: A_2C_B_X1<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1(y, c1, c2);
output y;
input c1;
input c2;
// -- signals ---
reg y;
reg _y;
wire c2;
wire c1;
// --- instances
endmodule
//
// Verilog module for: A_3C_B_X1<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0A__3C__B__X1(y, c1, c2, c3);
output y;
input c1;
input c2;
input c3;
// -- signals ---
reg _y;
reg y;
wire c3;
wire c1;
wire c2;
// --- instances
endmodule
//
// Verilog module for: ctree<15>
//
module _0_0tmpl_0_0dataflow__neuro_0_0ctree_315_4(\in[0] , \in[1] , \in[2] , \in[3] , \in[4] , \in[5] , \in[6] , \in[7] , \in[8] , \in[9] , \in[10] , \in[11] , \in[12] , \in[13] , \in[14] , out);
input \in[0] ;
input \in[1] ;
input \in[2] ;
input \in[3] ;
input \in[4] ;
input \in[5] ;
input \in[6] ;
input \in[7] ;
input \in[8] ;
input \in[9] ;
input \in[10] ;
input \in[11] ;
input \in[12] ;
input \in[13] ;
input \in[14] ;
output out;
// -- signals ---
wire \in[4] ;
wire \in[11] ;
wire \in[12] ;
reg \tmp[21] ;
wire \in[3] ;
reg out;
reg \tmp[23] ;
wire \in[6] ;
wire \in[0] ;
reg \tmp[18] ;
wire \in[10] ;
reg \tmp[15] ;
reg \tmp[16] ;
wire \in[13] ;
wire \in[1] ;
wire \in[9] ;
wire \in[2] ;
wire \in[5] ;
reg \tmp[24] ;
wire \in[14] ;
reg \tmp[19] ;
wire \in[7] ;
reg \tmp[22] ;
reg \tmp[20] ;
wire \in[8] ;
reg \tmp[17] ;
// --- instances
_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[0] (.y(\tmp[15] ), .c1(\in[0] ), .c2(\in[1] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[1] (.y(\tmp[16] ), .c1(\in[2] ), .c2(\in[3] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[2] (.y(\tmp[17] ), .c1(\in[4] ), .c2(\in[5] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[3] (.y(\tmp[18] ), .c1(\in[6] ), .c2(\in[7] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[4] (.y(\tmp[19] ), .c1(\in[8] ), .c2(\in[9] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[5] (.y(\tmp[20] ), .c1(\in[10] ), .c2(\in[11] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[6] (.y(\tmp[22] ), .c1(\tmp[15] ), .c2(\tmp[16] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[7] (.y(\tmp[23] ), .c1(\tmp[17] ), .c2(\tmp[18] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__3C__B__X1 \C3Els[0] (.y(\tmp[21] ), .c1(\in[12] ), .c2(\in[13] ), .c3(\in[14] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__3C__B__X1 \C3Els[1] (.y(\tmp[24] ), .c1(\tmp[19] ), .c2(\tmp[20] ), .c3(\tmp[21] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__3C__B__X1 \C3Els[2] (.y(out), .c1(\tmp[22] ), .c2(\tmp[23] ), .c3(\tmp[24] ));
endmodule
//
// Verilog module for: OR2_X1<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0OR2__X1(y, a, b);
output y;
input a;
input b;
// -- signals ---
reg y;
wire a;
reg _y;
wire b;
// --- instances
endmodule
//
// Verilog module for: vtree<15>
//
module _0_0tmpl_0_0dataflow__neuro_0_0vtree_315_4(\in.d[0].d[0] , \in.d[0].d[1] , \in.d[1].d[0] , \in.d[1].d[1] , \in.d[2].d[0] , \in.d[2].d[1] , \in.d[3].d[0] , \in.d[3].d[1] , \in.d[4].d[0] , \in.d[4].d[1] , \in.d[5].d[0] , \in.d[5].d[1] , \in.d[6].d[0] , \in.d[6].d[1] , \in.d[7].d[0] , \in.d[7].d[1] , \in.d[8].d[0] , \in.d[8].d[1] , \in.d[9].d[0] , \in.d[9].d[1] , \in.d[10].d[0] , \in.d[10].d[1] , \in.d[11].d[0] , \in.d[11].d[1] , \in.d[12].d[0] , \in.d[12].d[1] , \in.d[13].d[0] , \in.d[13].d[1] , \in.d[14].d[0] , \in.d[14].d[1] , out);
input \in.d[0].d[0] ;
input \in.d[0].d[1] ;
input \in.d[1].d[0] ;
input \in.d[1].d[1] ;
input \in.d[2].d[0] ;
input \in.d[2].d[1] ;
input \in.d[3].d[0] ;
input \in.d[3].d[1] ;
input \in.d[4].d[0] ;
input \in.d[4].d[1] ;
input \in.d[5].d[0] ;
input \in.d[5].d[1] ;
input \in.d[6].d[0] ;
input \in.d[6].d[1] ;
input \in.d[7].d[0] ;
input \in.d[7].d[1] ;
input \in.d[8].d[0] ;
input \in.d[8].d[1] ;
input \in.d[9].d[0] ;
input \in.d[9].d[1] ;
input \in.d[10].d[0] ;
input \in.d[10].d[1] ;
input \in.d[11].d[0] ;
input \in.d[11].d[1] ;
input \in.d[12].d[0] ;
input \in.d[12].d[1] ;
input \in.d[13].d[0] ;
input \in.d[13].d[1] ;
input \in.d[14].d[0] ;
input \in.d[14].d[1] ;
output out;
// -- signals ---
reg \ct.in[14] ;
reg \ct.in[13] ;
wire \in.d[7].d[0] ;
wire \in.d[1].d[0] ;
wire \in.d[0].d[0] ;
reg \ct.in[4] ;
reg out;
wire \in.d[10].d[0] ;
wire \in.d[4].d[1] ;
reg \ct.in[3] ;
wire \in.d[9].d[1] ;
wire \in.d[1].d[1] ;
wire \in.d[2].d[0] ;
wire \in.d[10].d[1] ;
reg \ct.in[8] ;
wire \in.d[12].d[0] ;
wire \in.d[5].d[0] ;
wire \in.d[4].d[0] ;
reg \ct.in[10] ;
reg \ct.in[0] ;
wire \in.d[11].d[0] ;
wire \in.d[7].d[1] ;
wire \in.d[3].d[1] ;
reg \ct.in[11] ;
reg \ct.in[2] ;
reg \ct.in[9] ;
wire \in.d[13].d[0] ;
wire \in.d[14].d[1] ;
wire \in.d[11].d[1] ;
wire \in.d[13].d[1] ;
wire \in.d[0].d[1] ;
reg \ct.in[1] ;
wire \in.d[14].d[0] ;
wire \in.d[12].d[1] ;
wire \in.d[9].d[0] ;
wire \in.d[2].d[1] ;
reg \ct.in[5] ;
wire \in.d[5].d[1] ;
reg \ct.in[12] ;
reg \ct.in[6] ;
wire \in.d[3].d[0] ;
wire \in.d[8].d[0] ;
wire \in.d[8].d[1] ;
reg \ct.in[7] ;
wire \in.d[6].d[0] ;
wire \in.d[6].d[1] ;
// --- instances
_0_0tmpl_0_0dataflow__neuro_0_0ctree_315_4 \ct (.\in[0] (\ct.in[0] ), .\in[1] (\ct.in[1] ), .\in[2] (\ct.in[2] ), .\in[3] (\ct.in[3] ), .\in[4] (\ct.in[4] ), .\in[5] (\ct.in[5] ), .\in[6] (\ct.in[6] ), .\in[7] (\ct.in[7] ), .\in[8] (\ct.in[8] ), .\in[9] (\ct.in[9] ), .\in[10] (\ct.in[10] ), .\in[11] (\ct.in[11] ), .\in[12] (\ct.in[12] ), .\in[13] (\ct.in[13] ), .\in[14] (\ct.in[14] ), .out(out));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[0] (.y(\ct.in[0] ), .a(\in.d[0].d[1] ), .b(\in.d[0].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[1] (.y(\ct.in[1] ), .a(\in.d[1].d[1] ), .b(\in.d[1].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[2] (.y(\ct.in[2] ), .a(\in.d[2].d[1] ), .b(\in.d[2].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[3] (.y(\ct.in[3] ), .a(\in.d[3].d[1] ), .b(\in.d[3].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[4] (.y(\ct.in[4] ), .a(\in.d[4].d[1] ), .b(\in.d[4].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[5] (.y(\ct.in[5] ), .a(\in.d[5].d[1] ), .b(\in.d[5].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[6] (.y(\ct.in[6] ), .a(\in.d[6].d[1] ), .b(\in.d[6].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[7] (.y(\ct.in[7] ), .a(\in.d[7].d[1] ), .b(\in.d[7].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[8] (.y(\ct.in[8] ), .a(\in.d[8].d[1] ), .b(\in.d[8].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[9] (.y(\ct.in[9] ), .a(\in.d[9].d[1] ), .b(\in.d[9].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[10] (.y(\ct.in[10] ), .a(\in.d[10].d[1] ), .b(\in.d[10].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[11] (.y(\ct.in[11] ), .a(\in.d[11].d[1] ), .b(\in.d[11].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[12] (.y(\ct.in[12] ), .a(\in.d[12].d[1] ), .b(\in.d[12].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[13] (.y(\ct.in[13] ), .a(\in.d[13].d[1] ), .b(\in.d[13].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[14] (.y(\ct.in[14] ), .a(\in.d[14].d[1] ), .b(\in.d[14].d[0] ));
endmodule
//
// Verilog module for: A_1C1P_X1<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0A__1C1P__X1(y, c1, p1);
output y;
input c1;
input p1;
// -- signals ---
reg y;
wire c1;
wire p1;
// --- instances
endmodule
//
// Verilog module for: BUF_X1<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0BUF__X1(y, a);
output y;
input a;
// -- signals ---
reg y;
wire a;
reg _y;
// --- instances
endmodule
//
// Verilog module for: A_2C1N_RB_X4<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4(y, c1, c2, n1, pr_B, sr_B);
output y;
input c1;
input c2;
input n1;
input pr_B;
input sr_B;
// -- signals ---
reg y;
wire pr_B;
wire c2;
wire n1;
wire c1;
reg _y;
wire sr_B;
// --- instances
endmodule
//
// Verilog module for: buffer<15>
//
module _0_0tmpl_0_0dataflow__neuro_0_0buffer_315_4(\in.d.d[0].d[0] , \in.d.d[0].d[1] , \in.d.d[1].d[0] , \in.d.d[1].d[1] , \in.d.d[2].d[0] , \in.d.d[2].d[1] , \in.d.d[3].d[0] , \in.d.d[3].d[1] , \in.d.d[4].d[0] , \in.d.d[4].d[1] , \in.d.d[5].d[0] , \in.d.d[5].d[1] , \in.d.d[6].d[0] , \in.d.d[6].d[1] , \in.d.d[7].d[0] , \in.d.d[7].d[1] , \in.d.d[8].d[0] , \in.d.d[8].d[1] , \in.d.d[9].d[0] , \in.d.d[9].d[1] , \in.d.d[10].d[0] , \in.d.d[10].d[1] , \in.d.d[11].d[0] , \in.d.d[11].d[1] , \in.d.d[12].d[0] , \in.d.d[12].d[1] , \in.d.d[13].d[0] , \in.d.d[13].d[1] , \in.d.d[14].d[0] , \in.d.d[14].d[1] , \in.a , \in.v , \out.d.d[0].d[0] , \out.d.d[0].d[1] , \out.d.d[1].d[0] , \out.d.d[1].d[1] , \out.d.d[2].d[0] , \out.d.d[2].d[1] , \out.d.d[3].d[0] , \out.d.d[3].d[1] , \out.d.d[4].d[0] , \out.d.d[4].d[1] , \out.d.d[5].d[0] , \out.d.d[5].d[1] , \out.d.d[6].d[0] , \out.d.d[6].d[1] , \out.d.d[7].d[0] , \out.d.d[7].d[1] , \out.d.d[8].d[0] , \out.d.d[8].d[1] , \out.d.d[9].d[0] , \out.d.d[9].d[1] , \out.d.d[10].d[0] , \out.d.d[10].d[1] , \out.d.d[11].d[0] , \out.d.d[11].d[1] , \out.d.d[12].d[0] , \out.d.d[12].d[1] , \out.d.d[13].d[0] , \out.d.d[13].d[1] , \out.d.d[14].d[0] , \out.d.d[14].d[1] , \out.a , \out.v , reset_B);
input \in.d.d[0].d[0] ;
input \in.d.d[0].d[1] ;
input \in.d.d[1].d[0] ;
input \in.d.d[1].d[1] ;
input \in.d.d[2].d[0] ;
input \in.d.d[2].d[1] ;
input \in.d.d[3].d[0] ;
input \in.d.d[3].d[1] ;
input \in.d.d[4].d[0] ;
input \in.d.d[4].d[1] ;
input \in.d.d[5].d[0] ;
input \in.d.d[5].d[1] ;
input \in.d.d[6].d[0] ;
input \in.d.d[6].d[1] ;
input \in.d.d[7].d[0] ;
input \in.d.d[7].d[1] ;
input \in.d.d[8].d[0] ;
input \in.d.d[8].d[1] ;
input \in.d.d[9].d[0] ;
input \in.d.d[9].d[1] ;
input \in.d.d[10].d[0] ;
input \in.d.d[10].d[1] ;
input \in.d.d[11].d[0] ;
input \in.d.d[11].d[1] ;
input \in.d.d[12].d[0] ;
input \in.d.d[12].d[1] ;
input \in.d.d[13].d[0] ;
input \in.d.d[13].d[1] ;
input \in.d.d[14].d[0] ;
input \in.d.d[14].d[1] ;
output \in.a ;
output \in.v ;
output \out.d.d[0].d[0] ;
output \out.d.d[0].d[1] ;
output \out.d.d[1].d[0] ;
output \out.d.d[1].d[1] ;
output \out.d.d[2].d[0] ;
output \out.d.d[2].d[1] ;
output \out.d.d[3].d[0] ;
output \out.d.d[3].d[1] ;
output \out.d.d[4].d[0] ;
output \out.d.d[4].d[1] ;
output \out.d.d[5].d[0] ;
output \out.d.d[5].d[1] ;
output \out.d.d[6].d[0] ;
output \out.d.d[6].d[1] ;
output \out.d.d[7].d[0] ;
output \out.d.d[7].d[1] ;
output \out.d.d[8].d[0] ;
output \out.d.d[8].d[1] ;
output \out.d.d[9].d[0] ;
output \out.d.d[9].d[1] ;
output \out.d.d[10].d[0] ;
output \out.d.d[10].d[1] ;
output \out.d.d[11].d[0] ;
output \out.d.d[11].d[1] ;
output \out.d.d[12].d[0] ;
output \out.d.d[12].d[1] ;
output \out.d.d[13].d[0] ;
output \out.d.d[13].d[1] ;
output \out.d.d[14].d[0] ;
output \out.d.d[14].d[1] ;
input \out.a ;
input \out.v ;
input reset_B;
// -- signals ---
reg \out.d.d[8].d[0] ;
reg \out.d.d[6].d[1] ;
reg \out.d.d[5].d[1] ;
reg \_en_X_f[0] ;
wire \in.d.d[14].d[0] ;
wire \in.d.d[12].d[1] ;
reg \out.d.d[12].d[1] ;
wire \in.d.d[5].d[0] ;
reg \out.d.d[11].d[0] ;
reg \out.d.d[7].d[0] ;
reg _reset_BX;
reg \_reset_BXX[0] ;
wire \in.d.d[14].d[1] ;
wire \in.d.d[10].d[1] ;
wire \in.d.d[2].d[0] ;
wire \out.a ;
reg \out.d.d[0].d[0] ;
wire \in.d.d[0].d[0] ;
reg \out.d.d[10].d[1] ;
wire \in.d.d[11].d[0] ;
wire \in.d.d[7].d[1] ;
wire \in.d.d[3].d[1] ;
reg _in_v;
reg \in.v ;
reg _out_a_B;
wire \in.d.d[9].d[1] ;
wire \in.d.d[9].d[0] ;
wire \in.d.d[4].d[1] ;
reg \out.d.d[10].d[0] ;
wire \in.d.d[1].d[1] ;
wire \in.d.d[12].d[0] ;
wire \in.d.d[1].d[0] ;
reg \_out_a_BX_f[0] ;
reg \out.d.d[3].d[1] ;
reg \out.d.d[0].d[1] ;
reg \out.d.d[2].d[1] ;
reg \out.d.d[4].d[1] ;
wire reset_B;
wire \in.d.d[8].d[0] ;
reg \out.d.d[12].d[0] ;
wire \in.d.d[5].d[1] ;
reg \out.d.d[9].d[0] ;
reg \out.d.d[7].d[1] ;
reg \_out_a_BX_t[0] ;
wire \in.d.d[10].d[0] ;
reg \out.d.d[1].d[0] ;
wire \in.d.d[6].d[0] ;
wire \in.d.d[7].d[0] ;
wire \in.d.d[13].d[1] ;
wire \out.v ;
reg \out.d.d[2].d[0] ;
wire \in.d.d[13].d[0] ;
wire \in.d.d[11].d[1] ;
wire \in.d.d[6].d[1] ;
reg \out.d.d[3].d[0] ;
reg \out.d.d[11].d[1] ;
reg \out.d.d[9].d[1] ;
wire \in.d.d[3].d[0] ;
reg _en;
reg \out.d.d[13].d[0] ;
reg \out.d.d[5].d[0] ;
reg \in.a ;
reg \out.d.d[14].d[0] ;
reg \out.d.d[4].d[0] ;
wire \in.d.d[8].d[1] ;
reg \out.d.d[13].d[1] ;
reg \out.d.d[8].d[1] ;
reg \out.d.d[14].d[1] ;
wire \in.d.d[2].d[1] ;
reg \out.d.d[6].d[0] ;
wire \in.d.d[4].d[0] ;
reg \out.d.d[1].d[1] ;
reg \_en_X_t[0] ;
wire \in.d.d[0].d[1] ;
// --- instances
_0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 \out_a_B_buf_t (.in(_out_a_B), .\out[0] (\_out_a_BX_f[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__3C__RB__X4 \inack_ctl (.y(\in.a ), .c1(_en), .c2(\in.v ), .c3(\out.v ), .pr_B(_reset_BX), .sr_B(_reset_BX));
_0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 \reset_bufarray (.in(_reset_BX), .\out[0] (\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0BUF__X4 \in_v_buf (.y(\in.v ), .a(_in_v));
_0_0tmpl_0_0dataflow__neuro_0_0INV__X1 \out_a_inv (.y(_out_a_B), .a(\out.a ));
_0_0tmpl_0_0dataflow__neuro_0_0vtree_315_4 \vc (.\in.d[0].d[0] (\in.d.d[0].d[0] ), .\in.d[0].d[1] (\in.d.d[0].d[1] ), .\in.d[1].d[0] (\in.d.d[1].d[0] ), .\in.d[1].d[1] (\in.d.d[1].d[1] ), .\in.d[2].d[0] (\in.d.d[2].d[0] ), .\in.d[2].d[1] (\in.d.d[2].d[1] ), .\in.d[3].d[0] (\in.d.d[3].d[0] ), .\in.d[3].d[1] (\in.d.d[3].d[1] ), .\in.d[4].d[0] (\in.d.d[4].d[0] ), .\in.d[4].d[1] (\in.d.d[4].d[1] ), .\in.d[5].d[0] (\in.d.d[5].d[0] ), .\in.d[5].d[1] (\in.d.d[5].d[1] ), .\in.d[6].d[0] (\in.d.d[6].d[0] ), .\in.d[6].d[1] (\in.d.d[6].d[1] ), .\in.d[7].d[0] (\in.d.d[7].d[0] ), .\in.d[7].d[1] (\in.d.d[7].d[1] ), .\in.d[8].d[0] (\in.d.d[8].d[0] ), .\in.d[8].d[1] (\in.d.d[8].d[1] ), .\in.d[9].d[0] (\in.d.d[9].d[0] ), .\in.d[9].d[1] (\in.d.d[9].d[1] ), .\in.d[10].d[0] (\in.d.d[10].d[0] ), .\in.d[10].d[1] (\in.d.d[10].d[1] ), .\in.d[11].d[0] (\in.d.d[11].d[0] ), .\in.d[11].d[1] (\in.d.d[11].d[1] ), .\in.d[12].d[0] (\in.d.d[12].d[0] ), .\in.d[12].d[1] (\in.d.d[12].d[1] ), .\in.d[13].d[0] (\in.d.d[13].d[0] ), .\in.d[13].d[1] (\in.d.d[13].d[1] ), .\in.d[14].d[0] (\in.d.d[14].d[0] ), .\in.d[14].d[1] (\in.d.d[14].d[1] ), .out(_in_v));
_0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 \out_a_B_buf_f (.in(_out_a_B), .\out[0] (\_out_a_BX_t[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__1C1P__X1 \en_ctl (.y(_en), .c1(\in.a ), .p1(\out.v ));
_0_0tmpl_0_0dataflow__neuro_0_0BUF__X1 \reset_buf (.y(_reset_BX), .a(reset_B));
_0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 \en_buf_f (.in(_en), .\out[0] (\_en_X_f[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 \en_buf_t (.in(_en), .\out[0] (\_en_X_t[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[0] (.y(\out.d.d[0].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[0].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[1] (.y(\out.d.d[1].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[1].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[2] (.y(\out.d.d[2].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[2].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[3] (.y(\out.d.d[3].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[3].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[4] (.y(\out.d.d[4].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[4].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[5] (.y(\out.d.d[5].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[5].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[6] (.y(\out.d.d[6].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[6].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[7] (.y(\out.d.d[7].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[7].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[8] (.y(\out.d.d[8].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[8].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[9] (.y(\out.d.d[9].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[9].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[10] (.y(\out.d.d[10].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[10].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[11] (.y(\out.d.d[11].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[11].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[12] (.y(\out.d.d[12].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[12].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[13] (.y(\out.d.d[13].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[13].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[14] (.y(\out.d.d[14].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[14].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[0] (.y(\out.d.d[0].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[0].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[1] (.y(\out.d.d[1].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[1].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[2] (.y(\out.d.d[2].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[2].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[3] (.y(\out.d.d[3].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[3].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[4] (.y(\out.d.d[4].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[4].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[5] (.y(\out.d.d[5].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[5].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[6] (.y(\out.d.d[6].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[6].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[7] (.y(\out.d.d[7].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[7].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[8] (.y(\out.d.d[8].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[8].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[9] (.y(\out.d.d[9].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[9].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[10] (.y(\out.d.d[10].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[10].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[11] (.y(\out.d.d[11].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[11].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[12] (.y(\out.d.d[12].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[12].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[13] (.y(\out.d.d[13].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[13].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[14] (.y(\out.d.d[14].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[14].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
endmodule
//
// Verilog module for: buffer_15<>
//
module buffer__15(\in.d.d[0].d[0] , \in.d.d[0].d[1] , \in.d.d[1].d[0] , \in.d.d[1].d[1] , \in.d.d[2].d[0] , \in.d.d[2].d[1] , \in.d.d[3].d[0] , \in.d.d[3].d[1] , \in.d.d[4].d[0] , \in.d.d[4].d[1] , \in.d.d[5].d[0] , \in.d.d[5].d[1] , \in.d.d[6].d[0] , \in.d.d[6].d[1] , \in.d.d[7].d[0] , \in.d.d[7].d[1] , \in.d.d[8].d[0] , \in.d.d[8].d[1] , \in.d.d[9].d[0] , \in.d.d[9].d[1] , \in.d.d[10].d[0] , \in.d.d[10].d[1] , \in.d.d[11].d[0] , \in.d.d[11].d[1] , \in.d.d[12].d[0] , \in.d.d[12].d[1] , \in.d.d[13].d[0] , \in.d.d[13].d[1] , \in.d.d[14].d[0] , \in.d.d[14].d[1] , \in.a , \in.v , \out.d.d[0].d[0] , \out.d.d[0].d[1] , \out.d.d[1].d[0] , \out.d.d[1].d[1] , \out.d.d[2].d[0] , \out.d.d[2].d[1] , \out.d.d[3].d[0] , \out.d.d[3].d[1] , \out.d.d[4].d[0] , \out.d.d[4].d[1] , \out.d.d[5].d[0] , \out.d.d[5].d[1] , \out.d.d[6].d[0] , \out.d.d[6].d[1] , \out.d.d[7].d[0] , \out.d.d[7].d[1] , \out.d.d[8].d[0] , \out.d.d[8].d[1] , \out.d.d[9].d[0] , \out.d.d[9].d[1] , \out.d.d[10].d[0] , \out.d.d[10].d[1] , \out.d.d[11].d[0] , \out.d.d[11].d[1] , \out.d.d[12].d[0] , \out.d.d[12].d[1] , \out.d.d[13].d[0] , \out.d.d[13].d[1] , \out.d.d[14].d[0] , \out.d.d[14].d[1] , \out.a , \out.v );
input \in.d.d[0].d[0] ;
input \in.d.d[0].d[1] ;
input \in.d.d[1].d[0] ;
input \in.d.d[1].d[1] ;
input \in.d.d[2].d[0] ;
input \in.d.d[2].d[1] ;
input \in.d.d[3].d[0] ;
input \in.d.d[3].d[1] ;
input \in.d.d[4].d[0] ;
input \in.d.d[4].d[1] ;
input \in.d.d[5].d[0] ;
input \in.d.d[5].d[1] ;
input \in.d.d[6].d[0] ;
input \in.d.d[6].d[1] ;
input \in.d.d[7].d[0] ;
input \in.d.d[7].d[1] ;
input \in.d.d[8].d[0] ;
input \in.d.d[8].d[1] ;
input \in.d.d[9].d[0] ;
input \in.d.d[9].d[1] ;
input \in.d.d[10].d[0] ;
input \in.d.d[10].d[1] ;
input \in.d.d[11].d[0] ;
input \in.d.d[11].d[1] ;
input \in.d.d[12].d[0] ;
input \in.d.d[12].d[1] ;
input \in.d.d[13].d[0] ;
input \in.d.d[13].d[1] ;
input \in.d.d[14].d[0] ;
input \in.d.d[14].d[1] ;
output \in.a ;
output \in.v ;
output \out.d.d[0].d[0] ;
output \out.d.d[0].d[1] ;
output \out.d.d[1].d[0] ;
output \out.d.d[1].d[1] ;
output \out.d.d[2].d[0] ;
output \out.d.d[2].d[1] ;
output \out.d.d[3].d[0] ;
output \out.d.d[3].d[1] ;
output \out.d.d[4].d[0] ;
output \out.d.d[4].d[1] ;
output \out.d.d[5].d[0] ;
output \out.d.d[5].d[1] ;
output \out.d.d[6].d[0] ;
output \out.d.d[6].d[1] ;
output \out.d.d[7].d[0] ;
output \out.d.d[7].d[1] ;
output \out.d.d[8].d[0] ;
output \out.d.d[8].d[1] ;
output \out.d.d[9].d[0] ;
output \out.d.d[9].d[1] ;
output \out.d.d[10].d[0] ;
output \out.d.d[10].d[1] ;
output \out.d.d[11].d[0] ;
output \out.d.d[11].d[1] ;
output \out.d.d[12].d[0] ;
output \out.d.d[12].d[1] ;
output \out.d.d[13].d[0] ;
output \out.d.d[13].d[1] ;
output \out.d.d[14].d[0] ;
output \out.d.d[14].d[1] ;
input \out.a ;
input \out.v ;
// -- signals ---
reg \out.d.d[2].d[1] ;
wire \in.d.d[10].d[0] ;
reg \out.d.d[1].d[0] ;
wire \in.d.d[10].d[1] ;
wire \in.d.d[4].d[0] ;
reg \out.d.d[10].d[1] ;
wire \in.d.d[13].d[0] ;
reg \out.d.d[13].d[0] ;
reg \out.d.d[9].d[1] ;
wire \in.d.d[2].d[1] ;
reg \out.d.d[2].d[0] ;
reg \out.d.d[0].d[0] ;
reg \out.d.d[14].d[0] ;
reg \out.d.d[5].d[0] ;
reg \in.a ;
reg _reset_B;
wire \out.v ;
wire \out.a ;
reg \out.d.d[4].d[0] ;
wire \in.d.d[9].d[1] ;
wire \in.d.d[3].d[0] ;
wire \in.d.d[11].d[0] ;
wire \in.d.d[2].d[0] ;
reg \out.d.d[6].d[0] ;
reg \out.d.d[13].d[1] ;
reg \out.d.d[10].d[0] ;
reg \out.d.d[7].d[1] ;
wire \in.d.d[12].d[1] ;
wire \in.d.d[6].d[1] ;
reg \out.d.d[7].d[0] ;
reg \out.d.d[3].d[0] ;
wire \in.d.d[1].d[0] ;
reg \out.d.d[14].d[1] ;
reg \out.d.d[8].d[0] ;
wire \in.d.d[13].d[1] ;
wire \in.d.d[7].d[0] ;
reg \out.d.d[12].d[0] ;
wire \in.d.d[8].d[1] ;
reg \out.d.d[4].d[1] ;
wire \in.d.d[14].d[0] ;
wire \in.d.d[5].d[1] ;
wire \in.d.d[1].d[1] ;
wire \in.d.d[9].d[0] ;
wire \in.d.d[14].d[1] ;
reg \out.d.d[11].d[0] ;
reg \out.d.d[6].d[1] ;
wire \in.d.d[12].d[0] ;
wire \in.d.d[7].d[1] ;
reg \out.d.d[0].d[1] ;
wire \in.d.d[11].d[1] ;
wire \in.d.d[8].d[0] ;
wire \in.d.d[5].d[0] ;
reg \out.d.d[1].d[1] ;
reg \in.v ;
wire \in.d.d[0].d[1] ;
wire \in.d.d[0].d[0] ;
reg \out.d.d[5].d[1] ;
reg \out.d.d[8].d[1] ;
reg \out.d.d[3].d[1] ;
wire \in.d.d[6].d[0] ;
reg \out.d.d[11].d[1] ;
wire \in.d.d[3].d[1] ;
reg \out.d.d[12].d[1] ;
wire \in.d.d[4].d[1] ;
reg \out.d.d[9].d[0] ;
// --- instances
_0_0tmpl_0_0dataflow__neuro_0_0buffer_315_4 \buffer_test (.\in.d.d[0].d[0] (\in.d.d[0].d[0] ), .\in.d.d[0].d[1] (\in.d.d[0].d[1] ), .\in.d.d[1].d[0] (\in.d.d[1].d[0] ), .\in.d.d[1].d[1] (\in.d.d[1].d[1] ), .\in.d.d[2].d[0] (\in.d.d[2].d[0] ), .\in.d.d[2].d[1] (\in.d.d[2].d[1] ), .\in.d.d[3].d[0] (\in.d.d[3].d[0] ), .\in.d.d[3].d[1] (\in.d.d[3].d[1] ), .\in.d.d[4].d[0] (\in.d.d[4].d[0] ), .\in.d.d[4].d[1] (\in.d.d[4].d[1] ), .\in.d.d[5].d[0] (\in.d.d[5].d[0] ), .\in.d.d[5].d[1] (\in.d.d[5].d[1] ), .\in.d.d[6].d[0] (\in.d.d[6].d[0] ), .\in.d.d[6].d[1] (\in.d.d[6].d[1] ), .\in.d.d[7].d[0] (\in.d.d[7].d[0] ), .\in.d.d[7].d[1] (\in.d.d[7].d[1] ), .\in.d.d[8].d[0] (\in.d.d[8].d[0] ), .\in.d.d[8].d[1] (\in.d.d[8].d[1] ), .\in.d.d[9].d[0] (\in.d.d[9].d[0] ), .\in.d.d[9].d[1] (\in.d.d[9].d[1] ), .\in.d.d[10].d[0] (\in.d.d[10].d[0] ), .\in.d.d[10].d[1] (\in.d.d[10].d[1] ), .\in.d.d[11].d[0] (\in.d.d[11].d[0] ), .\in.d.d[11].d[1] (\in.d.d[11].d[1] ), .\in.d.d[12].d[0] (\in.d.d[12].d[0] ), .\in.d.d[12].d[1] (\in.d.d[12].d[1] ), .\in.d.d[13].d[0] (\in.d.d[13].d[0] ), .\in.d.d[13].d[1] (\in.d.d[13].d[1] ), .\in.d.d[14].d[0] (\in.d.d[14].d[0] ), .\in.d.d[14].d[1] (\in.d.d[14].d[1] ), .\in.a (\in.a ), .\in.v (\in.v ), .\out.d.d[0].d[0] (\out.d.d[0].d[0] ), .\out.d.d[0].d[1] (\out.d.d[0].d[1] ), .\out.d.d[1].d[0] (\out.d.d[1].d[0] ), .\out.d.d[1].d[1] (\out.d.d[1].d[1] ), .\out.d.d[2].d[0] (\out.d.d[2].d[0] ), .\out.d.d[2].d[1] (\out.d.d[2].d[1] ), .\out.d.d[3].d[0] (\out.d.d[3].d[0] ), .\out.d.d[3].d[1] (\out.d.d[3].d[1] ), .\out.d.d[4].d[0] (\out.d.d[4].d[0] ), .\out.d.d[4].d[1] (\out.d.d[4].d[1] ), .\out.d.d[5].d[0] (\out.d.d[5].d[0] ), .\out.d.d[5].d[1] (\out.d.d[5].d[1] ), .\out.d.d[6].d[0] (\out.d.d[6].d[0] ), .\out.d.d[6].d[1] (\out.d.d[6].d[1] ), .\out.d.d[7].d[0] (\out.d.d[7].d[0] ), .\out.d.d[7].d[1] (\out.d.d[7].d[1] ), .\out.d.d[8].d[0] (\out.d.d[8].d[0] ), .\out.d.d[8].d[1] (\out.d.d[8].d[1] ), .\out.d.d[9].d[0] (\out.d.d[9].d[0] ), .\out.d.d[9].d[1] (\out.d.d[9].d[1] ), .\out.d.d[10].d[0] (\out.d.d[10].d[0] ), .\out.d.d[10].d[1] (\out.d.d[10].d[1] ), .\out.d.d[11].d[0] (\out.d.d[11].d[0] ), .\out.d.d[11].d[1] (\out.d.d[11].d[1] ), .\out.d.d[12].d[0] (\out.d.d[12].d[0] ), .\out.d.d[12].d[1] (\out.d.d[12].d[1] ), .\out.d.d[13].d[0] (\out.d.d[13].d[0] ), .\out.d.d[13].d[1] (\out.d.d[13].d[1] ), .\out.d.d[14].d[0] (\out.d.d[14].d[0] ), .\out.d.d[14].d[1] (\out.d.d[14].d[1] ), .\out.a (\out.a ), .\out.v (\out.v ), .reset_B(_reset_B));
endmodule

571
test/unit_tests/buf_15_friendly2.v
View File

@@ -1,571 +0,0 @@
//
// Verilog module for: BUF_X6<>
//
//
// Verilog module for: sigbuf<15>
//
module _0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4(in, \out[0] , vdd, vss);
input vdd;
input vss;
input in;
output \out[0] ;
// -- signals ---
wire in;
reg \out[0] ;
// --- instances
BUF_X6 \buf6 (.y(\out[0] ), .a(in), .vdd(vdd), .vss(vss));
endmodule
//
// Verilog module for: A_3C_RB_X4<>
//
//
// Verilog module for: BUF_X4<>
//
//
// Verilog module for: INV_X1<>
//
//
// Verilog module for: A_2C_B_X1<>
//
//
// Verilog module for: A_3C_B_X1<>
//
//
// Verilog module for: ctree<15>
//
module _0_0tmpl_0_0dataflow__neuro_0_0ctree_315_4(\in[0] , \in[1] , \in[2] , \in[3] , \in[4] , \in[5] , \in[6] , \in[7] , \in[8] , \in[9] , \in[10] , \in[11] , \in[12] , \in[13] , \in[14] , out, vdd, vss);
input vdd;
input vss;
input \in[0] ;
input \in[1] ;
input \in[2] ;
input \in[3] ;
input \in[4] ;
input \in[5] ;
input \in[6] ;
input \in[7] ;
input \in[8] ;
input \in[9] ;
input \in[10] ;
input \in[11] ;
input \in[12] ;
input \in[13] ;
input \in[14] ;
output out;
// -- signals ---
wire \in[4] ;
wire \in[11] ;
wire \in[12] ;
reg \tmp[21] ;
wire \in[3] ;
reg out;
reg \tmp[23] ;
wire \in[6] ;
wire \in[0] ;
reg \tmp[18] ;
wire \in[10] ;
reg \tmp[15] ;
reg \tmp[16] ;
wire \in[13] ;
wire \in[1] ;
wire \in[9] ;
wire \in[2] ;
wire \in[5] ;
reg \tmp[24] ;
wire \in[14] ;
reg \tmp[19] ;
wire \in[7] ;
reg \tmp[22] ;
reg \tmp[20] ;
wire \in[8] ;
reg \tmp[17] ;
// --- instances
A_2C_B_X1 \C2Els[0] (.y(\tmp[15] ), .c1(\in[0] ), .c2(\in[1] ), .vdd(vdd), .vss(vss));
A_2C_B_X1 \C2Els[1] (.y(\tmp[16] ), .c1(\in[2] ), .c2(\in[3] ), .vdd(vdd), .vss(vss));
A_2C_B_X1 \C2Els[2] (.y(\tmp[17] ), .c1(\in[4] ), .c2(\in[5] ), .vdd(vdd), .vss(vss));
A_2C_B_X1 \C2Els[3] (.y(\tmp[18] ), .c1(\in[6] ), .c2(\in[7] ), .vdd(vdd), .vss(vss));
A_2C_B_X1 \C2Els[4] (.y(\tmp[19] ), .c1(\in[8] ), .c2(\in[9] ), .vdd(vdd), .vss(vss));
A_2C_B_X1 \C2Els[5] (.y(\tmp[20] ), .c1(\in[10] ), .c2(\in[11] ), .vdd(vdd), .vss(vss));
A_2C_B_X1 \C2Els[6] (.y(\tmp[22] ), .c1(\tmp[15] ), .c2(\tmp[16] ), .vdd(vdd), .vss(vss));
A_2C_B_X1 \C2Els[7] (.y(\tmp[23] ), .c1(\tmp[17] ), .c2(\tmp[18] ), .vdd(vdd), .vss(vss));
A_3C_B_X1 \C3Els[0] (.y(\tmp[21] ), .c1(\in[12] ), .c2(\in[13] ), .c3(\in[14] ), .vdd(vdd), .vss(vss));
A_3C_B_X1 \C3Els[1] (.y(\tmp[24] ), .c1(\tmp[19] ), .c2(\tmp[20] ), .c3(\tmp[21] ), .vdd(vdd), .vss(vss));
A_3C_B_X1 \C3Els[2] (.y(out), .c1(\tmp[22] ), .c2(\tmp[23] ), .c3(\tmp[24] ), .vdd(vdd), .vss(vss));
endmodule
//
// Verilog module for: OR2_X1<>
//
//
// Verilog module for: vtree<15>
//
module _0_0tmpl_0_0dataflow__neuro_0_0vtree_315_4(\in.d[0].d[0] , \in.d[0].d[1] , \in.d[1].d[0] , \in.d[1].d[1] , \in.d[2].d[0] , \in.d[2].d[1] , \in.d[3].d[0] , \in.d[3].d[1] , \in.d[4].d[0] , \in.d[4].d[1] , \in.d[5].d[0] , \in.d[5].d[1] , \in.d[6].d[0] , \in.d[6].d[1] , \in.d[7].d[0] , \in.d[7].d[1] , \in.d[8].d[0] , \in.d[8].d[1] , \in.d[9].d[0] , \in.d[9].d[1] , \in.d[10].d[0] , \in.d[10].d[1] , \in.d[11].d[0] , \in.d[11].d[1] , \in.d[12].d[0] , \in.d[12].d[1] , \in.d[13].d[0] , \in.d[13].d[1] , \in.d[14].d[0] , \in.d[14].d[1] , out, vdd, vss);
input vdd;
input vss;
input \in.d[0].d[0] ;
input \in.d[0].d[1] ;
input \in.d[1].d[0] ;
input \in.d[1].d[1] ;
input \in.d[2].d[0] ;
input \in.d[2].d[1] ;
input \in.d[3].d[0] ;
input \in.d[3].d[1] ;
input \in.d[4].d[0] ;
input \in.d[4].d[1] ;
input \in.d[5].d[0] ;
input \in.d[5].d[1] ;
input \in.d[6].d[0] ;
input \in.d[6].d[1] ;
input \in.d[7].d[0] ;
input \in.d[7].d[1] ;
input \in.d[8].d[0] ;
input \in.d[8].d[1] ;
input \in.d[9].d[0] ;
input \in.d[9].d[1] ;
input \in.d[10].d[0] ;
input \in.d[10].d[1] ;
input \in.d[11].d[0] ;
input \in.d[11].d[1] ;
input \in.d[12].d[0] ;
input \in.d[12].d[1] ;
input \in.d[13].d[0] ;
input \in.d[13].d[1] ;
input \in.d[14].d[0] ;
input \in.d[14].d[1] ;
output out;
// -- signals ---
reg \ct.in[14] ;
reg \ct.in[13] ;
wire \in.d[7].d[0] ;
wire \in.d[1].d[0] ;
wire \in.d[0].d[0] ;
reg \ct.in[4] ;
reg out;
wire \in.d[10].d[0] ;
wire \in.d[4].d[1] ;
reg \ct.in[3] ;
wire \in.d[9].d[1] ;
wire \in.d[1].d[1] ;
wire \in.d[2].d[0] ;
wire \in.d[10].d[1] ;
reg \ct.in[8] ;
wire \in.d[12].d[0] ;
wire \in.d[5].d[0] ;
wire \in.d[4].d[0] ;
reg \ct.in[10] ;
reg \ct.in[0] ;
wire \in.d[11].d[0] ;
wire \in.d[7].d[1] ;
wire \in.d[3].d[1] ;
reg \ct.in[11] ;
reg \ct.in[2] ;
reg \ct.in[9] ;
wire \in.d[13].d[0] ;
wire \in.d[14].d[1] ;
wire \in.d[11].d[1] ;
wire \in.d[13].d[1] ;
wire \in.d[0].d[1] ;
reg \ct.in[1] ;
wire \in.d[14].d[0] ;
wire \in.d[12].d[1] ;
wire \in.d[9].d[0] ;
wire \in.d[2].d[1] ;
reg \ct.in[5] ;
wire \in.d[5].d[1] ;
reg \ct.in[12] ;
reg \ct.in[6] ;
wire \in.d[3].d[0] ;
wire \in.d[8].d[0] ;
wire \in.d[8].d[1] ;
reg \ct.in[7] ;
wire \in.d[6].d[0] ;
wire \in.d[6].d[1] ;
// --- instances
_0_0tmpl_0_0dataflow__neuro_0_0ctree_315_4 \ct (.\in[0] (\ct.in[0] ), .\in[1] (\ct.in[1] ), .\in[2] (\ct.in[2] ), .\in[3] (\ct.in[3] ), .\in[4] (\ct.in[4] ), .\in[5] (\ct.in[5] ), .\in[6] (\ct.in[6] ), .\in[7] (\ct.in[7] ), .\in[8] (\ct.in[8] ), .\in[9] (\ct.in[9] ), .\in[10] (\ct.in[10] ), .\in[11] (\ct.in[11] ), .\in[12] (\ct.in[12] ), .\in[13] (\ct.in[13] ), .\in[14] (\ct.in[14] ), .out(out), .vdd(vdd), .vss(vss));
OR2_X1 \OR2_tf[0] (.y(\ct.in[0] ), .a(\in.d[0].d[1] ), .b(\in.d[0].d[0] ), .vdd(vdd), .vss(vss));
OR2_X1 \OR2_tf[1] (.y(\ct.in[1] ), .a(\in.d[1].d[1] ), .b(\in.d[1].d[0] ), .vdd(vdd), .vss(vss));
OR2_X1 \OR2_tf[2] (.y(\ct.in[2] ), .a(\in.d[2].d[1] ), .b(\in.d[2].d[0] ), .vdd(vdd), .vss(vss));
OR2_X1 \OR2_tf[3] (.y(\ct.in[3] ), .a(\in.d[3].d[1] ), .b(\in.d[3].d[0] ), .vdd(vdd), .vss(vss));
OR2_X1 \OR2_tf[4] (.y(\ct.in[4] ), .a(\in.d[4].d[1] ), .b(\in.d[4].d[0] ), .vdd(vdd), .vss(vss));
OR2_X1 \OR2_tf[5] (.y(\ct.in[5] ), .a(\in.d[5].d[1] ), .b(\in.d[5].d[0] ), .vdd(vdd), .vss(vss));
OR2_X1 \OR2_tf[6] (.y(\ct.in[6] ), .a(\in.d[6].d[1] ), .b(\in.d[6].d[0] ), .vdd(vdd), .vss(vss));
OR2_X1 \OR2_tf[7] (.y(\ct.in[7] ), .a(\in.d[7].d[1] ), .b(\in.d[7].d[0] ), .vdd(vdd), .vss(vss));
OR2_X1 \OR2_tf[8] (.y(\ct.in[8] ), .a(\in.d[8].d[1] ), .b(\in.d[8].d[0] ), .vdd(vdd), .vss(vss));
OR2_X1 \OR2_tf[9] (.y(\ct.in[9] ), .a(\in.d[9].d[1] ), .b(\in.d[9].d[0] ), .vdd(vdd), .vss(vss));
OR2_X1 \OR2_tf[10] (.y(\ct.in[10] ), .a(\in.d[10].d[1] ), .b(\in.d[10].d[0] ), .vdd(vdd), .vss(vss));
OR2_X1 \OR2_tf[11] (.y(\ct.in[11] ), .a(\in.d[11].d[1] ), .b(\in.d[11].d[0] ), .vdd(vdd), .vss(vss));
OR2_X1 \OR2_tf[12] (.y(\ct.in[12] ), .a(\in.d[12].d[1] ), .b(\in.d[12].d[0] ), .vdd(vdd), .vss(vss));
OR2_X1 \OR2_tf[13] (.y(\ct.in[13] ), .a(\in.d[13].d[1] ), .b(\in.d[13].d[0] ), .vdd(vdd), .vss(vss));
OR2_X1 \OR2_tf[14] (.y(\ct.in[14] ), .a(\in.d[14].d[1] ), .b(\in.d[14].d[0] ), .vdd(vdd), .vss(vss));
endmodule
//
// Verilog module for: A_1C1P_X1<>
//
//
// Verilog module for: BUF_X1<>
//
//
// Verilog module for: A_2C1N_RB_X4<>
//
//
// Verilog module for: buffer<15>
//
module _0_0tmpl_0_0dataflow__neuro_0_0buffer_315_4(\in.d.d[0].d[0] , \in.d.d[0].d[1] , \in.d.d[1].d[0] , \in.d.d[1].d[1] , \in.d.d[2].d[0] , \in.d.d[2].d[1] , \in.d.d[3].d[0] , \in.d.d[3].d[1] , \in.d.d[4].d[0] , \in.d.d[4].d[1] , \in.d.d[5].d[0] , \in.d.d[5].d[1] , \in.d.d[6].d[0] , \in.d.d[6].d[1] , \in.d.d[7].d[0] , \in.d.d[7].d[1] , \in.d.d[8].d[0] , \in.d.d[8].d[1] , \in.d.d[9].d[0] , \in.d.d[9].d[1] , \in.d.d[10].d[0] , \in.d.d[10].d[1] , \in.d.d[11].d[0] , \in.d.d[11].d[1] , \in.d.d[12].d[0] , \in.d.d[12].d[1] , \in.d.d[13].d[0] , \in.d.d[13].d[1] , \in.d.d[14].d[0] , \in.d.d[14].d[1] , \in.a , \in.v , \out.d.d[0].d[0] , \out.d.d[0].d[1] , \out.d.d[1].d[0] , \out.d.d[1].d[1] , \out.d.d[2].d[0] , \out.d.d[2].d[1] , \out.d.d[3].d[0] , \out.d.d[3].d[1] , \out.d.d[4].d[0] , \out.d.d[4].d[1] , \out.d.d[5].d[0] , \out.d.d[5].d[1] , \out.d.d[6].d[0] , \out.d.d[6].d[1] , \out.d.d[7].d[0] , \out.d.d[7].d[1] , \out.d.d[8].d[0] , \out.d.d[8].d[1] , \out.d.d[9].d[0] , \out.d.d[9].d[1] , \out.d.d[10].d[0] , \out.d.d[10].d[1] , \out.d.d[11].d[0] , \out.d.d[11].d[1] , \out.d.d[12].d[0] , \out.d.d[12].d[1] , \out.d.d[13].d[0] , \out.d.d[13].d[1] , \out.d.d[14].d[0] , \out.d.d[14].d[1] , \out.a , \out.v , reset_B, vdd, vss);
input vdd;
input vss;
input \in.d.d[0].d[0] ;
input \in.d.d[0].d[1] ;
input \in.d.d[1].d[0] ;
input \in.d.d[1].d[1] ;
input \in.d.d[2].d[0] ;
input \in.d.d[2].d[1] ;
input \in.d.d[3].d[0] ;
input \in.d.d[3].d[1] ;
input \in.d.d[4].d[0] ;
input \in.d.d[4].d[1] ;
input \in.d.d[5].d[0] ;
input \in.d.d[5].d[1] ;
input \in.d.d[6].d[0] ;
input \in.d.d[6].d[1] ;
input \in.d.d[7].d[0] ;
input \in.d.d[7].d[1] ;
input \in.d.d[8].d[0] ;
input \in.d.d[8].d[1] ;
input \in.d.d[9].d[0] ;
input \in.d.d[9].d[1] ;
input \in.d.d[10].d[0] ;
input \in.d.d[10].d[1] ;
input \in.d.d[11].d[0] ;
input \in.d.d[11].d[1] ;
input \in.d.d[12].d[0] ;
input \in.d.d[12].d[1] ;
input \in.d.d[13].d[0] ;
input \in.d.d[13].d[1] ;
input \in.d.d[14].d[0] ;
input \in.d.d[14].d[1] ;
output \in.a ;
output \in.v ;
output \out.d.d[0].d[0] ;
output \out.d.d[0].d[1] ;
output \out.d.d[1].d[0] ;
output \out.d.d[1].d[1] ;
output \out.d.d[2].d[0] ;
output \out.d.d[2].d[1] ;
output \out.d.d[3].d[0] ;
output \out.d.d[3].d[1] ;
output \out.d.d[4].d[0] ;
output \out.d.d[4].d[1] ;
output \out.d.d[5].d[0] ;
output \out.d.d[5].d[1] ;
output \out.d.d[6].d[0] ;
output \out.d.d[6].d[1] ;
output \out.d.d[7].d[0] ;
output \out.d.d[7].d[1] ;
output \out.d.d[8].d[0] ;
output \out.d.d[8].d[1] ;
output \out.d.d[9].d[0] ;
output \out.d.d[9].d[1] ;
output \out.d.d[10].d[0] ;
output \out.d.d[10].d[1] ;
output \out.d.d[11].d[0] ;
output \out.d.d[11].d[1] ;
output \out.d.d[12].d[0] ;
output \out.d.d[12].d[1] ;
output \out.d.d[13].d[0] ;
output \out.d.d[13].d[1] ;
output \out.d.d[14].d[0] ;
output \out.d.d[14].d[1] ;
input \out.a ;
input \out.v ;
input reset_B;
// -- signals ---
reg \out.d.d[8].d[0] ;
reg \out.d.d[6].d[1] ;
reg \out.d.d[5].d[1] ;
reg \_en_X_f[0] ;
wire \in.d.d[14].d[0] ;
wire \in.d.d[12].d[1] ;
reg \out.d.d[12].d[1] ;
wire \in.d.d[5].d[0] ;
reg \out.d.d[11].d[0] ;
reg \out.d.d[7].d[0] ;
reg _reset_BX;
reg \_reset_BXX[0] ;
wire \in.d.d[14].d[1] ;
wire \in.d.d[10].d[1] ;
wire \in.d.d[2].d[0] ;
wire \out.a ;
reg \out.d.d[0].d[0] ;
wire \in.d.d[0].d[0] ;
reg \out.d.d[10].d[1] ;
wire \in.d.d[11].d[0] ;
wire \in.d.d[7].d[1] ;
wire \in.d.d[3].d[1] ;
reg _in_v;
reg \in.v ;
reg _out_a_B;
wire \in.d.d[9].d[1] ;
wire \in.d.d[9].d[0] ;
wire \in.d.d[4].d[1] ;
reg \out.d.d[10].d[0] ;
wire \in.d.d[1].d[1] ;
wire \in.d.d[12].d[0] ;
wire \in.d.d[1].d[0] ;
reg \_out_a_BX_f[0] ;
reg \out.d.d[3].d[1] ;
reg \out.d.d[0].d[1] ;
reg \out.d.d[2].d[1] ;
reg \out.d.d[4].d[1] ;
wire reset_B;
wire \in.d.d[8].d[0] ;
reg \out.d.d[12].d[0] ;
wire \in.d.d[5].d[1] ;
reg \out.d.d[9].d[0] ;
reg \out.d.d[7].d[1] ;
reg \_out_a_BX_t[0] ;
wire \in.d.d[10].d[0] ;
reg \out.d.d[1].d[0] ;
wire \in.d.d[6].d[0] ;
wire \in.d.d[7].d[0] ;
wire \in.d.d[13].d[1] ;
wire \out.v ;
reg \out.d.d[2].d[0] ;
wire \in.d.d[13].d[0] ;
wire \in.d.d[11].d[1] ;
wire \in.d.d[6].d[1] ;
reg \out.d.d[3].d[0] ;
reg \out.d.d[11].d[1] ;
reg \out.d.d[9].d[1] ;
wire \in.d.d[3].d[0] ;
reg _en;
reg \out.d.d[13].d[0] ;
reg \out.d.d[5].d[0] ;
reg \in.a ;
reg \out.d.d[14].d[0] ;
reg \out.d.d[4].d[0] ;
wire \in.d.d[8].d[1] ;
reg \out.d.d[13].d[1] ;
reg \out.d.d[8].d[1] ;
reg \out.d.d[14].d[1] ;
wire \in.d.d[2].d[1] ;
reg \out.d.d[6].d[0] ;
wire \in.d.d[4].d[0] ;
reg \out.d.d[1].d[1] ;
reg \_en_X_t[0] ;
wire \in.d.d[0].d[1] ;
// --- instances
_0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 \out_a_B_buf_t (.in(_out_a_B), .\out[0] (\_out_a_BX_f[0] ), .vdd(vdd), .vss(vss));
A_3C_RB_X4 \inack_ctl (.y(\in.a ), .c1(_en), .c2(\in.v ), .c3(\out.v ), .pr_B(_reset_BX), .sr_B(_reset_BX), .vdd(vdd), .vss(vss));
_0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 \reset_bufarray (.in(_reset_BX), .\out[0] (\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
BUF_X4 \in_v_buf (.y(\in.v ), .a(_in_v), .vdd(vdd), .vss(vss));
INV_X1 \out_a_inv (.y(_out_a_B), .a(\out.a ), .vdd(vdd), .vss(vss));
_0_0tmpl_0_0dataflow__neuro_0_0vtree_315_4 \vc (.\in.d[0].d[0] (\in.d.d[0].d[0] ), .\in.d[0].d[1] (\in.d.d[0].d[1] ), .\in.d[1].d[0] (\in.d.d[1].d[0] ), .\in.d[1].d[1] (\in.d.d[1].d[1] ), .\in.d[2].d[0] (\in.d.d[2].d[0] ), .\in.d[2].d[1] (\in.d.d[2].d[1] ), .\in.d[3].d[0] (\in.d.d[3].d[0] ), .\in.d[3].d[1] (\in.d.d[3].d[1] ), .\in.d[4].d[0] (\in.d.d[4].d[0] ), .\in.d[4].d[1] (\in.d.d[4].d[1] ), .\in.d[5].d[0] (\in.d.d[5].d[0] ), .\in.d[5].d[1] (\in.d.d[5].d[1] ), .\in.d[6].d[0] (\in.d.d[6].d[0] ), .\in.d[6].d[1] (\in.d.d[6].d[1] ), .\in.d[7].d[0] (\in.d.d[7].d[0] ), .\in.d[7].d[1] (\in.d.d[7].d[1] ), .\in.d[8].d[0] (\in.d.d[8].d[0] ), .\in.d[8].d[1] (\in.d.d[8].d[1] ), .\in.d[9].d[0] (\in.d.d[9].d[0] ), .\in.d[9].d[1] (\in.d.d[9].d[1] ), .\in.d[10].d[0] (\in.d.d[10].d[0] ), .\in.d[10].d[1] (\in.d.d[10].d[1] ), .\in.d[11].d[0] (\in.d.d[11].d[0] ), .\in.d[11].d[1] (\in.d.d[11].d[1] ), .\in.d[12].d[0] (\in.d.d[12].d[0] ), .\in.d[12].d[1] (\in.d.d[12].d[1] ), .\in.d[13].d[0] (\in.d.d[13].d[0] ), .\in.d[13].d[1] (\in.d.d[13].d[1] ), .\in.d[14].d[0] (\in.d.d[14].d[0] ), .\in.d[14].d[1] (\in.d.d[14].d[1] ), .out(_in_v), .vdd(vdd), .vss(vss));
_0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 \out_a_B_buf_f (.in(_out_a_B), .\out[0] (\_out_a_BX_t[0] ), .vdd(vdd), .vss(vss));
A_1C1P_X1 \en_ctl (.y(_en), .c1(\in.a ), .p1(\out.v ), .vdd(vdd), .vss(vss));
BUF_X1 \reset_buf (.y(_reset_BX), .a(reset_B), .vdd(vdd), .vss(vss));
_0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 \en_buf_f (.in(_en), .\out[0] (\_en_X_f[0] ), .vdd(vdd), .vss(vss));
_0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 \en_buf_t (.in(_en), .\out[0] (\_en_X_t[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \t_buf_func[0] (.y(\out.d.d[0].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[0].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \t_buf_func[1] (.y(\out.d.d[1].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[1].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \t_buf_func[2] (.y(\out.d.d[2].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[2].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \t_buf_func[3] (.y(\out.d.d[3].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[3].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \t_buf_func[4] (.y(\out.d.d[4].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[4].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \t_buf_func[5] (.y(\out.d.d[5].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[5].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \t_buf_func[6] (.y(\out.d.d[6].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[6].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \t_buf_func[7] (.y(\out.d.d[7].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[7].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \t_buf_func[8] (.y(\out.d.d[8].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[8].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \t_buf_func[9] (.y(\out.d.d[9].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[9].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \t_buf_func[10] (.y(\out.d.d[10].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[10].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \t_buf_func[11] (.y(\out.d.d[11].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[11].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \t_buf_func[12] (.y(\out.d.d[12].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[12].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \t_buf_func[13] (.y(\out.d.d[13].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[13].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \t_buf_func[14] (.y(\out.d.d[14].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[14].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \f_buf_func[0] (.y(\out.d.d[0].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[0].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \f_buf_func[1] (.y(\out.d.d[1].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[1].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \f_buf_func[2] (.y(\out.d.d[2].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[2].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \f_buf_func[3] (.y(\out.d.d[3].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[3].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \f_buf_func[4] (.y(\out.d.d[4].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[4].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \f_buf_func[5] (.y(\out.d.d[5].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[5].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \f_buf_func[6] (.y(\out.d.d[6].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[6].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \f_buf_func[7] (.y(\out.d.d[7].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[7].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \f_buf_func[8] (.y(\out.d.d[8].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[8].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \f_buf_func[9] (.y(\out.d.d[9].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[9].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \f_buf_func[10] (.y(\out.d.d[10].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[10].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \f_buf_func[11] (.y(\out.d.d[11].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[11].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \f_buf_func[12] (.y(\out.d.d[12].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[12].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \f_buf_func[13] (.y(\out.d.d[13].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[13].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \f_buf_func[14] (.y(\out.d.d[14].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[14].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
endmodule
//
// Verilog module for: buffer_15<>
//
module buffer__15(\in.d.d[0].d[0] , \in.d.d[0].d[1] , \in.d.d[1].d[0] , \in.d.d[1].d[1] , \in.d.d[2].d[0] , \in.d.d[2].d[1] , \in.d.d[3].d[0] , \in.d.d[3].d[1] , \in.d.d[4].d[0] , \in.d.d[4].d[1] , \in.d.d[5].d[0] , \in.d.d[5].d[1] , \in.d.d[6].d[0] , \in.d.d[6].d[1] , \in.d.d[7].d[0] , \in.d.d[7].d[1] , \in.d.d[8].d[0] , \in.d.d[8].d[1] , \in.d.d[9].d[0] , \in.d.d[9].d[1] , \in.d.d[10].d[0] , \in.d.d[10].d[1] , \in.d.d[11].d[0] , \in.d.d[11].d[1] , \in.d.d[12].d[0] , \in.d.d[12].d[1] , \in.d.d[13].d[0] , \in.d.d[13].d[1] , \in.d.d[14].d[0] , \in.d.d[14].d[1] , \in.a , \in.v , \out.d.d[0].d[0] , \out.d.d[0].d[1] , \out.d.d[1].d[0] , \out.d.d[1].d[1] , \out.d.d[2].d[0] , \out.d.d[2].d[1] , \out.d.d[3].d[0] , \out.d.d[3].d[1] , \out.d.d[4].d[0] , \out.d.d[4].d[1] , \out.d.d[5].d[0] , \out.d.d[5].d[1] , \out.d.d[6].d[0] , \out.d.d[6].d[1] , \out.d.d[7].d[0] , \out.d.d[7].d[1] , \out.d.d[8].d[0] , \out.d.d[8].d[1] , \out.d.d[9].d[0] , \out.d.d[9].d[1] , \out.d.d[10].d[0] , \out.d.d[10].d[1] , \out.d.d[11].d[0] , \out.d.d[11].d[1] , \out.d.d[12].d[0] , \out.d.d[12].d[1] , \out.d.d[13].d[0] , \out.d.d[13].d[1] , \out.d.d[14].d[0] , \out.d.d[14].d[1] , \out.a , \out.v , vdd, vss);
input vdd;
input vss;
input \in.d.d[0].d[0] ;
input \in.d.d[0].d[1] ;
input \in.d.d[1].d[0] ;
input \in.d.d[1].d[1] ;
input \in.d.d[2].d[0] ;
input \in.d.d[2].d[1] ;
input \in.d.d[3].d[0] ;
input \in.d.d[3].d[1] ;
input \in.d.d[4].d[0] ;
input \in.d.d[4].d[1] ;
input \in.d.d[5].d[0] ;
input \in.d.d[5].d[1] ;
input \in.d.d[6].d[0] ;
input \in.d.d[6].d[1] ;
input \in.d.d[7].d[0] ;
input \in.d.d[7].d[1] ;
input \in.d.d[8].d[0] ;
input \in.d.d[8].d[1] ;
input \in.d.d[9].d[0] ;
input \in.d.d[9].d[1] ;
input \in.d.d[10].d[0] ;
input \in.d.d[10].d[1] ;
input \in.d.d[11].d[0] ;
input \in.d.d[11].d[1] ;
input \in.d.d[12].d[0] ;
input \in.d.d[12].d[1] ;
input \in.d.d[13].d[0] ;
input \in.d.d[13].d[1] ;
input \in.d.d[14].d[0] ;
input \in.d.d[14].d[1] ;
output \in.a ;
output \in.v ;
output \out.d.d[0].d[0] ;
output \out.d.d[0].d[1] ;
output \out.d.d[1].d[0] ;
output \out.d.d[1].d[1] ;
output \out.d.d[2].d[0] ;
output \out.d.d[2].d[1] ;
output \out.d.d[3].d[0] ;
output \out.d.d[3].d[1] ;
output \out.d.d[4].d[0] ;
output \out.d.d[4].d[1] ;
output \out.d.d[5].d[0] ;
output \out.d.d[5].d[1] ;
output \out.d.d[6].d[0] ;
output \out.d.d[6].d[1] ;
output \out.d.d[7].d[0] ;
output \out.d.d[7].d[1] ;
output \out.d.d[8].d[0] ;
output \out.d.d[8].d[1] ;
output \out.d.d[9].d[0] ;
output \out.d.d[9].d[1] ;
output \out.d.d[10].d[0] ;
output \out.d.d[10].d[1] ;
output \out.d.d[11].d[0] ;
output \out.d.d[11].d[1] ;
output \out.d.d[12].d[0] ;
output \out.d.d[12].d[1] ;
output \out.d.d[13].d[0] ;
output \out.d.d[13].d[1] ;
output \out.d.d[14].d[0] ;
output \out.d.d[14].d[1] ;
input \out.a ;
input \out.v ;
// -- signals ---
reg \out.d.d[2].d[1] ;
wire \in.d.d[10].d[0] ;
reg \out.d.d[1].d[0] ;
wire \in.d.d[10].d[1] ;
wire \in.d.d[4].d[0] ;
reg \out.d.d[10].d[1] ;
wire \in.d.d[13].d[0] ;
reg \out.d.d[13].d[0] ;
reg \out.d.d[9].d[1] ;
wire \in.d.d[2].d[1] ;
reg \out.d.d[2].d[0] ;
reg \out.d.d[0].d[0] ;
reg \out.d.d[14].d[0] ;
reg \out.d.d[5].d[0] ;
reg \in.a ;
reg _reset_B;
wire \out.v ;
wire \out.a ;
reg \out.d.d[4].d[0] ;
wire \in.d.d[9].d[1] ;
wire \in.d.d[3].d[0] ;
wire \in.d.d[11].d[0] ;
wire \in.d.d[2].d[0] ;
reg \out.d.d[6].d[0] ;
reg \out.d.d[13].d[1] ;
reg \out.d.d[10].d[0] ;
reg \out.d.d[7].d[1] ;
wire \in.d.d[12].d[1] ;
wire \in.d.d[6].d[1] ;
reg \out.d.d[7].d[0] ;
reg \out.d.d[3].d[0] ;
wire \in.d.d[1].d[0] ;
reg \out.d.d[14].d[1] ;
reg \out.d.d[8].d[0] ;
wire \in.d.d[13].d[1] ;
wire \in.d.d[7].d[0] ;
reg \out.d.d[12].d[0] ;
wire \in.d.d[8].d[1] ;
reg \out.d.d[4].d[1] ;
wire \in.d.d[14].d[0] ;
wire \in.d.d[5].d[1] ;
wire \in.d.d[1].d[1] ;
wire \in.d.d[9].d[0] ;
wire \in.d.d[14].d[1] ;
reg \out.d.d[11].d[0] ;
reg \out.d.d[6].d[1] ;
wire \in.d.d[12].d[0] ;
wire \in.d.d[7].d[1] ;
reg \out.d.d[0].d[1] ;
wire \in.d.d[11].d[1] ;
wire \in.d.d[8].d[0] ;
wire \in.d.d[5].d[0] ;
reg \out.d.d[1].d[1] ;
reg \in.v ;
wire \in.d.d[0].d[1] ;
wire \in.d.d[0].d[0] ;
reg \out.d.d[5].d[1] ;
reg \out.d.d[8].d[1] ;
reg \out.d.d[3].d[1] ;
wire \in.d.d[6].d[0] ;
reg \out.d.d[11].d[1] ;
wire \in.d.d[3].d[1] ;
reg \out.d.d[12].d[1] ;
wire \in.d.d[4].d[1] ;
reg \out.d.d[9].d[0] ;
// --- instances
_0_0tmpl_0_0dataflow__neuro_0_0buffer_315_4 \buffer_test (.\in.d.d[0].d[0] (\in.d.d[0].d[0] ), .\in.d.d[0].d[1] (\in.d.d[0].d[1] ), .\in.d.d[1].d[0] (\in.d.d[1].d[0] ), .\in.d.d[1].d[1] (\in.d.d[1].d[1] ), .\in.d.d[2].d[0] (\in.d.d[2].d[0] ), .\in.d.d[2].d[1] (\in.d.d[2].d[1] ), .\in.d.d[3].d[0] (\in.d.d[3].d[0] ), .\in.d.d[3].d[1] (\in.d.d[3].d[1] ), .\in.d.d[4].d[0] (\in.d.d[4].d[0] ), .\in.d.d[4].d[1] (\in.d.d[4].d[1] ), .\in.d.d[5].d[0] (\in.d.d[5].d[0] ), .\in.d.d[5].d[1] (\in.d.d[5].d[1] ), .\in.d.d[6].d[0] (\in.d.d[6].d[0] ), .\in.d.d[6].d[1] (\in.d.d[6].d[1] ), .\in.d.d[7].d[0] (\in.d.d[7].d[0] ), .\in.d.d[7].d[1] (\in.d.d[7].d[1] ), .\in.d.d[8].d[0] (\in.d.d[8].d[0] ), .\in.d.d[8].d[1] (\in.d.d[8].d[1] ), .\in.d.d[9].d[0] (\in.d.d[9].d[0] ), .\in.d.d[9].d[1] (\in.d.d[9].d[1] ), .\in.d.d[10].d[0] (\in.d.d[10].d[0] ), .\in.d.d[10].d[1] (\in.d.d[10].d[1] ), .\in.d.d[11].d[0] (\in.d.d[11].d[0] ), .\in.d.d[11].d[1] (\in.d.d[11].d[1] ), .\in.d.d[12].d[0] (\in.d.d[12].d[0] ), .\in.d.d[12].d[1] (\in.d.d[12].d[1] ), .\in.d.d[13].d[0] (\in.d.d[13].d[0] ), .\in.d.d[13].d[1] (\in.d.d[13].d[1] ), .\in.d.d[14].d[0] (\in.d.d[14].d[0] ), .\in.d.d[14].d[1] (\in.d.d[14].d[1] ), .\in.a (\in.a ), .\in.v (\in.v ), .\out.d.d[0].d[0] (\out.d.d[0].d[0] ), .\out.d.d[0].d[1] (\out.d.d[0].d[1] ), .\out.d.d[1].d[0] (\out.d.d[1].d[0] ), .\out.d.d[1].d[1] (\out.d.d[1].d[1] ), .\out.d.d[2].d[0] (\out.d.d[2].d[0] ), .\out.d.d[2].d[1] (\out.d.d[2].d[1] ), .\out.d.d[3].d[0] (\out.d.d[3].d[0] ), .\out.d.d[3].d[1] (\out.d.d[3].d[1] ), .\out.d.d[4].d[0] (\out.d.d[4].d[0] ), .\out.d.d[4].d[1] (\out.d.d[4].d[1] ), .\out.d.d[5].d[0] (\out.d.d[5].d[0] ), .\out.d.d[5].d[1] (\out.d.d[5].d[1] ), .\out.d.d[6].d[0] (\out.d.d[6].d[0] ), .\out.d.d[6].d[1] (\out.d.d[6].d[1] ), .\out.d.d[7].d[0] (\out.d.d[7].d[0] ), .\out.d.d[7].d[1] (\out.d.d[7].d[1] ), .\out.d.d[8].d[0] (\out.d.d[8].d[0] ), .\out.d.d[8].d[1] (\out.d.d[8].d[1] ), .\out.d.d[9].d[0] (\out.d.d[9].d[0] ), .\out.d.d[9].d[1] (\out.d.d[9].d[1] ), .\out.d.d[10].d[0] (\out.d.d[10].d[0] ), .\out.d.d[10].d[1] (\out.d.d[10].d[1] ), .\out.d.d[11].d[0] (\out.d.d[11].d[0] ), .\out.d.d[11].d[1] (\out.d.d[11].d[1] ), .\out.d.d[12].d[0] (\out.d.d[12].d[0] ), .\out.d.d[12].d[1] (\out.d.d[12].d[1] ), .\out.d.d[13].d[0] (\out.d.d[13].d[0] ), .\out.d.d[13].d[1] (\out.d.d[13].d[1] ), .\out.d.d[14].d[0] (\out.d.d[14].d[0] ), .\out.d.d[14].d[1] (\out.d.d[14].d[1] ), .\out.a (\out.a ), .\out.v (\out.v ), .reset_B(_reset_B), .vdd(vdd), .vss(vss));
endmodule

355
test/unit_tests/decoder_2d_dly_8_16/run/prsim.out
View File

@@ -1,355 +0,0 @@
b.b.addr_buf.vc.ct.in[1] b.b.dly.dly[9].__y b.b.addr_buf.out_a_B_buf_f.buf2._y b.b.addr_buf.vc.OR2_tf[6]._y b.b.addr_buf.vc.ct.in[0] b.b.addr_buf.vc.ct.C2Els[1]._y b.dly_cfg[2] b.in.d.d[4].f b.b.addr_buf._out_a_BX_f[0] b.in.d.d[1].f b.b.dly._a[1] b.in.d.d[1].t b.b.addr_buf.vc.ct.tmp[8] b.in.d.d[6].t b.b.addr_buf.vc.ct.in[6] b.b.addr_buf.in_v_buf._y b.b.addr_buf._in_v b.dly_cfg[3] b.b.dly.dly[10].y b.b.dly.dly[6]._y b.in.d.d[3].t b.b.dly.dly[7].y b.in.d.d[4].t b.b.addr_buf.vc.ct.in[4] b.b.dly._a[3] b.b.dly.dly[5].y b.in.d.d[3].f b.in.v b.b.addr_buf.vc.ct.tmp[9] b.b.dly.dly[9].___y b.b.addr_buf._out_a_BX_t[0] b.b.addr_buf.vc.ct.in[2] b.b.dly.dly[14].___y b.in.d.d[0].f b.b.dly.mu2[0]._y b.b.dly.dly[6].___y b.b.dly.mu2[3]._y b.b.dly.and2[3]._y b.in.d.d[5].t b.b.dly.dly[14].__y b.b.dly.mu2[2]._y b.in.d.d[0].t b.in.d.d[6].f b.b.addr_buf._out_a_B b.in.d.d[2].t b.b.addr_buf.vc.ct.tmp[7] b.b.dly.dly[7]._y b.b.dly.out b.b.dly.dly[4].__y b.b.dly.dly[12].__y b.b.dly.dly[1].y b.b.dly.dly[14]._y b.b.addr_buf.vc.ct.in[5] b.b.addr_buf.vc.OR2_tf[4]._y b.b.dly.dly[3].a b.b.dly.mu2[3].b b.in.d.d[5].f b.dly_cfg[1] b.b.dly.dly[7].a b.b.dly.dly[8].y b.b.dly.dly[3].___y b.b.dly._a[2] b.b.addr_buf.vc.ct.C3Els[1]._y b.b.dly.dly[1].a b.in.d.d[2].f b.b.addr_buf.vc.ct.in[3] b.b.dly.dly[3]._y b.b.dly.dly[10].__y b.b.dly.dly[1]._y b.b.dly.dly[11]._y b.b.dly.and2[1]._y b.b.dly.dly[9].y b.b.addr_buf.out_a_B_buf_t.buf2._y b.b.dly.dly[13]._y b.b.addr_buf.vc.OR2_tf[3]._y b.b.dly.dly[5].___y b.b.dly.dly[13].__y b.b.dly.dly[11].__y b.b.dly.dly[13].y b.b.dly.dly[4]._y b.b.dly.dly[11].y b.b.dly.dly[7].___y b.b.dly.dly[8].__y b.b.dly.dly[4].___y b.b.dly.dly[8]._y b.dly_cfg[0] b.b.dly.dly[12].___y b.b.dly.dly[12].y b.b.addr_buf.vc.OR2_tf[2]._y b.b.dly.dly[6].y b.b.dly.dly[2].y b.b.dly.mu2[1]._s b.b.dly.dly[4].y b.b.dly.dly[13].___y b.b.addr_buf.vc.OR2_tf[5]._y b.b.dly.dly[12]._y b.b.dly.dly[2].___y b.b.dly.mu2[2]._s b.b.dly.dly[10].___y b.b.dly.dly[6].__y b.b.dly.dly[3].y b.b.dly.dly[5].__y b.b.dly.mu2[0]._s b.b.addr_buf.vc.OR2_tf[0]._y b.b.dly.mu2[1]._y b.b.dly.mu2[3]._s b.b.dly.dly[1].___y b.b.dly.dly[2]._y b.b.dly.dly[7].__y b.b.dly.dly[8].___y b.b.addr_buf.vc.ct.C2Els[0]._y b.b.dly.dly[5]._y b.b.addr_buf.vc.ct.C3Els[0]._y b.b.dly.dly[1].__y b.b.addr_buf.vc.OR2_tf[1]._y b.b.dly.and2[2]._y b.b.dly.dly[11].___y b.b.dly.dly[2].__y b.b.dly.dly[3].__y b.b.dly.dly[9]._y b.b.dly.dly[10]._y
175726 b.in.d.d[0].f : 0
175726 b.dly_cfg[3] : 0
175726 b.dly_cfg[2] : 0
175726 b.in.d.d[1].f : 0
175726 b.in.d.d[3].f : 0
175726 b.b.dly.out : 0
175726 b.in.d.d[6].t : 0
175726 b.in.d.d[2].t : 0
175726 b.dly_cfg[1] : 1
175726 b.dly_cfg[0] : 1
175726 b.in.d.d[6].f : 0
175726 b.in.d.d[5].t : 0
175726 b.in.d.d[0].t : 0
175726 Reset : 0
175726 b.in.d.d[2].f : 0
175726 b.in.d.d[5].f : 0
175726 b.in.d.d[4].t : 0
175726 b.in.d.d[1].t : 0
175726 b.in.d.d[4].f : 0
175726 b.in.d.d[3].t : 0
175727 b.b.dly.mu2[3]._s : 1 [by b.dly_cfg[3]:=0]
175730 b.b.addr_buf.vc.OR2_tf[5]._y : 1 [by b.in.d.d[5].f:=0]
175734 b.b.addr_buf.vc.OR2_tf[6]._y : 1 [by b.in.d.d[6].f:=0]
175760 b.b.addr_buf.vc.OR2_tf[0]._y : 1 [by b.in.d.d[0].t:=0]
175763 b.b.addr_buf.vc.ct.in[0] : 0 [by b.b.addr_buf.vc.OR2_tf[0]._y:=1]
175768 b.b.dly.and2[2]._y : 1 [by b.dly_cfg[2]:=0]
175782 b.b.addr_buf.vc.ct.in[6] : 0 [by b.b.addr_buf.vc.OR2_tf[6]._y:=1]
175821 b.b.dly.mu2[1]._s : 0 [by b.dly_cfg[1]:=1]
175946 b.b.dly.dly[3].a : 0 [by b.b.dly.and2[2]._y:=1]
176061 b.b.dly.mu2[0]._s : 0 [by b.dly_cfg[0]:=1]
176644 b.b.addr_buf.vc.OR2_tf[2]._y : 1 [by b.in.d.d[2].f:=0]
178124 b.b.addr_buf.vc.OR2_tf[4]._y : 1 [by b.in.d.d[4].f:=0]
178543 b.b.dly.mu2[2]._s : 1 [by b.dly_cfg[2]:=0]
178941 b.b.addr_buf.vc.OR2_tf[3]._y : 1 [by b.in.d.d[3].t:=0]
179768 b.b.addr_buf.vc.ct.in[3] : 0 [by b.b.addr_buf.vc.OR2_tf[3]._y:=1]
182595 b.b.addr_buf.vc.ct.in[2] : 0 [by b.b.addr_buf.vc.OR2_tf[2]._y:=1]
182768 b.b.addr_buf.vc.ct.C2Els[1]._y : 1 [by b.b.addr_buf.vc.ct.in[2]:=0]
182952 b.b.addr_buf.vc.ct.tmp[8] : 0 [by b.b.addr_buf.vc.ct.C2Els[1]._y:=1]
187960 b.b.dly.mu2[0]._y : 1 [by b.b.dly.mu2[0]._s:=0]
187961 b.b.dly._a[1] : 0 [by b.b.dly.mu2[0]._y:=1]
188034 b.b.dly.and2[1]._y : 1 [by b.b.dly._a[1]:=0]
188038 b.b.dly.dly[1].a : 0 [by b.b.dly.and2[1]._y:=1]
189459 b.b.addr_buf._out_a_B : 1 [by b.b.dly.out:=0]
189555 b.b.addr_buf.out_a_B_buf_t.buf2._y : 0 [by b.b.addr_buf._out_a_B:=1]
189556 b.b.addr_buf._out_a_BX_f[0] : 1 [by b.b.addr_buf.out_a_B_buf_t.buf2._y:=0]
189595 b.b.addr_buf.out_a_B_buf_f.buf2._y : 0 [by b.b.addr_buf._out_a_B:=1]
189613 b._reset_B : 1 [by Reset:=0]
189854 b.b.addr_buf.reset_buf._y : 0 [by b._reset_B:=1]
193813 b.b.addr_buf._reset_BX : 1 [by b.b.addr_buf.reset_buf._y:=0]
193825 b.b.addr_buf.reset_bufarray.buf2._y : 0 [by b.b.addr_buf._reset_BX:=1]
196923 b.b.dly.dly[3]._y : 1 [by b.b.dly.dly[3].a:=0]
197725 b.b.addr_buf._reset_BXX[0] : 1 [by b.b.addr_buf.reset_bufarray.buf2._y:=0]
197952 b.b.dly.dly[3].__y : 0 [by b.b.dly.dly[3]._y:=1]
197953 b.b.dly.dly[3].___y : 1 [by b.b.dly.dly[3].__y:=0]
198009 b.b.dly.dly[3].y : 0 [by b.b.dly.dly[3].___y:=1]
208641 b.b.addr_buf._out_a_BX_t[0] : 1 [by b.b.addr_buf.out_a_B_buf_f.buf2._y:=0]
217609 b.b.addr_buf.vc.ct.in[4] : 0 [by b.b.addr_buf.vc.OR2_tf[4]._y:=1]
222104 b.b.addr_buf.vc.OR2_tf[1]._y : 1 [by b.in.d.d[1].t:=0]
222105 b.b.addr_buf.vc.ct.in[1] : 0 [by b.b.addr_buf.vc.OR2_tf[1]._y:=1]
222142 b.b.addr_buf.vc.ct.C2Els[0]._y : 1 [by b.b.addr_buf.vc.ct.in[1]:=0]
222849 b.b.addr_buf.vc.ct.in[5] : 0 [by b.b.addr_buf.vc.OR2_tf[5]._y:=1]
222850 b.b.addr_buf.vc.ct.C3Els[0]._y : 1 [by b.b.addr_buf.vc.ct.in[5]:=0]
225326 b.b.dly.dly[1]._y : 1 [by b.b.dly.dly[1].a:=0]
226414 b.b.addr_buf.vc.ct.tmp[9] : 0 [by b.b.addr_buf.vc.ct.C3Els[0]._y:=1]
227018 b.b.dly.dly[1].__y : 0 [by b.b.dly.dly[1]._y:=1]
227031 b.b.dly.dly[1].___y : 1 [by b.b.dly.dly[1].__y:=0]
234688 b.b.dly.and2[3]._y : 1 [by b.dly_cfg[3]:=0]
235045 b.b.dly.dly[7].a : 0 [by b.b.dly.and2[3]._y:=1]
235070 b.b.dly.dly[7]._y : 1 [by b.b.dly.dly[7].a:=0]
235091 b.b.dly.dly[7].__y : 0 [by b.b.dly.dly[7]._y:=1]
235092 b.b.dly.dly[7].___y : 1 [by b.b.dly.dly[7].__y:=0]
243015 b.b.dly.dly[4]._y : 1 [by b.b.dly.dly[3].y:=0]
243016 b.b.dly.dly[4].__y : 0 [by b.b.dly.dly[4]._y:=1]
243017 b.b.dly.dly[4].___y : 1 [by b.b.dly.dly[4].__y:=0]
243178 b.b.dly.dly[4].y : 0 [by b.b.dly.dly[4].___y:=1]
244015 b.b.dly.dly[1].y : 0 [by b.b.dly.dly[1].___y:=1]
244020 b.b.dly.dly[2]._y : 1 [by b.b.dly.dly[1].y:=0]
244215 b.b.dly.dly[5]._y : 1 [by b.b.dly.dly[4].y:=0]
244601 b.b.dly.dly[2].__y : 0 [by b.b.dly.dly[2]._y:=1]
244612 b.b.dly.dly[2].___y : 1 [by b.b.dly.dly[2].__y:=0]
244623 b.b.dly.dly[5].__y : 0 [by b.b.dly.dly[5]._y:=1]
244637 b.b.dly.dly[5].___y : 1 [by b.b.dly.dly[5].__y:=0]
244655 b.b.dly.dly[5].y : 0 [by b.b.dly.dly[5].___y:=1]
244659 b.b.dly.dly[6]._y : 1 [by b.b.dly.dly[5].y:=0]
244740 b.b.dly.dly[7].y : 0 [by b.b.dly.dly[7].___y:=1]
244763 b.b.dly.dly[6].__y : 0 [by b.b.dly.dly[6]._y:=1]
245517 b.b.addr_buf.vc.ct.tmp[7] : 0 [by b.b.addr_buf.vc.ct.C2Els[0]._y:=1]
245659 b.b.dly.dly[2].y : 0 [by b.b.dly.dly[2].___y:=1]
245887 b.b.dly.mu2[1]._y : 1 [by b.b.dly.dly[2].y:=0]
245967 b.b.dly.dly[6].___y : 1 [by b.b.dly.dly[6].__y:=0]
246730 b.b.dly._a[2] : 0 [by b.b.dly.mu2[1]._y:=1]
246800 b.b.dly.mu2[2]._y : 1 [by b.b.dly._a[2]:=0]
247426 b.b.dly.dly[6].y : 0 [by b.b.dly.dly[6].___y:=1]
253972 b.b.addr_buf.vc.ct.C3Els[1]._y : 1 [by b.b.addr_buf.vc.ct.tmp[7]:=0]
253983 b.b.addr_buf._in_v : 0 [by b.b.addr_buf.vc.ct.C3Els[1]._y:=1]
253986 b.b.addr_buf.in_v_buf._y : 1 [by b.b.addr_buf._in_v:=0]
254040 b.in.v : 0 [by b.b.addr_buf.in_v_buf._y:=1]
276184 b.b.dly.dly[8]._y : 1 [by b.b.dly.dly[7].y:=0]
277332 b.b.dly.dly[8].__y : 0 [by b.b.dly.dly[8]._y:=1]
278493 b.b.dly.dly[8].___y : 1 [by b.b.dly.dly[8].__y:=0]
287145 b.b.dly.dly[8].y : 0 [by b.b.dly.dly[8].___y:=1]
287226 b.b.dly.dly[9]._y : 1 [by b.b.dly.dly[8].y:=0]
297222 b.b.dly._a[3] : 0 [by b.b.dly.mu2[2]._y:=1]
298303 b.b.dly.dly[9].__y : 0 [by b.b.dly.dly[9]._y:=1]
298395 b.b.dly.dly[9].___y : 1 [by b.b.dly.dly[9].__y:=0]
306706 b.b.dly.dly[9].y : 0 [by b.b.dly.dly[9].___y:=1]
308450 b.b.dly.dly[10]._y : 1 [by b.b.dly.dly[9].y:=0]
309063 b.b.dly.dly[10].__y : 0 [by b.b.dly.dly[10]._y:=1]
315205 b.b.dly.mu2[3]._y : 1 [by b.b.dly._a[3]:=0]
323085 b.b.dly.dly[10].___y : 1 [by b.b.dly.dly[10].__y:=0]
323130 b.b.dly.dly[10].y : 0 [by b.b.dly.dly[10].___y:=1]
324127 b.b.dly.dly[11]._y : 1 [by b.b.dly.dly[10].y:=0]
325776 b.b.dly.dly[11].__y : 0 [by b.b.dly.dly[11]._y:=1]
326301 b.b.dly.dly[11].___y : 1 [by b.b.dly.dly[11].__y:=0]
327201 b.b.dly.dly[11].y : 0 [by b.b.dly.dly[11].___y:=1]
327253 b.b.dly.dly[12]._y : 1 [by b.b.dly.dly[11].y:=0]
327260 b.b.dly.dly[12].__y : 0 [by b.b.dly.dly[12]._y:=1]
342872 b.b.dly.dly[12].___y : 1 [by b.b.dly.dly[12].__y:=0]
349339 b.b.dly.dly[12].y : 0 [by b.b.dly.dly[12].___y:=1]
349341 b.b.dly.dly[13]._y : 1 [by b.b.dly.dly[12].y:=0]
349695 b.b.dly.dly[13].__y : 0 [by b.b.dly.dly[13]._y:=1]
349828 b.b.dly.dly[13].___y : 1 [by b.b.dly.dly[13].__y:=0]
349829 b.b.dly.dly[13].y : 0 [by b.b.dly.dly[13].___y:=1]
349833 b.b.dly.dly[14]._y : 1 [by b.b.dly.dly[13].y:=0]
350379 b.b.dly.dly[14].__y : 0 [by b.b.dly.dly[14]._y:=1]
395942 b.b.dly.dly[14].___y : 1 [by b.b.dly.dly[14].__y:=0]
395943 b.b.dly.mu2[3].b : 0 [by b.b.dly.dly[14].___y:=1]
[] set Reset 1
395943 Reset : 1
408321 b._reset_B : 0 [by Reset:=1]
408400 b.b.addr_buf.reset_buf._y : 1 [by b._reset_B:=0]
410833 b.b.addr_buf._reset_BX : 0 [by b.b.addr_buf.reset_buf._y:=1]
410921 b.b.addr_buf.reset_bufarray.buf2._y : 1 [by b.b.addr_buf._reset_BX:=0]
418703 b.b.addr_buf._reset_BXX[0] : 0 [by b.b.addr_buf.reset_bufarray.buf2._y:=1]
[] set Reset 0
418703 Reset : 0
447030 b._reset_B : 1 [by Reset:=0]
447089 b.b.addr_buf.reset_buf._y : 0 [by b._reset_B:=1]
447119 b.b.addr_buf._reset_BX : 1 [by b.b.addr_buf.reset_buf._y:=0]
448586 b.b.addr_buf.reset_bufarray.buf2._y : 0 [by b.b.addr_buf._reset_BX:=1]
508090 b.b.addr_buf._reset_BXX[0] : 1 [by b.b.addr_buf.reset_bufarray.buf2._y:=0]
[] Sending packet in
508090 b.in.d.d[0].t : 1
508090 b.in.d.d[6].t : 1
508090 b.in.d.d[2].t : 1
508090 b.in.d.d[5].t : 1
508090 b.in.d.d[1].t : 1
508090 b.in.d.d[4].t : 1
508090 b.in.d.d[3].t : 1
508091 b.b.addr_buf.t_buf_func[4]._y : 0 [by b.in.d.d[4].t:=1]
508093 b.b.addr_buf.t_buf_func[1]._y : 0 [by b.in.d.d[1].t:=1]
508095 b.b.atree_x[2].in[1] : 1 [by b.b.addr_buf.t_buf_func[1]._y:=0]
508096 b.b.vtree_x.OR2_tf[1]._y : 0 [by b.b.atree_x[2].in[1]:=1]
508102 b.b.addr_buf.vc.OR2_tf[5]._y : 0 [by b.in.d.d[5].t:=1]
508104 b.b.addr_buf.vc.ct.in[5] : 1 [by b.b.addr_buf.vc.OR2_tf[5]._y:=0]
508128 b.b.addr_buf.vc.OR2_tf[4]._y : 0 [by b.in.d.d[4].t:=1]
508133 b.b.addr_buf.t_buf_func[2]._y : 0 [by b.in.d.d[2].t:=1]
508146 b.b.addr_buf.vc.ct.in[4] : 1 [by b.b.addr_buf.vc.OR2_tf[4]._y:=0]
508182 b.b.addr_buf.t_buf_func[3]._y : 0 [by b.in.d.d[3].t:=1]
508217 b.b.addr_buf.t_buf_func[6]._y : 0 [by b.in.d.d[6].t:=1]
508225 b.b.atree_y[8].in[3] : 1 [by b.b.addr_buf.t_buf_func[6]._y:=0]
508252 b.b.atree_x[4].in[2] : 1 [by b.b.addr_buf.t_buf_func[2]._y:=0]
508259 b.b.addr_buf.vc.OR2_tf[2]._y : 0 [by b.in.d.d[2].t:=1]
508264 b.b.addr_buf.vc.ct.in[2] : 1 [by b.b.addr_buf.vc.OR2_tf[2]._y:=0]
508279 b.b.vtree_y.OR2_tf[3]._y : 0 [by b.b.atree_y[8].in[3]:=1]
508323 b.b.addr_buf.vc.OR2_tf[1]._y : 0 [by b.in.d.d[1].t:=1]
508324 b.b.addr_buf.vc.ct.in[1] : 1 [by b.b.addr_buf.vc.OR2_tf[1]._y:=0]
508775 b.b.addr_buf.t_buf_func[0]._y : 0 [by b.in.d.d[0].t:=1]
508913 b.b.atree_x[1].in[0] : 1 [by b.b.addr_buf.t_buf_func[0]._y:=0]
508914 b.b.atree_x[7].and3s[0]._y : 0 [by b.b.atree_x[1].in[0]:=1]
508977 b.b.vtree_x.OR2_tf[0]._y : 0 [by b.b.atree_x[1].in[0]:=1]
508979 b.b.vtree_x.ct.in[0] : 1 [by b.b.vtree_x.OR2_tf[0]._y:=0]
509037 b.outx[7] : 1 [by b.b.atree_x[7].and3s[0]._y:=0]
509346 b.b.vtree_y.ct.in[3] : 1 [by b.b.vtree_y.OR2_tf[3]._y:=0]
509369 b.b.addr_buf.t_buf_func[5]._y : 0 [by b.in.d.d[5].t:=1]
509406 b.b.atree_y[4].in[2] : 1 [by b.b.addr_buf.t_buf_func[5]._y:=0]
509407 b.b.vtree_y.OR2_tf[2]._y : 0 [by b.b.atree_y[4].in[2]:=1]
509416 b.b.vtree_y.ct.in[2] : 1 [by b.b.vtree_y.OR2_tf[2]._y:=0]
509417 b.b.atree_y[14].and2s[1]._y : 0 [by b.b.atree_y[4].in[2]:=1]
509441 b.b.vtree_y.ct.C2Els[1]._y : 0 [by b.b.vtree_y.ct.in[2]:=1]
509457 b.b.atree_y[12].and2s[1]._y : 0 [by b.b.atree_y[4].in[2]:=1]
509549 b.b.atree_y[15].and2s[1]._y : 0 [by b.b.atree_y[4].in[2]:=1]
509597 b.b.vtree_x.ct.in[1] : 1 [by b.b.vtree_x.OR2_tf[1]._y:=0]
509602 b.b.atree_y[12].tmp[5] : 1 [by b.b.atree_y[12].and2s[1]._y:=0]
509848 b.b.atree_y[13].and2s[1]._y : 0 [by b.b.atree_y[4].in[2]:=1]
510078 b.b.atree_y[13].tmp[5] : 1 [by b.b.atree_y[13].and2s[1]._y:=0]
510818 b.b.atree_y[2].in[1] : 1 [by b.b.addr_buf.t_buf_func[4]._y:=0]
511509 b.b.vtree_y.OR2_tf[1]._y : 0 [by b.b.atree_y[2].in[1]:=1]
511523 b.b.vtree_y.ct.in[1] : 1 [by b.b.vtree_y.OR2_tf[1]._y:=0]
512962 b.b.vtree_y.ct.tmp[5] : 1 [by b.b.vtree_y.ct.C2Els[1]._y:=0]
513902 b.b.atree_y[1].in[0] : 1 [by b.b.addr_buf.t_buf_func[3]._y:=0]
513903 b.b.vtree_y.OR2_tf[0]._y : 0 [by b.b.atree_y[1].in[0]:=1]
513904 b.b.vtree_y.ct.in[0] : 1 [by b.b.vtree_y.OR2_tf[0]._y:=0]
513913 b.b.atree_y[11].and2s[0]._y : 0 [by b.b.atree_y[1].in[0]:=1]
514552 b.b.atree_y[11].tmp[4] : 1 [by b.b.atree_y[11].and2s[0]._y:=0]
515445 b.b.atree_y[15].and2s[0]._y : 0 [by b.b.atree_y[1].in[0]:=1]
515513 b.b.atree_y[3].and2s[0]._y : 0 [by b.b.atree_y[1].in[0]:=1]
515645 b.b.atree_y[3].tmp[4] : 1 [by b.b.atree_y[3].and2s[0]._y:=0]
517238 b.b.atree_y[15].tmp[4] : 1 [by b.b.atree_y[15].and2s[0]._y:=0]
519670 b.b.atree_y[14].tmp[5] : 1 [by b.b.atree_y[14].and2s[1]._y:=0]
520405 b.b.vtree_y.ct.C2Els[0]._y : 0 [by b.b.vtree_y.ct.in[0]:=1]
520406 b.b.vtree_y.ct.tmp[4] : 1 [by b.b.vtree_y.ct.C2Els[0]._y:=0]
520423 b.b.vtree_y.ct.C2Els[2]._y : 0 [by b.b.vtree_y.ct.tmp[4]:=1]
520575 b.b.C2el.c2 : 1 [by b.b.vtree_y.ct.C2Els[2]._y:=0]
520842 b.b.addr_buf.vc.OR2_tf[3]._y : 0 [by b.in.d.d[3].t:=1]
523825 b.b.addr_buf.vc.ct.in[3] : 1 [by b.b.addr_buf.vc.OR2_tf[3]._y:=0]
523828 b.b.addr_buf.vc.ct.C2Els[1]._y : 0 [by b.b.addr_buf.vc.ct.in[3]:=1]
524252 b.b.addr_buf.vc.ct.tmp[8] : 1 [by b.b.addr_buf.vc.ct.C2Els[1]._y:=0]
524805 b.b.addr_buf.vc.OR2_tf[6]._y : 0 [by b.in.d.d[6].t:=1]
524811 b.b.addr_buf.vc.ct.in[6] : 1 [by b.b.addr_buf.vc.OR2_tf[6]._y:=0]
525717 b.b.atree_y[15].tmp[5] : 1 [by b.b.atree_y[15].and2s[1]._y:=0]
527399 b.b.addr_buf.vc.ct.C3Els[0]._y : 0 [by b.b.addr_buf.vc.ct.in[6]:=1]
527474 b.b.addr_buf.vc.OR2_tf[0]._y : 0 [by b.in.d.d[0].t:=1]
528178 b.b.atree_y[15].and2s[2]._y : 0 [by b.b.atree_y[15].tmp[5]:=1]
528180 b.outy[15] : 1 [by b.b.atree_y[15].and2s[2]._y:=0]
528229 b.b.addr_buf.vc.ct.tmp[9] : 1 [by b.b.addr_buf.vc.ct.C3Els[0]._y:=0]
531414 b.b.atree_y[7].and2s[0]._y : 0 [by b.b.atree_y[1].in[0]:=1]
531608 b.b.atree_y[7].tmp[4] : 1 [by b.b.atree_y[7].and2s[0]._y:=0]
550406 b.b.addr_buf.vc.ct.in[0] : 1 [by b.b.addr_buf.vc.OR2_tf[0]._y:=0]
551009 b.b.addr_buf.vc.ct.C2Els[0]._y : 0 [by b.b.addr_buf.vc.ct.in[0]:=1]
551147 b.b.addr_buf.vc.ct.tmp[7] : 1 [by b.b.addr_buf.vc.ct.C2Els[0]._y:=0]
551164 b.b.addr_buf.vc.ct.C3Els[1]._y : 0 [by b.b.addr_buf.vc.ct.tmp[7]:=1]
551181 b.b.addr_buf._in_v : 1 [by b.b.addr_buf.vc.ct.C3Els[1]._y:=0]
551607 b.b.addr_buf.in_v_buf._y : 0 [by b.b.addr_buf._in_v:=1]
551608 b.in.v : 1 [by b.b.addr_buf.in_v_buf._y:=0]
558790 b.b.vtree_x.OR2_tf[2]._y : 0 [by b.b.atree_x[4].in[2]:=1]
558791 b.b.vtree_x.ct.in[2] : 1 [by b.b.vtree_x.OR2_tf[2]._y:=0]
559817 b.b.vtree_x.ct.C3Els[0]._y : 0 [by b.b.vtree_x.ct.in[2]:=1]
559818 b.b.C2el.c1 : 1 [by b.b.vtree_x.ct.C3Els[0]._y:=0]
559837 b.b.C2el._y : 0 [by b.b.C2el.c1:=1]
560005 b.b.C2el.y : 1 [by b.b.C2el._y:=0]
560166 b.b.addr_buf.inack_ctl._y : 0 [by b.b.C2el.y:=1]
560339 b.in.a : 1 [by b.b.addr_buf.inack_ctl._y:=0]
560544 b.b.dly.and2[0]._y : 0 [by b.b.C2el.y:=1]
562886 b.b.addr_buf._en : 0 [by b.in.a:=1]
562887 b.b.addr_buf.en_buf_f.buf2._y : 1 [by b.b.addr_buf._en:=0]
562887 b.b.addr_buf.en_buf_t.buf2._y : 1 [by b.b.addr_buf._en:=0]
563094 b.b.addr_buf._en_X_t[0] : 0 [by b.b.addr_buf.en_buf_t.buf2._y:=1]
563277 b.b.addr_buf._en_X_f[0] : 0 [by b.b.addr_buf.en_buf_f.buf2._y:=1]
575605 b.b.dly.dly[0].a : 1 [by b.b.dly.and2[0]._y:=0]
576438 b.b.dly.dly[0]._y : 0 [by b.b.dly.dly[0].a:=1]
576466 b.b.dly.dly[0].__y : 1 [by b.b.dly.dly[0]._y:=0]
576473 b.b.dly.dly[0].___y : 0 [by b.b.dly.dly[0].__y:=1]
576887 b.b.dly.dly[0].y : 1 [by b.b.dly.dly[0].___y:=0]
576891 b.b.dly.mu2[0]._y : 0 [by b.b.dly.dly[0].y:=1]
578670 b.b.dly._a[1] : 1 [by b.b.dly.mu2[0]._y:=0]
601544 b.b.dly.and2[1]._y : 0 [by b.b.dly._a[1]:=1]
601710 b.b.dly.dly[1].a : 1 [by b.b.dly.and2[1]._y:=0]
641580 b.b.dly.dly[1]._y : 0 [by b.b.dly.dly[1].a:=1]
650225 b.b.dly.dly[1].__y : 1 [by b.b.dly.dly[1]._y:=0]
651158 b.b.dly.dly[1].___y : 0 [by b.b.dly.dly[1].__y:=1]
652014 b.b.dly.dly[1].y : 1 [by b.b.dly.dly[1].___y:=0]
652153 b.b.dly.dly[2]._y : 0 [by b.b.dly.dly[1].y:=1]
678362 b.b.dly.dly[2].__y : 1 [by b.b.dly.dly[2]._y:=0]
678557 b.b.dly.dly[2].___y : 0 [by b.b.dly.dly[2].__y:=1]
678559 b.b.dly.dly[2].y : 1 [by b.b.dly.dly[2].___y:=0]
732008 b.b.dly.mu2[1]._y : 0 [by b.b.dly.dly[2].y:=1]
732014 b.b.dly._a[2] : 1 [by b.b.dly.mu2[1]._y:=0]
732268 b.b.dly.mu2[2]._y : 0 [by b.b.dly._a[2]:=1]
732276 b.b.dly._a[3] : 1 [by b.b.dly.mu2[2]._y:=0]
732277 b.b.dly.mu2[3]._y : 0 [by b.b.dly._a[3]:=1]
732283 b.b.dly.out : 1 [by b.b.dly.mu2[3]._y:=0]
783319 b.b.addr_buf._out_a_B : 0 [by b.b.dly.out:=1]
783545 b.b.addr_buf.out_a_B_buf_f.buf2._y : 1 [by b.b.addr_buf._out_a_B:=0]
784364 b.b.addr_buf._out_a_BX_t[0] : 0 [by b.b.addr_buf.out_a_B_buf_f.buf2._y:=1]
784365 b.b.addr_buf.t_buf_func[0]._y : 1 [by b.b.addr_buf._out_a_BX_t[0]:=0]
784366 b.b.addr_buf.t_buf_func[2]._y : 1 [by b.b.addr_buf._out_a_BX_t[0]:=0]
784370 b.b.addr_buf.t_buf_func[1]._y : 1 [by b.b.addr_buf._out_a_BX_t[0]:=0]
784379 b.b.addr_buf.t_buf_func[4]._y : 1 [by b.b.addr_buf._out_a_BX_t[0]:=0]
784458 b.b.atree_x[1].in[0] : 0 [by b.b.addr_buf.t_buf_func[0]._y:=1]
784471 b.b.addr_buf.t_buf_func[6]._y : 1 [by b.b.addr_buf._out_a_BX_t[0]:=0]
784472 b.b.atree_y[8].in[3] : 0 [by b.b.addr_buf.t_buf_func[6]._y:=1]
784473 b.b.atree_y[12].and2s[1]._y : 1 [by b.b.atree_y[8].in[3]:=0]
784473 b.b.vtree_y.OR2_tf[3]._y : 1 [by b.b.atree_y[8].in[3]:=0]
784474 b.b.vtree_y.ct.in[3] : 0 [by b.b.vtree_y.OR2_tf[3]._y:=1]
784479 b.b.atree_y[12].tmp[5] : 0 [by b.b.atree_y[12].and2s[1]._y:=1]
785137 b.b.atree_y[2].in[1] : 0 [by b.b.addr_buf.t_buf_func[4]._y:=1]
785144 b.b.vtree_y.OR2_tf[1]._y : 1 [by b.b.atree_y[2].in[1]:=0]
785159 b.b.atree_y[7].and2s[0]._y : 1 [by b.b.atree_y[2].in[1]:=0]
785172 b.b.atree_y[7].tmp[4] : 0 [by b.b.atree_y[7].and2s[0]._y:=1]
785174 b.b.vtree_x.OR2_tf[0]._y : 1 [by b.b.atree_x[1].in[0]:=0]
785209 b.b.vtree_y.ct.in[1] : 0 [by b.b.vtree_y.OR2_tf[1]._y:=1]
786018 b.b.atree_x[4].in[2] : 0 [by b.b.addr_buf.t_buf_func[2]._y:=1]
786122 b.b.vtree_x.OR2_tf[2]._y : 1 [by b.b.atree_x[4].in[2]:=0]
786163 b.b.vtree_x.ct.in[2] : 0 [by b.b.vtree_x.OR2_tf[2]._y:=1]
786212 b.b.atree_y[15].and2s[1]._y : 1 [by b.b.atree_y[8].in[3]:=0]
786213 b.b.atree_y[15].tmp[5] : 0 [by b.b.atree_y[15].and2s[1]._y:=1]
786214 b.b.atree_y[15].and2s[2]._y : 1 [by b.b.atree_y[15].tmp[5]:=0]
786298 b.b.vtree_x.ct.in[0] : 0 [by b.b.vtree_x.OR2_tf[0]._y:=1]
786409 b.b.addr_buf.out_a_B_buf_t.buf2._y : 1 [by b.b.addr_buf._out_a_B:=0]
787081 b.b.atree_x[7].and3s[0]._y : 1 [by b.b.atree_x[1].in[0]:=0]
787082 b.outx[7] : 0 [by b.b.atree_x[7].and3s[0]._y:=1]
787926 b.b.addr_buf.t_buf_func[3]._y : 1 [by b.b.addr_buf._out_a_BX_t[0]:=0]
788309 b.b.atree_x[2].in[1] : 0 [by b.b.addr_buf.t_buf_func[1]._y:=1]
791445 b.b.vtree_x.OR2_tf[1]._y : 1 [by b.b.atree_x[2].in[1]:=0]
792271 b.b.vtree_x.ct.in[1] : 0 [by b.b.vtree_x.OR2_tf[1]._y:=1]
794104 b.b.vtree_x.ct.C3Els[0]._y : 1 [by b.b.vtree_x.ct.in[1]:=0]
796624 b.b.atree_y[13].and2s[1]._y : 1 [by b.b.atree_y[8].in[3]:=0]
796682 b.b.atree_y[13].tmp[5] : 0 [by b.b.atree_y[13].and2s[1]._y:=1]
799581 b.b.addr_buf._out_a_BX_f[0] : 0 [by b.b.addr_buf.out_a_B_buf_t.buf2._y:=1]
805165 b.b.addr_buf.t_buf_func[5]._y : 1 [by b.b.addr_buf._out_a_BX_t[0]:=0]
806736 b.b.atree_y[3].and2s[0]._y : 1 [by b.b.atree_y[2].in[1]:=0]
807608 b.b.atree_y[4].in[2] : 0 [by b.b.addr_buf.t_buf_func[5]._y:=1]
807645 b.b.atree_y[11].and2s[0]._y : 1 [by b.b.atree_y[2].in[1]:=0]
807659 b.b.atree_y[11].tmp[4] : 0 [by b.b.atree_y[11].and2s[0]._y:=1]
807751 b.b.atree_y[1].in[0] : 0 [by b.b.addr_buf.t_buf_func[3]._y:=1]
808107 b.b.vtree_y.OR2_tf[0]._y : 1 [by b.b.atree_y[1].in[0]:=0]
810652 b.b.C2el.c1 : 0 [by b.b.vtree_x.ct.C3Els[0]._y:=1]
812671 b.b.atree_y[14].and2s[1]._y : 1 [by b.b.atree_y[8].in[3]:=0]
812776 b.b.atree_y[14].tmp[5] : 0 [by b.b.atree_y[14].and2s[1]._y:=1]
823509 b.b.atree_y[3].tmp[4] : 0 [by b.b.atree_y[3].and2s[0]._y:=1]
824626 b.b.atree_y[15].and2s[0]._y : 1 [by b.b.atree_y[2].in[1]:=0]
824735 b.b.atree_y[15].tmp[4] : 0 [by b.b.atree_y[15].and2s[0]._y:=1]
843945 b.b.vtree_y.ct.in[0] : 0 [by b.b.vtree_y.OR2_tf[0]._y:=1]
843946 b.b.vtree_y.ct.C2Els[0]._y : 1 [by b.b.vtree_y.ct.in[0]:=0]
843955 b.b.vtree_y.ct.tmp[4] : 0 [by b.b.vtree_y.ct.C2Els[0]._y:=1]
844807 b.b.vtree_y.OR2_tf[2]._y : 1 [by b.b.atree_y[4].in[2]:=0]
850592 b.outy[15] : 0 [by b.b.atree_y[15].and2s[2]._y:=1]
882760 b.b.vtree_y.ct.in[2] : 0 [by b.b.vtree_y.OR2_tf[2]._y:=1]
882761 b.b.vtree_y.ct.C2Els[1]._y : 1 [by b.b.vtree_y.ct.in[2]:=0]
919155 b.b.vtree_y.ct.tmp[5] : 0 [by b.b.vtree_y.ct.C2Els[1]._y:=1]
919156 b.b.vtree_y.ct.C2Els[2]._y : 1 [by b.b.vtree_y.ct.tmp[5]:=0]
922245 b.b.C2el.c2 : 0 [by b.b.vtree_y.ct.C2Els[2]._y:=1]
970971 b.b.C2el._y : 1 [by b.b.C2el.c2:=0]
971721 b.b.C2el.y : 0 [by b.b.C2el._y:=1]
978476 b.b.dly.and2[0]._y : 1 [by b.b.C2el.y:=0]
978527 b.b.dly.dly[0].a : 0 [by b.b.dly.and2[0]._y:=1]
978537 b.b.dly.dly[0]._y : 1 [by b.b.dly.dly[0].a:=0]
978857 b.b.dly.dly[0].__y : 0 [by b.b.dly.dly[0]._y:=1]
986439 b.b.dly.dly[0].___y : 1 [by b.b.dly.dly[0].__y:=0]
986440 b.b.dly.dly[0].y : 0 [by b.b.dly.dly[0].___y:=1]
986441 b.b.dly.mu2[0]._y : 1 [by b.b.dly.dly[0].y:=0]
988171 b.b.dly._a[1] : 0 [by b.b.dly.mu2[0]._y:=1]
989858 b.b.dly.and2[1]._y : 1 [by b.b.dly._a[1]:=0]
989873 b.b.dly.dly[1].a : 0 [by b.b.dly.and2[1]._y:=1]
1014147 b.b.dly.dly[1]._y : 1 [by b.b.dly.dly[1].a:=0]
1014601 b.b.dly.dly[1].__y : 0 [by b.b.dly.dly[1]._y:=1]
1014917 b.b.dly.dly[1].___y : 1 [by b.b.dly.dly[1].__y:=0]
1014918 b.b.dly.dly[1].y : 0 [by b.b.dly.dly[1].___y:=1]
1015301 b.b.dly.dly[2]._y : 1 [by b.b.dly.dly[1].y:=0]
1022764 b.b.dly.dly[2].__y : 0 [by b.b.dly.dly[2]._y:=1]
1022784 b.b.dly.dly[2].___y : 1 [by b.b.dly.dly[2].__y:=0]
1024107 b.b.dly.dly[2].y : 0 [by b.b.dly.dly[2].___y:=1]
1024194 b.b.dly.mu2[1]._y : 1 [by b.b.dly.dly[2].y:=0]
1030916 b.b.dly._a[2] : 0 [by b.b.dly.mu2[1]._y:=1]
1030928 b.b.dly.mu2[2]._y : 1 [by b.b.dly._a[2]:=0]
1031073 b.b.dly._a[3] : 0 [by b.b.dly.mu2[2]._y:=1]
1031974 b.b.dly.mu2[3]._y : 1 [by b.b.dly._a[3]:=0]
1033323 b.b.dly.out : 0 [by b.b.dly.mu2[3]._y:=1]
1033542 b.b.addr_buf._out_a_B : 1 [by b.b.dly.out:=0]
1041873 b.b.addr_buf.out_a_B_buf_t.buf2._y : 0 [by b.b.addr_buf._out_a_B:=1]
1041891 b.b.addr_buf._out_a_BX_f[0] : 1 [by b.b.addr_buf.out_a_B_buf_t.buf2._y:=0]
1065123 b.b.addr_buf.out_a_B_buf_f.buf2._y : 0 [by b.b.addr_buf._out_a_B:=1]
1067317 b.b.addr_buf._out_a_BX_t[0] : 1 [by b.b.addr_buf.out_a_B_buf_f.buf2._y:=0]

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test/unit_tests/decoder_2d_dly_8_16/run/prsim.pdf
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test/unit_tests/decoder_2d_dly_8_16/run/test.prs
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47
test/unit_tests/decoder_2d_dly_8_16/test.act
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@@ -1,47 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/coders.act";
import globals;
open tmpl::dataflow_neuro;
defproc decoder_2d_dly_8_16(avMx1of2<3+4> in; bool? outx[8], outy[16], dly_cfg[4])
{
bool _reset_B;
prs {
Reset => _reset_B-
}
decoder_2d_dly<3,4,8,16,4> b(.in = in, .outx = outx, .outy = outy, .dly_cfg = dly_cfg);
b.supply.vdd = Vdd;
b.supply.vss = GND;
b.reset_B = _reset_B;
}
decoder_2d_dly_8_16 b;

59
test/unit_tests/decoder_2d_dly_8_16/test.prsim
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@@ -1,59 +0,0 @@
watchall
set-qdi-channel-neutral "b.in" 7
set b.b.addr_buf.out.a 0
set Reset 0
# Set delay config lines
set b.dly_cfg[0] 1
set b.dly_cfg[1] 1
set b.dly_cfg[2] 0
set b.dly_cfg[3] 0
cycle
system "echo '[] set Reset 1'"
set Reset 1
cycle
system "echo '[] set Reset 0'"
set Reset 0
mode run
cycle
system "echo '[] Sending packet in'"
set-qdi-channel-valid "b.in" 7 127
cycle
assert b.in.a 1
assert b.in.v 1
# system "echo '[]' Setting ack from DLY high"
# set b.b.addr_buf.out.a 1
cycle
assert b.outx[0] 0
assert b.outx[1] 0
assert b.outx[2] 0
assert b.outx[3] 0
assert b.outx[4] 0
assert b.outx[5] 0
assert b.outx[6] 0
assert b.outx[7] 0
assert b.outy[0] 0
assert b.outy[1] 0
assert b.outy[2] 0
assert b.outy[3] 0
assert b.outy[4] 0
assert b.outy[5] 0
assert b.outy[6] 0
assert b.outy[7] 0
assert b.outy[8] 0
assert b.outy[9] 0
assert b.outy[10] 0
assert b.outy[11] 0
assert b.outy[12] 0
assert b.outy[13] 0
assert b.outy[14] 0
assert b.outy[15] 0

351
test/unit_tests/decoder_2d_dly_and_2_4/run/prsim.out
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@@ -1,351 +0,0 @@
t.de.dly.dly[2].y t.de.dly.dly[4].y t.de.addr_buf._in_v t.de.dly._a[2] t.in.d.d[1].f t.de.dly.mu2[3].b t.de.dly.dly[3].y t.de.dly.dly[7].y t.de.dly.dly[3].___y t.in.d.d[0].t t.dly_cfg[1] t.de.dly.dly[13].__y t.de.dly.dly[1]._y t.de.dly.dly[13]._y t.de.addr_buf._out_a_BX_t[0] t.de.dly.dly[7].a t.de.dly.mu2[3]._y t.de.dly.dly[3].a t.in.d.d[0].f t.de.dly.dly[5]._y t.de.dly.dly[7].__y t.de.addr_buf._out_a_B t.de.dly.dly[3].__y t.dly_cfg[2] t.de.dly.dly[2].__y t.de.dly.dly[8].___y t.de.addr_buf._out_a_BX_f[0] t.de.addr_buf.vc.ct.in[0] t.de.dly.dly[13].___y t.de.dly.dly[1].a t.in.d.d[1].t t.in.v t.de.dly.dly[5].__y t.in.d.d[2].t t.de.addr_buf.in_v_buf._y t.de.dly.dly[9].y t.dly_cfg[0] t.in.d.d[2].f t.de.dly.out t.de.dly.mu2[2]._y t.dly_cfg[3] t.de.dly.dly[10]._y t.de.dly.dly[9].__y t.de.dly.and2[3]._y t.de.dly._a[3] t.de.addr_buf.vc.OR2_tf[1]._y t.de.addr_buf.vc.ct.in[2] t.de.dly.dly[5].y t.de.dly.dly[11].___y t.de.dly.dly[4].__y t.de.dly.and2[1]._y t.de.dly.dly[6].___y t.de.dly.dly[10].y t.de.dly.dly[11]._y t.de.dly.dly[10].__y t.de.dly.dly[12].__y t.de.dly.dly[1].__y t.de.addr_buf.vc.ct.in[1] t.de.addr_buf.out_a_B_buf_f.buf1._y t.de.dly._a[1] t.de.dly.dly[14].__y t.de.dly.dly[6].y t.de.dly.dly[11].y t.de.dly.dly[7]._y t.de.addr_buf.vc.ct.C3Els[0]._y t.de.dly.mu2[1]._y t.de.dly.dly[9]._y t.de.dly.dly[5].___y t.de.dly.dly[14]._y t.de.dly.and2[2]._y t.de.dly.dly[8].y t.de.dly.dly[9].___y t.de.dly.mu2[0]._s t.de.dly.mu2[1]._s t.de.dly.dly[2]._y t.de.dly.dly[8].__y t.de.dly.dly[12].___y t.de.dly.dly[13].y t.de.dly.dly[10].___y t.de.dly.dly[1].y t.de.dly.dly[1].___y t.de.dly.dly[2].___y t.de.addr_buf.out_a_B_buf_t.buf1._y t.de.dly.dly[4]._y t.de.dly.dly[8]._y t.de.dly.dly[4].___y t.de.dly.dly[12].y t.de.dly.dly[6].__y t.de.dly.dly[7].___y t.de.addr_buf.vc.OR2_tf[2]._y t.de.dly.dly[3]._y t.de.dly.dly[14].___y t.de.dly.mu2[3]._s t.de.dly.dly[11].__y t.de.dly.dly[6]._y t.de.addr_buf.vc.OR2_tf[0]._y t.de.dly.mu2[2]._s t.de.dly.mu2[0]._y t.de.dly.dly[12]._y
244317 t.in.d.d[0].f : 0
244317 t.dly_cfg[3] : 1
244317 t.dly_cfg[2] : 1
244317 t.in.d.d[1].f : 0
244317 Reset : 0
244317 t.dly_cfg[1] : 1
244317 t.in.d.d[2].t : 0
244317 t.in.d.d[0].t : 0
244317 t.dly_cfg[0] : 1
244317 t.in.d.d[2].f : 0
244317 t.in.d.d[1].t : 0
244318 t._reset_B : 1 [by Reset:=0]
244404 t.de.dly.mu2[3]._s : 0 [by t.dly_cfg[3]:=1]
244495 t.de.addr_buf.vc.OR2_tf[1]._y : 1 [by t.in.d.d[1].t:=0]
244611 t.de.dly.mu2[2]._s : 0 [by t.dly_cfg[2]:=1]
244659 t.de.addr_buf.vc.ct.in[1] : 0 [by t.de.addr_buf.vc.OR2_tf[1]._y:=1]
244907 t.de.addr_buf.vc.OR2_tf[2]._y : 1 [by t.in.d.d[2].f:=0]
245121 t.de.addr_buf.reset_buf._y : 0 [by t._reset_B:=1]
245143 t.de.addr_buf._reset_BX : 1 [by t.de.addr_buf.reset_buf._y:=0]
245526 t.de.dly.mu2[0]._s : 0 [by t.dly_cfg[0]:=1]
245990 t.de.addr_buf.reset_bufarray.buf1._y : 0 [by t.de.addr_buf._reset_BX:=1]
246123 t.de.dly.mu2[1]._s : 0 [by t.dly_cfg[1]:=1]
246123 t.de.addr_buf._reset_BXX[0] : 1 [by t.de.addr_buf.reset_bufarray.buf1._y:=0]
246324 t.de.addr_buf.vc.OR2_tf[0]._y : 1 [by t.in.d.d[0].t:=0]
247102 t.de.addr_buf.vc.ct.in[2] : 0 [by t.de.addr_buf.vc.OR2_tf[2]._y:=1]
261986 t.de.addr_buf.vc.ct.in[0] : 0 [by t.de.addr_buf.vc.OR2_tf[0]._y:=1]
262345 t.de.addr_buf.vc.ct.C3Els[0]._y : 1 [by t.de.addr_buf.vc.ct.in[0]:=0]
275654 t.de.dly.mu2[0]._y : 1 [by t.de.dly.mu2[0]._s:=0]
275875 t.de.dly._a[1] : 0 [by t.de.dly.mu2[0]._y:=1]
275882 t.de.dly.and2[1]._y : 1 [by t.de.dly._a[1]:=0]
275912 t.de.dly.dly[1].a : 0 [by t.de.dly.and2[1]._y:=1]
276461 t.de.addr_buf._in_v : 0 [by t.de.addr_buf.vc.ct.C3Els[0]._y:=1]
282625 t.de.dly.dly[1]._y : 1 [by t.de.dly.dly[1].a:=0]
282716 t.de.dly.dly[1].__y : 0 [by t.de.dly.dly[1]._y:=1]
284905 t.de.dly.dly[1].___y : 1 [by t.de.dly.dly[1].__y:=0]
284912 t.de.dly.dly[1].y : 0 [by t.de.dly.dly[1].___y:=1]
287699 t.de.dly.dly[2]._y : 1 [by t.de.dly.dly[1].y:=0]
287805 t.de.dly.dly[2].__y : 0 [by t.de.dly.dly[2]._y:=1]
287883 t.de.dly.dly[2].___y : 1 [by t.de.dly.dly[2].__y:=0]
288158 t.de.dly.dly[2].y : 0 [by t.de.dly.dly[2].___y:=1]
307154 t.de.dly.mu2[1]._y : 1 [by t.de.dly.dly[2].y:=0]
307609 t.de.dly._a[2] : 0 [by t.de.dly.mu2[1]._y:=1]
307621 t.de.dly.and2[2]._y : 1 [by t.de.dly._a[2]:=0]
308025 t.de.dly.dly[3].a : 0 [by t.de.dly.and2[2]._y:=1]
308037 t.de.dly.dly[3]._y : 1 [by t.de.dly.dly[3].a:=0]
313953 t.de.dly.dly[3].__y : 0 [by t.de.dly.dly[3]._y:=1]
318229 t.de.dly.dly[3].___y : 1 [by t.de.dly.dly[3].__y:=0]
321128 t.de.dly.dly[3].y : 0 [by t.de.dly.dly[3].___y:=1]
325423 t.de.dly.dly[4]._y : 1 [by t.de.dly.dly[3].y:=0]
325425 t.de.dly.dly[4].__y : 0 [by t.de.dly.dly[4]._y:=1]
329960 t.de.dly.dly[4].___y : 1 [by t.de.dly.dly[4].__y:=0]
331209 t.de.dly.dly[4].y : 0 [by t.de.dly.dly[4].___y:=1]
333922 t.de.addr_buf.in_v_buf._y : 1 [by t.de.addr_buf._in_v:=0]
334088 t.in.v : 0 [by t.de.addr_buf.in_v_buf._y:=1]
334708 t.de.dly.dly[5]._y : 1 [by t.de.dly.dly[4].y:=0]
334783 t.de.dly.dly[5].__y : 0 [by t.de.dly.dly[5]._y:=1]
335128 t.de.dly.dly[5].___y : 1 [by t.de.dly.dly[5].__y:=0]
335266 t.de.dly.dly[5].y : 0 [by t.de.dly.dly[5].___y:=1]
340529 t.de.dly.dly[6]._y : 1 [by t.de.dly.dly[5].y:=0]
340531 t.de.dly.dly[6].__y : 0 [by t.de.dly.dly[6]._y:=1]
384448 t.de.dly.dly[6].___y : 1 [by t.de.dly.dly[6].__y:=0]
384449 t.de.dly.dly[6].y : 0 [by t.de.dly.dly[6].___y:=1]
384997 t.de.dly.mu2[2]._y : 1 [by t.de.dly.dly[6].y:=0]
385008 t.de.dly._a[3] : 0 [by t.de.dly.mu2[2]._y:=1]
385378 t.de.dly.and2[3]._y : 1 [by t.de.dly._a[3]:=0]
385445 t.de.dly.dly[7].a : 0 [by t.de.dly.and2[3]._y:=1]
388086 t.de.dly.dly[7]._y : 1 [by t.de.dly.dly[7].a:=0]
388102 t.de.dly.dly[7].__y : 0 [by t.de.dly.dly[7]._y:=1]
392664 t.de.dly.dly[7].___y : 1 [by t.de.dly.dly[7].__y:=0]
393192 t.de.dly.dly[7].y : 0 [by t.de.dly.dly[7].___y:=1]
395627 t.de.dly.dly[8]._y : 1 [by t.de.dly.dly[7].y:=0]
422507 t.de.dly.dly[8].__y : 0 [by t.de.dly.dly[8]._y:=1]
446432 t.de.dly.dly[8].___y : 1 [by t.de.dly.dly[8].__y:=0]
459473 t.de.dly.dly[8].y : 0 [by t.de.dly.dly[8].___y:=1]
459475 t.de.dly.dly[9]._y : 1 [by t.de.dly.dly[8].y:=0]
520433 t.de.dly.dly[9].__y : 0 [by t.de.dly.dly[9]._y:=1]
520436 t.de.dly.dly[9].___y : 1 [by t.de.dly.dly[9].__y:=0]
520465 t.de.dly.dly[9].y : 0 [by t.de.dly.dly[9].___y:=1]
520782 t.de.dly.dly[10]._y : 1 [by t.de.dly.dly[9].y:=0]
522383 t.de.dly.dly[10].__y : 0 [by t.de.dly.dly[10]._y:=1]
522536 t.de.dly.dly[10].___y : 1 [by t.de.dly.dly[10].__y:=0]
522580 t.de.dly.dly[10].y : 0 [by t.de.dly.dly[10].___y:=1]
525341 t.de.dly.dly[11]._y : 1 [by t.de.dly.dly[10].y:=0]
539024 t.de.dly.dly[11].__y : 0 [by t.de.dly.dly[11]._y:=1]
539025 t.de.dly.dly[11].___y : 1 [by t.de.dly.dly[11].__y:=0]
539242 t.de.dly.dly[11].y : 0 [by t.de.dly.dly[11].___y:=1]
539264 t.de.dly.dly[12]._y : 1 [by t.de.dly.dly[11].y:=0]
539265 t.de.dly.dly[12].__y : 0 [by t.de.dly.dly[12]._y:=1]
540846 t.de.dly.dly[12].___y : 1 [by t.de.dly.dly[12].__y:=0]
550191 t.de.dly.dly[12].y : 0 [by t.de.dly.dly[12].___y:=1]
550350 t.de.dly.dly[13]._y : 1 [by t.de.dly.dly[12].y:=0]
570026 t.de.dly.dly[13].__y : 0 [by t.de.dly.dly[13]._y:=1]
571313 t.de.dly.dly[13].___y : 1 [by t.de.dly.dly[13].__y:=0]
573545 t.de.dly.dly[13].y : 0 [by t.de.dly.dly[13].___y:=1]
573690 t.de.dly.dly[14]._y : 1 [by t.de.dly.dly[13].y:=0]
576522 t.de.dly.dly[14].__y : 0 [by t.de.dly.dly[14]._y:=1]
582876 t.de.dly.dly[14].___y : 1 [by t.de.dly.dly[14].__y:=0]
582877 t.de.dly.mu2[3].b : 0 [by t.de.dly.dly[14].___y:=1]
622161 t.de.dly.mu2[3]._y : 1 [by t.de.dly.mu2[3].b:=0]
622323 t.de.dly.out : 0 [by t.de.dly.mu2[3]._y:=1]
629692 t.de.addr_buf._out_a_B : 1 [by t.de.dly.out:=0]
629699 t.de.addr_buf.out_a_B_buf_f.buf1._y : 0 [by t.de.addr_buf._out_a_B:=1]
629706 t.de.addr_buf.out_a_B_buf_t.buf1._y : 0 [by t.de.addr_buf._out_a_B:=1]
629859 t.de.addr_buf._out_a_BX_t[0] : 1 [by t.de.addr_buf.out_a_B_buf_f.buf1._y:=0]
651263 t.de.addr_buf._out_a_BX_f[0] : 1 [by t.de.addr_buf.out_a_B_buf_t.buf1._y:=0]
[] set Reset 1
651263 Reset : 1
651264 t._reset_B : 0 [by Reset:=1]
651265 t.de.addr_buf.reset_buf._y : 1 [by t._reset_B:=0]
651266 t.de.addr_buf._reset_BX : 0 [by t.de.addr_buf.reset_buf._y:=1]
653509 t.de.addr_buf.reset_bufarray.buf1._y : 1 [by t.de.addr_buf._reset_BX:=0]
653696 t.de.addr_buf._reset_BXX[0] : 0 [by t.de.addr_buf.reset_bufarray.buf1._y:=1]
[] set Reset 0
653696 Reset : 0
653697 t._reset_B : 1 [by Reset:=0]
657879 t.de.addr_buf.reset_buf._y : 0 [by t._reset_B:=1]
692661 t.de.addr_buf._reset_BX : 1 [by t.de.addr_buf.reset_buf._y:=0]
692662 t.de.addr_buf.reset_bufarray.buf1._y : 0 [by t.de.addr_buf._reset_BX:=1]
693515 t.de.addr_buf._reset_BXX[0] : 1 [by t.de.addr_buf.reset_bufarray.buf1._y:=0]
[] Sending packet in
693515 t.in.d.d[0].t : 1
693515 t.in.d.d[2].t : 1
693515 t.in.d.d[1].t : 1
693516 t.de.addr_buf.vc.OR2_tf[2]._y : 0 [by t.in.d.d[2].t:=1]
693519 t.de.addr_buf.vc.ct.in[2] : 1 [by t.de.addr_buf.vc.OR2_tf[2]._y:=0]
693520 t.de.addr_buf.vc.OR2_tf[0]._y : 0 [by t.in.d.d[0].t:=1]
693532 t.de.addr_buf.t_buf_func[2]._y : 0 [by t.in.d.d[2].t:=1]
694406 t.de.addr_buf.t_buf_func[0]._y : 0 [by t.in.d.d[0].t:=1]
694407 t.de.atree_x[1].in[0] : 1 [by t.de.addr_buf.t_buf_func[0]._y:=0]
694449 t.de.atree_x[1].b._y : 0 [by t.de.atree_x[1].in[0]:=1]
694461 t.de.addr_buf.vc.ct.in[0] : 1 [by t.de.addr_buf.vc.OR2_tf[0]._y:=0]
696088 t.de.addr_buf.vc.OR2_tf[1]._y : 0 [by t.in.d.d[1].t:=1]
696183 t.de.addr_buf.vc.ct.in[1] : 1 [by t.de.addr_buf.vc.OR2_tf[1]._y:=0]
696518 t.de.addr_buf.vc.ct.C3Els[0]._y : 0 [by t.de.addr_buf.vc.ct.in[1]:=1]
696526 t.de.addr_buf._in_v : 1 [by t.de.addr_buf.vc.ct.C3Els[0]._y:=0]
696560 t.de.addr_buf.in_v_buf._y : 0 [by t.de.addr_buf._in_v:=1]
697224 t.de.vtree_x.OR2_tf[0]._y : 0 [by t.de.atree_x[1].in[0]:=1]
698142 t.de.vtree_x.ct.in[0] : 1 [by t.de.vtree_x.OR2_tf[0]._y:=0]
698146 t.de.vtree_x.ct.b._y : 0 [by t.de.vtree_x.ct.in[0]:=1]
701876 t.de.addr_buf.t_buf_func[1]._y : 0 [by t.in.d.d[1].t:=1]
704274 t.de.atree_y[1].in[0] : 1 [by t.de.addr_buf.t_buf_func[1]._y:=0]
707489 t.de.vtree_y.OR2_tf[0]._y : 0 [by t.de.atree_y[1].in[0]:=1]
708182 t.ag.inx[1] : 1 [by t.de.atree_x[1].b._y:=0]
710447 t.in.v : 1 [by t.de.addr_buf.in_v_buf._y:=0]
744524 t.de.C2el.c1 : 1 [by t.de.vtree_x.ct.b._y:=0]
752494 t.de.atree_y[2].in[1] : 1 [by t.de.addr_buf.t_buf_func[2]._y:=0]
752497 t.de.vtree_y.OR2_tf[1]._y : 0 [by t.de.atree_y[2].in[1]:=1]
752542 t.de.atree_y[3].and2s[0]._y : 0 [by t.de.atree_y[2].in[1]:=1]
752675 t.de.vtree_y.ct.in[1] : 1 [by t.de.vtree_y.OR2_tf[1]._y:=0]
754608 t.de.vtree_y.ct.in[0] : 1 [by t.de.vtree_y.OR2_tf[0]._y:=0]
766507 t.de.vtree_y.ct.C2Els[0]._y : 0 [by t.de.vtree_y.ct.in[0]:=1]
772458 t.de.C2el.c2 : 1 [by t.de.vtree_y.ct.C2Els[0]._y:=0]
773519 t.ag.iny[3] : 1 [by t.de.atree_y[3].and2s[0]._y:=0]
774346 t.ag.ands[7]._y : 0 [by t.ag.iny[3]:=1]
774519 t.out[7] : 1 [by t.ag.ands[7]._y:=0]
811943 t.de.C2el._y : 0 [by t.de.C2el.c2:=1]
812127 t.de.C2el.y : 1 [by t.de.C2el._y:=0]
812128 t.de.dly.and2[0]._y : 0 [by t.de.C2el.y:=1]
812132 t.de.dly.dly[0].a : 1 [by t.de.dly.and2[0]._y:=0]
812200 t.de.addr_buf.inack_ctl._y : 0 [by t.de.C2el.y:=1]
812296 t.in.a : 1 [by t.de.addr_buf.inack_ctl._y:=0]
812432 t.de.addr_buf._en : 0 [by t.in.a:=1]
812433 t.de.addr_buf.en_buf_f.buf1._y : 1 [by t.de.addr_buf._en:=0]
812674 t.de.addr_buf._en_X_f[0] : 0 [by t.de.addr_buf.en_buf_f.buf1._y:=1]
831478 t.de.addr_buf.en_buf_t.buf1._y : 1 [by t.de.addr_buf._en:=0]
835437 t.de.addr_buf._en_X_t[0] : 0 [by t.de.addr_buf.en_buf_t.buf1._y:=1]
849420 t.de.dly.dly[0]._y : 0 [by t.de.dly.dly[0].a:=1]
849432 t.de.dly.dly[0].__y : 1 [by t.de.dly.dly[0]._y:=0]
853332 t.de.dly.dly[0].___y : 0 [by t.de.dly.dly[0].__y:=1]
854361 t.de.dly.dly[0].y : 1 [by t.de.dly.dly[0].___y:=0]
854362 t.de.dly.mu2[0]._y : 0 [by t.de.dly.dly[0].y:=1]
854418 t.de.dly._a[1] : 1 [by t.de.dly.mu2[0]._y:=0]
899424 t.de.dly.and2[1]._y : 0 [by t.de.dly._a[1]:=1]
899425 t.de.dly.dly[1].a : 1 [by t.de.dly.and2[1]._y:=0]
899462 t.de.dly.dly[1]._y : 0 [by t.de.dly.dly[1].a:=1]
922837 t.de.dly.dly[1].__y : 1 [by t.de.dly.dly[1]._y:=0]
922838 t.de.dly.dly[1].___y : 0 [by t.de.dly.dly[1].__y:=1]
926402 t.de.dly.dly[1].y : 1 [by t.de.dly.dly[1].___y:=0]
928094 t.de.dly.dly[2]._y : 0 [by t.de.dly.dly[1].y:=1]
928107 t.de.dly.dly[2].__y : 1 [by t.de.dly.dly[2]._y:=0]
945091 t.de.dly.dly[2].___y : 0 [by t.de.dly.dly[2].__y:=1]
945448 t.de.dly.dly[2].y : 1 [by t.de.dly.dly[2].___y:=0]
945473 t.de.dly.mu2[1]._y : 0 [by t.de.dly.dly[2].y:=1]
945494 t.de.dly._a[2] : 1 [by t.de.dly.mu2[1]._y:=0]
945495 t.de.dly.and2[2]._y : 0 [by t.de.dly._a[2]:=1]
955143 t.de.dly.dly[3].a : 1 [by t.de.dly.and2[2]._y:=0]
955144 t.de.dly.dly[3]._y : 0 [by t.de.dly.dly[3].a:=1]
955145 t.de.dly.dly[3].__y : 1 [by t.de.dly.dly[3]._y:=0]
955306 t.de.dly.dly[3].___y : 0 [by t.de.dly.dly[3].__y:=1]
956343 t.de.dly.dly[3].y : 1 [by t.de.dly.dly[3].___y:=0]
956348 t.de.dly.dly[4]._y : 0 [by t.de.dly.dly[3].y:=1]
956929 t.de.dly.dly[4].__y : 1 [by t.de.dly.dly[4]._y:=0]
957337 t.de.dly.dly[4].___y : 0 [by t.de.dly.dly[4].__y:=1]
957348 t.de.dly.dly[4].y : 1 [by t.de.dly.dly[4].___y:=0]
958395 t.de.dly.dly[5]._y : 0 [by t.de.dly.dly[4].y:=1]
958409 t.de.dly.dly[5].__y : 1 [by t.de.dly.dly[5]._y:=0]
958427 t.de.dly.dly[5].___y : 0 [by t.de.dly.dly[5].__y:=1]
958431 t.de.dly.dly[5].y : 1 [by t.de.dly.dly[5].___y:=0]
958535 t.de.dly.dly[6]._y : 0 [by t.de.dly.dly[5].y:=1]
989979 t.de.dly.dly[6].__y : 1 [by t.de.dly.dly[6]._y:=0]
991183 t.de.dly.dly[6].___y : 0 [by t.de.dly.dly[6].__y:=1]
999638 t.de.dly.dly[6].y : 1 [by t.de.dly.dly[6].___y:=0]
999866 t.de.dly.mu2[2]._y : 0 [by t.de.dly.dly[6].y:=1]
1000709 t.de.dly._a[3] : 1 [by t.de.dly.mu2[2]._y:=0]
1002168 t.de.dly.and2[3]._y : 0 [by t.de.dly._a[3]:=1]
1002238 t.de.dly.dly[7].a : 1 [by t.de.dly.and2[3]._y:=0]
1052660 t.de.dly.dly[7]._y : 0 [by t.de.dly.dly[7].a:=1]
1052671 t.de.dly.dly[7].__y : 1 [by t.de.dly.dly[7]._y:=0]
1052674 t.de.dly.dly[7].___y : 0 [by t.de.dly.dly[7].__y:=1]
1052728 t.de.dly.dly[7].y : 1 [by t.de.dly.dly[7].___y:=0]
1053876 t.de.dly.dly[8]._y : 0 [by t.de.dly.dly[7].y:=1]
1055037 t.de.dly.dly[8].__y : 1 [by t.de.dly.dly[8]._y:=0]
1063689 t.de.dly.dly[8].___y : 0 [by t.de.dly.dly[8].__y:=1]
1063770 t.de.dly.dly[8].y : 1 [by t.de.dly.dly[8].___y:=0]
1074847 t.de.dly.dly[9]._y : 0 [by t.de.dly.dly[8].y:=1]
1092830 t.de.dly.dly[9].__y : 1 [by t.de.dly.dly[9]._y:=0]
1092922 t.de.dly.dly[9].___y : 0 [by t.de.dly.dly[9].__y:=1]
1101233 t.de.dly.dly[9].y : 1 [by t.de.dly.dly[9].___y:=0]
1102977 t.de.dly.dly[10]._y : 0 [by t.de.dly.dly[9].y:=1]
1103590 t.de.dly.dly[10].__y : 1 [by t.de.dly.dly[10]._y:=0]
1117612 t.de.dly.dly[10].___y : 0 [by t.de.dly.dly[10].__y:=1]
1117657 t.de.dly.dly[10].y : 1 [by t.de.dly.dly[10].___y:=0]
1118654 t.de.dly.dly[11]._y : 0 [by t.de.dly.dly[10].y:=1]
1120303 t.de.dly.dly[11].__y : 1 [by t.de.dly.dly[11]._y:=0]
1120828 t.de.dly.dly[11].___y : 0 [by t.de.dly.dly[11].__y:=1]
1121728 t.de.dly.dly[11].y : 1 [by t.de.dly.dly[11].___y:=0]
1121780 t.de.dly.dly[12]._y : 0 [by t.de.dly.dly[11].y:=1]
1121787 t.de.dly.dly[12].__y : 1 [by t.de.dly.dly[12]._y:=0]
1137399 t.de.dly.dly[12].___y : 0 [by t.de.dly.dly[12].__y:=1]
1143866 t.de.dly.dly[12].y : 1 [by t.de.dly.dly[12].___y:=0]
1143868 t.de.dly.dly[13]._y : 0 [by t.de.dly.dly[12].y:=1]
1144222 t.de.dly.dly[13].__y : 1 [by t.de.dly.dly[13]._y:=0]
1144355 t.de.dly.dly[13].___y : 0 [by t.de.dly.dly[13].__y:=1]
1144356 t.de.dly.dly[13].y : 1 [by t.de.dly.dly[13].___y:=0]
1144360 t.de.dly.dly[14]._y : 0 [by t.de.dly.dly[13].y:=1]
1144906 t.de.dly.dly[14].__y : 1 [by t.de.dly.dly[14]._y:=0]
1190469 t.de.dly.dly[14].___y : 0 [by t.de.dly.dly[14].__y:=1]
1190470 t.de.dly.mu2[3].b : 1 [by t.de.dly.dly[14].___y:=0]
1202848 t.de.dly.mu2[3]._y : 0 [by t.de.dly.mu2[3].b:=1]
1202927 t.de.dly.out : 1 [by t.de.dly.mu2[3]._y:=0]
1205360 t.de.addr_buf._out_a_B : 0 [by t.de.dly.out:=1]
1205448 t.de.addr_buf.out_a_B_buf_t.buf1._y : 1 [by t.de.addr_buf._out_a_B:=0]
1213142 t.de.addr_buf.out_a_B_buf_f.buf1._y : 1 [by t.de.addr_buf._out_a_B:=0]
1213201 t.de.addr_buf._out_a_BX_t[0] : 0 [by t.de.addr_buf.out_a_B_buf_f.buf1._y:=1]
1213231 t.de.addr_buf.t_buf_func[0]._y : 1 [by t.de.addr_buf._out_a_BX_t[0]:=0]
1214668 t.de.addr_buf.t_buf_func[1]._y : 1 [by t.de.addr_buf._out_a_BX_t[0]:=0]
1215353 t.de.atree_y[1].in[0] : 0 [by t.de.addr_buf.t_buf_func[1]._y:=1]
1215480 t.de.vtree_y.OR2_tf[0]._y : 1 [by t.de.atree_y[1].in[0]:=0]
1215649 t.de.vtree_y.ct.in[0] : 0 [by t.de.vtree_y.OR2_tf[0]._y:=1]
1232068 t.de.atree_y[3].and2s[0]._y : 1 [by t.de.atree_y[1].in[0]:=0]
1232111 t.ag.iny[3] : 0 [by t.de.atree_y[3].and2s[0]._y:=1]
1232123 t.ag.ands[7]._y : 1 [by t.ag.iny[3]:=0]
1232615 t.de.atree_x[1].in[0] : 0 [by t.de.addr_buf.t_buf_func[0]._y:=1]
1232618 t.de.vtree_x.OR2_tf[0]._y : 1 [by t.de.atree_x[1].in[0]:=0]
1232656 t.de.vtree_x.ct.in[0] : 0 [by t.de.vtree_x.OR2_tf[0]._y:=1]
1232657 t.de.vtree_x.ct.b._y : 1 [by t.de.vtree_x.ct.in[0]:=0]
1232848 t.de.atree_x[1].b._y : 1 [by t.de.atree_x[1].in[0]:=0]
1232940 t.ag.inx[1] : 0 [by t.de.atree_x[1].b._y:=1]
1233402 t.out[7] : 0 [by t.ag.ands[7]._y:=1]
1233775 t.de.addr_buf._out_a_BX_f[0] : 0 [by t.de.addr_buf.out_a_B_buf_t.buf1._y:=1]
1245409 t.de.C2el.c1 : 0 [by t.de.vtree_x.ct.b._y:=1]
1272705 t.de.addr_buf.t_buf_func[2]._y : 1 [by t.de.addr_buf._out_a_BX_t[0]:=0]
1275432 t.de.atree_y[2].in[1] : 0 [by t.de.addr_buf.t_buf_func[2]._y:=1]
1275434 t.de.vtree_y.OR2_tf[1]._y : 1 [by t.de.atree_y[2].in[1]:=0]
1275435 t.de.vtree_y.ct.in[1] : 0 [by t.de.vtree_y.OR2_tf[1]._y:=1]
1276936 t.de.vtree_y.ct.C2Els[0]._y : 1 [by t.de.vtree_y.ct.in[1]:=0]
1276938 t.de.C2el.c2 : 0 [by t.de.vtree_y.ct.C2Els[0]._y:=1]
1276956 t.de.C2el._y : 1 [by t.de.C2el.c2:=0]
1277075 t.de.C2el.y : 0 [by t.de.C2el._y:=1]
1282795 t.de.dly.and2[0]._y : 1 [by t.de.C2el.y:=0]
1282803 t.de.dly.dly[0].a : 0 [by t.de.dly.and2[0]._y:=1]
1282857 t.de.dly.dly[0]._y : 1 [by t.de.dly.dly[0].a:=0]
1333395 t.de.dly.dly[0].__y : 0 [by t.de.dly.dly[0]._y:=1]
1333400 t.de.dly.dly[0].___y : 1 [by t.de.dly.dly[0].__y:=0]
1334467 t.de.dly.dly[0].y : 0 [by t.de.dly.dly[0].___y:=1]
1334468 t.de.dly.mu2[0]._y : 1 [by t.de.dly.dly[0].y:=0]
1334606 t.de.dly._a[1] : 0 [by t.de.dly.mu2[0]._y:=1]
1334607 t.de.dly.and2[1]._y : 1 [by t.de.dly._a[1]:=0]
1334671 t.de.dly.dly[1].a : 0 [by t.de.dly.and2[1]._y:=1]
1334794 t.de.dly.dly[1]._y : 1 [by t.de.dly.dly[1].a:=0]
1334796 t.de.dly.dly[1].__y : 0 [by t.de.dly.dly[1]._y:=1]
1334833 t.de.dly.dly[1].___y : 1 [by t.de.dly.dly[1].__y:=0]
1334976 t.de.dly.dly[1].y : 0 [by t.de.dly.dly[1].___y:=1]
1335027 t.de.dly.dly[2]._y : 1 [by t.de.dly.dly[1].y:=0]
1335469 t.de.dly.dly[2].__y : 0 [by t.de.dly.dly[2]._y:=1]
1335480 t.de.dly.dly[2].___y : 1 [by t.de.dly.dly[2].__y:=0]
1335481 t.de.dly.dly[2].y : 0 [by t.de.dly.dly[2].___y:=1]
1335490 t.de.dly.mu2[1]._y : 1 [by t.de.dly.dly[2].y:=0]
1335515 t.de.dly._a[2] : 0 [by t.de.dly.mu2[1]._y:=1]
1345768 t.de.dly.and2[2]._y : 1 [by t.de.dly._a[2]:=0]
1349289 t.de.dly.dly[3].a : 0 [by t.de.dly.and2[2]._y:=1]
1349434 t.de.dly.dly[3]._y : 1 [by t.de.dly.dly[3].a:=0]
1365602 t.de.dly.dly[3].__y : 0 [by t.de.dly.dly[3]._y:=1]
1365832 t.de.dly.dly[3].___y : 1 [by t.de.dly.dly[3].__y:=0]
1366523 t.de.dly.dly[3].y : 0 [by t.de.dly.dly[3].___y:=1]
1366537 t.de.dly.dly[4]._y : 1 [by t.de.dly.dly[3].y:=0]
1368080 t.de.dly.dly[4].__y : 0 [by t.de.dly.dly[4]._y:=1]
1369691 t.de.dly.dly[4].___y : 1 [by t.de.dly.dly[4].__y:=0]
1387203 t.de.dly.dly[4].y : 0 [by t.de.dly.dly[4].___y:=1]
1387214 t.de.dly.dly[5]._y : 1 [by t.de.dly.dly[4].y:=0]
1387215 t.de.dly.dly[5].__y : 0 [by t.de.dly.dly[5]._y:=1]
1387216 t.de.dly.dly[5].___y : 1 [by t.de.dly.dly[5].__y:=0]
1393717 t.de.dly.dly[5].y : 0 [by t.de.dly.dly[5].___y:=1]
1394356 t.de.dly.dly[6]._y : 1 [by t.de.dly.dly[5].y:=0]
1396149 t.de.dly.dly[6].__y : 0 [by t.de.dly.dly[6]._y:=1]
1396281 t.de.dly.dly[6].___y : 1 [by t.de.dly.dly[6].__y:=0]
1396282 t.de.dly.dly[6].y : 0 [by t.de.dly.dly[6].___y:=1]
1396299 t.de.dly.mu2[2]._y : 1 [by t.de.dly.dly[6].y:=0]
1396451 t.de.dly._a[3] : 0 [by t.de.dly.mu2[2]._y:=1]
1399434 t.de.dly.and2[3]._y : 1 [by t.de.dly._a[3]:=0]
1399437 t.de.dly.dly[7].a : 0 [by t.de.dly.and2[3]._y:=1]
1399861 t.de.dly.dly[7]._y : 1 [by t.de.dly.dly[7].a:=0]
1399867 t.de.dly.dly[7].__y : 0 [by t.de.dly.dly[7]._y:=1]
1402455 t.de.dly.dly[7].___y : 1 [by t.de.dly.dly[7].__y:=0]
1404916 t.de.dly.dly[7].y : 0 [by t.de.dly.dly[7].___y:=1]
1405746 t.de.dly.dly[8]._y : 1 [by t.de.dly.dly[7].y:=0]
1428678 t.de.dly.dly[8].__y : 0 [by t.de.dly.dly[8]._y:=1]
1428680 t.de.dly.dly[8].___y : 1 [by t.de.dly.dly[8].__y:=0]
1428874 t.de.dly.dly[8].y : 0 [by t.de.dly.dly[8].___y:=1]
1429477 t.de.dly.dly[9]._y : 1 [by t.de.dly.dly[8].y:=0]
1429615 t.de.dly.dly[9].__y : 0 [by t.de.dly.dly[9]._y:=1]
1429632 t.de.dly.dly[9].___y : 1 [by t.de.dly.dly[9].__y:=0]
1429649 t.de.dly.dly[9].y : 0 [by t.de.dly.dly[9].___y:=1]
1430075 t.de.dly.dly[10]._y : 1 [by t.de.dly.dly[9].y:=0]
1430076 t.de.dly.dly[10].__y : 0 [by t.de.dly.dly[10]._y:=1]
1430077 t.de.dly.dly[10].___y : 1 [by t.de.dly.dly[10].__y:=0]
1431103 t.de.dly.dly[10].y : 0 [by t.de.dly.dly[10].___y:=1]
1431104 t.de.dly.dly[11]._y : 1 [by t.de.dly.dly[10].y:=0]
1431123 t.de.dly.dly[11].__y : 0 [by t.de.dly.dly[11]._y:=1]
1431291 t.de.dly.dly[11].___y : 1 [by t.de.dly.dly[11].__y:=0]
1431830 t.de.dly.dly[11].y : 0 [by t.de.dly.dly[11].___y:=1]
1431991 t.de.dly.dly[12]._y : 1 [by t.de.dly.dly[11].y:=0]
1432164 t.de.dly.dly[12].__y : 0 [by t.de.dly.dly[12]._y:=1]
1434711 t.de.dly.dly[12].___y : 1 [by t.de.dly.dly[12].__y:=0]
1449772 t.de.dly.dly[12].y : 0 [by t.de.dly.dly[12].___y:=1]
1449773 t.de.dly.dly[13]._y : 1 [by t.de.dly.dly[12].y:=0]
1449774 t.de.dly.dly[13].__y : 0 [by t.de.dly.dly[13]._y:=1]
1450164 t.de.dly.dly[13].___y : 1 [by t.de.dly.dly[13].__y:=0]
1450371 t.de.dly.dly[13].y : 0 [by t.de.dly.dly[13].___y:=1]
1451204 t.de.dly.dly[14]._y : 1 [by t.de.dly.dly[13].y:=0]
1451232 t.de.dly.dly[14].__y : 0 [by t.de.dly.dly[14]._y:=1]
1451239 t.de.dly.dly[14].___y : 1 [by t.de.dly.dly[14].__y:=0]
1451653 t.de.dly.mu2[3].b : 0 [by t.de.dly.dly[14].___y:=1]
1451657 t.de.dly.mu2[3]._y : 1 [by t.de.dly.mu2[3].b:=0]
1453436 t.de.dly.out : 0 [by t.de.dly.mu2[3]._y:=1]
1476310 t.de.addr_buf._out_a_B : 1 [by t.de.dly.out:=0]
1476476 t.de.addr_buf.out_a_B_buf_t.buf1._y : 0 [by t.de.addr_buf._out_a_B:=1]
1485121 t.de.addr_buf._out_a_BX_f[0] : 1 [by t.de.addr_buf.out_a_B_buf_t.buf1._y:=0]
1516180 t.de.addr_buf.out_a_B_buf_f.buf1._y : 0 [by t.de.addr_buf._out_a_B:=1]
1517113 t.de.addr_buf._out_a_BX_t[0] : 1 [by t.de.addr_buf.out_a_B_buf_f.buf1._y:=0]

BIN
test/unit_tests/decoder_2d_dly_and_2_4/run/prsim.pdf
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test/unit_tests/decoder_2d_dly_and_2_4/run/test.prs
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@@ -1,948 +0,0 @@
= "GND" "GND"
= "Vdd" "Vdd"
= "Reset" "Reset"
"Reset"->"t._reset_B"-
~("Reset")->"t._reset_B"+
= "t._reset_B" "t.de.reset_B"
= "t.ag.iny[0]" "t.ag.ands[1].b"
= "t.ag.iny[0]" "t.ag.ands[0].b"
= "t.ag.iny[1]" "t.ag.ands[3].b"
= "t.ag.iny[1]" "t.ag.ands[2].b"
= "t.ag.iny[2]" "t.ag.ands[5].b"
= "t.ag.iny[2]" "t.ag.ands[4].b"
= "t.ag.iny[3]" "t.ag.ands[7].b"
= "t.ag.iny[3]" "t.ag.ands[6].b"
= "t.ag.inx[0]" "t.ag.ands[6].a"
= "t.ag.inx[0]" "t.ag.ands[4].a"
= "t.ag.inx[0]" "t.ag.ands[2].a"
= "t.ag.inx[0]" "t.ag.ands[0].a"
= "t.ag.inx[1]" "t.ag.ands[7].a"
= "t.ag.inx[1]" "t.ag.ands[5].a"
= "t.ag.inx[1]" "t.ag.ands[3].a"
= "t.ag.inx[1]" "t.ag.ands[1].a"
"t.ag.ands[0].a"&"t.ag.ands[0].b"->"t.ag.ands[0]._y"-
~("t.ag.ands[0].a"&"t.ag.ands[0].b")->"t.ag.ands[0]._y"+
"t.ag.ands[0]._y"->"t.ag.ands[0].y"-
~("t.ag.ands[0]._y")->"t.ag.ands[0].y"+
"t.ag.ands[1].a"&"t.ag.ands[1].b"->"t.ag.ands[1]._y"-
~("t.ag.ands[1].a"&"t.ag.ands[1].b")->"t.ag.ands[1]._y"+
"t.ag.ands[1]._y"->"t.ag.ands[1].y"-
~("t.ag.ands[1]._y")->"t.ag.ands[1].y"+
"t.ag.ands[2].a"&"t.ag.ands[2].b"->"t.ag.ands[2]._y"-
~("t.ag.ands[2].a"&"t.ag.ands[2].b")->"t.ag.ands[2]._y"+
"t.ag.ands[2]._y"->"t.ag.ands[2].y"-
~("t.ag.ands[2]._y")->"t.ag.ands[2].y"+
"t.ag.ands[3].a"&"t.ag.ands[3].b"->"t.ag.ands[3]._y"-
~("t.ag.ands[3].a"&"t.ag.ands[3].b")->"t.ag.ands[3]._y"+
"t.ag.ands[3]._y"->"t.ag.ands[3].y"-
~("t.ag.ands[3]._y")->"t.ag.ands[3].y"+
"t.ag.ands[4].a"&"t.ag.ands[4].b"->"t.ag.ands[4]._y"-
~("t.ag.ands[4].a"&"t.ag.ands[4].b")->"t.ag.ands[4]._y"+
"t.ag.ands[4]._y"->"t.ag.ands[4].y"-
~("t.ag.ands[4]._y")->"t.ag.ands[4].y"+
"t.ag.ands[5].a"&"t.ag.ands[5].b"->"t.ag.ands[5]._y"-
~("t.ag.ands[5].a"&"t.ag.ands[5].b")->"t.ag.ands[5]._y"+
"t.ag.ands[5]._y"->"t.ag.ands[5].y"-
~("t.ag.ands[5]._y")->"t.ag.ands[5].y"+
"t.ag.ands[6].a"&"t.ag.ands[6].b"->"t.ag.ands[6]._y"-
~("t.ag.ands[6].a"&"t.ag.ands[6].b")->"t.ag.ands[6]._y"+
"t.ag.ands[6]._y"->"t.ag.ands[6].y"-
~("t.ag.ands[6]._y")->"t.ag.ands[6].y"+
"t.ag.ands[7].a"&"t.ag.ands[7].b"->"t.ag.ands[7]._y"-
~("t.ag.ands[7].a"&"t.ag.ands[7].b")->"t.ag.ands[7]._y"+
"t.ag.ands[7]._y"->"t.ag.ands[7].y"-
~("t.ag.ands[7]._y")->"t.ag.ands[7].y"+
= "t.ag.supply.vdd" "t.ag.ands[7].vdd"
= "t.ag.supply.vdd" "t.ag.ands[6].vdd"
= "t.ag.supply.vdd" "t.ag.ands[5].vdd"
= "t.ag.supply.vdd" "t.ag.ands[4].vdd"
= "t.ag.supply.vdd" "t.ag.ands[3].vdd"
= "t.ag.supply.vdd" "t.ag.ands[2].vdd"
= "t.ag.supply.vdd" "t.ag.ands[1].vdd"
= "t.ag.supply.vdd" "t.ag.ands[0].vdd"
= "t.ag.supply.vss" "t.ag.ands[7].vss"
= "t.ag.supply.vss" "t.ag.ands[6].vss"
= "t.ag.supply.vss" "t.ag.ands[5].vss"
= "t.ag.supply.vss" "t.ag.ands[4].vss"
= "t.ag.supply.vss" "t.ag.ands[3].vss"
= "t.ag.supply.vss" "t.ag.ands[2].vss"
= "t.ag.supply.vss" "t.ag.ands[1].vss"
= "t.ag.supply.vss" "t.ag.ands[0].vss"
= "t.ag.out[0]" "t.ag.ands[0].y"
= "t.ag.out[1]" "t.ag.ands[1].y"
= "t.ag.out[2]" "t.ag.ands[2].y"
= "t.ag.out[3]" "t.ag.ands[3].y"
= "t.ag.out[4]" "t.ag.ands[4].y"
= "t.ag.out[5]" "t.ag.ands[5].y"
= "t.ag.out[6]" "t.ag.ands[6].y"
= "t.ag.out[7]" "t.ag.ands[7].y"
= "t.ag.inx[0]" "t.de.outx[0]"
= "t.ag.inx[1]" "t.de.outx[1]"
= "t.ag.iny[0]" "t.de.outy[0]"
= "t.ag.iny[1]" "t.de.outy[1]"
= "t.ag.iny[2]" "t.de.outy[2]"
= "t.ag.iny[3]" "t.de.outy[3]"
= "Vdd" "t.ag.supply.vdd"
= "GND" "t.ag.supply.vss"
"t.de.atree_x[0].b.a"->"t.de.atree_x[0].b._y"-
~("t.de.atree_x[0].b.a")->"t.de.atree_x[0].b._y"+
"t.de.atree_x[0].b._y"->"t.de.atree_x[0].b.y"-
~("t.de.atree_x[0].b._y")->"t.de.atree_x[0].b.y"+
= "t.de.atree_x[0].supply.vdd" "t.de.atree_x[0].b.vdd"
= "t.de.atree_x[0].supply.vss" "t.de.atree_x[0].b.vss"
= "t.de.atree_x[0].out" "t.de.atree_x[0].b.y"
= "t.de.atree_x[0].in[0]" "t.de.atree_x[0].b.a"
"t.de.atree_x[1].b.a"->"t.de.atree_x[1].b._y"-
~("t.de.atree_x[1].b.a")->"t.de.atree_x[1].b._y"+
"t.de.atree_x[1].b._y"->"t.de.atree_x[1].b.y"-
~("t.de.atree_x[1].b._y")->"t.de.atree_x[1].b.y"+
= "t.de.atree_x[1].supply.vdd" "t.de.atree_x[1].b.vdd"
= "t.de.atree_x[1].supply.vss" "t.de.atree_x[1].b.vss"
= "t.de.atree_x[1].out" "t.de.atree_x[1].b.y"
= "t.de.atree_x[1].in[0]" "t.de.atree_x[1].b.a"
= "t.de.atree_x[1].in[0]" "t.de.addr_buf.out.d.d[0].t"
= "t.de.atree_x[1].in[0]" "t.de.addr_buf.out.d.d[0].d[1]"
= "t.de.atree_x[1].in[0]" "t.de.vtree_x.in.d[0].t"
= "t.de.atree_x[1].in[0]" "t.de.vtree_x.in.d[0].d[1]"
= "t.de.atree_x[0].in[0]" "t.de.addr_buf.out.d.d[0].f"
= "t.de.atree_x[0].in[0]" "t.de.addr_buf.out.d.d[0].d[0]"
= "t.de.atree_x[0].in[0]" "t.de.vtree_x.in.d[0].f"
= "t.de.atree_x[0].in[0]" "t.de.vtree_x.in.d[0].d[0]"
= "t.de.dly_cfg[0]" "t.de.dly.s[0]"
= "t.de.dly_cfg[1]" "t.de.dly.s[1]"
= "t.de.dly_cfg[2]" "t.de.dly.s[2]"
= "t.de.dly_cfg[3]" "t.de.dly.s[3]"
= "t.de.supply.vss" "t.de.atree_y[3].supply.vss"
= "t.de.supply.vdd" "t.de.atree_y[3].supply.vdd"
= "t.de.supply.vss" "t.de.atree_y[2].supply.vss"
= "t.de.supply.vdd" "t.de.atree_y[2].supply.vdd"
= "t.de.supply.vss" "t.de.atree_y[1].supply.vss"
= "t.de.supply.vdd" "t.de.atree_y[1].supply.vdd"
= "t.de.supply.vss" "t.de.atree_y[0].supply.vss"
= "t.de.supply.vdd" "t.de.atree_y[0].supply.vdd"
= "t.de.supply.vss" "t.de.atree_x[1].supply.vss"
= "t.de.supply.vdd" "t.de.atree_x[1].supply.vdd"
= "t.de.supply.vss" "t.de.atree_x[0].supply.vss"
= "t.de.supply.vdd" "t.de.atree_x[0].supply.vdd"
= "t.de.supply.vss" "t.de.dly.supply.vss"
= "t.de.supply.vdd" "t.de.dly.supply.vdd"
= "t.de.supply.vss" "t.de.vtree_y.supply.vss"
= "t.de.supply.vdd" "t.de.vtree_y.supply.vdd"
= "t.de.supply.vss" "t.de.vtree_x.supply.vss"
= "t.de.supply.vdd" "t.de.vtree_x.supply.vdd"
= "t.de.supply.vss" "t.de.addr_buf.supply.vss"
= "t.de.supply.vdd" "t.de.addr_buf.supply.vdd"
= "t.de.supply.vdd" "t.de.C2el.vdd"
= "t.de.supply.vss" "t.de.C2el.vss"
~"t.de.C2el.c1"&~"t.de.C2el.c2"->"t.de.C2el._y"+
"t.de.C2el.c1"&"t.de.C2el.c2"->"t.de.C2el._y"-
"t.de.C2el._y"->"t.de.C2el.y"-
~("t.de.C2el._y")->"t.de.C2el.y"+
= "t.de.C2el.c1" "t.de.vtree_x.out"
= "t.de.C2el.c2" "t.de.vtree_y.out"
"t.de.dly.and2[0].a"&"t.de.dly.and2[0].b"->"t.de.dly.and2[0]._y"-
~("t.de.dly.and2[0].a"&"t.de.dly.and2[0].b")->"t.de.dly.and2[0]._y"+
"t.de.dly.and2[0]._y"->"t.de.dly.and2[0].y"-
~("t.de.dly.and2[0]._y")->"t.de.dly.and2[0].y"+
"t.de.dly.and2[1].a"&"t.de.dly.and2[1].b"->"t.de.dly.and2[1]._y"-
~("t.de.dly.and2[1].a"&"t.de.dly.and2[1].b")->"t.de.dly.and2[1]._y"+
"t.de.dly.and2[1]._y"->"t.de.dly.and2[1].y"-
~("t.de.dly.and2[1]._y")->"t.de.dly.and2[1].y"+
"t.de.dly.and2[2].a"&"t.de.dly.and2[2].b"->"t.de.dly.and2[2]._y"-
~("t.de.dly.and2[2].a"&"t.de.dly.and2[2].b")->"t.de.dly.and2[2]._y"+
"t.de.dly.and2[2]._y"->"t.de.dly.and2[2].y"-
~("t.de.dly.and2[2]._y")->"t.de.dly.and2[2].y"+
"t.de.dly.and2[3].a"&"t.de.dly.and2[3].b"->"t.de.dly.and2[3]._y"-
~("t.de.dly.and2[3].a"&"t.de.dly.and2[3].b")->"t.de.dly.and2[3]._y"+
"t.de.dly.and2[3]._y"->"t.de.dly.and2[3].y"-
~("t.de.dly.and2[3]._y")->"t.de.dly.and2[3].y"+
= "t.de.dly.s[0]" "t.de.dly.mu2[0].s"
= "t.de.dly.s[0]" "t.de.dly.and2[0].b"
= "t.de.dly.s[1]" "t.de.dly.mu2[1].s"
= "t.de.dly.s[1]" "t.de.dly.and2[1].b"
= "t.de.dly.s[2]" "t.de.dly.mu2[2].s"
= "t.de.dly.s[2]" "t.de.dly.and2[2].b"
= "t.de.dly.s[3]" "t.de.dly.mu2[3].s"
= "t.de.dly.s[3]" "t.de.dly.and2[3].b"
= "t.de.dly.supply.vdd" "t.de.dly.dly[14].vdd"
= "t.de.dly.supply.vdd" "t.de.dly.dly[13].vdd"
= "t.de.dly.supply.vdd" "t.de.dly.dly[12].vdd"
= "t.de.dly.supply.vdd" "t.de.dly.dly[11].vdd"
= "t.de.dly.supply.vdd" "t.de.dly.dly[10].vdd"
= "t.de.dly.supply.vdd" "t.de.dly.dly[9].vdd"
= "t.de.dly.supply.vdd" "t.de.dly.dly[8].vdd"
= "t.de.dly.supply.vdd" "t.de.dly.dly[7].vdd"
= "t.de.dly.supply.vdd" "t.de.dly.dly[6].vdd"
= "t.de.dly.supply.vdd" "t.de.dly.dly[5].vdd"
= "t.de.dly.supply.vdd" "t.de.dly.dly[4].vdd"
= "t.de.dly.supply.vdd" "t.de.dly.dly[3].vdd"
= "t.de.dly.supply.vdd" "t.de.dly.dly[2].vdd"
= "t.de.dly.supply.vdd" "t.de.dly.dly[1].vdd"
= "t.de.dly.supply.vdd" "t.de.dly.dly[0].vdd"
= "t.de.dly.supply.vdd" "t.de.dly.mu2[3].vdd"
= "t.de.dly.supply.vdd" "t.de.dly.mu2[2].vdd"
= "t.de.dly.supply.vdd" "t.de.dly.mu2[1].vdd"
= "t.de.dly.supply.vdd" "t.de.dly.mu2[0].vdd"
= "t.de.dly.supply.vdd" "t.de.dly.and2[3].vdd"
= "t.de.dly.supply.vdd" "t.de.dly.and2[2].vdd"
= "t.de.dly.supply.vdd" "t.de.dly.and2[1].vdd"
= "t.de.dly.supply.vdd" "t.de.dly.and2[0].vdd"
= "t.de.dly.supply.vss" "t.de.dly.dly[14].vss"
= "t.de.dly.supply.vss" "t.de.dly.dly[13].vss"
= "t.de.dly.supply.vss" "t.de.dly.dly[12].vss"
= "t.de.dly.supply.vss" "t.de.dly.dly[11].vss"
= "t.de.dly.supply.vss" "t.de.dly.dly[10].vss"
= "t.de.dly.supply.vss" "t.de.dly.dly[9].vss"
= "t.de.dly.supply.vss" "t.de.dly.dly[8].vss"
= "t.de.dly.supply.vss" "t.de.dly.dly[7].vss"
= "t.de.dly.supply.vss" "t.de.dly.dly[6].vss"
= "t.de.dly.supply.vss" "t.de.dly.dly[5].vss"
= "t.de.dly.supply.vss" "t.de.dly.dly[4].vss"
= "t.de.dly.supply.vss" "t.de.dly.dly[3].vss"
= "t.de.dly.supply.vss" "t.de.dly.dly[2].vss"
= "t.de.dly.supply.vss" "t.de.dly.dly[1].vss"
= "t.de.dly.supply.vss" "t.de.dly.dly[0].vss"
= "t.de.dly.supply.vss" "t.de.dly.mu2[3].vss"
= "t.de.dly.supply.vss" "t.de.dly.mu2[2].vss"
= "t.de.dly.supply.vss" "t.de.dly.mu2[1].vss"
= "t.de.dly.supply.vss" "t.de.dly.mu2[0].vss"
= "t.de.dly.supply.vss" "t.de.dly.and2[3].vss"
= "t.de.dly.supply.vss" "t.de.dly.and2[2].vss"
= "t.de.dly.supply.vss" "t.de.dly.and2[1].vss"
= "t.de.dly.supply.vss" "t.de.dly.and2[0].vss"
"t.de.dly.mu2[0].s"->"t.de.dly.mu2[0]._s"-
~("t.de.dly.mu2[0].s")->"t.de.dly.mu2[0]._s"+
~"t.de.dly.mu2[0].a"&~"t.de.dly.mu2[0].s"|~"t.de.dly.mu2[0].b"&~"t.de.dly.mu2[0]._s"->"t.de.dly.mu2[0]._y"+
"t.de.dly.mu2[0].a"&"t.de.dly.mu2[0]._s"|"t.de.dly.mu2[0].b"&"t.de.dly.mu2[0].s"->"t.de.dly.mu2[0]._y"-
"t.de.dly.mu2[0]._y"->"t.de.dly.mu2[0].y"-
~("t.de.dly.mu2[0]._y")->"t.de.dly.mu2[0].y"+
"t.de.dly.mu2[1].s"->"t.de.dly.mu2[1]._s"-
~("t.de.dly.mu2[1].s")->"t.de.dly.mu2[1]._s"+
~"t.de.dly.mu2[1].a"&~"t.de.dly.mu2[1].s"|~"t.de.dly.mu2[1].b"&~"t.de.dly.mu2[1]._s"->"t.de.dly.mu2[1]._y"+
"t.de.dly.mu2[1].a"&"t.de.dly.mu2[1]._s"|"t.de.dly.mu2[1].b"&"t.de.dly.mu2[1].s"->"t.de.dly.mu2[1]._y"-
"t.de.dly.mu2[1]._y"->"t.de.dly.mu2[1].y"-
~("t.de.dly.mu2[1]._y")->"t.de.dly.mu2[1].y"+
"t.de.dly.mu2[2].s"->"t.de.dly.mu2[2]._s"-
~("t.de.dly.mu2[2].s")->"t.de.dly.mu2[2]._s"+
~"t.de.dly.mu2[2].a"&~"t.de.dly.mu2[2].s"|~"t.de.dly.mu2[2].b"&~"t.de.dly.mu2[2]._s"->"t.de.dly.mu2[2]._y"+
"t.de.dly.mu2[2].a"&"t.de.dly.mu2[2]._s"|"t.de.dly.mu2[2].b"&"t.de.dly.mu2[2].s"->"t.de.dly.mu2[2]._y"-
"t.de.dly.mu2[2]._y"->"t.de.dly.mu2[2].y"-
~("t.de.dly.mu2[2]._y")->"t.de.dly.mu2[2].y"+
"t.de.dly.mu2[3].s"->"t.de.dly.mu2[3]._s"-
~("t.de.dly.mu2[3].s")->"t.de.dly.mu2[3]._s"+
~"t.de.dly.mu2[3].a"&~"t.de.dly.mu2[3].s"|~"t.de.dly.mu2[3].b"&~"t.de.dly.mu2[3]._s"->"t.de.dly.mu2[3]._y"+
"t.de.dly.mu2[3].a"&"t.de.dly.mu2[3]._s"|"t.de.dly.mu2[3].b"&"t.de.dly.mu2[3].s"->"t.de.dly.mu2[3]._y"-
"t.de.dly.mu2[3]._y"->"t.de.dly.mu2[3].y"-
~("t.de.dly.mu2[3]._y")->"t.de.dly.mu2[3].y"+
"t.de.dly.dly[0].a"->"t.de.dly.dly[0]._y"-
~("t.de.dly.dly[0].a")->"t.de.dly.dly[0]._y"+
"t.de.dly.dly[0]._y"->"t.de.dly.dly[0].__y"-
~("t.de.dly.dly[0]._y")->"t.de.dly.dly[0].__y"+
"t.de.dly.dly[0].__y"->"t.de.dly.dly[0].___y"-
~("t.de.dly.dly[0].__y")->"t.de.dly.dly[0].___y"+
"t.de.dly.dly[0].___y"->"t.de.dly.dly[0].y"-
~("t.de.dly.dly[0].___y")->"t.de.dly.dly[0].y"+
"t.de.dly.dly[1].a"->"t.de.dly.dly[1]._y"-
~("t.de.dly.dly[1].a")->"t.de.dly.dly[1]._y"+
"t.de.dly.dly[1]._y"->"t.de.dly.dly[1].__y"-
~("t.de.dly.dly[1]._y")->"t.de.dly.dly[1].__y"+
"t.de.dly.dly[1].__y"->"t.de.dly.dly[1].___y"-
~("t.de.dly.dly[1].__y")->"t.de.dly.dly[1].___y"+
"t.de.dly.dly[1].___y"->"t.de.dly.dly[1].y"-
~("t.de.dly.dly[1].___y")->"t.de.dly.dly[1].y"+
"t.de.dly.dly[2].a"->"t.de.dly.dly[2]._y"-
~("t.de.dly.dly[2].a")->"t.de.dly.dly[2]._y"+
"t.de.dly.dly[2]._y"->"t.de.dly.dly[2].__y"-
~("t.de.dly.dly[2]._y")->"t.de.dly.dly[2].__y"+
"t.de.dly.dly[2].__y"->"t.de.dly.dly[2].___y"-
~("t.de.dly.dly[2].__y")->"t.de.dly.dly[2].___y"+
"t.de.dly.dly[2].___y"->"t.de.dly.dly[2].y"-
~("t.de.dly.dly[2].___y")->"t.de.dly.dly[2].y"+
"t.de.dly.dly[3].a"->"t.de.dly.dly[3]._y"-
~("t.de.dly.dly[3].a")->"t.de.dly.dly[3]._y"+
"t.de.dly.dly[3]._y"->"t.de.dly.dly[3].__y"-
~("t.de.dly.dly[3]._y")->"t.de.dly.dly[3].__y"+
"t.de.dly.dly[3].__y"->"t.de.dly.dly[3].___y"-
~("t.de.dly.dly[3].__y")->"t.de.dly.dly[3].___y"+
"t.de.dly.dly[3].___y"->"t.de.dly.dly[3].y"-
~("t.de.dly.dly[3].___y")->"t.de.dly.dly[3].y"+
"t.de.dly.dly[4].a"->"t.de.dly.dly[4]._y"-
~("t.de.dly.dly[4].a")->"t.de.dly.dly[4]._y"+
"t.de.dly.dly[4]._y"->"t.de.dly.dly[4].__y"-
~("t.de.dly.dly[4]._y")->"t.de.dly.dly[4].__y"+
"t.de.dly.dly[4].__y"->"t.de.dly.dly[4].___y"-
~("t.de.dly.dly[4].__y")->"t.de.dly.dly[4].___y"+
"t.de.dly.dly[4].___y"->"t.de.dly.dly[4].y"-
~("t.de.dly.dly[4].___y")->"t.de.dly.dly[4].y"+
"t.de.dly.dly[5].a"->"t.de.dly.dly[5]._y"-
~("t.de.dly.dly[5].a")->"t.de.dly.dly[5]._y"+
"t.de.dly.dly[5]._y"->"t.de.dly.dly[5].__y"-
~("t.de.dly.dly[5]._y")->"t.de.dly.dly[5].__y"+
"t.de.dly.dly[5].__y"->"t.de.dly.dly[5].___y"-
~("t.de.dly.dly[5].__y")->"t.de.dly.dly[5].___y"+
"t.de.dly.dly[5].___y"->"t.de.dly.dly[5].y"-
~("t.de.dly.dly[5].___y")->"t.de.dly.dly[5].y"+
"t.de.dly.dly[6].a"->"t.de.dly.dly[6]._y"-
~("t.de.dly.dly[6].a")->"t.de.dly.dly[6]._y"+
"t.de.dly.dly[6]._y"->"t.de.dly.dly[6].__y"-
~("t.de.dly.dly[6]._y")->"t.de.dly.dly[6].__y"+
"t.de.dly.dly[6].__y"->"t.de.dly.dly[6].___y"-
~("t.de.dly.dly[6].__y")->"t.de.dly.dly[6].___y"+
"t.de.dly.dly[6].___y"->"t.de.dly.dly[6].y"-
~("t.de.dly.dly[6].___y")->"t.de.dly.dly[6].y"+
"t.de.dly.dly[7].a"->"t.de.dly.dly[7]._y"-
~("t.de.dly.dly[7].a")->"t.de.dly.dly[7]._y"+
"t.de.dly.dly[7]._y"->"t.de.dly.dly[7].__y"-
~("t.de.dly.dly[7]._y")->"t.de.dly.dly[7].__y"+
"t.de.dly.dly[7].__y"->"t.de.dly.dly[7].___y"-
~("t.de.dly.dly[7].__y")->"t.de.dly.dly[7].___y"+
"t.de.dly.dly[7].___y"->"t.de.dly.dly[7].y"-
~("t.de.dly.dly[7].___y")->"t.de.dly.dly[7].y"+
"t.de.dly.dly[8].a"->"t.de.dly.dly[8]._y"-
~("t.de.dly.dly[8].a")->"t.de.dly.dly[8]._y"+
"t.de.dly.dly[8]._y"->"t.de.dly.dly[8].__y"-
~("t.de.dly.dly[8]._y")->"t.de.dly.dly[8].__y"+
"t.de.dly.dly[8].__y"->"t.de.dly.dly[8].___y"-
~("t.de.dly.dly[8].__y")->"t.de.dly.dly[8].___y"+
"t.de.dly.dly[8].___y"->"t.de.dly.dly[8].y"-
~("t.de.dly.dly[8].___y")->"t.de.dly.dly[8].y"+
"t.de.dly.dly[9].a"->"t.de.dly.dly[9]._y"-
~("t.de.dly.dly[9].a")->"t.de.dly.dly[9]._y"+
"t.de.dly.dly[9]._y"->"t.de.dly.dly[9].__y"-
~("t.de.dly.dly[9]._y")->"t.de.dly.dly[9].__y"+
"t.de.dly.dly[9].__y"->"t.de.dly.dly[9].___y"-
~("t.de.dly.dly[9].__y")->"t.de.dly.dly[9].___y"+
"t.de.dly.dly[9].___y"->"t.de.dly.dly[9].y"-
~("t.de.dly.dly[9].___y")->"t.de.dly.dly[9].y"+
"t.de.dly.dly[10].a"->"t.de.dly.dly[10]._y"-
~("t.de.dly.dly[10].a")->"t.de.dly.dly[10]._y"+
"t.de.dly.dly[10]._y"->"t.de.dly.dly[10].__y"-
~("t.de.dly.dly[10]._y")->"t.de.dly.dly[10].__y"+
"t.de.dly.dly[10].__y"->"t.de.dly.dly[10].___y"-
~("t.de.dly.dly[10].__y")->"t.de.dly.dly[10].___y"+
"t.de.dly.dly[10].___y"->"t.de.dly.dly[10].y"-
~("t.de.dly.dly[10].___y")->"t.de.dly.dly[10].y"+
"t.de.dly.dly[11].a"->"t.de.dly.dly[11]._y"-
~("t.de.dly.dly[11].a")->"t.de.dly.dly[11]._y"+
"t.de.dly.dly[11]._y"->"t.de.dly.dly[11].__y"-
~("t.de.dly.dly[11]._y")->"t.de.dly.dly[11].__y"+
"t.de.dly.dly[11].__y"->"t.de.dly.dly[11].___y"-
~("t.de.dly.dly[11].__y")->"t.de.dly.dly[11].___y"+
"t.de.dly.dly[11].___y"->"t.de.dly.dly[11].y"-
~("t.de.dly.dly[11].___y")->"t.de.dly.dly[11].y"+
"t.de.dly.dly[12].a"->"t.de.dly.dly[12]._y"-
~("t.de.dly.dly[12].a")->"t.de.dly.dly[12]._y"+
"t.de.dly.dly[12]._y"->"t.de.dly.dly[12].__y"-
~("t.de.dly.dly[12]._y")->"t.de.dly.dly[12].__y"+
"t.de.dly.dly[12].__y"->"t.de.dly.dly[12].___y"-
~("t.de.dly.dly[12].__y")->"t.de.dly.dly[12].___y"+
"t.de.dly.dly[12].___y"->"t.de.dly.dly[12].y"-
~("t.de.dly.dly[12].___y")->"t.de.dly.dly[12].y"+
"t.de.dly.dly[13].a"->"t.de.dly.dly[13]._y"-
~("t.de.dly.dly[13].a")->"t.de.dly.dly[13]._y"+
"t.de.dly.dly[13]._y"->"t.de.dly.dly[13].__y"-
~("t.de.dly.dly[13]._y")->"t.de.dly.dly[13].__y"+
"t.de.dly.dly[13].__y"->"t.de.dly.dly[13].___y"-
~("t.de.dly.dly[13].__y")->"t.de.dly.dly[13].___y"+
"t.de.dly.dly[13].___y"->"t.de.dly.dly[13].y"-
~("t.de.dly.dly[13].___y")->"t.de.dly.dly[13].y"+
"t.de.dly.dly[14].a"->"t.de.dly.dly[14]._y"-
~("t.de.dly.dly[14].a")->"t.de.dly.dly[14]._y"+
"t.de.dly.dly[14]._y"->"t.de.dly.dly[14].__y"-
~("t.de.dly.dly[14]._y")->"t.de.dly.dly[14].__y"+
"t.de.dly.dly[14].__y"->"t.de.dly.dly[14].___y"-
~("t.de.dly.dly[14].__y")->"t.de.dly.dly[14].___y"+
"t.de.dly.dly[14].___y"->"t.de.dly.dly[14].y"-
~("t.de.dly.dly[14].___y")->"t.de.dly.dly[14].y"+
= "t.de.dly.dly[14].y" "t.de.dly.mu2[3].b"
= "t.de.dly.dly[14].a" "t.de.dly.dly[13].y"
= "t.de.dly.dly[13].a" "t.de.dly.dly[12].y"
= "t.de.dly.dly[12].a" "t.de.dly.dly[11].y"
= "t.de.dly.dly[11].a" "t.de.dly.dly[10].y"
= "t.de.dly.dly[10].a" "t.de.dly.dly[9].y"
= "t.de.dly.dly[9].a" "t.de.dly.dly[8].y"
= "t.de.dly.dly[8].a" "t.de.dly.dly[7].y"
= "t.de.dly.dly[7].a" "t.de.dly.and2[3].y"
= "t.de.dly.dly[6].y" "t.de.dly.mu2[2].b"
= "t.de.dly.dly[6].a" "t.de.dly.dly[5].y"
= "t.de.dly.dly[5].a" "t.de.dly.dly[4].y"
= "t.de.dly.dly[4].a" "t.de.dly.dly[3].y"
= "t.de.dly.dly[3].a" "t.de.dly.and2[2].y"
= "t.de.dly.dly[2].y" "t.de.dly.mu2[1].b"
= "t.de.dly.dly[2].a" "t.de.dly.dly[1].y"
= "t.de.dly.dly[1].a" "t.de.dly.and2[1].y"
= "t.de.dly.dly[0].y" "t.de.dly.mu2[0].b"
= "t.de.dly.dly[0].a" "t.de.dly.and2[0].y"
= "t.de.dly._a[1]" "t.de.dly.mu2[1].a"
= "t.de.dly._a[1]" "t.de.dly.and2[1].a"
= "t.de.dly._a[1]" "t.de.dly.mu2[0].y"
= "t.de.dly._a[2]" "t.de.dly.mu2[2].a"
= "t.de.dly._a[2]" "t.de.dly.and2[2].a"
= "t.de.dly._a[2]" "t.de.dly.mu2[1].y"
= "t.de.dly._a[3]" "t.de.dly.mu2[3].a"
= "t.de.dly._a[3]" "t.de.dly.and2[3].a"
= "t.de.dly._a[3]" "t.de.dly.mu2[2].y"
= "t.de.dly.out" "t.de.dly.mu2[3].y"
= "t.de.dly.out" "t.de.dly._a[4]"
= "t.de.dly.in" "t.de.dly.mu2[0].a"
= "t.de.dly.in" "t.de.dly.and2[0].a"
= "t.de.dly.in" "t.de.dly._a[0]"
= "t.de.dly.out" "t.de.addr_buf.out.a"
= "t.de.dly.in" "t.de.addr_buf.out.v"
= "t.de.dly.in" "t.de.C2el.y"
= "t.de.atree_y[0].supply.vdd" "t.de.atree_y[0].and2s[0].vdd"
= "t.de.atree_y[0].supply.vss" "t.de.atree_y[0].and2s[0].vss"
"t.de.atree_y[0].and2s[0].a"&"t.de.atree_y[0].and2s[0].b"->"t.de.atree_y[0].and2s[0]._y"-
~("t.de.atree_y[0].and2s[0].a"&"t.de.atree_y[0].and2s[0].b")->"t.de.atree_y[0].and2s[0]._y"+
"t.de.atree_y[0].and2s[0]._y"->"t.de.atree_y[0].and2s[0].y"-
~("t.de.atree_y[0].and2s[0]._y")->"t.de.atree_y[0].and2s[0].y"+
= "t.de.atree_y[0].in[0]" "t.de.atree_y[0].and2s[0].a"
= "t.de.atree_y[0].in[0]" "t.de.atree_y[0].tmp[0]"
= "t.de.atree_y[0].in[1]" "t.de.atree_y[0].and2s[0].b"
= "t.de.atree_y[0].in[1]" "t.de.atree_y[0].tmp[1]"
= "t.de.atree_y[0].out" "t.de.atree_y[0].and2s[0].y"
= "t.de.atree_y[0].out" "t.de.atree_y[0].tmp[2]"
= "t.de.atree_y[1].supply.vdd" "t.de.atree_y[1].and2s[0].vdd"
= "t.de.atree_y[1].supply.vss" "t.de.atree_y[1].and2s[0].vss"
"t.de.atree_y[1].and2s[0].a"&"t.de.atree_y[1].and2s[0].b"->"t.de.atree_y[1].and2s[0]._y"-
~("t.de.atree_y[1].and2s[0].a"&"t.de.atree_y[1].and2s[0].b")->"t.de.atree_y[1].and2s[0]._y"+
"t.de.atree_y[1].and2s[0]._y"->"t.de.atree_y[1].and2s[0].y"-
~("t.de.atree_y[1].and2s[0]._y")->"t.de.atree_y[1].and2s[0].y"+
= "t.de.atree_y[1].in[0]" "t.de.atree_y[1].and2s[0].a"
= "t.de.atree_y[1].in[0]" "t.de.atree_y[1].tmp[0]"
= "t.de.atree_y[1].in[1]" "t.de.atree_y[1].and2s[0].b"
= "t.de.atree_y[1].in[1]" "t.de.atree_y[1].tmp[1]"
= "t.de.atree_y[1].out" "t.de.atree_y[1].and2s[0].y"
= "t.de.atree_y[1].out" "t.de.atree_y[1].tmp[2]"
= "t.de.atree_y[2].supply.vdd" "t.de.atree_y[2].and2s[0].vdd"
= "t.de.atree_y[2].supply.vss" "t.de.atree_y[2].and2s[0].vss"
"t.de.atree_y[2].and2s[0].a"&"t.de.atree_y[2].and2s[0].b"->"t.de.atree_y[2].and2s[0]._y"-
~("t.de.atree_y[2].and2s[0].a"&"t.de.atree_y[2].and2s[0].b")->"t.de.atree_y[2].and2s[0]._y"+
"t.de.atree_y[2].and2s[0]._y"->"t.de.atree_y[2].and2s[0].y"-
~("t.de.atree_y[2].and2s[0]._y")->"t.de.atree_y[2].and2s[0].y"+
= "t.de.atree_y[2].in[0]" "t.de.atree_y[2].and2s[0].a"
= "t.de.atree_y[2].in[0]" "t.de.atree_y[2].tmp[0]"
= "t.de.atree_y[2].in[1]" "t.de.atree_y[2].and2s[0].b"
= "t.de.atree_y[2].in[1]" "t.de.atree_y[2].tmp[1]"
= "t.de.atree_y[2].out" "t.de.atree_y[2].and2s[0].y"
= "t.de.atree_y[2].out" "t.de.atree_y[2].tmp[2]"
= "t.de.atree_y[3].supply.vdd" "t.de.atree_y[3].and2s[0].vdd"
= "t.de.atree_y[3].supply.vss" "t.de.atree_y[3].and2s[0].vss"
"t.de.atree_y[3].and2s[0].a"&"t.de.atree_y[3].and2s[0].b"->"t.de.atree_y[3].and2s[0]._y"-
~("t.de.atree_y[3].and2s[0].a"&"t.de.atree_y[3].and2s[0].b")->"t.de.atree_y[3].and2s[0]._y"+
"t.de.atree_y[3].and2s[0]._y"->"t.de.atree_y[3].and2s[0].y"-
~("t.de.atree_y[3].and2s[0]._y")->"t.de.atree_y[3].and2s[0].y"+
= "t.de.atree_y[3].in[0]" "t.de.atree_y[3].and2s[0].a"
= "t.de.atree_y[3].in[0]" "t.de.atree_y[3].tmp[0]"
= "t.de.atree_y[3].in[1]" "t.de.atree_y[3].and2s[0].b"
= "t.de.atree_y[3].in[1]" "t.de.atree_y[3].tmp[1]"
= "t.de.atree_y[3].out" "t.de.atree_y[3].and2s[0].y"
= "t.de.atree_y[3].out" "t.de.atree_y[3].tmp[2]"
= "t.de.atree_y[3].in[0]" "t.de.addr_buf.out.d.d[1].t"
= "t.de.atree_y[3].in[0]" "t.de.addr_buf.out.d.d[1].d[1]"
= "t.de.atree_y[3].in[0]" "t.de.vtree_y.in.d[0].t"
= "t.de.atree_y[3].in[0]" "t.de.vtree_y.in.d[0].d[1]"
= "t.de.atree_y[3].in[0]" "t.de.atree_y[1].in[0]"
= "t.de.atree_y[3].in[1]" "t.de.addr_buf.out.d.d[2].t"
= "t.de.atree_y[3].in[1]" "t.de.addr_buf.out.d.d[2].d[1]"
= "t.de.atree_y[3].in[1]" "t.de.vtree_y.in.d[1].t"
= "t.de.atree_y[3].in[1]" "t.de.vtree_y.in.d[1].d[1]"
= "t.de.atree_y[3].in[1]" "t.de.atree_y[2].in[1]"
= "t.de.atree_y[2].in[0]" "t.de.addr_buf.out.d.d[1].f"
= "t.de.atree_y[2].in[0]" "t.de.addr_buf.out.d.d[1].d[0]"
= "t.de.atree_y[2].in[0]" "t.de.vtree_y.in.d[0].f"
= "t.de.atree_y[2].in[0]" "t.de.vtree_y.in.d[0].d[0]"
= "t.de.atree_y[2].in[0]" "t.de.atree_y[0].in[0]"
= "t.de.atree_y[1].in[1]" "t.de.addr_buf.out.d.d[2].f"
= "t.de.atree_y[1].in[1]" "t.de.addr_buf.out.d.d[2].d[0]"
= "t.de.atree_y[1].in[1]" "t.de.vtree_y.in.d[1].f"
= "t.de.atree_y[1].in[1]" "t.de.vtree_y.in.d[1].d[0]"
= "t.de.atree_y[1].in[1]" "t.de.atree_y[0].in[1]"
= "t.de.in.d.d[0].d[0]" "t.de.in.d.d[0].f"
= "t.de.in.d.d[0].d[1]" "t.de.in.d.d[0].t"
= "t.de.in.d.d[1].d[0]" "t.de.in.d.d[1].f"
= "t.de.in.d.d[1].d[1]" "t.de.in.d.d[1].t"
= "t.de.in.d.d[2].d[0]" "t.de.in.d.d[2].f"
= "t.de.in.d.d[2].d[1]" "t.de.in.d.d[2].t"
= "t.de.in.d.d[2].d[0]" "t.de.in.d.d[2].f"
= "t.de.in.d.d[2].d[1]" "t.de.in.d.d[2].t"
= "t.de.in.d.d[1].d[0]" "t.de.in.d.d[1].f"
= "t.de.in.d.d[1].d[1]" "t.de.in.d.d[1].t"
= "t.de.in.d.d[0].d[0]" "t.de.in.d.d[0].f"
= "t.de.in.d.d[0].d[1]" "t.de.in.d.d[0].t"
= "t.de.in.d.d[2].d[0]" "t.de.in.d.d[2].f"
= "t.de.in.d.d[2].d[1]" "t.de.in.d.d[2].t"
= "t.de.in.d.d[1].d[0]" "t.de.in.d.d[1].f"
= "t.de.in.d.d[1].d[1]" "t.de.in.d.d[1].t"
= "t.de.in.d.d[0].d[0]" "t.de.in.d.d[0].f"
= "t.de.in.d.d[0].d[1]" "t.de.in.d.d[0].t"
= "t.de.in.v" "t.de.addr_buf.in.v"
= "t.de.in.a" "t.de.addr_buf.in.a"
= "t.de.in.d.d[0].f" "t.de.addr_buf.in.d.d[0].f"
= "t.de.in.d.d[0].t" "t.de.addr_buf.in.d.d[0].t"
= "t.de.in.d.d[0].d[0]" "t.de.addr_buf.in.d.d[0].d[0]"
= "t.de.in.d.d[0].d[1]" "t.de.addr_buf.in.d.d[0].d[1]"
= "t.de.in.d.d[1].f" "t.de.addr_buf.in.d.d[1].f"
= "t.de.in.d.d[1].t" "t.de.addr_buf.in.d.d[1].t"
= "t.de.in.d.d[1].d[0]" "t.de.addr_buf.in.d.d[1].d[0]"
= "t.de.in.d.d[1].d[1]" "t.de.addr_buf.in.d.d[1].d[1]"
= "t.de.in.d.d[2].f" "t.de.addr_buf.in.d.d[2].f"
= "t.de.in.d.d[2].t" "t.de.addr_buf.in.d.d[2].t"
= "t.de.in.d.d[2].d[0]" "t.de.addr_buf.in.d.d[2].d[0]"
= "t.de.in.d.d[2].d[1]" "t.de.addr_buf.in.d.d[2].d[1]"
= "t.de.in.d.d[2].d[0]" "t.de.in.d.d[2].f"
= "t.de.in.d.d[2].d[1]" "t.de.in.d.d[2].t"
= "t.de.in.d.d[1].d[0]" "t.de.in.d.d[1].f"
= "t.de.in.d.d[1].d[1]" "t.de.in.d.d[1].t"
= "t.de.in.d.d[0].d[0]" "t.de.in.d.d[0].f"
= "t.de.in.d.d[0].d[1]" "t.de.in.d.d[0].t"
~"t.de.vtree_y.ct.C2Els[0].c1"&~"t.de.vtree_y.ct.C2Els[0].c2"->"t.de.vtree_y.ct.C2Els[0]._y"+
"t.de.vtree_y.ct.C2Els[0].c1"&"t.de.vtree_y.ct.C2Els[0].c2"->"t.de.vtree_y.ct.C2Els[0]._y"-
"t.de.vtree_y.ct.C2Els[0]._y"->"t.de.vtree_y.ct.C2Els[0].y"-
~("t.de.vtree_y.ct.C2Els[0]._y")->"t.de.vtree_y.ct.C2Els[0].y"+
= "t.de.vtree_y.ct.supply.vdd" "t.de.vtree_y.ct.C2Els[0].vdd"
= "t.de.vtree_y.ct.supply.vss" "t.de.vtree_y.ct.C2Els[0].vss"
= "t.de.vtree_y.ct.in[0]" "t.de.vtree_y.ct.C2Els[0].c1"
= "t.de.vtree_y.ct.in[0]" "t.de.vtree_y.ct.tmp[0]"
= "t.de.vtree_y.ct.in[1]" "t.de.vtree_y.ct.C2Els[0].c2"
= "t.de.vtree_y.ct.in[1]" "t.de.vtree_y.ct.tmp[1]"
= "t.de.vtree_y.ct.out" "t.de.vtree_y.ct.C2Els[0].y"
= "t.de.vtree_y.ct.out" "t.de.vtree_y.ct.tmp[2]"
= "t.de.vtree_y.ct.in[0]" "t.de.vtree_y.OR2_tf[0].y"
= "t.de.vtree_y.ct.in[1]" "t.de.vtree_y.OR2_tf[1].y"
"t.de.vtree_y.OR2_tf[0].a"|"t.de.vtree_y.OR2_tf[0].b"->"t.de.vtree_y.OR2_tf[0]._y"-
~("t.de.vtree_y.OR2_tf[0].a"|"t.de.vtree_y.OR2_tf[0].b")->"t.de.vtree_y.OR2_tf[0]._y"+
"t.de.vtree_y.OR2_tf[0]._y"->"t.de.vtree_y.OR2_tf[0].y"-
~("t.de.vtree_y.OR2_tf[0]._y")->"t.de.vtree_y.OR2_tf[0].y"+
"t.de.vtree_y.OR2_tf[1].a"|"t.de.vtree_y.OR2_tf[1].b"->"t.de.vtree_y.OR2_tf[1]._y"-
~("t.de.vtree_y.OR2_tf[1].a"|"t.de.vtree_y.OR2_tf[1].b")->"t.de.vtree_y.OR2_tf[1]._y"+
"t.de.vtree_y.OR2_tf[1]._y"->"t.de.vtree_y.OR2_tf[1].y"-
~("t.de.vtree_y.OR2_tf[1]._y")->"t.de.vtree_y.OR2_tf[1].y"+
= "t.de.vtree_y.supply.vss" "t.de.vtree_y.ct.supply.vss"
= "t.de.vtree_y.supply.vdd" "t.de.vtree_y.ct.supply.vdd"
= "t.de.vtree_y.supply.vdd" "t.de.vtree_y.OR2_tf[1].vdd"
= "t.de.vtree_y.supply.vdd" "t.de.vtree_y.OR2_tf[0].vdd"
= "t.de.vtree_y.supply.vss" "t.de.vtree_y.OR2_tf[1].vss"
= "t.de.vtree_y.supply.vss" "t.de.vtree_y.OR2_tf[0].vss"
= "t.de.vtree_y.out" "t.de.vtree_y.ct.out"
= "t.de.vtree_y.in.d[0].d[0]" "t.de.vtree_y.in.d[0].f"
= "t.de.vtree_y.in.d[0].d[1]" "t.de.vtree_y.in.d[0].t"
= "t.de.vtree_y.in.d[1].d[0]" "t.de.vtree_y.in.d[1].f"
= "t.de.vtree_y.in.d[1].d[1]" "t.de.vtree_y.in.d[1].t"
= "t.de.vtree_y.in.d[1].d[0]" "t.de.vtree_y.in.d[1].f"
= "t.de.vtree_y.in.d[1].d[1]" "t.de.vtree_y.in.d[1].t"
= "t.de.vtree_y.in.d[0].d[0]" "t.de.vtree_y.in.d[0].f"
= "t.de.vtree_y.in.d[0].d[1]" "t.de.vtree_y.in.d[0].t"
= "t.de.vtree_y.in.d[1].d[0]" "t.de.vtree_y.OR2_tf[1].b"
= "t.de.vtree_y.in.d[1].d[0]" "t.de.vtree_y.in.d[1].f"
= "t.de.vtree_y.in.d[1].d[1]" "t.de.vtree_y.OR2_tf[1].a"
= "t.de.vtree_y.in.d[1].d[1]" "t.de.vtree_y.in.d[1].t"
= "t.de.vtree_y.in.d[0].d[0]" "t.de.vtree_y.OR2_tf[0].b"
= "t.de.vtree_y.in.d[0].d[0]" "t.de.vtree_y.in.d[0].f"
= "t.de.vtree_y.in.d[0].d[1]" "t.de.vtree_y.OR2_tf[0].a"
= "t.de.vtree_y.in.d[0].d[1]" "t.de.vtree_y.in.d[0].t"
= "t.de.outy[0]" "t.de.atree_y[0].out"
= "t.de.outy[1]" "t.de.atree_y[1].out"
= "t.de.outy[2]" "t.de.atree_y[2].out"
= "t.de.outy[3]" "t.de.atree_y[3].out"
= "t.de.outx[0]" "t.de.atree_x[0].out"
= "t.de.outx[1]" "t.de.atree_x[1].out"
= "t.de.reset_B" "t.de.addr_buf.reset_B"
"t.de.addr_buf.out_a_B_buf_t.buf1.a"->"t.de.addr_buf.out_a_B_buf_t.buf1._y"-
~("t.de.addr_buf.out_a_B_buf_t.buf1.a")->"t.de.addr_buf.out_a_B_buf_t.buf1._y"+
"t.de.addr_buf.out_a_B_buf_t.buf1._y"->"t.de.addr_buf.out_a_B_buf_t.buf1.y"-
~("t.de.addr_buf.out_a_B_buf_t.buf1._y")->"t.de.addr_buf.out_a_B_buf_t.buf1.y"+
= "t.de.addr_buf.out_a_B_buf_t.supply.vdd" "t.de.addr_buf.out_a_B_buf_t.buf1.vdd"
= "t.de.addr_buf.out_a_B_buf_t.supply.vss" "t.de.addr_buf.out_a_B_buf_t.buf1.vss"
= "t.de.addr_buf.out_a_B_buf_t.out[0]" "t.de.addr_buf.out_a_B_buf_t.out[2]"
= "t.de.addr_buf.out_a_B_buf_t.out[0]" "t.de.addr_buf.out_a_B_buf_t.out[1]"
= "t.de.addr_buf.out_a_B_buf_t.out[0]" "t.de.addr_buf.out_a_B_buf_t.buf1.y"
= "t.de.addr_buf.out_a_B_buf_t.in" "t.de.addr_buf.out_a_B_buf_t.buf1.a"
= "t.de.addr_buf._en_X_f[0]" "t.de.addr_buf.en_buf_f.out[0]"
= "t.de.addr_buf._en_X_f[1]" "t.de.addr_buf.en_buf_f.out[1]"
= "t.de.addr_buf._en_X_f[2]" "t.de.addr_buf.en_buf_f.out[2]"
= "t.de.addr_buf._en_X_f[0]" "t.de.addr_buf.f_buf_func[2].c1"
= "t.de.addr_buf._en_X_f[0]" "t.de.addr_buf.f_buf_func[1].c1"
= "t.de.addr_buf._en_X_f[0]" "t.de.addr_buf.f_buf_func[0].c1"
= "t.de.addr_buf._en_X_f[0]" "t.de.addr_buf._en_X_f[2]"
= "t.de.addr_buf._en_X_f[0]" "t.de.addr_buf._en_X_f[1]"
~"t.de.addr_buf.inack_ctl.c1"&~"t.de.addr_buf.inack_ctl.c2"&~"t.de.addr_buf.inack_ctl.c3"|~"t.de.addr_buf.inack_ctl.pr_B"->"t.de.addr_buf.inack_ctl._y"+
"t.de.addr_buf.inack_ctl.c1"&"t.de.addr_buf.inack_ctl.c2"&"t.de.addr_buf.inack_ctl.c3"&"t.de.addr_buf.inack_ctl.sr_B"->"t.de.addr_buf.inack_ctl._y"-
"t.de.addr_buf.inack_ctl._y"->"t.de.addr_buf.inack_ctl.y"-
~("t.de.addr_buf.inack_ctl._y")->"t.de.addr_buf.inack_ctl.y"+
"t.de.addr_buf.reset_bufarray.buf1.a"->"t.de.addr_buf.reset_bufarray.buf1._y"-
~("t.de.addr_buf.reset_bufarray.buf1.a")->"t.de.addr_buf.reset_bufarray.buf1._y"+
"t.de.addr_buf.reset_bufarray.buf1._y"->"t.de.addr_buf.reset_bufarray.buf1.y"-
~("t.de.addr_buf.reset_bufarray.buf1._y")->"t.de.addr_buf.reset_bufarray.buf1.y"+
= "t.de.addr_buf.reset_bufarray.supply.vdd" "t.de.addr_buf.reset_bufarray.buf1.vdd"
= "t.de.addr_buf.reset_bufarray.supply.vss" "t.de.addr_buf.reset_bufarray.buf1.vss"
= "t.de.addr_buf.reset_bufarray.out[0]" "t.de.addr_buf.reset_bufarray.out[2]"
= "t.de.addr_buf.reset_bufarray.out[0]" "t.de.addr_buf.reset_bufarray.out[1]"
= "t.de.addr_buf.reset_bufarray.out[0]" "t.de.addr_buf.reset_bufarray.buf1.y"
= "t.de.addr_buf.reset_bufarray.in" "t.de.addr_buf.reset_bufarray.buf1.a"
"t.de.addr_buf.in_v_buf.a"->"t.de.addr_buf.in_v_buf._y"-
~("t.de.addr_buf.in_v_buf.a")->"t.de.addr_buf.in_v_buf._y"+
"t.de.addr_buf.in_v_buf._y"->"t.de.addr_buf.in_v_buf.y"-
~("t.de.addr_buf.in_v_buf._y")->"t.de.addr_buf.in_v_buf.y"+
"t.de.addr_buf.out_a_inv.a"->"t.de.addr_buf.out_a_inv.y"-
~("t.de.addr_buf.out_a_inv.a")->"t.de.addr_buf.out_a_inv.y"+
= "t.de.addr_buf.supply.vss" "t.de.addr_buf.en_buf_f.supply.vss"
= "t.de.addr_buf.supply.vdd" "t.de.addr_buf.en_buf_f.supply.vdd"
= "t.de.addr_buf.supply.vss" "t.de.addr_buf.en_buf_t.supply.vss"
= "t.de.addr_buf.supply.vdd" "t.de.addr_buf.en_buf_t.supply.vdd"
= "t.de.addr_buf.supply.vss" "t.de.addr_buf.vc.supply.vss"
= "t.de.addr_buf.supply.vdd" "t.de.addr_buf.vc.supply.vdd"
= "t.de.addr_buf.supply.vdd" "t.de.addr_buf.t_buf_func[2].vdd"
= "t.de.addr_buf.supply.vdd" "t.de.addr_buf.f_buf_func[2].vdd"
= "t.de.addr_buf.supply.vdd" "t.de.addr_buf.t_buf_func[1].vdd"
= "t.de.addr_buf.supply.vdd" "t.de.addr_buf.f_buf_func[1].vdd"
= "t.de.addr_buf.supply.vdd" "t.de.addr_buf.t_buf_func[0].vdd"
= "t.de.addr_buf.supply.vdd" "t.de.addr_buf.f_buf_func[0].vdd"
= "t.de.addr_buf.supply.vdd" "t.de.addr_buf.in_v_buf.vdd"
= "t.de.addr_buf.supply.vdd" "t.de.addr_buf.reset_buf.vdd"
= "t.de.addr_buf.supply.vdd" "t.de.addr_buf.en_ctl.vdd"
= "t.de.addr_buf.supply.vdd" "t.de.addr_buf.inack_ctl.vdd"
= "t.de.addr_buf.supply.vss" "t.de.addr_buf.t_buf_func[2].vss"
= "t.de.addr_buf.supply.vss" "t.de.addr_buf.f_buf_func[2].vss"
= "t.de.addr_buf.supply.vss" "t.de.addr_buf.t_buf_func[1].vss"
= "t.de.addr_buf.supply.vss" "t.de.addr_buf.f_buf_func[1].vss"
= "t.de.addr_buf.supply.vss" "t.de.addr_buf.t_buf_func[0].vss"
= "t.de.addr_buf.supply.vss" "t.de.addr_buf.f_buf_func[0].vss"
= "t.de.addr_buf.supply.vss" "t.de.addr_buf.in_v_buf.vss"
= "t.de.addr_buf.supply.vss" "t.de.addr_buf.reset_buf.vss"
= "t.de.addr_buf.supply.vss" "t.de.addr_buf.en_ctl.vss"
= "t.de.addr_buf.supply.vss" "t.de.addr_buf.inack_ctl.vss"
~"t.de.addr_buf.vc.ct.C3Els[0].c1"&~"t.de.addr_buf.vc.ct.C3Els[0].c2"&~"t.de.addr_buf.vc.ct.C3Els[0].c3"->"t.de.addr_buf.vc.ct.C3Els[0]._y"+
"t.de.addr_buf.vc.ct.C3Els[0].c1"&"t.de.addr_buf.vc.ct.C3Els[0].c2"&"t.de.addr_buf.vc.ct.C3Els[0].c3"->"t.de.addr_buf.vc.ct.C3Els[0]._y"-
"t.de.addr_buf.vc.ct.C3Els[0]._y"->"t.de.addr_buf.vc.ct.C3Els[0].y"-
~("t.de.addr_buf.vc.ct.C3Els[0]._y")->"t.de.addr_buf.vc.ct.C3Els[0].y"+
= "t.de.addr_buf.vc.ct.supply.vdd" "t.de.addr_buf.vc.ct.C3Els[0].vdd"
= "t.de.addr_buf.vc.ct.supply.vss" "t.de.addr_buf.vc.ct.C3Els[0].vss"
= "t.de.addr_buf.vc.ct.in[0]" "t.de.addr_buf.vc.ct.C3Els[0].c1"
= "t.de.addr_buf.vc.ct.in[0]" "t.de.addr_buf.vc.ct.tmp[0]"
= "t.de.addr_buf.vc.ct.in[1]" "t.de.addr_buf.vc.ct.C3Els[0].c2"
= "t.de.addr_buf.vc.ct.in[1]" "t.de.addr_buf.vc.ct.tmp[1]"
= "t.de.addr_buf.vc.ct.in[2]" "t.de.addr_buf.vc.ct.C3Els[0].c3"
= "t.de.addr_buf.vc.ct.in[2]" "t.de.addr_buf.vc.ct.tmp[2]"
= "t.de.addr_buf.vc.ct.out" "t.de.addr_buf.vc.ct.C3Els[0].y"
= "t.de.addr_buf.vc.ct.out" "t.de.addr_buf.vc.ct.tmp[3]"
= "t.de.addr_buf.vc.ct.in[0]" "t.de.addr_buf.vc.OR2_tf[0].y"
= "t.de.addr_buf.vc.ct.in[1]" "t.de.addr_buf.vc.OR2_tf[1].y"
= "t.de.addr_buf.vc.ct.in[2]" "t.de.addr_buf.vc.OR2_tf[2].y"
"t.de.addr_buf.vc.OR2_tf[0].a"|"t.de.addr_buf.vc.OR2_tf[0].b"->"t.de.addr_buf.vc.OR2_tf[0]._y"-
~("t.de.addr_buf.vc.OR2_tf[0].a"|"t.de.addr_buf.vc.OR2_tf[0].b")->"t.de.addr_buf.vc.OR2_tf[0]._y"+
"t.de.addr_buf.vc.OR2_tf[0]._y"->"t.de.addr_buf.vc.OR2_tf[0].y"-
~("t.de.addr_buf.vc.OR2_tf[0]._y")->"t.de.addr_buf.vc.OR2_tf[0].y"+
"t.de.addr_buf.vc.OR2_tf[1].a"|"t.de.addr_buf.vc.OR2_tf[1].b"->"t.de.addr_buf.vc.OR2_tf[1]._y"-
~("t.de.addr_buf.vc.OR2_tf[1].a"|"t.de.addr_buf.vc.OR2_tf[1].b")->"t.de.addr_buf.vc.OR2_tf[1]._y"+
"t.de.addr_buf.vc.OR2_tf[1]._y"->"t.de.addr_buf.vc.OR2_tf[1].y"-
~("t.de.addr_buf.vc.OR2_tf[1]._y")->"t.de.addr_buf.vc.OR2_tf[1].y"+
"t.de.addr_buf.vc.OR2_tf[2].a"|"t.de.addr_buf.vc.OR2_tf[2].b"->"t.de.addr_buf.vc.OR2_tf[2]._y"-
~("t.de.addr_buf.vc.OR2_tf[2].a"|"t.de.addr_buf.vc.OR2_tf[2].b")->"t.de.addr_buf.vc.OR2_tf[2]._y"+
"t.de.addr_buf.vc.OR2_tf[2]._y"->"t.de.addr_buf.vc.OR2_tf[2].y"-
~("t.de.addr_buf.vc.OR2_tf[2]._y")->"t.de.addr_buf.vc.OR2_tf[2].y"+
= "t.de.addr_buf.vc.supply.vss" "t.de.addr_buf.vc.ct.supply.vss"
= "t.de.addr_buf.vc.supply.vdd" "t.de.addr_buf.vc.ct.supply.vdd"
= "t.de.addr_buf.vc.supply.vdd" "t.de.addr_buf.vc.OR2_tf[2].vdd"
= "t.de.addr_buf.vc.supply.vdd" "t.de.addr_buf.vc.OR2_tf[1].vdd"
= "t.de.addr_buf.vc.supply.vdd" "t.de.addr_buf.vc.OR2_tf[0].vdd"
= "t.de.addr_buf.vc.supply.vss" "t.de.addr_buf.vc.OR2_tf[2].vss"
= "t.de.addr_buf.vc.supply.vss" "t.de.addr_buf.vc.OR2_tf[1].vss"
= "t.de.addr_buf.vc.supply.vss" "t.de.addr_buf.vc.OR2_tf[0].vss"
= "t.de.addr_buf.vc.out" "t.de.addr_buf.vc.ct.out"
= "t.de.addr_buf.vc.in.d[0].d[0]" "t.de.addr_buf.vc.in.d[0].f"
= "t.de.addr_buf.vc.in.d[0].d[1]" "t.de.addr_buf.vc.in.d[0].t"
= "t.de.addr_buf.vc.in.d[1].d[0]" "t.de.addr_buf.vc.in.d[1].f"
= "t.de.addr_buf.vc.in.d[1].d[1]" "t.de.addr_buf.vc.in.d[1].t"
= "t.de.addr_buf.vc.in.d[2].d[0]" "t.de.addr_buf.vc.in.d[2].f"
= "t.de.addr_buf.vc.in.d[2].d[1]" "t.de.addr_buf.vc.in.d[2].t"
= "t.de.addr_buf.vc.in.d[2].d[0]" "t.de.addr_buf.vc.in.d[2].f"
= "t.de.addr_buf.vc.in.d[2].d[1]" "t.de.addr_buf.vc.in.d[2].t"
= "t.de.addr_buf.vc.in.d[1].d[0]" "t.de.addr_buf.vc.in.d[1].f"
= "t.de.addr_buf.vc.in.d[1].d[1]" "t.de.addr_buf.vc.in.d[1].t"
= "t.de.addr_buf.vc.in.d[0].d[0]" "t.de.addr_buf.vc.in.d[0].f"
= "t.de.addr_buf.vc.in.d[0].d[1]" "t.de.addr_buf.vc.in.d[0].t"
= "t.de.addr_buf.vc.in.d[2].d[0]" "t.de.addr_buf.vc.OR2_tf[2].b"
= "t.de.addr_buf.vc.in.d[2].d[0]" "t.de.addr_buf.vc.in.d[2].f"
= "t.de.addr_buf.vc.in.d[2].d[1]" "t.de.addr_buf.vc.OR2_tf[2].a"
= "t.de.addr_buf.vc.in.d[2].d[1]" "t.de.addr_buf.vc.in.d[2].t"
= "t.de.addr_buf.vc.in.d[1].d[0]" "t.de.addr_buf.vc.OR2_tf[1].b"
= "t.de.addr_buf.vc.in.d[1].d[0]" "t.de.addr_buf.vc.in.d[1].f"
= "t.de.addr_buf.vc.in.d[1].d[1]" "t.de.addr_buf.vc.OR2_tf[1].a"
= "t.de.addr_buf.vc.in.d[1].d[1]" "t.de.addr_buf.vc.in.d[1].t"
= "t.de.addr_buf.vc.in.d[0].d[0]" "t.de.addr_buf.vc.OR2_tf[0].b"
= "t.de.addr_buf.vc.in.d[0].d[0]" "t.de.addr_buf.vc.in.d[0].f"
= "t.de.addr_buf.vc.in.d[0].d[1]" "t.de.addr_buf.vc.OR2_tf[0].a"
= "t.de.addr_buf.vc.in.d[0].d[1]" "t.de.addr_buf.vc.in.d[0].t"
= "t.de.addr_buf._out_a_BX_f[0]" "t.de.addr_buf.out_a_B_buf_t.out[0]"
= "t.de.addr_buf._out_a_BX_f[1]" "t.de.addr_buf.out_a_B_buf_t.out[1]"
= "t.de.addr_buf._out_a_BX_f[2]" "t.de.addr_buf.out_a_B_buf_t.out[2]"
= "t.de.addr_buf._out_a_BX_f[0]" "t.de.addr_buf.f_buf_func[2].c2"
= "t.de.addr_buf._out_a_BX_f[0]" "t.de.addr_buf.f_buf_func[1].c2"
= "t.de.addr_buf._out_a_BX_f[0]" "t.de.addr_buf.f_buf_func[0].c2"
= "t.de.addr_buf._out_a_BX_f[0]" "t.de.addr_buf._out_a_BX_f[2]"
= "t.de.addr_buf._out_a_BX_f[0]" "t.de.addr_buf._out_a_BX_f[1]"
"t.de.addr_buf.out_a_B_buf_f.buf1.a"->"t.de.addr_buf.out_a_B_buf_f.buf1._y"-
~("t.de.addr_buf.out_a_B_buf_f.buf1.a")->"t.de.addr_buf.out_a_B_buf_f.buf1._y"+
"t.de.addr_buf.out_a_B_buf_f.buf1._y"->"t.de.addr_buf.out_a_B_buf_f.buf1.y"-
~("t.de.addr_buf.out_a_B_buf_f.buf1._y")->"t.de.addr_buf.out_a_B_buf_f.buf1.y"+
= "t.de.addr_buf.out_a_B_buf_f.supply.vdd" "t.de.addr_buf.out_a_B_buf_f.buf1.vdd"
= "t.de.addr_buf.out_a_B_buf_f.supply.vss" "t.de.addr_buf.out_a_B_buf_f.buf1.vss"
= "t.de.addr_buf.out_a_B_buf_f.out[0]" "t.de.addr_buf.out_a_B_buf_f.out[2]"
= "t.de.addr_buf.out_a_B_buf_f.out[0]" "t.de.addr_buf.out_a_B_buf_f.out[1]"
= "t.de.addr_buf.out_a_B_buf_f.out[0]" "t.de.addr_buf.out_a_B_buf_f.buf1.y"
= "t.de.addr_buf.out_a_B_buf_f.in" "t.de.addr_buf.out_a_B_buf_f.buf1.a"
= "t.de.addr_buf._en" "t.de.addr_buf.en_buf_f.in"
= "t.de.addr_buf._en" "t.de.addr_buf.en_buf_t.in"
= "t.de.addr_buf._en" "t.de.addr_buf.en_ctl.y"
= "t.de.addr_buf._en" "t.de.addr_buf.inack_ctl.c1"
~"t.de.addr_buf.en_ctl.p1"&~"t.de.addr_buf.en_ctl.c1"->"t.de.addr_buf.en_ctl.y"+
"t.de.addr_buf.en_ctl.c1"->"t.de.addr_buf.en_ctl.y"-
= "t.de.addr_buf.out.d.d[0].d[0]" "t.de.addr_buf.out.d.d[0].f"
= "t.de.addr_buf.out.d.d[0].d[1]" "t.de.addr_buf.out.d.d[0].t"
= "t.de.addr_buf.out.d.d[1].d[0]" "t.de.addr_buf.out.d.d[1].f"
= "t.de.addr_buf.out.d.d[1].d[1]" "t.de.addr_buf.out.d.d[1].t"
= "t.de.addr_buf.out.d.d[2].d[0]" "t.de.addr_buf.out.d.d[2].f"
= "t.de.addr_buf.out.d.d[2].d[1]" "t.de.addr_buf.out.d.d[2].t"
= "t.de.addr_buf.out.d.d[2].d[0]" "t.de.addr_buf.out.d.d[2].f"
= "t.de.addr_buf.out.d.d[2].d[1]" "t.de.addr_buf.out.d.d[2].t"
= "t.de.addr_buf.out.d.d[1].d[0]" "t.de.addr_buf.out.d.d[1].f"
= "t.de.addr_buf.out.d.d[1].d[1]" "t.de.addr_buf.out.d.d[1].t"
= "t.de.addr_buf.out.d.d[0].d[0]" "t.de.addr_buf.out.d.d[0].f"
= "t.de.addr_buf.out.d.d[0].d[1]" "t.de.addr_buf.out.d.d[0].t"
= "t.de.addr_buf.out.d.d[2].d[0]" "t.de.addr_buf.out.d.d[2].f"
= "t.de.addr_buf.out.d.d[2].d[1]" "t.de.addr_buf.out.d.d[2].t"
= "t.de.addr_buf.out.d.d[1].d[0]" "t.de.addr_buf.out.d.d[1].f"
= "t.de.addr_buf.out.d.d[1].d[1]" "t.de.addr_buf.out.d.d[1].t"
= "t.de.addr_buf.out.d.d[0].d[0]" "t.de.addr_buf.out.d.d[0].f"
= "t.de.addr_buf.out.d.d[0].d[1]" "t.de.addr_buf.out.d.d[0].t"
= "t.de.addr_buf.out.a" "t.de.addr_buf.out_a_inv.a"
= "t.de.addr_buf.out.v" "t.de.addr_buf.en_ctl.p1"
= "t.de.addr_buf.out.v" "t.de.addr_buf.inack_ctl.c3"
= "t.de.addr_buf.out.d.d[2].d[0]" "t.de.addr_buf.f_buf_func[2].y"
= "t.de.addr_buf.out.d.d[2].d[0]" "t.de.addr_buf.out.d.d[2].f"
= "t.de.addr_buf.out.d.d[2].d[1]" "t.de.addr_buf.t_buf_func[2].y"
= "t.de.addr_buf.out.d.d[2].d[1]" "t.de.addr_buf.out.d.d[2].t"
= "t.de.addr_buf.out.d.d[1].d[0]" "t.de.addr_buf.f_buf_func[1].y"
= "t.de.addr_buf.out.d.d[1].d[0]" "t.de.addr_buf.out.d.d[1].f"
= "t.de.addr_buf.out.d.d[1].d[1]" "t.de.addr_buf.t_buf_func[1].y"
= "t.de.addr_buf.out.d.d[1].d[1]" "t.de.addr_buf.out.d.d[1].t"
= "t.de.addr_buf.out.d.d[0].d[0]" "t.de.addr_buf.f_buf_func[0].y"
= "t.de.addr_buf.out.d.d[0].d[0]" "t.de.addr_buf.out.d.d[0].f"
= "t.de.addr_buf.out.d.d[0].d[1]" "t.de.addr_buf.t_buf_func[0].y"
= "t.de.addr_buf.out.d.d[0].d[1]" "t.de.addr_buf.out.d.d[0].t"
= "t.de.addr_buf.in.d.d[0].d[0]" "t.de.addr_buf.in.d.d[0].f"
= "t.de.addr_buf.in.d.d[0].d[1]" "t.de.addr_buf.in.d.d[0].t"
= "t.de.addr_buf.in.d.d[1].d[0]" "t.de.addr_buf.in.d.d[1].f"
= "t.de.addr_buf.in.d.d[1].d[1]" "t.de.addr_buf.in.d.d[1].t"
= "t.de.addr_buf.in.d.d[2].d[0]" "t.de.addr_buf.in.d.d[2].f"
= "t.de.addr_buf.in.d.d[2].d[1]" "t.de.addr_buf.in.d.d[2].t"
= "t.de.addr_buf.in.d.d[2].d[0]" "t.de.addr_buf.in.d.d[2].f"
= "t.de.addr_buf.in.d.d[2].d[1]" "t.de.addr_buf.in.d.d[2].t"
= "t.de.addr_buf.in.d.d[1].d[0]" "t.de.addr_buf.in.d.d[1].f"
= "t.de.addr_buf.in.d.d[1].d[1]" "t.de.addr_buf.in.d.d[1].t"
= "t.de.addr_buf.in.d.d[0].d[0]" "t.de.addr_buf.in.d.d[0].f"
= "t.de.addr_buf.in.d.d[0].d[1]" "t.de.addr_buf.in.d.d[0].t"
= "t.de.addr_buf.in.d.d[2].d[0]" "t.de.addr_buf.in.d.d[2].f"
= "t.de.addr_buf.in.d.d[2].d[1]" "t.de.addr_buf.in.d.d[2].t"
= "t.de.addr_buf.in.d.d[1].d[0]" "t.de.addr_buf.in.d.d[1].f"
= "t.de.addr_buf.in.d.d[1].d[1]" "t.de.addr_buf.in.d.d[1].t"
= "t.de.addr_buf.in.d.d[0].d[0]" "t.de.addr_buf.in.d.d[0].f"
= "t.de.addr_buf.in.d.d[0].d[1]" "t.de.addr_buf.in.d.d[0].t"
= "t.de.addr_buf.in.d.d[0].f" "t.de.addr_buf.vc.in.d[0].f"
= "t.de.addr_buf.in.d.d[0].t" "t.de.addr_buf.vc.in.d[0].t"
= "t.de.addr_buf.in.d.d[0].d[0]" "t.de.addr_buf.vc.in.d[0].d[0]"
= "t.de.addr_buf.in.d.d[0].d[1]" "t.de.addr_buf.vc.in.d[0].d[1]"
= "t.de.addr_buf.in.d.d[1].f" "t.de.addr_buf.vc.in.d[1].f"
= "t.de.addr_buf.in.d.d[1].t" "t.de.addr_buf.vc.in.d[1].t"
= "t.de.addr_buf.in.d.d[1].d[0]" "t.de.addr_buf.vc.in.d[1].d[0]"
= "t.de.addr_buf.in.d.d[1].d[1]" "t.de.addr_buf.vc.in.d[1].d[1]"
= "t.de.addr_buf.in.d.d[2].f" "t.de.addr_buf.vc.in.d[2].f"
= "t.de.addr_buf.in.d.d[2].t" "t.de.addr_buf.vc.in.d[2].t"
= "t.de.addr_buf.in.d.d[2].d[0]" "t.de.addr_buf.vc.in.d[2].d[0]"
= "t.de.addr_buf.in.d.d[2].d[1]" "t.de.addr_buf.vc.in.d[2].d[1]"
= "t.de.addr_buf.in.a" "t.de.addr_buf.en_ctl.c1"
= "t.de.addr_buf.in.a" "t.de.addr_buf.inack_ctl.y"
= "t.de.addr_buf.in.v" "t.de.addr_buf.in_v_buf.y"
= "t.de.addr_buf.in.v" "t.de.addr_buf.inack_ctl.c2"
= "t.de.addr_buf.in.d.d[2].d[0]" "t.de.addr_buf.f_buf_func[2].n1"
= "t.de.addr_buf.in.d.d[2].d[0]" "t.de.addr_buf.in.d.d[2].f"
= "t.de.addr_buf.in.d.d[2].d[1]" "t.de.addr_buf.t_buf_func[2].n1"
= "t.de.addr_buf.in.d.d[2].d[1]" "t.de.addr_buf.in.d.d[2].t"
= "t.de.addr_buf.in.d.d[1].d[0]" "t.de.addr_buf.f_buf_func[1].n1"
= "t.de.addr_buf.in.d.d[1].d[0]" "t.de.addr_buf.in.d.d[1].f"
= "t.de.addr_buf.in.d.d[1].d[1]" "t.de.addr_buf.t_buf_func[1].n1"
= "t.de.addr_buf.in.d.d[1].d[1]" "t.de.addr_buf.in.d.d[1].t"
= "t.de.addr_buf.in.d.d[0].d[0]" "t.de.addr_buf.f_buf_func[0].n1"
= "t.de.addr_buf.in.d.d[0].d[0]" "t.de.addr_buf.in.d.d[0].f"
= "t.de.addr_buf.in.d.d[0].d[1]" "t.de.addr_buf.t_buf_func[0].n1"
= "t.de.addr_buf.in.d.d[0].d[1]" "t.de.addr_buf.in.d.d[0].t"
"t.de.addr_buf.reset_buf.a"->"t.de.addr_buf.reset_buf._y"-
~("t.de.addr_buf.reset_buf.a")->"t.de.addr_buf.reset_buf._y"+
"t.de.addr_buf.reset_buf._y"->"t.de.addr_buf.reset_buf.y"-
~("t.de.addr_buf.reset_buf._y")->"t.de.addr_buf.reset_buf.y"+
= "t.de.addr_buf._in_v" "t.de.addr_buf.in_v_buf.a"
= "t.de.addr_buf._in_v" "t.de.addr_buf.vc.out"
= "t.de.addr_buf._reset_BX" "t.de.addr_buf.reset_bufarray.in"
= "t.de.addr_buf._reset_BX" "t.de.addr_buf.reset_buf.y"
= "t.de.addr_buf._reset_BX" "t.de.addr_buf.inack_ctl.sr_B"
= "t.de.addr_buf._reset_BX" "t.de.addr_buf.inack_ctl.pr_B"
= "t.de.addr_buf.reset_B" "t.de.addr_buf.reset_buf.a"
= "t.de.addr_buf._out_a_BX_t[0]" "t.de.addr_buf.out_a_B_buf_f.out[0]"
= "t.de.addr_buf._out_a_BX_t[1]" "t.de.addr_buf.out_a_B_buf_f.out[1]"
= "t.de.addr_buf._out_a_BX_t[2]" "t.de.addr_buf.out_a_B_buf_f.out[2]"
= "t.de.addr_buf._out_a_BX_t[0]" "t.de.addr_buf.t_buf_func[2].c2"
= "t.de.addr_buf._out_a_BX_t[0]" "t.de.addr_buf.t_buf_func[1].c2"
= "t.de.addr_buf._out_a_BX_t[0]" "t.de.addr_buf.t_buf_func[0].c2"
= "t.de.addr_buf._out_a_BX_t[0]" "t.de.addr_buf._out_a_BX_t[2]"
= "t.de.addr_buf._out_a_BX_t[0]" "t.de.addr_buf._out_a_BX_t[1]"
"t.de.addr_buf.en_buf_f.buf1.a"->"t.de.addr_buf.en_buf_f.buf1._y"-
~("t.de.addr_buf.en_buf_f.buf1.a")->"t.de.addr_buf.en_buf_f.buf1._y"+
"t.de.addr_buf.en_buf_f.buf1._y"->"t.de.addr_buf.en_buf_f.buf1.y"-
~("t.de.addr_buf.en_buf_f.buf1._y")->"t.de.addr_buf.en_buf_f.buf1.y"+
= "t.de.addr_buf.en_buf_f.supply.vdd" "t.de.addr_buf.en_buf_f.buf1.vdd"
= "t.de.addr_buf.en_buf_f.supply.vss" "t.de.addr_buf.en_buf_f.buf1.vss"
= "t.de.addr_buf.en_buf_f.out[0]" "t.de.addr_buf.en_buf_f.out[2]"
= "t.de.addr_buf.en_buf_f.out[0]" "t.de.addr_buf.en_buf_f.out[1]"
= "t.de.addr_buf.en_buf_f.out[0]" "t.de.addr_buf.en_buf_f.buf1.y"
= "t.de.addr_buf.en_buf_f.in" "t.de.addr_buf.en_buf_f.buf1.a"
"t.de.addr_buf.en_buf_t.buf1.a"->"t.de.addr_buf.en_buf_t.buf1._y"-
~("t.de.addr_buf.en_buf_t.buf1.a")->"t.de.addr_buf.en_buf_t.buf1._y"+
"t.de.addr_buf.en_buf_t.buf1._y"->"t.de.addr_buf.en_buf_t.buf1.y"-
~("t.de.addr_buf.en_buf_t.buf1._y")->"t.de.addr_buf.en_buf_t.buf1.y"+
= "t.de.addr_buf.en_buf_t.supply.vdd" "t.de.addr_buf.en_buf_t.buf1.vdd"
= "t.de.addr_buf.en_buf_t.supply.vss" "t.de.addr_buf.en_buf_t.buf1.vss"
= "t.de.addr_buf.en_buf_t.out[0]" "t.de.addr_buf.en_buf_t.out[2]"
= "t.de.addr_buf.en_buf_t.out[0]" "t.de.addr_buf.en_buf_t.out[1]"
= "t.de.addr_buf.en_buf_t.out[0]" "t.de.addr_buf.en_buf_t.buf1.y"
= "t.de.addr_buf.en_buf_t.in" "t.de.addr_buf.en_buf_t.buf1.a"
= "t.de.addr_buf._out_a_B" "t.de.addr_buf.out_a_B_buf_t.in"
= "t.de.addr_buf._out_a_B" "t.de.addr_buf.out_a_B_buf_f.in"
= "t.de.addr_buf._out_a_B" "t.de.addr_buf.out_a_inv.y"
= "t.de.addr_buf._reset_BXX[0]" "t.de.addr_buf.reset_bufarray.out[0]"
= "t.de.addr_buf._reset_BXX[1]" "t.de.addr_buf.reset_bufarray.out[1]"
= "t.de.addr_buf._reset_BXX[2]" "t.de.addr_buf.reset_bufarray.out[2]"
= "t.de.addr_buf._reset_BXX[0]" "t.de.addr_buf.f_buf_func[2].sr_B"
= "t.de.addr_buf._reset_BXX[0]" "t.de.addr_buf.f_buf_func[2].pr_B"
= "t.de.addr_buf._reset_BXX[0]" "t.de.addr_buf.t_buf_func[2].sr_B"
= "t.de.addr_buf._reset_BXX[0]" "t.de.addr_buf.t_buf_func[2].pr_B"
= "t.de.addr_buf._reset_BXX[0]" "t.de.addr_buf.f_buf_func[1].sr_B"
= "t.de.addr_buf._reset_BXX[0]" "t.de.addr_buf.f_buf_func[1].pr_B"
= "t.de.addr_buf._reset_BXX[0]" "t.de.addr_buf.t_buf_func[1].sr_B"
= "t.de.addr_buf._reset_BXX[0]" "t.de.addr_buf.t_buf_func[1].pr_B"
= "t.de.addr_buf._reset_BXX[0]" "t.de.addr_buf.f_buf_func[0].sr_B"
= "t.de.addr_buf._reset_BXX[0]" "t.de.addr_buf.f_buf_func[0].pr_B"
= "t.de.addr_buf._reset_BXX[0]" "t.de.addr_buf.t_buf_func[0].sr_B"
= "t.de.addr_buf._reset_BXX[0]" "t.de.addr_buf.t_buf_func[0].pr_B"
= "t.de.addr_buf._reset_BXX[0]" "t.de.addr_buf._reset_BXX[2]"
= "t.de.addr_buf._reset_BXX[0]" "t.de.addr_buf._reset_BXX[1]"
~"t.de.addr_buf.t_buf_func[0].c1"&~"t.de.addr_buf.t_buf_func[0].c2"|~"t.de.addr_buf.t_buf_func[0].pr_B"->"t.de.addr_buf.t_buf_func[0]._y"+
"t.de.addr_buf.t_buf_func[0].c1"&"t.de.addr_buf.t_buf_func[0].c2"&"t.de.addr_buf.t_buf_func[0].n1"&"t.de.addr_buf.t_buf_func[0].sr_B"->"t.de.addr_buf.t_buf_func[0]._y"-
"t.de.addr_buf.t_buf_func[0]._y"->"t.de.addr_buf.t_buf_func[0].y"-
~("t.de.addr_buf.t_buf_func[0]._y")->"t.de.addr_buf.t_buf_func[0].y"+
~"t.de.addr_buf.t_buf_func[1].c1"&~"t.de.addr_buf.t_buf_func[1].c2"|~"t.de.addr_buf.t_buf_func[1].pr_B"->"t.de.addr_buf.t_buf_func[1]._y"+
"t.de.addr_buf.t_buf_func[1].c1"&"t.de.addr_buf.t_buf_func[1].c2"&"t.de.addr_buf.t_buf_func[1].n1"&"t.de.addr_buf.t_buf_func[1].sr_B"->"t.de.addr_buf.t_buf_func[1]._y"-
"t.de.addr_buf.t_buf_func[1]._y"->"t.de.addr_buf.t_buf_func[1].y"-
~("t.de.addr_buf.t_buf_func[1]._y")->"t.de.addr_buf.t_buf_func[1].y"+
~"t.de.addr_buf.t_buf_func[2].c1"&~"t.de.addr_buf.t_buf_func[2].c2"|~"t.de.addr_buf.t_buf_func[2].pr_B"->"t.de.addr_buf.t_buf_func[2]._y"+
"t.de.addr_buf.t_buf_func[2].c1"&"t.de.addr_buf.t_buf_func[2].c2"&"t.de.addr_buf.t_buf_func[2].n1"&"t.de.addr_buf.t_buf_func[2].sr_B"->"t.de.addr_buf.t_buf_func[2]._y"-
"t.de.addr_buf.t_buf_func[2]._y"->"t.de.addr_buf.t_buf_func[2].y"-
~("t.de.addr_buf.t_buf_func[2]._y")->"t.de.addr_buf.t_buf_func[2].y"+
~"t.de.addr_buf.f_buf_func[0].c1"&~"t.de.addr_buf.f_buf_func[0].c2"|~"t.de.addr_buf.f_buf_func[0].pr_B"->"t.de.addr_buf.f_buf_func[0]._y"+
"t.de.addr_buf.f_buf_func[0].c1"&"t.de.addr_buf.f_buf_func[0].c2"&"t.de.addr_buf.f_buf_func[0].n1"&"t.de.addr_buf.f_buf_func[0].sr_B"->"t.de.addr_buf.f_buf_func[0]._y"-
"t.de.addr_buf.f_buf_func[0]._y"->"t.de.addr_buf.f_buf_func[0].y"-
~("t.de.addr_buf.f_buf_func[0]._y")->"t.de.addr_buf.f_buf_func[0].y"+
~"t.de.addr_buf.f_buf_func[1].c1"&~"t.de.addr_buf.f_buf_func[1].c2"|~"t.de.addr_buf.f_buf_func[1].pr_B"->"t.de.addr_buf.f_buf_func[1]._y"+
"t.de.addr_buf.f_buf_func[1].c1"&"t.de.addr_buf.f_buf_func[1].c2"&"t.de.addr_buf.f_buf_func[1].n1"&"t.de.addr_buf.f_buf_func[1].sr_B"->"t.de.addr_buf.f_buf_func[1]._y"-
"t.de.addr_buf.f_buf_func[1]._y"->"t.de.addr_buf.f_buf_func[1].y"-
~("t.de.addr_buf.f_buf_func[1]._y")->"t.de.addr_buf.f_buf_func[1].y"+
~"t.de.addr_buf.f_buf_func[2].c1"&~"t.de.addr_buf.f_buf_func[2].c2"|~"t.de.addr_buf.f_buf_func[2].pr_B"->"t.de.addr_buf.f_buf_func[2]._y"+
"t.de.addr_buf.f_buf_func[2].c1"&"t.de.addr_buf.f_buf_func[2].c2"&"t.de.addr_buf.f_buf_func[2].n1"&"t.de.addr_buf.f_buf_func[2].sr_B"->"t.de.addr_buf.f_buf_func[2]._y"-
"t.de.addr_buf.f_buf_func[2]._y"->"t.de.addr_buf.f_buf_func[2].y"-
~("t.de.addr_buf.f_buf_func[2]._y")->"t.de.addr_buf.f_buf_func[2].y"+
= "t.de.addr_buf._en_X_t[0]" "t.de.addr_buf.en_buf_t.out[0]"
= "t.de.addr_buf._en_X_t[1]" "t.de.addr_buf.en_buf_t.out[1]"
= "t.de.addr_buf._en_X_t[2]" "t.de.addr_buf.en_buf_t.out[2]"
= "t.de.addr_buf._en_X_t[0]" "t.de.addr_buf.t_buf_func[2].c1"
= "t.de.addr_buf._en_X_t[0]" "t.de.addr_buf.t_buf_func[1].c1"
= "t.de.addr_buf._en_X_t[0]" "t.de.addr_buf.t_buf_func[0].c1"
= "t.de.addr_buf._en_X_t[0]" "t.de.addr_buf._en_X_t[2]"
= "t.de.addr_buf._en_X_t[0]" "t.de.addr_buf._en_X_t[1]"
"t.de.vtree_x.ct.b.a"->"t.de.vtree_x.ct.b._y"-
~("t.de.vtree_x.ct.b.a")->"t.de.vtree_x.ct.b._y"+
"t.de.vtree_x.ct.b._y"->"t.de.vtree_x.ct.b.y"-
~("t.de.vtree_x.ct.b._y")->"t.de.vtree_x.ct.b.y"+
= "t.de.vtree_x.ct.supply.vdd" "t.de.vtree_x.ct.b.vdd"
= "t.de.vtree_x.ct.supply.vss" "t.de.vtree_x.ct.b.vss"
= "t.de.vtree_x.ct.out" "t.de.vtree_x.ct.b.y"
= "t.de.vtree_x.ct.in[0]" "t.de.vtree_x.ct.b.a"
= "t.de.vtree_x.ct.in[0]" "t.de.vtree_x.OR2_tf[0].y"
"t.de.vtree_x.OR2_tf[0].a"|"t.de.vtree_x.OR2_tf[0].b"->"t.de.vtree_x.OR2_tf[0]._y"-
~("t.de.vtree_x.OR2_tf[0].a"|"t.de.vtree_x.OR2_tf[0].b")->"t.de.vtree_x.OR2_tf[0]._y"+
"t.de.vtree_x.OR2_tf[0]._y"->"t.de.vtree_x.OR2_tf[0].y"-
~("t.de.vtree_x.OR2_tf[0]._y")->"t.de.vtree_x.OR2_tf[0].y"+
= "t.de.vtree_x.supply.vss" "t.de.vtree_x.ct.supply.vss"
= "t.de.vtree_x.supply.vdd" "t.de.vtree_x.ct.supply.vdd"
= "t.de.vtree_x.supply.vdd" "t.de.vtree_x.OR2_tf[0].vdd"
= "t.de.vtree_x.supply.vss" "t.de.vtree_x.OR2_tf[0].vss"
= "t.de.vtree_x.out" "t.de.vtree_x.ct.out"
= "t.de.vtree_x.in.d[0].d[0]" "t.de.vtree_x.in.d[0].f"
= "t.de.vtree_x.in.d[0].d[1]" "t.de.vtree_x.in.d[0].t"
= "t.de.vtree_x.in.d[0].d[0]" "t.de.vtree_x.in.d[0].f"
= "t.de.vtree_x.in.d[0].d[1]" "t.de.vtree_x.in.d[0].t"
= "t.de.vtree_x.in.d[0].d[0]" "t.de.vtree_x.OR2_tf[0].b"
= "t.de.vtree_x.in.d[0].d[0]" "t.de.vtree_x.in.d[0].f"
= "t.de.vtree_x.in.d[0].d[1]" "t.de.vtree_x.OR2_tf[0].a"
= "t.de.vtree_x.in.d[0].d[1]" "t.de.vtree_x.in.d[0].t"
= "Vdd" "t.de.supply.vdd"
= "GND" "t.de.supply.vss"
= "t.dly_cfg[0]" "t.de.dly_cfg[0]"
= "t.dly_cfg[1]" "t.de.dly_cfg[1]"
= "t.dly_cfg[2]" "t.de.dly_cfg[2]"
= "t.dly_cfg[3]" "t.de.dly_cfg[3]"
= "t.out[0]" "t.ag.out[0]"
= "t.out[1]" "t.ag.out[1]"
= "t.out[2]" "t.ag.out[2]"
= "t.out[3]" "t.ag.out[3]"
= "t.out[4]" "t.ag.out[4]"
= "t.out[5]" "t.ag.out[5]"
= "t.out[6]" "t.ag.out[6]"
= "t.out[7]" "t.ag.out[7]"
= "t.in.d.d[0].d[0]" "t.in.d.d[0].f"
= "t.in.d.d[0].d[1]" "t.in.d.d[0].t"
= "t.in.d.d[1].d[0]" "t.in.d.d[1].f"
= "t.in.d.d[1].d[1]" "t.in.d.d[1].t"
= "t.in.d.d[2].d[0]" "t.in.d.d[2].f"
= "t.in.d.d[2].d[1]" "t.in.d.d[2].t"
= "t.in.d.d[2].d[0]" "t.in.d.d[2].f"
= "t.in.d.d[2].d[1]" "t.in.d.d[2].t"
= "t.in.d.d[1].d[0]" "t.in.d.d[1].f"
= "t.in.d.d[1].d[1]" "t.in.d.d[1].t"
= "t.in.d.d[0].d[0]" "t.in.d.d[0].f"
= "t.in.d.d[0].d[1]" "t.in.d.d[0].t"
= "t.in.d.d[2].d[0]" "t.in.d.d[2].f"
= "t.in.d.d[2].d[1]" "t.in.d.d[2].t"
= "t.in.d.d[1].d[0]" "t.in.d.d[1].f"
= "t.in.d.d[1].d[1]" "t.in.d.d[1].t"
= "t.in.d.d[0].d[0]" "t.in.d.d[0].f"
= "t.in.d.d[0].d[1]" "t.in.d.d[0].t"
= "t.in.v" "t.de.in.v"
= "t.in.a" "t.de.in.a"
= "t.in.d.d[0].f" "t.de.in.d.d[0].f"
= "t.in.d.d[0].t" "t.de.in.d.d[0].t"
= "t.in.d.d[0].d[0]" "t.de.in.d.d[0].d[0]"
= "t.in.d.d[0].d[1]" "t.de.in.d.d[0].d[1]"
= "t.in.d.d[1].f" "t.de.in.d.d[1].f"
= "t.in.d.d[1].t" "t.de.in.d.d[1].t"
= "t.in.d.d[1].d[0]" "t.de.in.d.d[1].d[0]"
= "t.in.d.d[1].d[1]" "t.de.in.d.d[1].d[1]"
= "t.in.d.d[2].f" "t.de.in.d.d[2].f"
= "t.in.d.d[2].t" "t.de.in.d.d[2].t"
= "t.in.d.d[2].d[0]" "t.de.in.d.d[2].d[0]"
= "t.in.d.d[2].d[1]" "t.de.in.d.d[2].d[1]"
= "t.in.d.d[2].d[0]" "t.in.d.d[2].f"
= "t.in.d.d[2].d[1]" "t.in.d.d[2].t"
= "t.in.d.d[1].d[0]" "t.in.d.d[1].f"
= "t.in.d.d[1].d[1]" "t.in.d.d[1].t"
= "t.in.d.d[0].d[0]" "t.in.d.d[0].f"
= "t.in.d.d[0].d[1]" "t.in.d.d[0].t"

52
test/unit_tests/decoder_2d_dly_and_2_4/test.act
View File

@@ -1,52 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/coders.act";
import globals;
open tmpl::dataflow_neuro;
defproc decoder_2d_dly_and_2_4(avMx1of2<1+2> in; bool? out[2*4], dly_cfg[4])
{
bool _reset_B;
prs {
Reset => _reset_B-
}
decoder_2d_dly<1,2,2,4,4> de(.in = in, .dly_cfg = dly_cfg);
de.supply.vdd = Vdd;
de.supply.vss = GND;
de.reset_B = _reset_B;
and_grid<2,4> ag(.inx = de.outx, .iny = de.outy, .out = out);
ag.supply.vdd = Vdd;
ag.supply.vss = GND;
}
decoder_2d_dly_and_2_4 t;

57
test/unit_tests/decoder_2d_dly_and_2_4/test.prsim
View File

@@ -1,57 +0,0 @@
watchall
set-qdi-channel-neutral "t.in" 3
set Reset 0
# Set delay config lines
set t.dly_cfg[0] 1
set t.dly_cfg[1] 1
set t.dly_cfg[2] 1
set t.dly_cfg[3] 1
cycle
system "echo '[] set Reset 1'"
set Reset 1
cycle
system "echo '[] set Reset 0'"
set Reset 0
mode run
cycle
system "echo '[] Sending packet in'"
set-qdi-channel-valid "t.in" 3 7
cycle
assert t.in.a 1
assert t.in.v 1
# system "echo '[]' Setting ack from DLY high"
# set b.b.addr_buf.out.a 1
# cycle
# assert b.outx[0] 0
# assert b.outx[1] 0
# assert b.outx[2] 0
# assert b.outx[3] 0
# assert b.outx[4] 0
# assert b.outx[5] 0
# assert b.outx[6] 0
# assert b.outx[7] 0
# assert b.outy[0] 0
# assert b.outy[1] 0
# assert b.outy[2] 0
# assert b.outy[3] 0
# assert b.outy[4] 0
# assert b.outy[5] 0
# assert b.outy[6] 0
# assert b.outy[7] 0
# assert b.outy[8] 0
# assert b.outy[9] 0
# assert b.outy[10] 0
# assert b.outy[11] 0
# assert b.outy[12] 0
# assert b.outy[13] 0
# assert b.outy[14] 0
# assert b.outy[15] 0

1022
test/unit_tests/decoder_2d_hs/run/prsim.out
View File

File diff suppressed because it is too large Load Diff

1636
test/unit_tests/decoder_2d_hs/run/test.prs
View File

File diff suppressed because it is too large Load Diff

76
test/unit_tests/decoder_2d_hs/test.act
View File

@@ -1,76 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/coders.act";
import "../../dataflow_neuro/primitives.act";
import "../../dataflow_neuro/cell_lib_async.act";
import "../../dataflow_neuro/cell_lib_std.act";
import globals;
import std::data;
open std::data;
open tmpl::dataflow_neuro;
defproc decoder_2d_hs_2x4 (avMx1of2<3> in; a1of1 out[8]){
bool _reset_B;
prs {
Reset => _reset_B-
}
power supply;
supply.vdd = Vdd;
supply.vss = GND;
decoder_2d_hs<1,2,2,4,3> decoder(.in = in, .out = out,
.reset_B = _reset_B, .supply = supply);
// model the synapse as having automatic pulldown of ack.
// Needed since still have the timing assumption,
// that the synapse ack is pulled down pretty soon after its req is removed.
// Otherwise it starts fighting the line pull down.
INV_X1 synapses[8];
PULLDOWN_X4 synapses2[8];
(i:8:
synapses[i].a = decoder.out[i].r;
synapses2[i].a = synapses[i].y;
synapses2[i].y = decoder.out[i].a;
synapses[i].vss = supply.vss;
synapses[i].vdd = supply.vdd;
synapses2[i].vss = supply.vss;
synapses2[i].vdd = supply.vdd;
)
}
// fifo_decoder_neurons_encoder_fifo e;
decoder_2d_hs_2x4 e;

153
test/unit_tests/decoder_2d_hs/test.prsim
View File

@@ -1,153 +0,0 @@
watchall
set e.out[0].a 0
set e.out[1].a 0
set e.out[2].a 0
set e.out[3].a 0
set e.out[4].a 0
set e.out[5].a 0
set e.out[6].a 0
set e.out[7].a 0
set-qdi-channel-neutral "e.in" 3
set Reset 1
cycle
mode run
system "echo '[] Set reset 0'"
status X
set Reset 0
cycle
system "echo '[] Sending in a 7 packet'"
set-qdi-channel-valid "e.in" 3 7
cycle
assert e.out[0].r 0
assert e.out[1].r 0
assert e.out[2].r 0
assert e.out[3].r 0
assert e.out[4].r 0
assert e.out[5].r 0
assert e.out[6].r 0
assert e.out[7].r 1
assert e.in.a 1
assert e.in.v 1
system "echo '[] Removing input'"
set-qdi-channel-neutral "e.in" 3
system "echo '[] Synapse [7] gives ack'"
set e.out[7].a 1
cycle
assert e.out[0].r 0
assert e.out[1].r 0
assert e.out[2].r 0
assert e.out[3].r 0
assert e.out[4].r 0
assert e.out[5].r 0
assert e.out[6].r 0
assert e.out[7].r 0
assert e.in.a 0
assert e.in.v 0
assert e.out[0].a 0
assert e.out[1].a 0
assert e.out[2].a 0
assert e.out[3].a 0
assert e.out[4].a 0
assert e.out[5].a 0
assert e.out[6].a 0
assert e.out[7].a 0
system "echo '[] Sending in a 5 packet'"
set-qdi-channel-valid "e.in" 3 5
cycle
assert e.out[0].r 0
assert e.out[1].r 0
assert e.out[2].r 0
assert e.out[3].r 0
assert e.out[4].r 0
assert e.out[5].r 1
assert e.out[6].r 0
assert e.out[7].r 0
assert e.in.a 1
assert e.in.v 1
system "echo '[] Removing input'"
set-qdi-channel-neutral "e.in" 3
system "echo '[] Synapse [5] gives ack'"
set e.out[5].a 1
cycle
assert e.out[0].r 0
assert e.out[1].r 0
assert e.out[2].r 0
assert e.out[3].r 0
assert e.out[4].r 0
assert e.out[5].r 0
assert e.out[6].r 0
assert e.out[7].r 0
assert e.in.a 0
assert e.in.v 0
assert e.out[0].a 0
assert e.out[1].a 0
assert e.out[2].a 0
assert e.out[3].a 0
assert e.out[4].a 0
assert e.out[5].a 0
assert e.out[6].a 0
assert e.out[7].a 0
system "echo '[] Sending in a 1 packet'"
set-qdi-channel-valid "e.in" 3 1
cycle
assert e.out[0].r 0
assert e.out[1].r 1
assert e.out[2].r 0
assert e.out[3].r 0
assert e.out[4].r 0
assert e.out[5].r 0
assert e.out[6].r 0
assert e.out[7].r 0
assert e.in.a 1
assert e.in.v 1
system "echo '[] Synapse [5] gives ack'"
set e.out[1].a 1
cycle
assert e.out[0].r 0
assert e.out[1].r 0
assert e.out[2].r 0
assert e.out[3].r 0
assert e.out[4].r 0
assert e.out[5].r 0
assert e.out[6].r 0
assert e.out[7].r 0
assert e.out[0].a 0
assert e.out[1].a 0
assert e.out[2].a 0
assert e.out[3].a 0
assert e.out[4].a 0
assert e.out[5].a 0
assert e.out[6].a 0
assert e.out[7].a 0
assert e.in.a 1
assert e.in.v 1
system "echo '[] Removing input'"
set-qdi-channel-neutral "e.in" 3
cycle
assert e.in.a 0
assert e.in.v 0

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test/unit_tests/decoder_2d_hybrid/run/prsim.out
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test/unit_tests/decoder_2d_hybrid/run/test.prs
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74
test/unit_tests/decoder_2d_hybrid/test.act
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@@ -1,74 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/coders.act";
import "../../dataflow_neuro/primitives.act";
import "../../dataflow_neuro/cell_lib_async.act";
import "../../dataflow_neuro/cell_lib_std.act";
import globals;
import std::data;
open std::data;
open tmpl::dataflow_neuro;
defproc decoder_2d_hybrid_2x4 (avMx1of2<3> in; a1of1 out[8]; bool? dly_cfg[4], hs_en){
bool _reset_B;
prs {
Reset => _reset_B-
}
power supply;
supply.vdd = Vdd;
supply.vss = GND;
decoder_2d_hybrid<1,2,2,4,4> decoder(.in = in, .out = out, .dly_cfg = dly_cfg, .hs_en = hs_en,
.reset_B = _reset_B, .supply = supply);
// model the synapse as having automatic pulldown of ack.
INV_X1 synapses[8];
PULLDOWN_X4 synapses2[8];
(i:8:
synapses[i].a = decoder.out[i].r;
synapses2[i].a = synapses[i].y;
synapses2[i].y = decoder.out[i].a;
synapses[i].vss = supply.vss;
synapses[i].vdd = supply.vdd;
synapses2[i].vss = supply.vss;
synapses2[i].vdd = supply.vdd;
)
}
// fifo_decoder_neurons_encoder_fifo e;
decoder_2d_hybrid_2x4 e;

341
test/unit_tests/decoder_2d_hybrid/test.prsim
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@@ -1,341 +0,0 @@
watchall
set e.out[0].a 0
set e.out[1].a 0
set e.out[2].a 0
set e.out[3].a 0
set e.out[4].a 0
set e.out[5].a 0
set e.out[6].a 0
set e.out[7].a 0
set e.dly_cfg[0] 0
set e.dly_cfg[1] 0
set e.dly_cfg[2] 0
set e.dly_cfg[3] 0
set e.hs_en 1
set-qdi-channel-neutral "e.in" 3
set Reset 1
cycle
mode run
system "echo '[] Set reset 0'"
status X
set Reset 0
cycle
system "echo '[] Sending in a 7 packet'"
set-qdi-channel-valid "e.in" 3 7
cycle
assert e.out[0].r 0
assert e.out[1].r 0
assert e.out[2].r 0
assert e.out[3].r 0
assert e.out[4].r 0
assert e.out[5].r 0
assert e.out[6].r 0
assert e.out[7].r 1
assert e.in.a 1
assert e.in.v 1
system "echo '[] Removing input'"
set-qdi-channel-neutral "e.in" 3
system "echo '[] Synapse [7] gives ack'"
set e.out[7].a 1
cycle
assert e.out[0].r 0
assert e.out[1].r 0
assert e.out[2].r 0
assert e.out[3].r 0
assert e.out[4].r 0
assert e.out[5].r 0
assert e.out[6].r 0
assert e.out[7].r 0
assert e.in.a 0
assert e.in.v 0
assert e.out[0].a 0
assert e.out[1].a 0
assert e.out[2].a 0
assert e.out[3].a 0
assert e.out[4].a 0
assert e.out[5].a 0
assert e.out[6].a 0
assert e.out[7].a 0
system "echo '[] Sending in a 5 packet'"
set-qdi-channel-valid "e.in" 3 5
cycle
assert e.out[0].r 0
assert e.out[1].r 0
assert e.out[2].r 0
assert e.out[3].r 0
assert e.out[4].r 0
assert e.out[5].r 1
assert e.out[6].r 0
assert e.out[7].r 0
assert e.in.a 1
assert e.in.v 1
system "echo '[] Removing input'"
set-qdi-channel-neutral "e.in" 3
system "echo '[] Synapse [5] gives ack'"
set e.out[5].a 1
cycle
assert e.out[0].r 0
assert e.out[1].r 0
assert e.out[2].r 0
assert e.out[3].r 0
assert e.out[4].r 0
assert e.out[5].r 0
assert e.out[6].r 0
assert e.out[7].r 0
assert e.in.a 0
assert e.in.v 0
assert e.out[0].a 0
assert e.out[1].a 0
assert e.out[2].a 0
assert e.out[3].a 0
assert e.out[4].a 0
assert e.out[5].a 0
assert e.out[6].a 0
assert e.out[7].a 0
system "echo '[] Sending in a 1 packet'"
set-qdi-channel-valid "e.in" 3 1
cycle
assert e.out[0].r 0
assert e.out[1].r 1
assert e.out[2].r 0
assert e.out[3].r 0
assert e.out[4].r 0
assert e.out[5].r 0
assert e.out[6].r 0
assert e.out[7].r 0
assert e.in.a 1
assert e.in.v 1
system "echo '[] Synapse [1] gives ack'"
set e.out[1].a 1
cycle
assert e.out[0].r 0
assert e.out[1].r 0
assert e.out[2].r 0
assert e.out[3].r 0
assert e.out[4].r 0
assert e.out[5].r 0
assert e.out[6].r 0
assert e.out[7].r 0
assert e.out[0].a 0
assert e.out[1].a 0
assert e.out[2].a 0
assert e.out[3].a 0
assert e.out[4].a 0
assert e.out[5].a 0
assert e.out[6].a 0
assert e.out[7].a 0
assert e.in.a 1
assert e.in.v 1
system "echo '[] Removing input, enabling delays'"
set-qdi-channel-neutral "e.in" 3
cycle
assert e.in.a 0
assert e.in.v 0
system "echo '[] Enabling delays'"
cycle
set e.dly_cfg[0] 1
set e.dly_cfg[1] 1
set e.dly_cfg[2] 1
set e.dly_cfg[3] 1
system "echo '[] Sending in a 7 packet, with delays'"
set-qdi-channel-valid "e.in" 3 7
cycle
assert e.out[0].r 0
assert e.out[1].r 0
assert e.out[2].r 0
assert e.out[3].r 0
assert e.out[4].r 0
assert e.out[5].r 0
assert e.out[6].r 0
assert e.out[7].r 1
assert e.in.a 1
assert e.in.v 1
system "echo '[] Removing input'"
set-qdi-channel-neutral "e.in" 3
system "echo '[] Synapse [7] gives ack'"
set e.out[7].a 1
cycle
assert e.out[0].r 0
assert e.out[1].r 0
assert e.out[2].r 0
assert e.out[3].r 0
assert e.out[4].r 0
assert e.out[5].r 0
assert e.out[6].r 0
assert e.out[7].r 0
assert e.in.a 0
assert e.in.v 0
assert e.out[0].a 0
assert e.out[1].a 0
assert e.out[2].a 0
assert e.out[3].a 0
assert e.out[4].a 0
assert e.out[5].a 0
assert e.out[6].a 0
assert e.out[7].a 0
system "echo '[] Sending in a 5 packet'"
set-qdi-channel-valid "e.in" 3 5
cycle
assert e.out[0].r 0
assert e.out[1].r 0
assert e.out[2].r 0
assert e.out[3].r 0
assert e.out[4].r 0
assert e.out[5].r 1
assert e.out[6].r 0
assert e.out[7].r 0
assert e.in.a 1
assert e.in.v 1
system "echo '[] Removing input'"
set-qdi-channel-neutral "e.in" 3
system "echo '[] Synapse [5] gives ack'"
set e.out[5].a 1
cycle
assert e.out[0].r 0
assert e.out[1].r 0
assert e.out[2].r 0
assert e.out[3].r 0
assert e.out[4].r 0
assert e.out[5].r 0
assert e.out[6].r 0
assert e.out[7].r 0
assert e.in.a 0
assert e.in.v 0
assert e.out[0].a 0
assert e.out[1].a 0
assert e.out[2].a 0
assert e.out[3].a 0
assert e.out[4].a 0
assert e.out[5].a 0
assert e.out[6].a 0
assert e.out[7].a 0
system "echo '[] Sending in a 1 packet'"
set-qdi-channel-valid "e.in" 3 1
cycle
assert e.out[0].r 0
assert e.out[1].r 1
assert e.out[2].r 0
assert e.out[3].r 0
assert e.out[4].r 0
assert e.out[5].r 0
assert e.out[6].r 0
assert e.out[7].r 0
assert e.in.a 1
assert e.in.v 1
system "echo '[] Synapse [1] gives ack'"
set e.out[1].a 1
cycle
assert e.out[0].r 0
assert e.out[1].r 0
assert e.out[2].r 0
assert e.out[3].r 0
assert e.out[4].r 0
assert e.out[5].r 0
assert e.out[6].r 0
assert e.out[7].r 0
assert e.out[0].a 0
assert e.out[1].a 0
assert e.out[2].a 0
assert e.out[3].a 0
assert e.out[4].a 0
assert e.out[5].a 0
assert e.out[6].a 0
assert e.out[7].a 0
assert e.in.a 1
assert e.in.v 1
system "echo '[] Removing input, disabling handshaking'"
set-qdi-channel-neutral "e.in" 3
cycle
assert e.in.a 0
assert e.in.v 0
set e.hs_en 0
cycle
system "echo '[] Sending in a 0, handshaking disabled'"
set-qdi-channel-valid "e.in" 3 0
cycle
assert e.in.a 1
assert e.in.v 1
system "echo '[] Removing input'"
set-qdi-channel-neutral "e.in" 3
cycle
assert e.in.a 0
assert e.in.v 0
system "echo '[] Sending in a 7, handshaking disabled'"
set-qdi-channel-valid "e.in" 3 7
cycle
assert e.in.a 1
assert e.in.v 1
system "echo '[] Removing input'"
set-qdi-channel-neutral "e.in" 3
cycle
assert e.in.a 0
assert e.in.v 0
system "echo '[] Sending in a 5, handshaking disabled'"
set-qdi-channel-valid "e.in" 3 5
cycle
assert e.in.a 1
assert e.in.v 1
system "echo '[] Removing input'"
set-qdi-channel-neutral "e.in" 3
cycle
assert e.in.a 0
assert e.in.v 0

52
test/unit_tests/demux_td_2/run/prsim.out
View File

@@ -1,4 +1,4 @@
my_demux.my_demux.vc.ct.in[0] my_demux.my_demux.out1_f_buf_func[1].n1 my_demux.my_demux.out1_t_buf_func[1].n1 my_demux.my_demux._out1_a_BX_f[0] my_demux.my_demux.out1_en_buf_t.buf1._y my_demux.my_demux.token_a_out my_demux.my_demux._out_v my_demux.my_demux._in_v my_demux.my_demux._c_d_buf[0] my_demux.my_demux._en my_demux.my_demux.cond_inv_f my_demux.my_demux._out1_a_B my_demux.my_demux.invout_f.a my_demux.my_demux._out1_a_BX_t[0] my_demux.in.v my_demux.my_demux._c_v my_demux.my_demux.invout_t.a my_demux.my_demux.out1_f_buf_func[0].n1 my_demux.out1.v my_demux.my_demux.out1_t_buf_func[0].n1 my_demux.my_demux.cond_inv_t my_demux.out1.a my_demux.my_demux.vc.ct.in[1] my_demux.my_demux._en1_X_f[0] my_demux.my_demux.out_or._y my_demux.my_demux._en1_X_t[0] my_demux.my_demux.vc.OR2_tf[0]._y my_demux.my_demux.in_v_buf._y my_demux.token.a my_demux.my_demux.vc.OR2_tf[1]._y my_demux.my_demux._in_c_v_ my_demux.my_demux.c_buf_tk_inv._y my_demux.my_demux.c_f_c_t_or._y my_demux.my_demux.out1_en_buf_f.buf1._y my_demux.my_demux.vc.ct.C2Els[0]._y my_demux.my_demux.c_buf_d_inv.buf1._y my_demux.my_demux._c_tk_buf my_demux.my_demux.out1_a_B_buf_f.buf1._y my_demux.my_demux.c_el._y my_demux.my_demux.out1_a_B_buf_t.buf1._y
my_demux.my_demux.out1_f_buf_func[1].n1 my_demux.my_demux.out1_t_buf_func[1].n1 my_demux.my_demux._out1_a_BX_f[0] my_demux.my_demux.out1_en_buf_t.buf1._y my_demux.my_demux.token_a_out my_demux.my_demux._out_v my_demux.my_demux._in_v my_demux.my_demux._c_d_buf[0] my_demux.my_demux._en my_demux.my_demux.vc.OR2_tf[1].y my_demux.my_demux.cond_inv_f my_demux.my_demux._out1_a_B my_demux.my_demux.invout_f.a my_demux.my_demux._out1_a_BX_t[0] my_demux.in.v my_demux.my_demux._c_v my_demux.my_demux.invout_t.a my_demux.my_demux.out1_f_buf_func[0].n1 my_demux.out1.v my_demux.my_demux.out1_t_buf_func[0].n1 my_demux.my_demux.cond_inv_t my_demux.out1.a my_demux.my_demux._en1_X_f[0] my_demux.my_demux.out_or._y my_demux.my_demux._en1_X_t[0] my_demux.my_demux.vc.OR2_tf[0]._y my_demux.my_demux.in_v_buf._y my_demux.my_demux.vc.OR2_tf[0].y my_demux.token.a my_demux.my_demux.vc.OR2_tf[1]._y my_demux.my_demux._in_c_v_ my_demux.my_demux.c_buf_tk_inv._y my_demux.my_demux.c_f_c_t_or._y my_demux.my_demux.out1_en_buf_f.buf1._y my_demux.my_demux.c_buf_d_inv.buf1._y my_demux.my_demux._c_tk_buf my_demux.my_demux.vc.myctree.C2Els[0]._y my_demux.my_demux.out1_a_B_buf_f.buf1._y my_demux.my_demux.c_el._y my_demux.my_demux.out1_a_B_buf_t.buf1._y
83058 my_demux.my_demux.out1_f_buf_func[0].n1 : 0
83058 my_demux.my_demux.invout_f.a : 0
83058 my_demux.my_demux.invout_t.a : 0
@@ -13,7 +13,7 @@ my_demux.my_demux.vc.ct.in[0] my_demux.my_demux.out1_f_buf_func[1].n1 my_demux.m
83113 my_demux.my_demux.vc.OR2_tf[1]._y : 1 [by my_demux.my_demux.out1_t_buf_func[1].n1:=0]
92187 my_demux.my_demux.token_a_out : 1 [by my_demux.token.a:=0]
96782 my_demux.my_demux.cond_inv_t : 1 [by my_demux.my_demux.invout_t.a:=0]
96962 my_demux.my_demux.vc.ct.in[1] : 0 [by my_demux.my_demux.vc.OR2_tf[1]._y:=1]
96962 my_demux.my_demux.vc.OR2_tf[1].y : 0 [by my_demux.my_demux.vc.OR2_tf[1]._y:=1]
112853 my_demux.my_demux._out_v : 0 [by my_demux.my_demux.out_or._y:=1]
119989 my_demux.my_demux._out1_a_B : 1 [by my_demux.out1.a:=0]
120411 my_demux.my_demux.out1_a_B_buf_f.buf1._y : 0 [by my_demux.my_demux._out1_a_B:=1]
@@ -29,9 +29,9 @@ my_demux.my_demux.vc.ct.in[0] my_demux.my_demux.out1_f_buf_func[1].n1 my_demux.m
127989 my_demux.my_demux._c_d_buf[0] : 1 [by my_demux.my_demux.c_buf_d_inv.buf1._y:=0]
129035 my_demux.my_demux._en1_X_t[0] : 1 [by my_demux.my_demux.out1_en_buf_t.buf1._y:=0]
134715 my_demux.my_demux._c_v : 0 [by my_demux.my_demux.c_f_c_t_or._y:=1]
146511 my_demux.my_demux.vc.ct.in[0] : 0 [by my_demux.my_demux.vc.OR2_tf[0]._y:=1]
147465 my_demux.my_demux.vc.ct.C2Els[0]._y : 1 [by my_demux.my_demux.vc.ct.in[0]:=0]
148546 my_demux.my_demux._in_v : 0 [by my_demux.my_demux.vc.ct.C2Els[0]._y:=1]
146511 my_demux.my_demux.vc.OR2_tf[0].y : 0 [by my_demux.my_demux.vc.OR2_tf[0]._y:=1]
147465 my_demux.my_demux.vc.myctree.C2Els[0]._y : 1 [by my_demux.my_demux.vc.OR2_tf[0].y:=0]
148546 my_demux.my_demux._in_v : 0 [by my_demux.my_demux.vc.myctree.C2Els[0]._y:=1]
149528 my_demux.my_demux.c_el._y : 1 [by my_demux.my_demux._in_v:=0]
149546 my_demux.my_demux._in_c_v_ : 0 [by my_demux.my_demux.c_el._y:=1]
149640 my_demux.my_demux._en1_X_f[0] : 1 [by my_demux.my_demux.out1_en_buf_f.buf1._y:=0]
@@ -39,7 +39,7 @@ my_demux.my_demux.vc.ct.in[0] my_demux.my_demux.out1_f_buf_func[1].n1 my_demux.m
172716 my_demux.my_demux._out1_a_BX_f[0] : 1 [by my_demux.my_demux.out1_a_B_buf_t.buf1._y:=0]
203016 my_demux.my_demux.in_v_buf._y : 1 [by my_demux.my_demux._in_v:=0]
207019 my_demux.in.v : 0 [by my_demux.my_demux.in_v_buf._y:=1]
[]System initialized
System initialized
207019 Reset : 0
251920 my_demux._reset_B : 1 [by Reset:=0]
273504 my_demux.my_demux.reset_buf._y : 0 [by my_demux._reset_B:=1]
@@ -48,25 +48,25 @@ my_demux.my_demux.vc.ct.in[0] my_demux.my_demux.out1_f_buf_func[1].n1 my_demux.m
278766 my_demux.my_demux.reset_bufarray.buf1._y : 0 [by my_demux.my_demux._reset_BX:=1]
278905 my_demux.my_demux._reset_BXX[0] : 1 [by my_demux.my_demux.reset_bufarray.buf1._y:=0]
280321 my_demux.my_demux._reset_BXt : 1 [by my_demux.my_demux.reset_buf_token._y:=0]
[]System reset completed
System reset completed
[]Output neutral checked
Output neutral checked
280321 my_demux.my_demux.invout_t.a : 1
280321 my_demux.my_demux.out1_t_buf_func[1].n1 : 1
280321 my_demux.my_demux.out1_t_buf_func[0].n1 : 1
280332 my_demux.my_demux.vc.OR2_tf[1]._y : 0 [by my_demux.my_demux.out1_t_buf_func[1].n1:=1]
280333 my_demux.my_demux.vc.ct.in[1] : 1 [by my_demux.my_demux.vc.OR2_tf[1]._y:=0]
280333 my_demux.my_demux.vc.OR2_tf[1].y : 1 [by my_demux.my_demux.vc.OR2_tf[1]._y:=0]
280336 my_demux.my_demux.out1_t_buf_func[0]._y : 0 [by my_demux.my_demux.out1_t_buf_func[0].n1:=1]
280373 my_demux.my_demux.out1_t_buf_func[0].y : 1 [by my_demux.my_demux.out1_t_buf_func[0]._y:=0]
280390 my_demux.my_demux.c_f_c_t_or._y : 0 [by my_demux.my_demux.invout_t.a:=1]
280525 my_demux.my_demux.vc.OR2_tf[0]._y : 0 [by my_demux.my_demux.out1_t_buf_func[0].n1:=1]
280637 my_demux.my_demux.vc.ct.in[0] : 1 [by my_demux.my_demux.vc.OR2_tf[0]._y:=0]
280637 my_demux.my_demux.vc.OR2_tf[0].y : 1 [by my_demux.my_demux.vc.OR2_tf[0]._y:=0]
281129 my_demux.my_demux._c_v : 1 [by my_demux.my_demux.c_f_c_t_or._y:=0]
316667 my_demux.my_demux.cond_inv_t : 0 [by my_demux.my_demux.invout_t.a:=1]
316707 my_demux.my_demux.c_buf_tk_inv._y : 1 [by my_demux.my_demux.cond_inv_t:=0]
316964 my_demux.my_demux._c_tk_buf : 0 [by my_demux.my_demux.c_buf_tk_inv._y:=1]
328149 my_demux.my_demux.vc.ct.C2Els[0]._y : 0 [by my_demux.my_demux.vc.ct.in[0]:=1]
328236 my_demux.my_demux._in_v : 1 [by my_demux.my_demux.vc.ct.C2Els[0]._y:=0]
328149 my_demux.my_demux.vc.myctree.C2Els[0]._y : 0 [by my_demux.my_demux.vc.OR2_tf[0].y:=1]
328236 my_demux.my_demux._in_v : 1 [by my_demux.my_demux.vc.myctree.C2Els[0]._y:=0]
328237 my_demux.my_demux.c_el._y : 0 [by my_demux.my_demux._in_v:=1]
328530 my_demux.my_demux.in_v_buf._y : 0 [by my_demux.my_demux._in_v:=1]
330043 my_demux.my_demux._in_c_v_ : 1 [by my_demux.my_demux.c_el._y:=0]
@@ -86,11 +86,11 @@ my_demux.my_demux.vc.ct.in[0] my_demux.my_demux.out1_f_buf_func[1].n1 my_demux.m
367396 my_demux.my_demux.out1_t_buf_func[0].n1 : 0
367396 my_demux.my_demux.out1_t_buf_func[1].n1 : 0
367755 my_demux.my_demux.vc.OR2_tf[1]._y : 1 [by my_demux.my_demux.out1_t_buf_func[1].n1:=0]
381871 my_demux.my_demux.vc.ct.in[1] : 0 [by my_demux.my_demux.vc.OR2_tf[1]._y:=1]
381871 my_demux.my_demux.vc.OR2_tf[1].y : 0 [by my_demux.my_demux.vc.OR2_tf[1]._y:=1]
383058 my_demux.my_demux.vc.OR2_tf[0]._y : 1 [by my_demux.my_demux.out1_t_buf_func[0].n1:=0]
383279 my_demux.my_demux.vc.ct.in[0] : 0 [by my_demux.my_demux.vc.OR2_tf[0]._y:=1]
383286 my_demux.my_demux.vc.ct.C2Els[0]._y : 1 [by my_demux.my_demux.vc.ct.in[0]:=0]
383316 my_demux.my_demux._in_v : 0 [by my_demux.my_demux.vc.ct.C2Els[0]._y:=1]
383279 my_demux.my_demux.vc.OR2_tf[0].y : 0 [by my_demux.my_demux.vc.OR2_tf[0]._y:=1]
383286 my_demux.my_demux.vc.myctree.C2Els[0]._y : 1 [by my_demux.my_demux.vc.OR2_tf[0].y:=0]
383316 my_demux.my_demux._in_v : 0 [by my_demux.my_demux.vc.myctree.C2Els[0]._y:=1]
390029 my_demux.my_demux.in_v_buf._y : 1 [by my_demux.my_demux._in_v:=0]
447490 my_demux.in.v : 0 [by my_demux.my_demux.in_v_buf._y:=1]
447490 my_demux.out1.a : 1
@@ -103,7 +103,7 @@ my_demux.my_demux.vc.ct.in[0] my_demux.my_demux.out1_f_buf_func[1].n1 my_demux.m
450375 my_demux.my_demux._out1_a_BX_f[0] : 0 [by my_demux.my_demux.out1_a_B_buf_t.buf1._y:=1]
450606 my_demux.my_demux.out1_t_buf_func[1].y : 0 [by my_demux.my_demux.out1_t_buf_func[1]._y:=1]
468950 my_demux.my_demux.out1_t_buf_func[0].y : 0 [by my_demux.my_demux.out1_t_buf_func[0]._y:=1]
[]First Cond Checked
First Cond Checked
468950 my_demux.my_demux.invout_t.a : 0
468950 my_demux.out1.v : 0
468950 my_demux.out1.a : 0
@@ -128,7 +128,7 @@ my_demux.my_demux.vc.ct.in[0] my_demux.my_demux.out1_f_buf_func[1].n1 my_demux.m
484418 my_demux.my_demux._en1_X_f[0] : 1 [by my_demux.my_demux.out1_en_buf_f.buf1._y:=0]
527786 my_demux.my_demux.out1_en_buf_t.buf1._y : 0 [by my_demux.my_demux._en:=1]
527797 my_demux.my_demux._en1_X_t[0] : 1 [by my_demux.my_demux.out1_en_buf_t.buf1._y:=0]
[]System initialized
System initialized
527797 my_demux.my_demux.invout_f.a : 1
527797 my_demux.my_demux.out1_t_buf_func[1].n1 : 1
527797 my_demux.my_demux.out1_t_buf_func[0].n1 : 1
@@ -138,15 +138,15 @@ my_demux.my_demux.vc.ct.in[0] my_demux.my_demux.out1_f_buf_func[1].n1 my_demux.m
528325 my_demux.my_demux.out1_t_buf_func[0]._y : 0 [by my_demux.my_demux.out1_t_buf_func[0].n1:=1]
530248 my_demux.my_demux.out1_t_buf_func[1].y : 1 [by my_demux.my_demux.out1_t_buf_func[1]._y:=0]
530438 my_demux.my_demux.vc.OR2_tf[1]._y : 0 [by my_demux.my_demux.out1_t_buf_func[1].n1:=1]
530440 my_demux.my_demux.vc.ct.in[1] : 1 [by my_demux.my_demux.vc.OR2_tf[1]._y:=0]
530440 my_demux.my_demux.vc.OR2_tf[1].y : 1 [by my_demux.my_demux.vc.OR2_tf[1]._y:=0]
532359 my_demux.my_demux.vc.OR2_tf[0]._y : 0 [by my_demux.my_demux.out1_t_buf_func[0].n1:=1]
541366 my_demux.my_demux.out1_t_buf_func[0].y : 1 [by my_demux.my_demux.out1_t_buf_func[0]._y:=0]
552092 my_demux.my_demux.c_buf_d_inv.buf1._y : 1 [by my_demux.my_demux.cond_inv_f:=0]
552095 my_demux.my_demux._c_d_buf[0] : 0 [by my_demux.my_demux.c_buf_d_inv.buf1._y:=1]
554744 my_demux.my_demux._c_v : 1 [by my_demux.my_demux.c_f_c_t_or._y:=0]
593317 my_demux.my_demux.vc.ct.in[0] : 1 [by my_demux.my_demux.vc.OR2_tf[0]._y:=0]
593346 my_demux.my_demux.vc.ct.C2Els[0]._y : 0 [by my_demux.my_demux.vc.ct.in[0]:=1]
593663 my_demux.my_demux._in_v : 1 [by my_demux.my_demux.vc.ct.C2Els[0]._y:=0]
593317 my_demux.my_demux.vc.OR2_tf[0].y : 1 [by my_demux.my_demux.vc.OR2_tf[0]._y:=0]
593346 my_demux.my_demux.vc.myctree.C2Els[0]._y : 0 [by my_demux.my_demux.vc.OR2_tf[0].y:=1]
593663 my_demux.my_demux._in_v : 1 [by my_demux.my_demux.vc.myctree.C2Els[0]._y:=0]
593707 my_demux.my_demux.c_el._y : 0 [by my_demux.my_demux._in_v:=1]
593816 my_demux.my_demux.in_v_buf._y : 0 [by my_demux.my_demux._in_v:=1]
595264 my_demux.my_demux.token_buf._y : 0 [by my_demux.my_demux._in_v:=1]
@@ -172,12 +172,12 @@ my_demux.my_demux.vc.ct.in[0] my_demux.my_demux.out1_f_buf_func[1].n1 my_demux.m
677919 my_demux.my_demux.out1_t_buf_func[1].n1 : 0
677919 my_demux.my_demux.out1_t_buf_func[0].n1 : 0
677933 my_demux.my_demux.vc.OR2_tf[0]._y : 1 [by my_demux.my_demux.out1_t_buf_func[0].n1:=0]
677940 my_demux.my_demux.vc.ct.in[0] : 0 [by my_demux.my_demux.vc.OR2_tf[0]._y:=1]
677940 my_demux.my_demux.vc.OR2_tf[0].y : 0 [by my_demux.my_demux.vc.OR2_tf[0]._y:=1]
678081 my_demux.my_demux.token_a_out : 1 [by my_demux.token.a:=0]
685288 my_demux.my_demux.vc.OR2_tf[1]._y : 1 [by my_demux.my_demux.out1_t_buf_func[1].n1:=0]
685448 my_demux.my_demux.vc.ct.in[1] : 0 [by my_demux.my_demux.vc.OR2_tf[1]._y:=1]
707005 my_demux.my_demux.vc.ct.C2Els[0]._y : 1 [by my_demux.my_demux.vc.ct.in[1]:=0]
707006 my_demux.my_demux._in_v : 0 [by my_demux.my_demux.vc.ct.C2Els[0]._y:=1]
685448 my_demux.my_demux.vc.OR2_tf[1].y : 0 [by my_demux.my_demux.vc.OR2_tf[1]._y:=1]
707005 my_demux.my_demux.vc.myctree.C2Els[0]._y : 1 [by my_demux.my_demux.vc.OR2_tf[1].y:=0]
707006 my_demux.my_demux._in_v : 0 [by my_demux.my_demux.vc.myctree.C2Els[0]._y:=1]
707007 my_demux.my_demux.in_v_buf._y : 1 [by my_demux.my_demux._in_v:=0]
707008 my_demux.in.v : 0 [by my_demux.my_demux.in_v_buf._y:=1]
707008 my_demux.my_demux.invout_f.a : 0

BIN
test/unit_tests/demux_td_2/run/prsim.pdf
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42
test/unit_tests/demux_td_2/run/test.prs
View File

@@ -239,20 +239,12 @@
= "my_demux.my_demux.token.d.d[0]" "my_demux.my_demux.token_buf.y"
= "my_demux.my_demux.token.d.d[0]" "my_demux.my_demux.out_or.b"
= "my_demux.my_demux.token.d.d[0]" "my_demux.my_demux.token.r"
= "my_demux.my_demux.supply.vss" "my_demux.my_demux.out1_a_B_buf_t.supply.vss"
= "my_demux.my_demux.supply.vdd" "my_demux.my_demux.out1_a_B_buf_t.supply.vdd"
= "my_demux.my_demux.supply.vss" "my_demux.my_demux.out1_a_B_buf_f.supply.vss"
= "my_demux.my_demux.supply.vdd" "my_demux.my_demux.out1_a_B_buf_f.supply.vdd"
= "my_demux.my_demux.supply.vss" "my_demux.my_demux.out1_en_buf_f.supply.vss"
= "my_demux.my_demux.supply.vdd" "my_demux.my_demux.out1_en_buf_f.supply.vdd"
= "my_demux.my_demux.supply.vss" "my_demux.my_demux.out1_en_buf_t.supply.vss"
= "my_demux.my_demux.supply.vdd" "my_demux.my_demux.out1_en_buf_t.supply.vdd"
= "my_demux.my_demux.supply.vss" "my_demux.my_demux.vc.supply.vss"
= "my_demux.my_demux.supply.vdd" "my_demux.my_demux.vc.supply.vdd"
= "my_demux.my_demux.supply.vss" "my_demux.my_demux.c_buf_d_inv.supply.vss"
= "my_demux.my_demux.supply.vdd" "my_demux.my_demux.c_buf_d_inv.supply.vdd"
= "my_demux.my_demux.supply.vss" "my_demux.my_demux.reset_bufarray.supply.vss"
= "my_demux.my_demux.supply.vdd" "my_demux.my_demux.reset_bufarray.supply.vdd"
= "my_demux.my_demux.supply.vdd" "my_demux.my_demux.token_buf.vdd"
= "my_demux.my_demux.supply.vdd" "my_demux.my_demux.out1_t_buf_func[1].vdd"
= "my_demux.my_demux.supply.vdd" "my_demux.my_demux.out1_f_buf_func[1].vdd"
@@ -285,20 +277,18 @@
= "my_demux.my_demux.supply.vss" "my_demux.my_demux.out_or.vss"
"my_demux.my_demux.invout_f.a"->"my_demux.my_demux.invout_f.y"-
~("my_demux.my_demux.invout_f.a")->"my_demux.my_demux.invout_f.y"+
~"my_demux.my_demux.vc.ct.C2Els[0].c1"&~"my_demux.my_demux.vc.ct.C2Els[0].c2"->"my_demux.my_demux.vc.ct.C2Els[0]._y"+
"my_demux.my_demux.vc.ct.C2Els[0].c1"&"my_demux.my_demux.vc.ct.C2Els[0].c2"->"my_demux.my_demux.vc.ct.C2Els[0]._y"-
"my_demux.my_demux.vc.ct.C2Els[0]._y"->"my_demux.my_demux.vc.ct.C2Els[0].y"-
~("my_demux.my_demux.vc.ct.C2Els[0]._y")->"my_demux.my_demux.vc.ct.C2Els[0].y"+
= "my_demux.my_demux.vc.ct.supply.vdd" "my_demux.my_demux.vc.ct.C2Els[0].vdd"
= "my_demux.my_demux.vc.ct.supply.vss" "my_demux.my_demux.vc.ct.C2Els[0].vss"
= "my_demux.my_demux.vc.ct.in[0]" "my_demux.my_demux.vc.ct.C2Els[0].c1"
= "my_demux.my_demux.vc.ct.in[0]" "my_demux.my_demux.vc.ct.tmp[0]"
= "my_demux.my_demux.vc.ct.in[1]" "my_demux.my_demux.vc.ct.C2Els[0].c2"
= "my_demux.my_demux.vc.ct.in[1]" "my_demux.my_demux.vc.ct.tmp[1]"
= "my_demux.my_demux.vc.ct.out" "my_demux.my_demux.vc.ct.C2Els[0].y"
= "my_demux.my_demux.vc.ct.out" "my_demux.my_demux.vc.ct.tmp[2]"
= "my_demux.my_demux.vc.ct.in[0]" "my_demux.my_demux.vc.OR2_tf[0].y"
= "my_demux.my_demux.vc.ct.in[1]" "my_demux.my_demux.vc.OR2_tf[1].y"
~"my_demux.my_demux.vc.myctree.C2Els[0].c1"&~"my_demux.my_demux.vc.myctree.C2Els[0].c2"->"my_demux.my_demux.vc.myctree.C2Els[0]._y"+
"my_demux.my_demux.vc.myctree.C2Els[0].c1"&"my_demux.my_demux.vc.myctree.C2Els[0].c2"->"my_demux.my_demux.vc.myctree.C2Els[0]._y"-
"my_demux.my_demux.vc.myctree.C2Els[0]._y"->"my_demux.my_demux.vc.myctree.C2Els[0].y"-
~("my_demux.my_demux.vc.myctree.C2Els[0]._y")->"my_demux.my_demux.vc.myctree.C2Els[0].y"+
= "my_demux.my_demux.vc.myctree.supply.vdd" "my_demux.my_demux.vc.myctree.C2Els[0].vdd"
= "my_demux.my_demux.vc.myctree.supply.vss" "my_demux.my_demux.vc.myctree.C2Els[0].vss"
= "my_demux.my_demux.vc.myctree.in[0]" "my_demux.my_demux.vc.myctree.C2Els[0].c1"
= "my_demux.my_demux.vc.myctree.in[0]" "my_demux.my_demux.vc.myctree.tmp[0]"
= "my_demux.my_demux.vc.myctree.in[1]" "my_demux.my_demux.vc.myctree.C2Els[0].c2"
= "my_demux.my_demux.vc.myctree.in[1]" "my_demux.my_demux.vc.myctree.tmp[1]"
= "my_demux.my_demux.vc.myctree.out" "my_demux.my_demux.vc.myctree.C2Els[0].y"
= "my_demux.my_demux.vc.myctree.out" "my_demux.my_demux.vc.myctree.tmp[2]"
"my_demux.my_demux.vc.OR2_tf[0].a"|"my_demux.my_demux.vc.OR2_tf[0].b"->"my_demux.my_demux.vc.OR2_tf[0]._y"-
~("my_demux.my_demux.vc.OR2_tf[0].a"|"my_demux.my_demux.vc.OR2_tf[0].b")->"my_demux.my_demux.vc.OR2_tf[0]._y"+
"my_demux.my_demux.vc.OR2_tf[0]._y"->"my_demux.my_demux.vc.OR2_tf[0].y"-
@@ -307,13 +297,15 @@
~("my_demux.my_demux.vc.OR2_tf[1].a"|"my_demux.my_demux.vc.OR2_tf[1].b")->"my_demux.my_demux.vc.OR2_tf[1]._y"+
"my_demux.my_demux.vc.OR2_tf[1]._y"->"my_demux.my_demux.vc.OR2_tf[1].y"-
~("my_demux.my_demux.vc.OR2_tf[1]._y")->"my_demux.my_demux.vc.OR2_tf[1].y"+
= "my_demux.my_demux.vc.supply.vss" "my_demux.my_demux.vc.ct.supply.vss"
= "my_demux.my_demux.vc.supply.vdd" "my_demux.my_demux.vc.ct.supply.vdd"
= "my_demux.my_demux.vc.OR2_tf[1].y" "my_demux.my_demux.vc.myctree.in[1]"
= "my_demux.my_demux.vc.OR2_tf[0].y" "my_demux.my_demux.vc.myctree.in[0]"
= "my_demux.my_demux.vc.supply.vss" "my_demux.my_demux.vc.myctree.supply.vss"
= "my_demux.my_demux.vc.supply.vdd" "my_demux.my_demux.vc.myctree.supply.vdd"
= "my_demux.my_demux.vc.supply.vdd" "my_demux.my_demux.vc.OR2_tf[1].vdd"
= "my_demux.my_demux.vc.supply.vdd" "my_demux.my_demux.vc.OR2_tf[0].vdd"
= "my_demux.my_demux.vc.supply.vss" "my_demux.my_demux.vc.OR2_tf[1].vss"
= "my_demux.my_demux.vc.supply.vss" "my_demux.my_demux.vc.OR2_tf[0].vss"
= "my_demux.my_demux.vc.out" "my_demux.my_demux.vc.ct.out"
= "my_demux.my_demux.vc.out" "my_demux.my_demux.vc.myctree.out"
= "my_demux.my_demux.vc.in.d[0].d[0]" "my_demux.my_demux.vc.in.d[0].f"
= "my_demux.my_demux.vc.in.d[0].d[1]" "my_demux.my_demux.vc.in.d[0].t"
= "my_demux.my_demux.vc.in.d[1].d[0]" "my_demux.my_demux.vc.in.d[1].f"

10
test/unit_tests/demux_td_2/test.prsim
View File

@@ -7,11 +7,11 @@ set my_demux.token.r 0
set my_demux.cond.d.d[0].t 0
set my_demux.cond.d.d[0].f 0
cycle
system "echo '[]System initialized'"
system "echo 'System initialized'"
set Reset 0
cycle
system "echo '[]System reset completed'"
system "echo 'System reset completed'"
status X
mode run
@@ -19,7 +19,7 @@ assert-qdi-channel-neutral "my_demux.out1" 2
assert-qdi-channel-neutral "my_demux.in" 2
cycle
system "echo '[]Output neutral checked'"
system "echo 'Output neutral checked'"
set my_demux.cond.d.d[0].t 1
set my_demux.cond.d.d[0].f 0
@@ -46,7 +46,7 @@ assert my_demux.in.a 1
set-qdi-channel-neutral "my_demux.in" 2
system "echo '[]First Cond Checked'"
system "echo 'First Cond Checked'"
set my_demux.out1.a 0
set my_demux.out1.v 0
@@ -56,7 +56,7 @@ set my_demux.cond.d.d[0].t 0
set my_demux.cond.d.d[0].f 0
cycle
system "echo '[]System initialized'"
system "echo 'System initialized'"
set my_demux.cond.d.d[0].t 0
set my_demux.cond.d.d[0].f 1

798
test/unit_tests/encoder2D_2x2/run/prsim.out
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@@ -1,798 +0,0 @@
e.y[0].r e.e.Yarb.arbs[0].or_cell._y e.e.x_ack_arb[0].buf1._y e.e.vtree_x.OR2_tf[0]._y e.e.buf_s_func._in_vX e.e._arb_out_x.r e.e.buf_s_func._en_X_t[0] e.y[0].a e.out.v e.e.buf_s_func._in_vXX_t[0] e.e.Yarb.arbs[0].ack_cell2._y e.e.y_ack_arb[1].buf1._y e.e._y_temp[1].a e.e.buf_s_func.out_a_B_buf_f.buf1._y e.e.buf_s_func._out_a_B e.e.buf_s_func._out_a_BX_t[0] e.e.x_enc_out.d[0].t e.x[0].r e.y[1].r e.e._x_temp[1].a e.e.Xarb.arbs[0]._y2_arb e.e._arb_out_y.r e.e._in_x_v e.out.a e.x[1].r e.e.y_enc_out.d[0].t e.e.x_enc_out.d[0].f e.e.y_enc_out.d[0].f e.e.y_encoder.ors_f[0].b._y e.e.vtree_y.OR2_tf[0]._y e.e.buf_s_func._in_vXX_f[0] e.e.buf_s_func._en_X_f[0] e.x[0].a e.e._y_temp[0].a e.e._in_xy_v.y e.e.vtree_x.ct.b._y e.e._x_temp[0].a e.e._en e.e.x_encoder.ors_t[0].b._y e.x[1].a e.e.buf_s_func.in_v_buf_f.buf1._y e.e.Yarb.arbs[0].ack_cell1._y e.e._in_y_v e.e.Yarb.arbs[0]._y1_arb e.e.vtree_x.ct.in[0] e.e.buf_s_func._out_a_BX_f[0] e.e.buf_s_func.in_v_prebuf._y e.e.vtree_y.ct.in[0] e.y[1].a e.e._x_v e.e.Xarb.arbs[0].arbiter._y1 e.e.Xarb.arbs[0].or_cell._y e.e._in_xy_v._y e.e.Xarb.arbs[0].ack_cell1._y e.e.Xarb.arbs[0]._y1_arb e.e.x_encoder.ors_f[0].b._y e.e.Yarb.arbs[0].arbiter._y1 e.e.y_encoder.ors_t[0].b._y e.e.vtree_y.ct.b._y e.e.buf_s_func.out_a_B_buf_t.buf1._y e.e._x_v_B e.e.Yarb.arbs[0]._y2_arb e.e.Xarb.arbs[0].arbiter._y2 e.e.Xarb.arbs[0].ack_cell2._y e.e.buf_s_func.in_v_buf_t.buf1._y e.e.y_ack_arb[0].buf1._y e.e.x_ack_arb[1].buf1._y e.e.Yarb.arbs[0].arbiter._y2 e.e.x_req_ortree.or2s[0]._y e.e.buf_s_func.en_buf_f.buf1._y e.e.buf_s_func.en_buf_t.buf1._y
[] Set Out Ack/Valid Low
97124 e.out.a : 0
97124 e.out.v : 0
97141 e.e.buf_s_func._out_a_B : 1 [by e.out.a:=0]
97142 e.e.buf_s_func.out_a_B_buf_f.buf1._y : 0 [by e.e.buf_s_func._out_a_B:=1]
97188 e.e._en : 1 [by e.out.v:=0]
97189 e.e.buf_s_func.en_buf_f.buf1._y : 0 [by e.e._en:=1]
97546 e.e.buf_s_func.out_a_B_buf_t.buf1._y : 0 [by e.e.buf_s_func._out_a_B:=1]
97722 e.e.buf_s_func._out_a_BX_f[0] : 1 [by e.e.buf_s_func.out_a_B_buf_t.buf1._y:=0]
108612 e.e.buf_s_func.en_buf_t.buf1._y : 0 [by e.e._en:=1]
108613 e.e.buf_s_func._en_X_t[0] : 1 [by e.e.buf_s_func.en_buf_t.buf1._y:=0]
109949 e.e.buf_s_func._en_X_f[0] : 1 [by e.e.buf_s_func.en_buf_f.buf1._y:=0]
162289 e.e.buf_s_func._out_a_BX_t[0] : 1 [by e.e.buf_s_func.out_a_B_buf_f.buf1._y:=0]
[] Setting Neuron Req Low
162289 e.y[0].r : 0
162289 e.x[1].r : 0
162289 e.x[0].r : 0
162289 e.y[1].r : 0
162292 e.e.Xarb.arbs[0].arbiter._y1 : 1 [by e.x[0].r:=0]
162296 e.e.Xarb.arbs[0].arbiter._y2 : 1 [by e.x[1].r:=0]
165550 e.e.Xarb.arbs[0]._y1_arb : 0 [by e.e.Xarb.arbs[0].arbiter._y1:=1]
165556 e.e.Xarb.arbs[0].ack_cell1._y : 1 [by e.e.Xarb.arbs[0]._y1_arb:=0]
165810 e.e._x_temp[0].a : 0 [by e.e.Xarb.arbs[0].ack_cell1._y:=1]
165992 e.e.x_ack_arb[0].buf1._y : 1 [by e.e._x_temp[0].a:=0]
169472 e.e.Yarb.arbs[0].arbiter._y2 : 1 [by e.y[1].r:=0]
169619 e.e.Yarb.arbs[0]._y2_arb : 0 [by e.e.Yarb.arbs[0].arbiter._y2:=1]
169620 e.e.Yarb.arbs[0].ack_cell2._y : 1 [by e.e.Yarb.arbs[0]._y2_arb:=0]
175703 e.e.x_req_ortree.or2s[0]._y : 1 [by e.x[0].r:=0]
175777 e.e._x_v : 0 [by e.e.x_req_ortree.or2s[0]._y:=1]
177674 e.e._x_v_B : 1 [by e.e._x_v:=0]
212927 e.e.Yarb.arbs[0].arbiter._y1 : 1 [by e.y[0].r:=0]
212928 e.e.Yarb.arbs[0]._y1_arb : 0 [by e.e.Yarb.arbs[0].arbiter._y1:=1]
212939 e.e.Yarb.arbs[0].ack_cell1._y : 1 [by e.e.Yarb.arbs[0]._y1_arb:=0]
212940 e.e._y_temp[0].a : 0 [by e.e.Yarb.arbs[0].ack_cell1._y:=1]
213039 e.e.y_ack_arb[0].buf1._y : 1 [by e.e._y_temp[0].a:=0]
213107 e.e.Yarb.arbs[0].or_cell._y : 1 [by e.e.Yarb.arbs[0]._y1_arb:=0]
213139 e.e._arb_out_y.r : 0 [by e.e.Yarb.arbs[0].or_cell._y:=1]
213498 e.x[0].a : 0 [by e.e.x_ack_arb[0].buf1._y:=1]
218276 e.e.Xarb.arbs[0]._y2_arb : 0 [by e.e.Xarb.arbs[0].arbiter._y2:=1]
218496 e.e.Xarb.arbs[0].ack_cell2._y : 1 [by e.e.Xarb.arbs[0]._y2_arb:=0]
218554 e.e._x_temp[1].a : 0 [by e.e.Xarb.arbs[0].ack_cell2._y:=1]
218782 e.e._y_temp[1].a : 0 [by e.e.Yarb.arbs[0].ack_cell2._y:=1]
218783 e.e.y_ack_arb[1].buf1._y : 1 [by e.e._y_temp[1].a:=0]
219117 e.e.x_encoder.ors_f[0].b._y : 1 [by e.x[0].a:=0]
219167 e.e.x_enc_out.d[0].f : 0 [by e.e.x_encoder.ors_f[0].b._y:=1]
219353 e.e.x_ack_arb[1].buf1._y : 1 [by e.e._x_temp[1].a:=0]
219882 e.y[0].a : 0 [by e.e.y_ack_arb[0].buf1._y:=1]
219902 e.e.y_encoder.ors_f[0].b._y : 1 [by e.y[0].a:=0]
226848 e.y[1].a : 0 [by e.e.y_ack_arb[1].buf1._y:=1]
226983 e.x[1].a : 0 [by e.e.x_ack_arb[1].buf1._y:=1]
228056 e.e.Xarb.arbs[0].or_cell._y : 1 [by e.e.Xarb.arbs[0]._y2_arb:=0]
229957 e.e._arb_out_x.r : 0 [by e.e.Xarb.arbs[0].or_cell._y:=1]
232524 e.e.x_encoder.ors_t[0].b._y : 1 [by e.x[1].a:=0]
233746 e.e.y_enc_out.d[0].f : 0 [by e.e.y_encoder.ors_f[0].b._y:=1]
243058 e.e.x_enc_out.d[0].t : 0 [by e.e.x_encoder.ors_t[0].b._y:=1]
264915 e.e.y_encoder.ors_t[0].b._y : 1 [by e.y[1].a:=0]
267412 e.e.y_enc_out.d[0].t : 0 [by e.e.y_encoder.ors_t[0].b._y:=1]
267413 e.e.vtree_y.OR2_tf[0]._y : 1 [by e.e.y_enc_out.d[0].t:=0]
267797 e.e.vtree_y.ct.in[0] : 0 [by e.e.vtree_y.OR2_tf[0]._y:=1]
285642 e.e.vtree_x.OR2_tf[0]._y : 1 [by e.e.x_enc_out.d[0].t:=0]
285744 e.e.vtree_x.ct.in[0] : 0 [by e.e.vtree_x.OR2_tf[0]._y:=1]
285846 e.e.vtree_x.ct.b._y : 1 [by e.e.vtree_x.ct.in[0]:=0]
285913 e.e._in_x_v : 0 [by e.e.vtree_x.ct.b._y:=1]
296652 e.e._in_xy_v._y : 1 [by e.e._in_x_v:=0]
296665 e.e._in_xy_v.y : 0 [by e.e._in_xy_v._y:=1]
299810 e.e.buf_s_func.in_v_prebuf._y : 1 [by e.e._in_xy_v.y:=0]
299928 e.e.buf_s_func._in_vX : 0 [by e.e.buf_s_func.in_v_prebuf._y:=1]
299930 e.e.buf_s_func.in_v_buf_f.buf1._y : 1 [by e.e.buf_s_func._in_vX:=0]
299938 e.e.buf_s_func.in_v_buf_t.buf1._y : 1 [by e.e.buf_s_func._in_vX:=0]
299952 e.e.buf_s_func._in_vXX_t[0] : 0 [by e.e.buf_s_func.in_v_buf_t.buf1._y:=1]
299959 e.e.buf_s_func._in_vXX_f[0] : 0 [by e.e.buf_s_func.in_v_buf_f.buf1._y:=1]
308558 e.e.vtree_y.ct.b._y : 1 [by e.e.vtree_y.ct.in[0]:=0]
308622 e.e._in_y_v : 0 [by e.e.vtree_y.ct.b._y:=1]
308622 Reset : 0
316374 e._reset_B : 1 [by Reset:=0]
316405 e.e.reset_buf._y : 0 [by e._reset_B:=1]
316427 e.e._reset_BX : 1 [by e.e.reset_buf._y:=0]
321791 e.e.buf_s_func.reset_buf._y : 0 [by e._reset_B:=1]
322907 e.e.buf_s_func._reset_BX : 1 [by e.e.buf_s_func.reset_buf._y:=0]
323689 e.e.buf_s_func.reset_bufarray.buf1._y : 0 [by e.e.buf_s_func._reset_BX:=1]
323972 e.e.buf_s_func._reset_BXX[0] : 1 [by e.e.buf_s_func.reset_bufarray.buf1._y:=0]
379361 e.e.reset_bufarray.buf1._y : 0 [by e.e._reset_BX:=1]
389772 e.e._reset_BXX[0] : 1 [by e.e.reset_bufarray.buf1._y:=0]
[] Single Neuron Spikes (0,0)
389772 e.y[0].r : 1
389772 e.x[0].r : 1
389773 e.e.Xarb.arbs[0].arbiter._y1 : 0 [by e.x[0].r:=1]
389780 e.e.Yarb.arbs[0].arbiter._y1 : 0 [by e.y[0].r:=1]
389780 e.e.Xarb.arbs[0]._y1_arb : 1 [by e.e.Xarb.arbs[0].arbiter._y1:=0]
389804 e.e.Yarb.arbs[0]._y1_arb : 1 [by e.e.Yarb.arbs[0].arbiter._y1:=0]
389813 e.e.Yarb.arbs[0].or_cell._y : 0 [by e.e.Yarb.arbs[0]._y1_arb:=1]
389842 e.e._arb_out_y.r : 1 [by e.e.Yarb.arbs[0].or_cell._y:=0]
389843 e.e.Y_ack_confirm._y : 0 [by e.e._arb_out_y.r:=1]
390326 e.e._arb_out_y.a : 1 [by e.e.Y_ack_confirm._y:=0]
390426 e.e.Yarb.arbs[0].ack_cell1._y : 0 [by e.e._arb_out_y.a:=1]
390428 e.e._y_temp[0].a : 1 [by e.e.Yarb.arbs[0].ack_cell1._y:=0]
392431 e.e.y_ack_arb[0].buf1._y : 0 [by e.e._y_temp[0].a:=1]
393052 e.e.x_req_ortree.or2s[0]._y : 0 [by e.x[0].r:=1]
394911 e.e.Xarb.arbs[0].or_cell._y : 0 [by e.e.Xarb.arbs[0]._y1_arb:=1]
394914 e.e._arb_out_x.r : 1 [by e.e.Xarb.arbs[0].or_cell._y:=0]
413074 e.e._x_v : 1 [by e.e.x_req_ortree.or2s[0]._y:=0]
413075 e.e._x_v_B : 0 [by e.e._x_v:=1]
434462 e.y[0].a : 1 [by e.e.y_ack_arb[0].buf1._y:=0]
434466 e.e.y_encoder.ors_f[0].b._y : 0 [by e.y[0].a:=1]
434795 e.e.y_enc_out.d[0].f : 1 [by e.e.y_encoder.ors_f[0].b._y:=0]
436021 e.e.vtree_y.OR2_tf[0]._y : 0 [by e.e.y_enc_out.d[0].f:=1]
458869 e.e.X_ack_confirm._y : 0 [by e.e._arb_out_x.r:=1]
459476 e.e._arb_out_x.a : 1 [by e.e.X_ack_confirm._y:=0]
461370 e.e.Xarb.arbs[0].ack_cell1._y : 0 [by e.e._arb_out_x.a:=1]
463151 e.e._x_temp[0].a : 1 [by e.e.Xarb.arbs[0].ack_cell1._y:=0]
463205 e.e.x_ack_arb[0].buf1._y : 0 [by e.e._x_temp[0].a:=1]
488653 e.x[0].a : 1 [by e.e.x_ack_arb[0].buf1._y:=0]
489010 e.e.x_encoder.ors_f[0].b._y : 0 [by e.x[0].a:=1]
494123 e.e.vtree_y.ct.in[0] : 1 [by e.e.vtree_y.OR2_tf[0]._y:=0]
494145 e.e.vtree_y.ct.b._y : 0 [by e.e.vtree_y.ct.in[0]:=1]
494154 e.e._in_y_v : 1 [by e.e.vtree_y.ct.b._y:=0]
515290 e.e.x_enc_out.d[0].f : 1 [by e.e.x_encoder.ors_f[0].b._y:=0]
515476 e.e.vtree_x.OR2_tf[0]._y : 0 [by e.e.x_enc_out.d[0].f:=1]
523146 e.e.vtree_x.ct.in[0] : 1 [by e.e.vtree_x.OR2_tf[0]._y:=0]
523151 e.e.vtree_x.ct.b._y : 0 [by e.e.vtree_x.ct.in[0]:=1]
523449 e.e._in_x_v : 1 [by e.e.vtree_x.ct.b._y:=0]
531696 e.e._in_xy_v._y : 0 [by e.e._in_x_v:=1]
531697 e.e._in_xy_v.y : 1 [by e.e._in_xy_v._y:=0]
531900 e.e.buf_s_func.in_v_prebuf._y : 0 [by e.e._in_xy_v.y:=1]
531901 e.e.buf_s_func._in_vX : 1 [by e.e.buf_s_func.in_v_prebuf._y:=0]
531926 e.e.buf_s_func.in_v_buf_t.buf1._y : 0 [by e.e.buf_s_func._in_vX:=1]
533933 e.e.buf_s_func._in_vXX_t[0] : 1 [by e.e.buf_s_func.in_v_buf_t.buf1._y:=0]
554229 e.e.buf_s_func.in_v_buf_f.buf1._y : 0 [by e.e.buf_s_func._in_vX:=1]
554230 e.e.buf_s_func._in_vXX_f[0] : 1 [by e.e.buf_s_func.in_v_buf_f.buf1._y:=0]
554243 e.e.buf_s_func.f_buf_func[1]._y : 0 [by e.e.buf_s_func._in_vXX_f[0]:=1]
554273 e.out.d.d[1].f : 1 [by e.e.buf_s_func.f_buf_func[1]._y:=0]
563252 e.e.buf_s_func.f_buf_func[0]._y : 0 [by e.e.buf_s_func._in_vXX_f[0]:=1]
563486 e.out.d.d[0].f : 1 [by e.e.buf_s_func.f_buf_func[0]._y:=0]
[] Check Arbiter Acks
[] Check Encoders
[] Check Buffer
[] Finish Neuron Handshake
563486 e.y[0].r : 0
563486 e.x[0].r : 0
563515 e.e.x_req_ortree.or2s[0]._y : 1 [by e.x[0].r:=0]
563516 e.e._x_v : 0 [by e.e.x_req_ortree.or2s[0]._y:=1]
563536 e.e.Yarb.arbs[0].arbiter._y1 : 1 [by e.y[0].r:=0]
563566 e.e.Xarb.arbs[0].arbiter._y1 : 1 [by e.x[0].r:=0]
563915 e.e.Xarb.arbs[0]._y1_arb : 0 [by e.e.Xarb.arbs[0].arbiter._y1:=1]
565505 e.e.Yarb.arbs[0]._y1_arb : 0 [by e.e.Yarb.arbs[0].arbiter._y1:=1]
567529 e.e.Yarb.arbs[0].or_cell._y : 1 [by e.e.Yarb.arbs[0]._y1_arb:=0]
567530 e.e._arb_out_y.r : 0 [by e.e.Yarb.arbs[0].or_cell._y:=1]
582131 e.e._x_v_B : 1 [by e.e._x_v:=0]
586219 e.e.Xarb.arbs[0].or_cell._y : 1 [by e.e.Xarb.arbs[0]._y1_arb:=0]
586223 e.e._arb_out_x.r : 0 [by e.e.Xarb.arbs[0].or_cell._y:=1]
586223 e.out.a : 1
586223 e.out.v : 1
586224 e.e.buf_s_func._out_a_B : 0 [by e.out.a:=1]
586229 e.e.buf_s_func.out_a_B_buf_t.buf1._y : 1 [by e.e.buf_s_func._out_a_B:=0]
586326 e.e._x_a_B : 0 [by e.out.v:=1]
586363 e.e.X_ack_confirm._y : 1 [by e.e._x_a_B:=0]
586365 e.e._arb_out_x.a : 0 [by e.e.X_ack_confirm._y:=1]
586367 e.e.Xarb.arbs[0].ack_cell1._y : 1 [by e.e._arb_out_x.a:=0]
586429 e.e._x_temp[0].a : 0 [by e.e.Xarb.arbs[0].ack_cell1._y:=1]
586457 e.e.buf_s_func._out_a_BX_f[0] : 0 [by e.e.buf_s_func.out_a_B_buf_t.buf1._y:=1]
586493 e.e.x_ack_arb[0].buf1._y : 1 [by e.e._x_temp[0].a:=0]
589727 e.x[0].a : 0 [by e.e.x_ack_arb[0].buf1._y:=1]
589728 e.e.x_encoder.ors_f[0].b._y : 1 [by e.x[0].a:=0]
589796 e.e.x_enc_out.d[0].f : 0 [by e.e.x_encoder.ors_f[0].b._y:=1]
590025 e.e.vtree_x.OR2_tf[0]._y : 1 [by e.e.x_enc_out.d[0].f:=0]
590319 e.e._x_a : 1 [by e.e._x_a_B:=0]
590320 e.e._en : 0 [by e.e._x_a:=1]
590322 e.e.buf_s_func.en_buf_t.buf1._y : 1 [by e.e._en:=0]
590445 e.e.buf_s_func.out_a_B_buf_f.buf1._y : 1 [by e.e.buf_s_func._out_a_B:=0]
590452 e.e.buf_s_func._out_a_BX_t[0] : 0 [by e.e.buf_s_func.out_a_B_buf_f.buf1._y:=1]
599706 e.e.vtree_x.ct.in[0] : 0 [by e.e.vtree_x.OR2_tf[0]._y:=1]
602847 e.e.vtree_x.ct.b._y : 1 [by e.e.vtree_x.ct.in[0]:=0]
616394 e.e._in_x_v : 0 [by e.e.vtree_x.ct.b._y:=1]
616396 e.e._in_xy_v._y : 1 [by e.e._in_x_v:=0]
616922 e.e._in_xy_v.y : 0 [by e.e._in_xy_v._y:=1]
618520 e.e.buf_s_func.en_buf_f.buf1._y : 1 [by e.e._en:=0]
618610 e.e.buf_s_func._en_X_f[0] : 0 [by e.e.buf_s_func.en_buf_f.buf1._y:=1]
618614 e.e.buf_s_func.f_buf_func[1]._y : 1 [by e.e.buf_s_func._en_X_f[0]:=0]
623363 e.e.buf_s_func._en_X_t[0] : 0 [by e.e.buf_s_func.en_buf_t.buf1._y:=1]
624924 e.e.buf_s_func.in_v_prebuf._y : 1 [by e.e._in_xy_v.y:=0]
625043 e.e.buf_s_func._in_vX : 0 [by e.e.buf_s_func.in_v_prebuf._y:=1]
625057 e.e.buf_s_func.in_v_buf_f.buf1._y : 1 [by e.e.buf_s_func._in_vX:=0]
625800 e.e.buf_s_func._in_vXX_f[0] : 0 [by e.e.buf_s_func.in_v_buf_f.buf1._y:=1]
627134 e.out.d.d[1].f : 0 [by e.e.buf_s_func.f_buf_func[1]._y:=1]
627372 e.e.Y_ack_confirm._y : 1 [by e.e._in_x_v:=0]
628660 e.e._arb_out_y.a : 0 [by e.e.Y_ack_confirm._y:=1]
629508 e.e.Yarb.arbs[0].ack_cell1._y : 1 [by e.e._arb_out_y.a:=0]
629750 e.e._y_temp[0].a : 0 [by e.e.Yarb.arbs[0].ack_cell1._y:=1]
629778 e.e.y_ack_arb[0].buf1._y : 1 [by e.e._y_temp[0].a:=0]
634136 e.y[0].a : 0 [by e.e.y_ack_arb[0].buf1._y:=1]
635046 e.e.buf_s_func.in_v_buf_t.buf1._y : 1 [by e.e.buf_s_func._in_vX:=0]
635201 e.e.buf_s_func._in_vXX_t[0] : 0 [by e.e.buf_s_func.in_v_buf_t.buf1._y:=1]
643929 e.e.y_encoder.ors_f[0].b._y : 1 [by e.y[0].a:=0]
644056 e.e.y_enc_out.d[0].f : 0 [by e.e.y_encoder.ors_f[0].b._y:=1]
650472 e.e.buf_s_func.f_buf_func[0]._y : 1 [by e.e.buf_s_func._en_X_f[0]:=0]
650474 e.out.d.d[0].f : 0 [by e.e.buf_s_func.f_buf_func[0]._y:=1]
665066 e.e.vtree_y.OR2_tf[0]._y : 1 [by e.e.y_enc_out.d[0].f:=0]
665067 e.e.vtree_y.ct.in[0] : 0 [by e.e.vtree_y.OR2_tf[0]._y:=1]
670826 e.e.vtree_y.ct.b._y : 1 [by e.e.vtree_y.ct.in[0]:=0]
734592 e.e._in_y_v : 0 [by e.e.vtree_y.ct.b._y:=1]
734989 e.e._x_a_B : 1 [by e.e._in_y_v:=0]
737310 e.e._x_a : 0 [by e.e._x_a_B:=1]
737310 e.out.a : 0
737310 e.out.v : 0
737380 e.e._en : 1 [by e.out.v:=0]
737381 e.e.buf_s_func.en_buf_f.buf1._y : 0 [by e.e._en:=1]
737388 e.e.buf_s_func._en_X_f[0] : 1 [by e.e.buf_s_func.en_buf_f.buf1._y:=0]
737814 e.e.buf_s_func._out_a_B : 1 [by e.out.a:=0]
749082 e.e.buf_s_func.out_a_B_buf_t.buf1._y : 0 [by e.e.buf_s_func._out_a_B:=1]
749115 e.e.buf_s_func._out_a_BX_f[0] : 1 [by e.e.buf_s_func.out_a_B_buf_t.buf1._y:=0]
767327 e.e.buf_s_func.en_buf_t.buf1._y : 0 [by e.e._en:=1]
767330 e.e.buf_s_func._en_X_t[0] : 1 [by e.e.buf_s_func.en_buf_t.buf1._y:=0]
784477 e.e.buf_s_func.out_a_B_buf_f.buf1._y : 0 [by e.e.buf_s_func._out_a_B:=1]
784500 e.e.buf_s_func._out_a_BX_t[0] : 1 [by e.e.buf_s_func.out_a_B_buf_f.buf1._y:=0]
[] Neuron (0,0) Encoded
[] Single Neuron Spikes (1,1)
784500 e.y[1].r : 1
784500 e.x[1].r : 1
784501 e.e.x_req_ortree.or2s[0]._y : 0 [by e.x[1].r:=1]
784521 e.e.Xarb.arbs[0].arbiter._y2 : 0 [by e.x[1].r:=1]
788853 e.e._x_v : 1 [by e.e.x_req_ortree.or2s[0]._y:=0]
792400 e.e.Xarb.arbs[0]._y2_arb : 1 [by e.e.Xarb.arbs[0].arbiter._y2:=0]
803719 e.e._x_v_B : 0 [by e.e._x_v:=1]
808636 e.e.Yarb.arbs[0].arbiter._y2 : 0 [by e.y[1].r:=1]
808667 e.e.Yarb.arbs[0]._y2_arb : 1 [by e.e.Yarb.arbs[0].arbiter._y2:=0]
808845 e.e.Yarb.arbs[0].or_cell._y : 0 [by e.e.Yarb.arbs[0]._y2_arb:=1]
808858 e.e._arb_out_y.r : 1 [by e.e.Yarb.arbs[0].or_cell._y:=0]
818105 e.e.Y_ack_confirm._y : 0 [by e.e._arb_out_y.r:=1]
818876 e.e._arb_out_y.a : 1 [by e.e.Y_ack_confirm._y:=0]
822694 e.e.Yarb.arbs[0].ack_cell2._y : 0 [by e.e._arb_out_y.a:=1]
822730 e.e._y_temp[1].a : 1 [by e.e.Yarb.arbs[0].ack_cell2._y:=0]
822731 e.e.y_ack_arb[1].buf1._y : 0 [by e.e._y_temp[1].a:=1]
841269 e.e.Xarb.arbs[0].or_cell._y : 0 [by e.e.Xarb.arbs[0]._y2_arb:=1]
850480 e.e._arb_out_x.r : 1 [by e.e.Xarb.arbs[0].or_cell._y:=0]
850824 e.e.X_ack_confirm._y : 0 [by e.e._arb_out_x.r:=1]
850854 e.e._arb_out_x.a : 1 [by e.e.X_ack_confirm._y:=0]
852159 e.e.Xarb.arbs[0].ack_cell2._y : 0 [by e.e._arb_out_x.a:=1]
852509 e.e._x_temp[1].a : 1 [by e.e.Xarb.arbs[0].ack_cell2._y:=0]
858620 e.e.x_ack_arb[1].buf1._y : 0 [by e.e._x_temp[1].a:=1]
860849 e.y[1].a : 1 [by e.e.y_ack_arb[1].buf1._y:=0]
861151 e.e.y_encoder.ors_t[0].b._y : 0 [by e.y[1].a:=1]
869979 e.e.y_enc_out.d[0].t : 1 [by e.e.y_encoder.ors_t[0].b._y:=0]
869987 e.e.vtree_y.OR2_tf[0]._y : 0 [by e.e.y_enc_out.d[0].t:=1]
870119 e.e.vtree_y.ct.in[0] : 1 [by e.e.vtree_y.OR2_tf[0]._y:=0]
874552 e.e.vtree_y.ct.b._y : 0 [by e.e.vtree_y.ct.in[0]:=1]
878673 e.e._in_y_v : 1 [by e.e.vtree_y.ct.b._y:=0]
897313 e.x[1].a : 1 [by e.e.x_ack_arb[1].buf1._y:=0]
908590 e.e.x_encoder.ors_t[0].b._y : 0 [by e.x[1].a:=1]
908604 e.e.x_enc_out.d[0].t : 1 [by e.e.x_encoder.ors_t[0].b._y:=0]
908614 e.e.vtree_x.OR2_tf[0]._y : 0 [by e.e.x_enc_out.d[0].t:=1]
908615 e.e.vtree_x.ct.in[0] : 1 [by e.e.vtree_x.OR2_tf[0]._y:=0]
909459 e.e.vtree_x.ct.b._y : 0 [by e.e.vtree_x.ct.in[0]:=1]
912160 e.e._in_x_v : 1 [by e.e.vtree_x.ct.b._y:=0]
927845 e.e._in_xy_v._y : 0 [by e.e._in_x_v:=1]
927855 e.e._in_xy_v.y : 1 [by e.e._in_xy_v._y:=0]
927856 e.e.buf_s_func.in_v_prebuf._y : 0 [by e.e._in_xy_v.y:=1]
929754 e.e.buf_s_func._in_vX : 1 [by e.e.buf_s_func.in_v_prebuf._y:=0]
929759 e.e.buf_s_func.in_v_buf_t.buf1._y : 0 [by e.e.buf_s_func._in_vX:=1]
929782 e.e.buf_s_func._in_vXX_t[0] : 1 [by e.e.buf_s_func.in_v_buf_t.buf1._y:=0]
929785 e.e.buf_s_func.t_buf_func[0]._y : 0 [by e.e.buf_s_func._in_vXX_t[0]:=1]
929801 e.e.buf_s_func.t_buf_func[1]._y : 0 [by e.e.buf_s_func._in_vXX_t[0]:=1]
929904 e.e.buf_s_func.in_v_buf_f.buf1._y : 0 [by e.e.buf_s_func._in_vX:=1]
931135 e.out.d.d[0].t : 1 [by e.e.buf_s_func.t_buf_func[0]._y:=0]
932725 e.out.d.d[1].t : 1 [by e.e.buf_s_func.t_buf_func[1]._y:=0]
989049 e.e.buf_s_func._in_vXX_f[0] : 1 [by e.e.buf_s_func.in_v_buf_f.buf1._y:=0]
[] Check Arbiter Acks
[] Check Encoders
[] Check Buffer
[] Finish Neuron Handshake
989049 e.y[1].r : 0
989049 e.x[1].r : 0
989053 e.e.x_req_ortree.or2s[0]._y : 1 [by e.x[1].r:=0]
989230 e.e.Xarb.arbs[0].arbiter._y2 : 1 [by e.x[1].r:=0]
989261 e.e.Xarb.arbs[0]._y2_arb : 0 [by e.e.Xarb.arbs[0].arbiter._y2:=1]
989342 e.e.Xarb.arbs[0].or_cell._y : 1 [by e.e.Xarb.arbs[0]._y2_arb:=0]
989343 e.e._arb_out_x.r : 0 [by e.e.Xarb.arbs[0].or_cell._y:=1]
989427 e.e.Yarb.arbs[0].arbiter._y2 : 1 [by e.y[1].r:=0]
993056 e.e.Yarb.arbs[0]._y2_arb : 0 [by e.e.Yarb.arbs[0].arbiter._y2:=1]
993677 e.e.Yarb.arbs[0].or_cell._y : 1 [by e.e.Yarb.arbs[0]._y2_arb:=0]
1000029 e.e._x_v : 0 [by e.e.x_req_ortree.or2s[0]._y:=1]
1000075 e.e._x_v_B : 1 [by e.e._x_v:=0]
1004028 e.e._arb_out_y.r : 0 [by e.e.Yarb.arbs[0].or_cell._y:=1]
1004028 e.out.a : 1
1004028 e.out.v : 1
1004078 e.e._x_a_B : 0 [by e.out.v:=1]
1004079 e.e.X_ack_confirm._y : 1 [by e.e._x_a_B:=0]
1004208 e.e._x_a : 1 [by e.e._x_a_B:=0]
1005641 e.e.buf_s_func._out_a_B : 0 [by e.out.a:=1]
1005645 e.e.buf_s_func.out_a_B_buf_f.buf1._y : 1 [by e.e.buf_s_func._out_a_B:=0]
1006742 e.e._en : 0 [by e.e._x_a:=1]
1006748 e.e.buf_s_func.en_buf_f.buf1._y : 1 [by e.e._en:=0]
1006749 e.e.buf_s_func._en_X_f[0] : 0 [by e.e.buf_s_func.en_buf_f.buf1._y:=1]
1006755 e.e._arb_out_x.a : 0 [by e.e.X_ack_confirm._y:=1]
1006791 e.e.buf_s_func.out_a_B_buf_t.buf1._y : 1 [by e.e.buf_s_func._out_a_B:=0]
1008619 e.e.buf_s_func.en_buf_t.buf1._y : 1 [by e.e._en:=0]
1010085 e.e.buf_s_func._out_a_BX_f[0] : 0 [by e.e.buf_s_func.out_a_B_buf_t.buf1._y:=1]
1010672 e.e.buf_s_func._en_X_t[0] : 0 [by e.e.buf_s_func.en_buf_t.buf1._y:=1]
1021976 e.e.Xarb.arbs[0].ack_cell2._y : 1 [by e.e._arb_out_x.a:=0]
1022037 e.e._x_temp[1].a : 0 [by e.e.Xarb.arbs[0].ack_cell2._y:=1]
1022097 e.e.x_ack_arb[1].buf1._y : 1 [by e.e._x_temp[1].a:=0]
1023667 e.x[1].a : 0 [by e.e.x_ack_arb[1].buf1._y:=1]
1042073 e.e.x_encoder.ors_t[0].b._y : 1 [by e.x[1].a:=0]
1042741 e.e.x_enc_out.d[0].t : 0 [by e.e.x_encoder.ors_t[0].b._y:=1]
1042797 e.e.vtree_x.OR2_tf[0]._y : 1 [by e.e.x_enc_out.d[0].t:=0]
1042886 e.e.vtree_x.ct.in[0] : 0 [by e.e.vtree_x.OR2_tf[0]._y:=1]
1042887 e.e.vtree_x.ct.b._y : 1 [by e.e.vtree_x.ct.in[0]:=0]
1042888 e.e._in_x_v : 0 [by e.e.vtree_x.ct.b._y:=1]
1042960 e.e._in_xy_v._y : 1 [by e.e._in_x_v:=0]
1043249 e.e.Y_ack_confirm._y : 1 [by e.e._in_x_v:=0]
1043260 e.e._arb_out_y.a : 0 [by e.e.Y_ack_confirm._y:=1]
1043261 e.e.Yarb.arbs[0].ack_cell2._y : 1 [by e.e._arb_out_y.a:=0]
1043316 e.e._in_xy_v.y : 0 [by e.e._in_xy_v._y:=1]
1043390 e.e._y_temp[1].a : 0 [by e.e.Yarb.arbs[0].ack_cell2._y:=1]
1043399 e.e.y_ack_arb[1].buf1._y : 1 [by e.e._y_temp[1].a:=0]
1046479 e.e.buf_s_func.in_v_prebuf._y : 1 [by e.e._in_xy_v.y:=0]
1046484 e.e.buf_s_func._in_vX : 0 [by e.e.buf_s_func.in_v_prebuf._y:=1]
1046493 e.e.buf_s_func.in_v_buf_t.buf1._y : 1 [by e.e.buf_s_func._in_vX:=0]
1046589 e.e.buf_s_func._out_a_BX_t[0] : 0 [by e.e.buf_s_func.out_a_B_buf_f.buf1._y:=1]
1046662 e.e.buf_s_func._in_vXX_t[0] : 0 [by e.e.buf_s_func.in_v_buf_t.buf1._y:=1]
1046846 e.e.buf_s_func.t_buf_func[1]._y : 1 [by e.e.buf_s_func._out_a_BX_t[0]:=0]
1046847 e.out.d.d[1].t : 0 [by e.e.buf_s_func.t_buf_func[1]._y:=1]
1047071 e.e.buf_s_func.in_v_buf_f.buf1._y : 1 [by e.e.buf_s_func._in_vX:=0]
1047108 e.e.buf_s_func._in_vXX_f[0] : 0 [by e.e.buf_s_func.in_v_buf_f.buf1._y:=1]
1047458 e.y[1].a : 0 [by e.e.y_ack_arb[1].buf1._y:=1]
1047574 e.e.y_encoder.ors_t[0].b._y : 1 [by e.y[1].a:=0]
1048525 e.e.y_enc_out.d[0].t : 0 [by e.e.y_encoder.ors_t[0].b._y:=1]
1048526 e.e.vtree_y.OR2_tf[0]._y : 1 [by e.e.y_enc_out.d[0].t:=0]
1048792 e.e.vtree_y.ct.in[0] : 0 [by e.e.vtree_y.OR2_tf[0]._y:=1]
1051657 e.e.buf_s_func.t_buf_func[0]._y : 1 [by e.e.buf_s_func._out_a_BX_t[0]:=0]
1054257 e.out.d.d[0].t : 0 [by e.e.buf_s_func.t_buf_func[0]._y:=1]
1110617 e.e.vtree_y.ct.b._y : 1 [by e.e.vtree_y.ct.in[0]:=0]
1110618 e.e._in_y_v : 0 [by e.e.vtree_y.ct.b._y:=1]
1112139 e.e._x_a_B : 1 [by e.e._in_y_v:=0]
1114785 e.e._x_a : 0 [by e.e._x_a_B:=1]
1114785 e.out.a : 0
1114785 e.out.v : 0
1115291 e.e._en : 1 [by e.out.v:=0]
1116226 e.e.buf_s_func.en_buf_f.buf1._y : 0 [by e.e._en:=1]
1120661 e.e.buf_s_func._out_a_B : 1 [by e.out.a:=0]
1120761 e.e.buf_s_func.out_a_B_buf_t.buf1._y : 0 [by e.e.buf_s_func._out_a_B:=1]
1124929 e.e.buf_s_func._out_a_BX_f[0] : 1 [by e.e.buf_s_func.out_a_B_buf_t.buf1._y:=0]
1127979 e.e.buf_s_func.en_buf_t.buf1._y : 0 [by e.e._en:=1]
1127981 e.e.buf_s_func._en_X_t[0] : 1 [by e.e.buf_s_func.en_buf_t.buf1._y:=0]
1132851 e.e.buf_s_func._en_X_f[0] : 1 [by e.e.buf_s_func.en_buf_f.buf1._y:=0]
1182244 e.e.buf_s_func.out_a_B_buf_f.buf1._y : 0 [by e.e.buf_s_func._out_a_B:=1]
1183241 e.e.buf_s_func._out_a_BX_t[0] : 1 [by e.e.buf_s_func.out_a_B_buf_f.buf1._y:=0]
[] Neuron (1,1) Encoded
[] Neuron Spikes (0,0), (1,0)
1183241 e.x[0].r : 1
1183241 e.x[1].r : 1
1183241 e.y[0].r : 1
1183243 e.e.Yarb.arbs[0].arbiter._y1 : 0 [by e.y[0].r:=1]
1187978 e.e.x_req_ortree.or2s[0]._y : 0 [by e.x[0].r:=1]
1188075 e.e._x_v : 1 [by e.e.x_req_ortree.or2s[0]._y:=0]
1188141 e.e._x_v_B : 0 [by e.e._x_v:=1]
1196259 e.e.Xarb.arbs[0].arbiter._y1 : 0 [by e.x[0].r:=1]
1196260 e.e.Xarb.arbs[0]._y1_arb : 1 [by e.e.Xarb.arbs[0].arbiter._y1:=0]
1196407 e.e.Xarb.arbs[0].or_cell._y : 0 [by e.e.Xarb.arbs[0]._y1_arb:=1]
1202758 e.e._arb_out_x.r : 1 [by e.e.Xarb.arbs[0].or_cell._y:=0]
1202769 e.e.X_ack_confirm._y : 0 [by e.e._arb_out_x.r:=1]
1205050 e.e._arb_out_x.a : 1 [by e.e.X_ack_confirm._y:=0]
1205122 e.e.Xarb.arbs[0].ack_cell1._y : 0 [by e.e._arb_out_x.a:=1]
1205136 e.e._x_temp[0].a : 1 [by e.e.Xarb.arbs[0].ack_cell1._y:=0]
1205148 e.e.x_ack_arb[0].buf1._y : 0 [by e.e._x_temp[0].a:=1]
1217465 e.x[0].a : 1 [by e.e.x_ack_arb[0].buf1._y:=0]
1239712 e.e.x_encoder.ors_f[0].b._y : 0 [by e.x[0].a:=1]
1243805 e.e.Yarb.arbs[0]._y1_arb : 1 [by e.e.Yarb.arbs[0].arbiter._y1:=0]
1244705 e.e.Yarb.arbs[0].or_cell._y : 0 [by e.e.Yarb.arbs[0]._y1_arb:=1]
1246272 e.e._arb_out_y.r : 1 [by e.e.Yarb.arbs[0].or_cell._y:=0]
1247160 e.e.x_enc_out.d[0].f : 1 [by e.e.x_encoder.ors_f[0].b._y:=0]
1247310 e.e.vtree_x.OR2_tf[0]._y : 0 [by e.e.x_enc_out.d[0].f:=1]
1249875 e.e.Y_ack_confirm._y : 0 [by e.e._arb_out_y.r:=1]
1250000 e.e._arb_out_y.a : 1 [by e.e.Y_ack_confirm._y:=0]
1250005 e.e.Yarb.arbs[0].ack_cell1._y : 0 [by e.e._arb_out_y.a:=1]
1250024 e.e._y_temp[0].a : 1 [by e.e.Yarb.arbs[0].ack_cell1._y:=0]
1250197 e.e.y_ack_arb[0].buf1._y : 0 [by e.e._y_temp[0].a:=1]
1277800 e.e.vtree_x.ct.in[0] : 1 [by e.e.vtree_x.OR2_tf[0]._y:=0]
1277859 e.e.vtree_x.ct.b._y : 0 [by e.e.vtree_x.ct.in[0]:=1]
1278700 e.e._in_x_v : 1 [by e.e.vtree_x.ct.b._y:=0]
1290184 e.y[0].a : 1 [by e.e.y_ack_arb[0].buf1._y:=0]
1290553 e.e.y_encoder.ors_f[0].b._y : 0 [by e.y[0].a:=1]
1355853 e.e.y_enc_out.d[0].f : 1 [by e.e.y_encoder.ors_f[0].b._y:=0]
1356441 e.e.vtree_y.OR2_tf[0]._y : 0 [by e.e.y_enc_out.d[0].f:=1]
1356912 e.e.vtree_y.ct.in[0] : 1 [by e.e.vtree_y.OR2_tf[0]._y:=0]
1357181 e.e.vtree_y.ct.b._y : 0 [by e.e.vtree_y.ct.in[0]:=1]
1357582 e.e._in_y_v : 1 [by e.e.vtree_y.ct.b._y:=0]
1357649 e.e._in_xy_v._y : 0 [by e.e._in_y_v:=1]
1360731 e.e._in_xy_v.y : 1 [by e.e._in_xy_v._y:=0]
1364009 e.e.buf_s_func.in_v_prebuf._y : 0 [by e.e._in_xy_v.y:=1]
1364011 e.e.buf_s_func._in_vX : 1 [by e.e.buf_s_func.in_v_prebuf._y:=0]
1365213 e.e.buf_s_func.in_v_buf_t.buf1._y : 0 [by e.e.buf_s_func._in_vX:=1]
1365236 e.e.buf_s_func._in_vXX_t[0] : 1 [by e.e.buf_s_func.in_v_buf_t.buf1._y:=0]
1382466 e.e.buf_s_func.in_v_buf_f.buf1._y : 0 [by e.e.buf_s_func._in_vX:=1]
1382505 e.e.buf_s_func._in_vXX_f[0] : 1 [by e.e.buf_s_func.in_v_buf_f.buf1._y:=0]
1392997 e.e.buf_s_func.f_buf_func[0]._y : 0 [by e.e.buf_s_func._in_vXX_f[0]:=1]
1396403 e.e.buf_s_func.f_buf_func[1]._y : 0 [by e.e.buf_s_func._in_vXX_f[0]:=1]
1396419 e.out.d.d[1].f : 1 [by e.e.buf_s_func.f_buf_func[1]._y:=0]
1408426 e.out.d.d[0].f : 1 [by e.e.buf_s_func.f_buf_func[0]._y:=0]
[] Check Arbiter Acks (0,0)
[] Check Encoders
[] Check Buffer
[] Finish Neuron Handshake (0,0)
1408426 e.x[0].r : 0
1424214 e.e.Xarb.arbs[0].arbiter._y1 : 1 [by e.x[0].r:=0]
1424216 e.e.Xarb.arbs[0].arbiter._y2 : 0 [by e.e.Xarb.arbs[0].arbiter._y1:=1]
1424221 e.e.Xarb.arbs[0]._y1_arb : 0 [by e.e.Xarb.arbs[0].arbiter._y1:=1]
1424249 e.e.Xarb.arbs[0].or_cell._y : 1 [by e.e.Xarb.arbs[0]._y1_arb:=0]
1437982 e.e._arb_out_x.r : 0 [by e.e.Xarb.arbs[0].or_cell._y:=1]
1437982 e.out.a : 1
1437982 e.out.v : 1
1439757 e.e._x_a_B : 0 [by e.out.v:=1]
1439759 e.e.X_ack_confirm._y : 1 [by e.e._x_a_B:=0]
1439769 e.e._arb_out_x.a : 0 [by e.e.X_ack_confirm._y:=1]
1444804 e.e.buf_s_func._out_a_B : 0 [by e.out.a:=1]
1444826 e.e.buf_s_func.out_a_B_buf_f.buf1._y : 1 [by e.e.buf_s_func._out_a_B:=0]
1444842 e.e.buf_s_func._out_a_BX_t[0] : 0 [by e.e.buf_s_func.out_a_B_buf_f.buf1._y:=1]
1461429 e.e._x_a : 1 [by e.e._x_a_B:=0]
1462134 e.e.buf_s_func.out_a_B_buf_t.buf1._y : 1 [by e.e.buf_s_func._out_a_B:=0]
1465425 e.e.Xarb.arbs[0].ack_cell1._y : 1 [by e.e._arb_out_x.a:=0]
1466607 e.e._en : 0 [by e.e._x_a:=1]
1466691 e.e._x_temp[0].a : 0 [by e.e.Xarb.arbs[0].ack_cell1._y:=1]
1466692 e.e.x_ack_arb[0].buf1._y : 1 [by e.e._x_temp[0].a:=0]
1466750 e.e.Xarb.arbs[0]._y2_arb : 1 [by e.e._x_temp[0].a:=0]
1466777 e.e.Xarb.arbs[0].or_cell._y : 0 [by e.e.Xarb.arbs[0]._y2_arb:=1]
1466793 e.x[0].a : 0 [by e.e.x_ack_arb[0].buf1._y:=1]
1468582 e.e.buf_s_func.en_buf_f.buf1._y : 1 [by e.e._en:=0]
1468583 e.e.buf_s_func._en_X_f[0] : 0 [by e.e.buf_s_func.en_buf_f.buf1._y:=1]
1469198 e.e.x_encoder.ors_f[0].b._y : 1 [by e.x[0].a:=0]
1475110 e.e.x_enc_out.d[0].f : 0 [by e.e.x_encoder.ors_f[0].b._y:=1]
1476279 e.e.buf_s_func._out_a_BX_f[0] : 0 [by e.e.buf_s_func.out_a_B_buf_t.buf1._y:=1]
1477549 e.e.vtree_x.OR2_tf[0]._y : 1 [by e.e.x_enc_out.d[0].f:=0]
1478015 e.e.buf_s_func.f_buf_func[0]._y : 1 [by e.e.buf_s_func._out_a_BX_f[0]:=0]
1478349 e.out.d.d[0].f : 0 [by e.e.buf_s_func.f_buf_func[0]._y:=1]
1484495 e.e.buf_s_func.en_buf_t.buf1._y : 1 [by e.e._en:=0]
1484501 e.e.buf_s_func._en_X_t[0] : 0 [by e.e.buf_s_func.en_buf_t.buf1._y:=1]
1491868 e.e.buf_s_func.f_buf_func[1]._y : 1 [by e.e.buf_s_func._out_a_BX_f[0]:=0]
1492991 e.e.vtree_x.ct.in[0] : 0 [by e.e.vtree_x.OR2_tf[0]._y:=1]
1494228 e.e.vtree_x.ct.b._y : 1 [by e.e.vtree_x.ct.in[0]:=0]
1494305 e.e._in_x_v : 0 [by e.e.vtree_x.ct.b._y:=1]
1494315 e.e._x_a_B : 1 [by e.e._in_x_v:=0]
1494446 e.e._in_xy_v._y : 1 [by e.e._in_x_v:=0]
1494447 e.e._in_xy_v.y : 0 [by e.e._in_xy_v._y:=1]
1499774 e.e.buf_s_func.in_v_prebuf._y : 1 [by e.e._in_xy_v.y:=0]
1499775 e.e.buf_s_func._in_vX : 0 [by e.e.buf_s_func.in_v_prebuf._y:=1]
1499776 e.e.buf_s_func.in_v_buf_f.buf1._y : 1 [by e.e.buf_s_func._in_vX:=0]
1499797 e.e.buf_s_func._in_vXX_f[0] : 0 [by e.e.buf_s_func.in_v_buf_f.buf1._y:=1]
1503641 e.e.buf_s_func.in_v_buf_t.buf1._y : 1 [by e.e.buf_s_func._in_vX:=0]
1503971 e.e.buf_s_func._in_vXX_t[0] : 0 [by e.e.buf_s_func.in_v_buf_t.buf1._y:=1]
1509570 e.e._x_a : 0 [by e.e._x_a_B:=1]
1519547 e.e._arb_out_x.r : 1 [by e.e.Xarb.arbs[0].or_cell._y:=0]
1544566 e.out.d.d[1].f : 0 [by e.e.buf_s_func.f_buf_func[1]._y:=1]
1566419 e.e.X_ack_confirm._y : 0 [by e.e._arb_out_x.r:=1]
1566421 e.e._arb_out_x.a : 1 [by e.e.X_ack_confirm._y:=0]
1575291 e.e.Xarb.arbs[0].ack_cell2._y : 0 [by e.e._arb_out_x.a:=1]
1575474 e.e._x_temp[1].a : 1 [by e.e.Xarb.arbs[0].ack_cell2._y:=0]
1604634 e.e.x_ack_arb[1].buf1._y : 0 [by e.e._x_temp[1].a:=1]
1617744 e.x[1].a : 1 [by e.e.x_ack_arb[1].buf1._y:=0]
1617856 e.e.x_encoder.ors_t[0].b._y : 0 [by e.x[1].a:=1]
1649639 e.e.x_enc_out.d[0].t : 1 [by e.e.x_encoder.ors_t[0].b._y:=0]
1649711 e.e.vtree_x.OR2_tf[0]._y : 0 [by e.e.x_enc_out.d[0].t:=1]
1650819 e.e.vtree_x.ct.in[0] : 1 [by e.e.vtree_x.OR2_tf[0]._y:=0]
1674016 e.e.vtree_x.ct.b._y : 0 [by e.e.vtree_x.ct.in[0]:=1]
1674020 e.e._in_x_v : 1 [by e.e.vtree_x.ct.b._y:=0]
1674419 e.e._in_xy_v._y : 0 [by e.e._in_x_v:=1]
1674462 e.e._in_xy_v.y : 1 [by e.e._in_xy_v._y:=0]
1688288 e.e.buf_s_func.in_v_prebuf._y : 0 [by e.e._in_xy_v.y:=1]
1688289 e.e.buf_s_func._in_vX : 1 [by e.e.buf_s_func.in_v_prebuf._y:=0]
1688308 e.e.buf_s_func.in_v_buf_t.buf1._y : 0 [by e.e.buf_s_func._in_vX:=1]
1696423 e.e.buf_s_func.in_v_buf_f.buf1._y : 0 [by e.e.buf_s_func._in_vX:=1]
1701517 e.e.buf_s_func._in_vXX_t[0] : 1 [by e.e.buf_s_func.in_v_buf_t.buf1._y:=0]
1711988 e.e.buf_s_func._in_vXX_f[0] : 1 [by e.e.buf_s_func.in_v_buf_f.buf1._y:=0]
1711988 e.out.a : 0
1711988 e.out.v : 0
1712363 e.e._en : 1 [by e.out.v:=0]
1712389 e.e.buf_s_func._out_a_B : 1 [by e.out.a:=0]
1712390 e.e.buf_s_func.out_a_B_buf_t.buf1._y : 0 [by e.e.buf_s_func._out_a_B:=1]
1712471 e.e.buf_s_func.en_buf_t.buf1._y : 0 [by e.e._en:=1]
1712697 e.e.buf_s_func.en_buf_f.buf1._y : 0 [by e.e._en:=1]
1712722 e.e.buf_s_func._en_X_t[0] : 1 [by e.e.buf_s_func.en_buf_t.buf1._y:=0]
1712856 e.e.buf_s_func.out_a_B_buf_f.buf1._y : 0 [by e.e.buf_s_func._out_a_B:=1]
1712875 e.e.buf_s_func._en_X_f[0] : 1 [by e.e.buf_s_func.en_buf_f.buf1._y:=0]
1713798 e.e.buf_s_func._out_a_BX_t[0] : 1 [by e.e.buf_s_func.out_a_B_buf_f.buf1._y:=0]
1713799 e.e.buf_s_func.t_buf_func[0]._y : 0 [by e.e.buf_s_func._out_a_BX_t[0]:=1]
1713800 e.out.d.d[0].t : 1 [by e.e.buf_s_func.t_buf_func[0]._y:=0]
1717122 e.e.buf_s_func._out_a_BX_f[0] : 1 [by e.e.buf_s_func.out_a_B_buf_t.buf1._y:=0]
1717342 e.e.buf_s_func.f_buf_func[1]._y : 0 [by e.e.buf_s_func._out_a_BX_f[0]:=1]
1717905 e.out.d.d[1].f : 1 [by e.e.buf_s_func.f_buf_func[1]._y:=0]
[] Neuron (0,0) Encoded
[] Check Neuron (1,0) Waiting
[] Check Arbiter Acks (1,0)
[] Check Encoders
[] Check Buffer
[] Finish Neuron Handshake (1,0)
1717905 e.x[1].r : 0
1717905 e.y[0].r : 0
1717983 e.e.x_req_ortree.or2s[0]._y : 1 [by e.x[1].r:=0]
1718134 e.e._x_v : 0 [by e.e.x_req_ortree.or2s[0]._y:=1]
1718234 e.e.Xarb.arbs[0].arbiter._y2 : 1 [by e.x[1].r:=0]
1718235 e.e.Xarb.arbs[0]._y2_arb : 0 [by e.e.Xarb.arbs[0].arbiter._y2:=1]
1718236 e.e.Xarb.arbs[0].or_cell._y : 1 [by e.e.Xarb.arbs[0]._y2_arb:=0]
1723161 e.e.Yarb.arbs[0].arbiter._y1 : 1 [by e.y[0].r:=0]
1723189 e.e.Yarb.arbs[0]._y1_arb : 0 [by e.e.Yarb.arbs[0].arbiter._y1:=1]
1723190 e.e.Yarb.arbs[0].or_cell._y : 1 [by e.e.Yarb.arbs[0]._y1_arb:=0]
1723463 e.e._arb_out_y.r : 0 [by e.e.Yarb.arbs[0].or_cell._y:=1]
1726003 e.e._x_v_B : 1 [by e.e._x_v:=0]
1727849 e.e._arb_out_x.r : 0 [by e.e.Xarb.arbs[0].or_cell._y:=1]
1727849 e.out.a : 1
1727849 e.out.v : 1
1727851 e.e._x_a_B : 0 [by e.out.v:=1]
1727852 e.e.X_ack_confirm._y : 1 [by e.e._x_a_B:=0]
1727857 e.e._arb_out_x.a : 0 [by e.e.X_ack_confirm._y:=1]
1727871 e.e.buf_s_func._out_a_B : 0 [by e.out.a:=1]
1727872 e.e.buf_s_func.out_a_B_buf_f.buf1._y : 1 [by e.e.buf_s_func._out_a_B:=0]
1728191 e.e.Xarb.arbs[0].ack_cell2._y : 1 [by e.e._arb_out_x.a:=0]
1728581 e.e._x_temp[1].a : 0 [by e.e.Xarb.arbs[0].ack_cell2._y:=1]
1728782 e.e.x_ack_arb[1].buf1._y : 1 [by e.e._x_temp[1].a:=0]
1729056 e.x[1].a : 0 [by e.e.x_ack_arb[1].buf1._y:=1]
1729082 e.e.x_encoder.ors_t[0].b._y : 1 [by e.x[1].a:=0]
1729178 e.e.x_enc_out.d[0].t : 0 [by e.e.x_encoder.ors_t[0].b._y:=1]
1729222 e.e.vtree_x.OR2_tf[0]._y : 1 [by e.e.x_enc_out.d[0].t:=0]
1729669 e.e.buf_s_func.out_a_B_buf_t.buf1._y : 1 [by e.e.buf_s_func._out_a_B:=0]
1740651 e.e.buf_s_func._out_a_BX_f[0] : 0 [by e.e.buf_s_func.out_a_B_buf_t.buf1._y:=1]
1743927 e.e.buf_s_func._out_a_BX_t[0] : 0 [by e.e.buf_s_func.out_a_B_buf_f.buf1._y:=1]
1744997 e.e.vtree_x.ct.in[0] : 0 [by e.e.vtree_x.OR2_tf[0]._y:=1]
1744999 e.e.vtree_x.ct.b._y : 1 [by e.e.vtree_x.ct.in[0]:=0]
1745006 e.e._in_x_v : 0 [by e.e.vtree_x.ct.b._y:=1]
1745115 e.e.Y_ack_confirm._y : 1 [by e.e._in_x_v:=0]
1745478 e.e._in_xy_v._y : 1 [by e.e._in_x_v:=0]
1745490 e.e._in_xy_v.y : 0 [by e.e._in_xy_v._y:=1]
1747869 e.e._arb_out_y.a : 0 [by e.e.Y_ack_confirm._y:=1]
1747896 e.e.Yarb.arbs[0].ack_cell1._y : 1 [by e.e._arb_out_y.a:=0]
1748176 e.e._y_temp[0].a : 0 [by e.e.Yarb.arbs[0].ack_cell1._y:=1]
1748177 e.e.y_ack_arb[0].buf1._y : 1 [by e.e._y_temp[0].a:=0]
1748212 e.y[0].a : 0 [by e.e.y_ack_arb[0].buf1._y:=1]
1748676 e.e.buf_s_func.in_v_prebuf._y : 1 [by e.e._in_xy_v.y:=0]
1781936 e.e._x_a : 1 [by e.e._x_a_B:=0]
1784614 e.e._en : 0 [by e.e._x_a:=1]
1784697 e.e.buf_s_func.en_buf_f.buf1._y : 1 [by e.e._en:=0]
1784698 e.e.buf_s_func._en_X_f[0] : 0 [by e.e.buf_s_func.en_buf_f.buf1._y:=1]
1787131 e.e.buf_s_func.f_buf_func[1]._y : 1 [by e.e.buf_s_func._en_X_f[0]:=0]
1788425 e.out.d.d[1].f : 0 [by e.e.buf_s_func.f_buf_func[1]._y:=1]
1810223 e.e.buf_s_func.en_buf_t.buf1._y : 1 [by e.e._en:=0]
1812632 e.e.y_encoder.ors_f[0].b._y : 1 [by e.y[0].a:=0]
1813810 e.e.buf_s_func._in_vX : 0 [by e.e.buf_s_func.in_v_prebuf._y:=1]
1814058 e.e.buf_s_func.in_v_buf_f.buf1._y : 1 [by e.e.buf_s_func._in_vX:=0]
1818030 e.e.buf_s_func.in_v_buf_t.buf1._y : 1 [by e.e.buf_s_func._in_vX:=0]
1818085 e.e.buf_s_func._in_vXX_t[0] : 0 [by e.e.buf_s_func.in_v_buf_t.buf1._y:=1]
1821686 e.e.y_enc_out.d[0].f : 0 [by e.e.y_encoder.ors_f[0].b._y:=1]
1821864 e.e.vtree_y.OR2_tf[0]._y : 1 [by e.e.y_enc_out.d[0].f:=0]
1821872 e.e.vtree_y.ct.in[0] : 0 [by e.e.vtree_y.OR2_tf[0]._y:=1]
1821905 e.e.vtree_y.ct.b._y : 1 [by e.e.vtree_y.ct.in[0]:=0]
1823077 e.e._in_y_v : 0 [by e.e.vtree_y.ct.b._y:=1]
1823101 e.e._x_a_B : 1 [by e.e._in_y_v:=0]
1839904 e.e._x_a : 0 [by e.e._x_a_B:=1]
1852952 e.e.buf_s_func._in_vXX_f[0] : 0 [by e.e.buf_s_func.in_v_buf_f.buf1._y:=1]
1855655 e.e.buf_s_func._en_X_t[0] : 0 [by e.e.buf_s_func.en_buf_t.buf1._y:=1]
1855985 e.e.buf_s_func.t_buf_func[0]._y : 1 [by e.e.buf_s_func._en_X_t[0]:=0]
1856043 e.out.d.d[0].t : 0 [by e.e.buf_s_func.t_buf_func[0]._y:=1]
1856043 e.out.a : 0
1856043 e.out.v : 0
1856055 e.e.buf_s_func._out_a_B : 1 [by e.out.a:=0]
1856063 e.e.buf_s_func.out_a_B_buf_f.buf1._y : 0 [by e.e.buf_s_func._out_a_B:=1]
1856196 e.e.buf_s_func._out_a_BX_t[0] : 1 [by e.e.buf_s_func.out_a_B_buf_f.buf1._y:=0]
1858380 e.e._en : 1 [by e.out.v:=0]
1858381 e.e.buf_s_func.en_buf_t.buf1._y : 0 [by e.e._en:=1]
1858386 e.e.buf_s_func._en_X_t[0] : 1 [by e.e.buf_s_func.en_buf_t.buf1._y:=0]
1861414 e.e.buf_s_func.en_buf_f.buf1._y : 0 [by e.e._en:=1]
1861808 e.e.buf_s_func._en_X_f[0] : 1 [by e.e.buf_s_func.en_buf_f.buf1._y:=0]
1920867 e.e.buf_s_func.out_a_B_buf_t.buf1._y : 0 [by e.e.buf_s_func._out_a_B:=1]
1923663 e.e.buf_s_func._out_a_BX_f[0] : 1 [by e.e.buf_s_func.out_a_B_buf_t.buf1._y:=0]
[] Neuron (1,0) Encoded
[] Neuron Spikes (1,0), (0,1)
1923663 e.x[1].r : 1
1923663 e.y[1].r : 1
1923663 e.x[0].r : 1
1923663 e.y[0].r : 1
1923678 e.e.Xarb.arbs[0].arbiter._y2 : 0 [by e.x[1].r:=1]
1923689 e.e.Xarb.arbs[0]._y2_arb : 1 [by e.e.Xarb.arbs[0].arbiter._y2:=0]
1923963 e.e.Xarb.arbs[0].or_cell._y : 0 [by e.e.Xarb.arbs[0]._y2_arb:=1]
1924013 e.e._arb_out_x.r : 1 [by e.e.Xarb.arbs[0].or_cell._y:=0]
1925427 e.e.Yarb.arbs[0].arbiter._y2 : 0 [by e.y[1].r:=1]
1925428 e.e.Yarb.arbs[0]._y2_arb : 1 [by e.e.Yarb.arbs[0].arbiter._y2:=0]
1927376 e.e.X_ack_confirm._y : 0 [by e.e._arb_out_x.r:=1]
1927379 e.e._arb_out_x.a : 1 [by e.e.X_ack_confirm._y:=0]
1927788 e.e.x_req_ortree.or2s[0]._y : 0 [by e.x[1].r:=1]
1928039 e.e.Xarb.arbs[0].ack_cell2._y : 0 [by e.e._arb_out_x.a:=1]
1928422 e.e._x_v : 1 [by e.e.x_req_ortree.or2s[0]._y:=0]
1928429 e.e._x_v_B : 0 [by e.e._x_v:=1]
1955687 e.e._x_temp[1].a : 1 [by e.e.Xarb.arbs[0].ack_cell2._y:=0]
1970275 e.e.x_ack_arb[1].buf1._y : 0 [by e.e._x_temp[1].a:=1]
1970305 e.x[1].a : 1 [by e.e.x_ack_arb[1].buf1._y:=0]
1971382 e.e.Yarb.arbs[0].or_cell._y : 0 [by e.e.Yarb.arbs[0]._y2_arb:=1]
1975226 e.e._arb_out_y.r : 1 [by e.e.Yarb.arbs[0].or_cell._y:=0]
1975341 e.e.Y_ack_confirm._y : 0 [by e.e._arb_out_y.r:=1]
1975348 e.e._arb_out_y.a : 1 [by e.e.Y_ack_confirm._y:=0]
1978383 e.e.x_encoder.ors_t[0].b._y : 0 [by e.x[1].a:=1]
1979045 e.e.x_enc_out.d[0].t : 1 [by e.e.x_encoder.ors_t[0].b._y:=0]
1979064 e.e.vtree_x.OR2_tf[0]._y : 0 [by e.e.x_enc_out.d[0].t:=1]
1979065 e.e.vtree_x.ct.in[0] : 1 [by e.e.vtree_x.OR2_tf[0]._y:=0]
1979389 e.e.vtree_x.ct.b._y : 0 [by e.e.vtree_x.ct.in[0]:=1]
1979466 e.e._in_x_v : 1 [by e.e.vtree_x.ct.b._y:=0]
2001633 e.e.Yarb.arbs[0].ack_cell2._y : 0 [by e.e._arb_out_y.a:=1]
2011174 e.e._y_temp[1].a : 1 [by e.e.Yarb.arbs[0].ack_cell2._y:=0]
2038849 e.e.y_ack_arb[1].buf1._y : 0 [by e.e._y_temp[1].a:=1]
2040377 e.y[1].a : 1 [by e.e.y_ack_arb[1].buf1._y:=0]
2045980 e.e.y_encoder.ors_t[0].b._y : 0 [by e.y[1].a:=1]
2046044 e.e.y_enc_out.d[0].t : 1 [by e.e.y_encoder.ors_t[0].b._y:=0]
2046053 e.e.vtree_y.OR2_tf[0]._y : 0 [by e.e.y_enc_out.d[0].t:=1]
2107723 e.e.vtree_y.ct.in[0] : 1 [by e.e.vtree_y.OR2_tf[0]._y:=0]
2130322 e.e.vtree_y.ct.b._y : 0 [by e.e.vtree_y.ct.in[0]:=1]
2131361 e.e._in_y_v : 1 [by e.e.vtree_y.ct.b._y:=0]
2131369 e.e._in_xy_v._y : 0 [by e.e._in_y_v:=1]
2139656 e.e._in_xy_v.y : 1 [by e.e._in_xy_v._y:=0]
2139748 e.e.buf_s_func.in_v_prebuf._y : 0 [by e.e._in_xy_v.y:=1]
2139784 e.e.buf_s_func._in_vX : 1 [by e.e.buf_s_func.in_v_prebuf._y:=0]
2139819 e.e.buf_s_func.in_v_buf_f.buf1._y : 0 [by e.e.buf_s_func._in_vX:=1]
2139841 e.e.buf_s_func.in_v_buf_t.buf1._y : 0 [by e.e.buf_s_func._in_vX:=1]
2140109 e.e.buf_s_func._in_vXX_f[0] : 1 [by e.e.buf_s_func.in_v_buf_f.buf1._y:=0]
2140812 e.e.buf_s_func._in_vXX_t[0] : 1 [by e.e.buf_s_func.in_v_buf_t.buf1._y:=0]
2140855 e.e.buf_s_func.t_buf_func[1]._y : 0 [by e.e.buf_s_func._in_vXX_t[0]:=1]
2148253 e.e.buf_s_func.t_buf_func[0]._y : 0 [by e.e.buf_s_func._in_vXX_t[0]:=1]
2148268 e.out.d.d[0].t : 1 [by e.e.buf_s_func.t_buf_func[0]._y:=0]
2157991 e.out.d.d[1].t : 1 [by e.e.buf_s_func.t_buf_func[1]._y:=0]
[] Check Arbiter Acks (1,0)
[] Check Encoders
[] Check Buffer
[] Finish Neuron Handshake (1,0)
2157991 e.x[1].r : 0
2157991 e.y[0].r : 0
2160804 e.e.Xarb.arbs[0].arbiter._y2 : 1 [by e.x[1].r:=0]
2161176 e.e.Xarb.arbs[0].arbiter._y1 : 0 [by e.e.Xarb.arbs[0].arbiter._y2:=1]
2164956 e.e.Xarb.arbs[0]._y2_arb : 0 [by e.e.Xarb.arbs[0].arbiter._y2:=1]
2165027 e.e.Xarb.arbs[0].or_cell._y : 1 [by e.e.Xarb.arbs[0]._y2_arb:=0]
2174083 e.e._arb_out_x.r : 0 [by e.e.Xarb.arbs[0].or_cell._y:=1]
2174083 e.out.a : 1
2174083 e.out.v : 1
2180951 e.e._x_a_B : 0 [by e.out.v:=1]
2180952 e.e.X_ack_confirm._y : 1 [by e.e._x_a_B:=0]
2181021 e.e._arb_out_x.a : 0 [by e.e.X_ack_confirm._y:=1]
2181040 e.e.Xarb.arbs[0].ack_cell2._y : 1 [by e.e._arb_out_x.a:=0]
2187170 e.e.buf_s_func._out_a_B : 0 [by e.out.a:=1]
2188142 e.e.buf_s_func.out_a_B_buf_t.buf1._y : 1 [by e.e.buf_s_func._out_a_B:=0]
2188242 e.e.buf_s_func._out_a_BX_f[0] : 0 [by e.e.buf_s_func.out_a_B_buf_t.buf1._y:=1]
2192682 e.e._x_a : 1 [by e.e._x_a_B:=0]
2199026 e.e._x_temp[1].a : 0 [by e.e.Xarb.arbs[0].ack_cell2._y:=1]
2199027 e.e.x_ack_arb[1].buf1._y : 1 [by e.e._x_temp[1].a:=0]
2199100 e.e.Xarb.arbs[0]._y1_arb : 1 [by e.e._x_temp[1].a:=0]
2199110 e.e.Xarb.arbs[0].or_cell._y : 0 [by e.e.Xarb.arbs[0]._y1_arb:=1]
2199123 e.e._arb_out_x.r : 1 [by e.e.Xarb.arbs[0].or_cell._y:=0]
2199143 e.x[1].a : 0 [by e.e.x_ack_arb[1].buf1._y:=1]
2199598 e.e.x_encoder.ors_t[0].b._y : 1 [by e.x[1].a:=0]
2207940 e.e.x_enc_out.d[0].t : 0 [by e.e.x_encoder.ors_t[0].b._y:=1]
2208247 e.e.vtree_x.OR2_tf[0]._y : 1 [by e.e.x_enc_out.d[0].t:=0]
2209490 e.e.vtree_x.ct.in[0] : 0 [by e.e.vtree_x.OR2_tf[0]._y:=1]
2214908 e.e._en : 0 [by e.e._x_a:=1]
2214960 e.e.buf_s_func.en_buf_f.buf1._y : 1 [by e.e._en:=0]
2214965 e.e.buf_s_func._en_X_f[0] : 0 [by e.e.buf_s_func.en_buf_f.buf1._y:=1]
2217525 e.e.buf_s_func.en_buf_t.buf1._y : 1 [by e.e._en:=0]
2218603 e.e.vtree_x.ct.b._y : 1 [by e.e.vtree_x.ct.in[0]:=0]
2218623 e.e._in_x_v : 0 [by e.e.vtree_x.ct.b._y:=1]
2218675 e.e._x_a_B : 1 [by e.e._in_x_v:=0]
2218918 e.e._in_xy_v._y : 1 [by e.e._in_x_v:=0]
2219146 e.e.X_ack_confirm._y : 0 [by e.e._x_a_B:=1]
2220500 e.e._arb_out_x.a : 1 [by e.e.X_ack_confirm._y:=0]
2222037 e.e.Xarb.arbs[0].ack_cell1._y : 0 [by e.e._arb_out_x.a:=1]
2222361 e.e._in_xy_v.y : 0 [by e.e._in_xy_v._y:=1]
2222362 e.e.buf_s_func.in_v_prebuf._y : 1 [by e.e._in_xy_v.y:=0]
2222415 e.e.buf_s_func._in_vX : 0 [by e.e.buf_s_func.in_v_prebuf._y:=1]
2224088 e.e.buf_s_func.in_v_buf_f.buf1._y : 1 [by e.e.buf_s_func._in_vX:=0]
2224090 e.e.buf_s_func._in_vXX_f[0] : 0 [by e.e.buf_s_func.in_v_buf_f.buf1._y:=1]
2225272 e.e.buf_s_func._en_X_t[0] : 0 [by e.e.buf_s_func.en_buf_t.buf1._y:=1]
2230095 e.e.buf_s_func.in_v_buf_t.buf1._y : 1 [by e.e.buf_s_func._in_vX:=0]
2230125 e.e.buf_s_func._in_vXX_t[0] : 0 [by e.e.buf_s_func.in_v_buf_t.buf1._y:=1]
2231524 e.e.buf_s_func.out_a_B_buf_f.buf1._y : 1 [by e.e.buf_s_func._out_a_B:=0]
2231821 e.e.buf_s_func._out_a_BX_t[0] : 0 [by e.e.buf_s_func.out_a_B_buf_f.buf1._y:=1]
2233455 e.e._x_temp[0].a : 1 [by e.e.Xarb.arbs[0].ack_cell1._y:=0]
2233698 e.e.x_ack_arb[0].buf1._y : 0 [by e.e._x_temp[0].a:=1]
2236810 e.x[0].a : 1 [by e.e.x_ack_arb[0].buf1._y:=0]
2237371 e.e.x_encoder.ors_f[0].b._y : 0 [by e.x[0].a:=1]
2237384 e.e.x_enc_out.d[0].f : 1 [by e.e.x_encoder.ors_f[0].b._y:=0]
2239108 e.e.buf_s_func.t_buf_func[1]._y : 1 [by e.e.buf_s_func._out_a_BX_t[0]:=0]
2239109 e.out.d.d[1].t : 0 [by e.e.buf_s_func.t_buf_func[1]._y:=1]
2257408 e.e.buf_s_func.t_buf_func[0]._y : 1 [by e.e.buf_s_func._out_a_BX_t[0]:=0]
2265227 e.out.d.d[0].t : 0 [by e.e.buf_s_func.t_buf_func[0]._y:=1]
2265638 e.e.vtree_x.OR2_tf[0]._y : 0 [by e.e.x_enc_out.d[0].f:=1]
2265687 e.e.vtree_x.ct.in[0] : 1 [by e.e.vtree_x.OR2_tf[0]._y:=0]
2276185 e.e.vtree_x.ct.b._y : 0 [by e.e.vtree_x.ct.in[0]:=1]
2276891 e.e._x_a : 0 [by e.e._x_a_B:=1]
2287272 e.e._in_x_v : 1 [by e.e.vtree_x.ct.b._y:=0]
2287425 e.e._in_xy_v._y : 0 [by e.e._in_x_v:=1]
2287487 e.e._in_xy_v.y : 1 [by e.e._in_xy_v._y:=0]
2287489 e.e.buf_s_func.in_v_prebuf._y : 0 [by e.e._in_xy_v.y:=1]
2288204 e.e.buf_s_func._in_vX : 1 [by e.e.buf_s_func.in_v_prebuf._y:=0]
2288235 e.e.buf_s_func.in_v_buf_f.buf1._y : 0 [by e.e.buf_s_func._in_vX:=1]
2288285 e.e.buf_s_func._in_vXX_f[0] : 1 [by e.e.buf_s_func.in_v_buf_f.buf1._y:=0]
2305580 e.e.buf_s_func.in_v_buf_t.buf1._y : 0 [by e.e.buf_s_func._in_vX:=1]
2305616 e.e.buf_s_func._in_vXX_t[0] : 1 [by e.e.buf_s_func.in_v_buf_t.buf1._y:=0]
2305616 e.out.a : 0
2305616 e.out.v : 0
2305622 e.e.buf_s_func._out_a_B : 1 [by e.out.a:=0]
2305626 e.e.buf_s_func.out_a_B_buf_f.buf1._y : 0 [by e.e.buf_s_func._out_a_B:=1]
2305654 e.e.buf_s_func._out_a_BX_t[0] : 1 [by e.e.buf_s_func.out_a_B_buf_f.buf1._y:=0]
2305784 e.e.buf_s_func.out_a_B_buf_t.buf1._y : 0 [by e.e.buf_s_func._out_a_B:=1]
2307525 e.e.buf_s_func._out_a_BX_f[0] : 1 [by e.e.buf_s_func.out_a_B_buf_t.buf1._y:=0]
2318778 e.e._en : 1 [by e.out.v:=0]
2318779 e.e.buf_s_func.en_buf_t.buf1._y : 0 [by e.e._en:=1]
2318828 e.e.buf_s_func._en_X_t[0] : 1 [by e.e.buf_s_func.en_buf_t.buf1._y:=0]
2332495 e.e.buf_s_func.en_buf_f.buf1._y : 0 [by e.e._en:=1]
2332518 e.e.buf_s_func._en_X_f[0] : 1 [by e.e.buf_s_func.en_buf_f.buf1._y:=0]
2332604 e.e.buf_s_func.f_buf_func[0]._y : 0 [by e.e.buf_s_func._en_X_f[0]:=1]
2332614 e.out.d.d[0].f : 1 [by e.e.buf_s_func.f_buf_func[0]._y:=0]
2383473 e.e.buf_s_func.t_buf_func[1]._y : 0 [by e.e.buf_s_func._en_X_t[0]:=1]
2384067 e.out.d.d[1].t : 1 [by e.e.buf_s_func.t_buf_func[1]._y:=0]
[] Neuron (1,0) Encoded
[] Check Neuron (0,1) Waiting
[] Check Arbiter Acks (0,1)
[] Check Encoders
[] Check Buffer
[] Finish Neuron Handshake (1,0)
2384067 e.x[0].r : 0
2384067 e.y[1].r : 0
2384070 e.e.Xarb.arbs[0].arbiter._y1 : 1 [by e.x[0].r:=0]
2384081 e.e.Xarb.arbs[0]._y1_arb : 0 [by e.e.Xarb.arbs[0].arbiter._y1:=1]
2387687 e.e.Xarb.arbs[0].or_cell._y : 1 [by e.e.Xarb.arbs[0]._y1_arb:=0]
2388990 e.e._arb_out_x.r : 0 [by e.e.Xarb.arbs[0].or_cell._y:=1]
2391381 e.e.x_req_ortree.or2s[0]._y : 1 [by e.x[0].r:=0]
2399331 e.e._x_v : 0 [by e.e.x_req_ortree.or2s[0]._y:=1]
2399837 e.e._x_v_B : 1 [by e.e._x_v:=0]
2434772 e.e.Yarb.arbs[0].arbiter._y2 : 1 [by e.y[1].r:=0]
2434773 e.e.Yarb.arbs[0]._y2_arb : 0 [by e.e.Yarb.arbs[0].arbiter._y2:=1]
2434775 e.e.Yarb.arbs[0].or_cell._y : 1 [by e.e.Yarb.arbs[0]._y2_arb:=0]
2434776 e.e._arb_out_y.r : 0 [by e.e.Yarb.arbs[0].or_cell._y:=1]
2434776 e.out.a : 1
2434776 e.out.v : 1
2434791 e.e._x_a_B : 0 [by e.out.v:=1]
2434838 e.e._x_a : 1 [by e.e._x_a_B:=0]
2435200 e.e.X_ack_confirm._y : 1 [by e.e._x_a_B:=0]
2435247 e.e._en : 0 [by e.e._x_a:=1]
2435275 e.e.buf_s_func.en_buf_f.buf1._y : 1 [by e.e._en:=0]
2435397 e.e.buf_s_func._en_X_f[0] : 0 [by e.e.buf_s_func.en_buf_f.buf1._y:=1]
2436697 e.e._arb_out_x.a : 0 [by e.e.X_ack_confirm._y:=1]
2436732 e.e.Xarb.arbs[0].ack_cell1._y : 1 [by e.e._arb_out_x.a:=0]
2437302 e.e.buf_s_func.en_buf_t.buf1._y : 1 [by e.e._en:=0]
2437305 e.e.buf_s_func._en_X_t[0] : 0 [by e.e.buf_s_func.en_buf_t.buf1._y:=1]
2437424 e.e._x_temp[0].a : 0 [by e.e.Xarb.arbs[0].ack_cell1._y:=1]
2437591 e.e.x_ack_arb[0].buf1._y : 1 [by e.e._x_temp[0].a:=0]
2437592 e.x[0].a : 0 [by e.e.x_ack_arb[0].buf1._y:=1]
2438672 e.e.x_encoder.ors_f[0].b._y : 1 [by e.x[0].a:=0]
2439331 e.e.x_enc_out.d[0].f : 0 [by e.e.x_encoder.ors_f[0].b._y:=1]
2439346 e.e.vtree_x.OR2_tf[0]._y : 1 [by e.e.x_enc_out.d[0].f:=0]
2439614 e.e.vtree_x.ct.in[0] : 0 [by e.e.vtree_x.OR2_tf[0]._y:=1]
2441871 e.e.vtree_x.ct.b._y : 1 [by e.e.vtree_x.ct.in[0]:=0]
2441872 e.e._in_x_v : 0 [by e.e.vtree_x.ct.b._y:=1]
2441873 e.e._in_xy_v._y : 1 [by e.e._in_x_v:=0]
2441875 e.e.Y_ack_confirm._y : 1 [by e.e._in_x_v:=0]
2441876 e.e._arb_out_y.a : 0 [by e.e.Y_ack_confirm._y:=1]
2441885 e.e.Yarb.arbs[0].ack_cell2._y : 1 [by e.e._arb_out_y.a:=0]
2441905 e.e._in_xy_v.y : 0 [by e.e._in_xy_v._y:=1]
2442491 e.e.buf_s_func.in_v_prebuf._y : 1 [by e.e._in_xy_v.y:=0]
2444195 e.e.buf_s_func._in_vX : 0 [by e.e.buf_s_func.in_v_prebuf._y:=1]
2444204 e.e.buf_s_func.in_v_buf_t.buf1._y : 1 [by e.e.buf_s_func._in_vX:=0]
2444205 e.e.buf_s_func._in_vXX_t[0] : 0 [by e.e.buf_s_func.in_v_buf_t.buf1._y:=1]
2445044 e.e.buf_s_func.in_v_buf_f.buf1._y : 1 [by e.e.buf_s_func._in_vX:=0]
2445683 e.e._y_temp[1].a : 0 [by e.e.Yarb.arbs[0].ack_cell2._y:=1]
2446299 e.e.y_ack_arb[1].buf1._y : 1 [by e.e._y_temp[1].a:=0]
2454986 e.e.buf_s_func._out_a_B : 0 [by e.out.a:=1]
2455310 e.e.buf_s_func.out_a_B_buf_t.buf1._y : 1 [by e.e.buf_s_func._out_a_B:=0]
2455311 e.e.buf_s_func._out_a_BX_f[0] : 0 [by e.e.buf_s_func.out_a_B_buf_t.buf1._y:=1]
2456060 e.e.buf_s_func.f_buf_func[0]._y : 1 [by e.e.buf_s_func._out_a_BX_f[0]:=0]
2457691 e.e.buf_s_func.out_a_B_buf_f.buf1._y : 1 [by e.e.buf_s_func._out_a_B:=0]
2458138 e.e.buf_s_func._out_a_BX_t[0] : 0 [by e.e.buf_s_func.out_a_B_buf_f.buf1._y:=1]
2458139 e.e.buf_s_func.t_buf_func[1]._y : 1 [by e.e.buf_s_func._out_a_BX_t[0]:=0]
2458280 e.out.d.d[1].t : 0 [by e.e.buf_s_func.t_buf_func[1]._y:=1]
2460246 e.out.d.d[0].f : 0 [by e.e.buf_s_func.f_buf_func[0]._y:=1]
2461163 e.e.buf_s_func._in_vXX_f[0] : 0 [by e.e.buf_s_func.in_v_buf_f.buf1._y:=1]
2466090 e.y[1].a : 0 [by e.e.y_ack_arb[1].buf1._y:=1]
2507916 e.e.y_encoder.ors_t[0].b._y : 1 [by e.y[1].a:=0]
2508120 e.e.y_enc_out.d[0].t : 0 [by e.e.y_encoder.ors_t[0].b._y:=1]
2508171 e.e.vtree_y.OR2_tf[0]._y : 1 [by e.e.y_enc_out.d[0].t:=0]
2508611 e.e.vtree_y.ct.in[0] : 0 [by e.e.vtree_y.OR2_tf[0]._y:=1]
2536780 e.e.vtree_y.ct.b._y : 1 [by e.e.vtree_y.ct.in[0]:=0]
2536964 e.e._in_y_v : 0 [by e.e.vtree_y.ct.b._y:=1]
2540299 e.e._x_a_B : 1 [by e.e._in_y_v:=0]
2540343 e.e._x_a : 0 [by e.e._x_a_B:=1]
2540343 e.out.a : 0
2540343 e.out.v : 0
2540344 e.e.buf_s_func._out_a_B : 1 [by e.out.a:=0]
2541410 e.e.buf_s_func.out_a_B_buf_f.buf1._y : 0 [by e.e.buf_s_func._out_a_B:=1]
2541422 e.e.buf_s_func._out_a_BX_t[0] : 1 [by e.e.buf_s_func.out_a_B_buf_f.buf1._y:=0]
2542137 e.e.buf_s_func.out_a_B_buf_t.buf1._y : 0 [by e.e.buf_s_func._out_a_B:=1]
2543304 e.e.buf_s_func._out_a_BX_f[0] : 1 [by e.e.buf_s_func.out_a_B_buf_t.buf1._y:=0]
2543348 e.e._en : 1 [by e.out.v:=0]
2544188 e.e.buf_s_func.en_buf_t.buf1._y : 0 [by e.e._en:=1]
2545169 e.e.buf_s_func._en_X_t[0] : 1 [by e.e.buf_s_func.en_buf_t.buf1._y:=0]
2553279 e.e.buf_s_func.en_buf_f.buf1._y : 0 [by e.e._en:=1]
2603344 e.e.buf_s_func._en_X_f[0] : 1 [by e.e.buf_s_func.en_buf_f.buf1._y:=0]
[] Neuron (1,0) Encoded

852
test/unit_tests/encoder2D_2x2/run/test.prs
View File

@@ -1,852 +0,0 @@
= "GND" "GND"
= "Vdd" "Vdd"
= "Reset" "Reset"
"Reset"->"e._reset_B"-
~("Reset")->"e._reset_B"+
= "e._reset_B" "e.e.reset_B"
= "e.e.y_encoder.tielo.y" "e.e.y_encoder.tielo.vss"
"e.e.y_encoder.ors_t[0].b.a"->"e.e.y_encoder.ors_t[0].b._y"-
~("e.e.y_encoder.ors_t[0].b.a")->"e.e.y_encoder.ors_t[0].b._y"+
"e.e.y_encoder.ors_t[0].b._y"->"e.e.y_encoder.ors_t[0].b.y"-
~("e.e.y_encoder.ors_t[0].b._y")->"e.e.y_encoder.ors_t[0].b.y"+
= "e.e.y_encoder.ors_t[0].supply.vdd" "e.e.y_encoder.ors_t[0].b.vdd"
= "e.e.y_encoder.ors_t[0].supply.vss" "e.e.y_encoder.ors_t[0].b.vss"
= "e.e.y_encoder.ors_t[0].out" "e.e.y_encoder.ors_t[0].b.y"
= "e.e.y_encoder.ors_t[0].in[0]" "e.e.y_encoder.ors_t[0].b.a"
"e.e.y_encoder.ors_f[0].b.a"->"e.e.y_encoder.ors_f[0].b._y"-
~("e.e.y_encoder.ors_f[0].b.a")->"e.e.y_encoder.ors_f[0].b._y"+
"e.e.y_encoder.ors_f[0].b._y"->"e.e.y_encoder.ors_f[0].b.y"-
~("e.e.y_encoder.ors_f[0].b._y")->"e.e.y_encoder.ors_f[0].b.y"+
= "e.e.y_encoder.ors_f[0].supply.vdd" "e.e.y_encoder.ors_f[0].b.vdd"
= "e.e.y_encoder.ors_f[0].supply.vss" "e.e.y_encoder.ors_f[0].b.vss"
= "e.e.y_encoder.ors_f[0].out" "e.e.y_encoder.ors_f[0].b.y"
= "e.e.y_encoder.ors_f[0].in[0]" "e.e.y_encoder.ors_f[0].b.a"
= "e.e.y_encoder.supply.vss" "e.e.y_encoder.ors_f[0].supply.vss"
= "e.e.y_encoder.supply.vdd" "e.e.y_encoder.ors_f[0].supply.vdd"
= "e.e.y_encoder.supply.vss" "e.e.y_encoder.ors_t[0].supply.vss"
= "e.e.y_encoder.supply.vdd" "e.e.y_encoder.ors_t[0].supply.vdd"
= "e.e.y_encoder.supply.vdd" "e.e.y_encoder.tielo.vdd"
= "e.e.y_encoder.supply.vss" "e.e.y_encoder.tielo.vss"
= "e.e.y_encoder.supply.vss" "e.e.y_encoder.tielo.y"
= "e.e.y_encoder.in[0]" "e.e.y_encoder.ors_f[0].in[0]"
= "e.e.y_encoder.in[1]" "e.e.y_encoder.ors_t[0].in[0]"
= "e.e.y_encoder.out.d[0].d[0]" "e.e.y_encoder.out.d[0].f"
= "e.e.y_encoder.out.d[0].d[1]" "e.e.y_encoder.out.d[0].t"
= "e.e.y_encoder.out.d[0].d[0]" "e.e.y_encoder.out.d[0].f"
= "e.e.y_encoder.out.d[0].d[1]" "e.e.y_encoder.out.d[0].t"
= "e.e.y_encoder.out.d[0].d[0]" "e.e.y_encoder.ors_f[0].out"
= "e.e.y_encoder.out.d[0].d[0]" "e.e.y_encoder.out.d[0].f"
= "e.e.y_encoder.out.d[0].d[1]" "e.e.y_encoder.ors_t[0].out"
= "e.e.y_encoder.out.d[0].d[1]" "e.e.y_encoder.out.d[0].t"
= "e.e.x_encoder.tielo.y" "e.e.x_encoder.tielo.vss"
"e.e.x_encoder.ors_t[0].b.a"->"e.e.x_encoder.ors_t[0].b._y"-
~("e.e.x_encoder.ors_t[0].b.a")->"e.e.x_encoder.ors_t[0].b._y"+
"e.e.x_encoder.ors_t[0].b._y"->"e.e.x_encoder.ors_t[0].b.y"-
~("e.e.x_encoder.ors_t[0].b._y")->"e.e.x_encoder.ors_t[0].b.y"+
= "e.e.x_encoder.ors_t[0].supply.vdd" "e.e.x_encoder.ors_t[0].b.vdd"
= "e.e.x_encoder.ors_t[0].supply.vss" "e.e.x_encoder.ors_t[0].b.vss"
= "e.e.x_encoder.ors_t[0].out" "e.e.x_encoder.ors_t[0].b.y"
= "e.e.x_encoder.ors_t[0].in[0]" "e.e.x_encoder.ors_t[0].b.a"
"e.e.x_encoder.ors_f[0].b.a"->"e.e.x_encoder.ors_f[0].b._y"-
~("e.e.x_encoder.ors_f[0].b.a")->"e.e.x_encoder.ors_f[0].b._y"+
"e.e.x_encoder.ors_f[0].b._y"->"e.e.x_encoder.ors_f[0].b.y"-
~("e.e.x_encoder.ors_f[0].b._y")->"e.e.x_encoder.ors_f[0].b.y"+
= "e.e.x_encoder.ors_f[0].supply.vdd" "e.e.x_encoder.ors_f[0].b.vdd"
= "e.e.x_encoder.ors_f[0].supply.vss" "e.e.x_encoder.ors_f[0].b.vss"
= "e.e.x_encoder.ors_f[0].out" "e.e.x_encoder.ors_f[0].b.y"
= "e.e.x_encoder.ors_f[0].in[0]" "e.e.x_encoder.ors_f[0].b.a"
= "e.e.x_encoder.supply.vss" "e.e.x_encoder.ors_f[0].supply.vss"
= "e.e.x_encoder.supply.vdd" "e.e.x_encoder.ors_f[0].supply.vdd"
= "e.e.x_encoder.supply.vss" "e.e.x_encoder.ors_t[0].supply.vss"
= "e.e.x_encoder.supply.vdd" "e.e.x_encoder.ors_t[0].supply.vdd"
= "e.e.x_encoder.supply.vdd" "e.e.x_encoder.tielo.vdd"
= "e.e.x_encoder.supply.vss" "e.e.x_encoder.tielo.vss"
= "e.e.x_encoder.supply.vss" "e.e.x_encoder.tielo.y"
= "e.e.x_encoder.in[0]" "e.e.x_encoder.ors_f[0].in[0]"
= "e.e.x_encoder.in[1]" "e.e.x_encoder.ors_t[0].in[0]"
= "e.e.x_encoder.out.d[0].d[0]" "e.e.x_encoder.out.d[0].f"
= "e.e.x_encoder.out.d[0].d[1]" "e.e.x_encoder.out.d[0].t"
= "e.e.x_encoder.out.d[0].d[0]" "e.e.x_encoder.out.d[0].f"
= "e.e.x_encoder.out.d[0].d[1]" "e.e.x_encoder.out.d[0].t"
= "e.e.x_encoder.out.d[0].d[0]" "e.e.x_encoder.ors_f[0].out"
= "e.e.x_encoder.out.d[0].d[0]" "e.e.x_encoder.out.d[0].f"
= "e.e.x_encoder.out.d[0].d[1]" "e.e.x_encoder.ors_t[0].out"
= "e.e.x_encoder.out.d[0].d[1]" "e.e.x_encoder.out.d[0].t"
"e.e.reset_bufarray.buf1.a"->"e.e.reset_bufarray.buf1._y"-
~("e.e.reset_bufarray.buf1.a")->"e.e.reset_bufarray.buf1._y"+
"e.e.reset_bufarray.buf1._y"->"e.e.reset_bufarray.buf1.y"-
~("e.e.reset_bufarray.buf1._y")->"e.e.reset_bufarray.buf1.y"+
= "e.e.reset_bufarray.supply.vdd" "e.e.reset_bufarray.buf1.vdd"
= "e.e.reset_bufarray.supply.vss" "e.e.reset_bufarray.buf1.vss"
= "e.e.reset_bufarray.out[0]" "e.e.reset_bufarray.out[3]"
= "e.e.reset_bufarray.out[0]" "e.e.reset_bufarray.out[2]"
= "e.e.reset_bufarray.out[0]" "e.e.reset_bufarray.out[1]"
= "e.e.reset_bufarray.out[0]" "e.e.reset_bufarray.buf1.y"
= "e.e.reset_bufarray.in" "e.e.reset_bufarray.buf1.a"
= "e.e.x[0].d.d[0]" "e.e.x[0].r"
= "e.e.x[1].d.d[0]" "e.e.x[1].r"
= "e.e.x[1].a" "e.e.x_acks[1]"
= "e.e.x[1].a" "e.e.x_ack_arb[1].out"
= "e.e.x[1].d.d[0]" "e.e._x_req_array[1]"
= "e.e.x[1].d.d[0]" "e.e._x_temp[1].r"
= "e.e.x[1].d.d[0]" "e.e._x_temp[1].d.d[0]"
= "e.e.x[1].d.d[0]" "e.e.x[1].r"
= "e.e.x[0].a" "e.e.x_acks[0]"
= "e.e.x[0].a" "e.e.x_ack_arb[0].out"
= "e.e.x[0].d.d[0]" "e.e._x_req_array[0]"
= "e.e.x[0].d.d[0]" "e.e._x_temp[0].r"
= "e.e.x[0].d.d[0]" "e.e._x_temp[0].d.d[0]"
= "e.e.x[0].d.d[0]" "e.e.x[0].r"
= "e.e.Xarb.arbs[0].in1.d.d[0]" "e.e.Xarb.arbs[0].in1.r"
= "e.e.Xarb.arbs[0].in1.a" "e.e.Xarb.arbs[0].arbiter.d"
= "e.e.Xarb.arbs[0].in1.a" "e.e.Xarb.arbs[0].ack_cell1.y"
= "e.e.Xarb.arbs[0].in1.d.d[0]" "e.e.Xarb.arbs[0].arbiter.a"
= "e.e.Xarb.arbs[0].in1.d.d[0]" "e.e.Xarb.arbs[0].in1.r"
~"e.e.Xarb.arbs[0].ack_cell1.c1"&~"e.e.Xarb.arbs[0].ack_cell1.c2"->"e.e.Xarb.arbs[0].ack_cell1._y"+
"e.e.Xarb.arbs[0].ack_cell1.c1"&"e.e.Xarb.arbs[0].ack_cell1.c2"->"e.e.Xarb.arbs[0].ack_cell1._y"-
"e.e.Xarb.arbs[0].ack_cell1._y"->"e.e.Xarb.arbs[0].ack_cell1.y"-
~("e.e.Xarb.arbs[0].ack_cell1._y")->"e.e.Xarb.arbs[0].ack_cell1.y"+
= "e.e.Xarb.arbs[0].in2.d.d[0]" "e.e.Xarb.arbs[0].in2.r"
= "e.e.Xarb.arbs[0].in2.a" "e.e.Xarb.arbs[0].arbiter.c"
= "e.e.Xarb.arbs[0].in2.a" "e.e.Xarb.arbs[0].ack_cell2.y"
= "e.e.Xarb.arbs[0].in2.d.d[0]" "e.e.Xarb.arbs[0].arbiter.b"
= "e.e.Xarb.arbs[0].in2.d.d[0]" "e.e.Xarb.arbs[0].in2.r"
= "e.e.Xarb.arbs[0].supply.vdd" "e.e.Xarb.arbs[0].arbiter.vdd"
= "e.e.Xarb.arbs[0].supply.vdd" "e.e.Xarb.arbs[0].or_cell.vdd"
= "e.e.Xarb.arbs[0].supply.vdd" "e.e.Xarb.arbs[0].ack_cell2.vdd"
= "e.e.Xarb.arbs[0].supply.vdd" "e.e.Xarb.arbs[0].ack_cell1.vdd"
= "e.e.Xarb.arbs[0].supply.vss" "e.e.Xarb.arbs[0].arbiter.vss"
= "e.e.Xarb.arbs[0].supply.vss" "e.e.Xarb.arbs[0].or_cell.vss"
= "e.e.Xarb.arbs[0].supply.vss" "e.e.Xarb.arbs[0].ack_cell2.vss"
= "e.e.Xarb.arbs[0].supply.vss" "e.e.Xarb.arbs[0].ack_cell1.vss"
"e.e.Xarb.arbs[0].arbiter.a"&"e.e.Xarb.arbs[0].arbiter._y2"->"e.e.Xarb.arbs[0].arbiter._y1"-
~"e.e.Xarb.arbs[0].arbiter.a"|~"e.e.Xarb.arbs[0].arbiter._y2"->"e.e.Xarb.arbs[0].arbiter._y1"+
"e.e.Xarb.arbs[0].arbiter.b"&"e.e.Xarb.arbs[0].arbiter._y1"->"e.e.Xarb.arbs[0].arbiter._y2"-
~"e.e.Xarb.arbs[0].arbiter.b"|~"e.e.Xarb.arbs[0].arbiter._y1"->"e.e.Xarb.arbs[0].arbiter._y2"+
"e.e.Xarb.arbs[0].arbiter._y1"|"e.e.Xarb.arbs[0].arbiter.c"->"e.e.Xarb.arbs[0].arbiter.y1"-
~("e.e.Xarb.arbs[0].arbiter._y1"|"e.e.Xarb.arbs[0].arbiter.c")->"e.e.Xarb.arbs[0].arbiter.y1"+
"e.e.Xarb.arbs[0].arbiter._y2"|"e.e.Xarb.arbs[0].arbiter.d"->"e.e.Xarb.arbs[0].arbiter.y2"-
~("e.e.Xarb.arbs[0].arbiter._y2"|"e.e.Xarb.arbs[0].arbiter.d")->"e.e.Xarb.arbs[0].arbiter.y2"+
mk_excllo("e.e.Xarb.arbs[0].arbiter._y1","e.e.Xarb.arbs[0].arbiter._y2")
= "e.e.Xarb.arbs[0]._y1_arb" "e.e.Xarb.arbs[0].arbiter.y1"
= "e.e.Xarb.arbs[0]._y1_arb" "e.e.Xarb.arbs[0].or_cell.a"
= "e.e.Xarb.arbs[0]._y1_arb" "e.e.Xarb.arbs[0].ack_cell1.c2"
~"e.e.Xarb.arbs[0].ack_cell2.c1"&~"e.e.Xarb.arbs[0].ack_cell2.c2"->"e.e.Xarb.arbs[0].ack_cell2._y"+
"e.e.Xarb.arbs[0].ack_cell2.c1"&"e.e.Xarb.arbs[0].ack_cell2.c2"->"e.e.Xarb.arbs[0].ack_cell2._y"-
"e.e.Xarb.arbs[0].ack_cell2._y"->"e.e.Xarb.arbs[0].ack_cell2.y"-
~("e.e.Xarb.arbs[0].ack_cell2._y")->"e.e.Xarb.arbs[0].ack_cell2.y"+
"e.e.Xarb.arbs[0].or_cell.a"|"e.e.Xarb.arbs[0].or_cell.b"->"e.e.Xarb.arbs[0].or_cell._y"-
~("e.e.Xarb.arbs[0].or_cell.a"|"e.e.Xarb.arbs[0].or_cell.b")->"e.e.Xarb.arbs[0].or_cell._y"+
"e.e.Xarb.arbs[0].or_cell._y"->"e.e.Xarb.arbs[0].or_cell.y"-
~("e.e.Xarb.arbs[0].or_cell._y")->"e.e.Xarb.arbs[0].or_cell.y"+
= "e.e.Xarb.arbs[0].out.d.d[0]" "e.e.Xarb.arbs[0].out.r"
= "e.e.Xarb.arbs[0].out.a" "e.e.Xarb.arbs[0].ack_cell2.c1"
= "e.e.Xarb.arbs[0].out.a" "e.e.Xarb.arbs[0].ack_cell1.c1"
= "e.e.Xarb.arbs[0].out.d.d[0]" "e.e.Xarb.arbs[0].or_cell.y"
= "e.e.Xarb.arbs[0].out.d.d[0]" "e.e.Xarb.arbs[0].out.r"
= "e.e.Xarb.arbs[0]._y2_arb" "e.e.Xarb.arbs[0].arbiter.y2"
= "e.e.Xarb.arbs[0]._y2_arb" "e.e.Xarb.arbs[0].or_cell.b"
= "e.e.Xarb.arbs[0]._y2_arb" "e.e.Xarb.arbs[0].ack_cell2.c2"
= "e.e.Xarb.supply.vss" "e.e.Xarb.arbs[0].supply.vss"
= "e.e.Xarb.supply.vdd" "e.e.Xarb.arbs[0].supply.vdd"
= "e.e.Xarb.in[0].d.d[0]" "e.e.Xarb.in[0].r"
= "e.e.Xarb.in[1].d.d[0]" "e.e.Xarb.in[1].r"
= "e.e.Xarb.in[0].r" "e.e.Xarb.arbs[0].in1.r"
= "e.e.Xarb.in[0].a" "e.e.Xarb.arbs[0].in1.a"
= "e.e.Xarb.in[0].d.d[0]" "e.e.Xarb.arbs[0].in1.d.d[0]"
= "e.e.Xarb.in[0].r" "e.e.Xarb.tmp[0].r"
= "e.e.Xarb.in[0].a" "e.e.Xarb.tmp[0].a"
= "e.e.Xarb.in[0].d.d[0]" "e.e.Xarb.tmp[0].d.d[0]"
= "e.e.Xarb.in[1].r" "e.e.Xarb.arbs[0].in2.r"
= "e.e.Xarb.in[1].a" "e.e.Xarb.arbs[0].in2.a"
= "e.e.Xarb.in[1].d.d[0]" "e.e.Xarb.arbs[0].in2.d.d[0]"
= "e.e.Xarb.in[1].r" "e.e.Xarb.tmp[1].r"
= "e.e.Xarb.in[1].a" "e.e.Xarb.tmp[1].a"
= "e.e.Xarb.in[1].d.d[0]" "e.e.Xarb.tmp[1].d.d[0]"
= "e.e.Xarb.in[1].d.d[0]" "e.e.Xarb.in[1].r"
= "e.e.Xarb.in[0].d.d[0]" "e.e.Xarb.in[0].r"
= "e.e.Xarb.out.d.d[0]" "e.e.Xarb.out.r"
= "e.e.Xarb.out.r" "e.e.Xarb.arbs[0].out.r"
= "e.e.Xarb.out.a" "e.e.Xarb.arbs[0].out.a"
= "e.e.Xarb.out.d.d[0]" "e.e.Xarb.arbs[0].out.d.d[0]"
= "e.e.Xarb.out.r" "e.e.Xarb.tmp[2].r"
= "e.e.Xarb.out.a" "e.e.Xarb.tmp[2].a"
= "e.e.Xarb.out.d.d[0]" "e.e.Xarb.tmp[2].d.d[0]"
= "e.e.Xarb.out.d.d[0]" "e.e.Xarb.out.r"
"e.e.y_ack_arb[0].buf1.a"->"e.e.y_ack_arb[0].buf1._y"-
~("e.e.y_ack_arb[0].buf1.a")->"e.e.y_ack_arb[0].buf1._y"+
"e.e.y_ack_arb[0].buf1._y"->"e.e.y_ack_arb[0].buf1.y"-
~("e.e.y_ack_arb[0].buf1._y")->"e.e.y_ack_arb[0].buf1.y"+
= "e.e.y_ack_arb[0].supply.vdd" "e.e.y_ack_arb[0].buf1.vdd"
= "e.e.y_ack_arb[0].supply.vss" "e.e.y_ack_arb[0].buf1.vss"
= "e.e.y_ack_arb[0].out" "e.e.y_ack_arb[0].buf1.y"
= "e.e.y_ack_arb[0].in" "e.e.y_ack_arb[0].buf1.a"
"e.e.y_ack_arb[1].buf1.a"->"e.e.y_ack_arb[1].buf1._y"-
~("e.e.y_ack_arb[1].buf1.a")->"e.e.y_ack_arb[1].buf1._y"+
"e.e.y_ack_arb[1].buf1._y"->"e.e.y_ack_arb[1].buf1.y"-
~("e.e.y_ack_arb[1].buf1._y")->"e.e.y_ack_arb[1].buf1.y"+
= "e.e.y_ack_arb[1].supply.vdd" "e.e.y_ack_arb[1].buf1.vdd"
= "e.e.y_ack_arb[1].supply.vss" "e.e.y_ack_arb[1].buf1.vss"
= "e.e.y_ack_arb[1].out" "e.e.y_ack_arb[1].buf1.y"
= "e.e.y_ack_arb[1].in" "e.e.y_ack_arb[1].buf1.a"
~"e.e.enabling.p1"&~"e.e.enabling.p2"&~"e.e.enabling.c1"->"e.e.enabling.y"+
"e.e.enabling.c1"->"e.e.enabling.y"-
= "e.e.into_buffer.d[0].d[0]" "e.e.into_buffer.d[0].f"
= "e.e.into_buffer.d[0].d[1]" "e.e.into_buffer.d[0].t"
= "e.e.into_buffer.d[1].d[0]" "e.e.into_buffer.d[1].f"
= "e.e.into_buffer.d[1].d[1]" "e.e.into_buffer.d[1].t"
= "e.e.into_buffer.d[1].d[0]" "e.e.into_buffer.d[1].f"
= "e.e.into_buffer.d[1].d[1]" "e.e.into_buffer.d[1].t"
= "e.e.into_buffer.d[0].d[0]" "e.e.into_buffer.d[0].f"
= "e.e.into_buffer.d[0].d[1]" "e.e.into_buffer.d[0].t"
= "e.e.into_buffer.d[0].f" "e.e.buf_s_func.in.d[0].f"
= "e.e.into_buffer.d[0].t" "e.e.buf_s_func.in.d[0].t"
= "e.e.into_buffer.d[0].d[0]" "e.e.buf_s_func.in.d[0].d[0]"
= "e.e.into_buffer.d[0].d[1]" "e.e.buf_s_func.in.d[0].d[1]"
= "e.e.into_buffer.d[1].f" "e.e.buf_s_func.in.d[1].f"
= "e.e.into_buffer.d[1].t" "e.e.buf_s_func.in.d[1].t"
= "e.e.into_buffer.d[1].d[0]" "e.e.buf_s_func.in.d[1].d[0]"
= "e.e.into_buffer.d[1].d[1]" "e.e.buf_s_func.in.d[1].d[1]"
= "e.e._en" "e.e.buf_s_func.en"
= "e.e._en" "e.e.enabling.y"
= "e.e._en" "e.e.x_ack.c1"
"e.e.vtree_y.ct.b.a"->"e.e.vtree_y.ct.b._y"-
~("e.e.vtree_y.ct.b.a")->"e.e.vtree_y.ct.b._y"+
"e.e.vtree_y.ct.b._y"->"e.e.vtree_y.ct.b.y"-
~("e.e.vtree_y.ct.b._y")->"e.e.vtree_y.ct.b.y"+
= "e.e.vtree_y.ct.supply.vdd" "e.e.vtree_y.ct.b.vdd"
= "e.e.vtree_y.ct.supply.vss" "e.e.vtree_y.ct.b.vss"
= "e.e.vtree_y.ct.out" "e.e.vtree_y.ct.b.y"
= "e.e.vtree_y.ct.in[0]" "e.e.vtree_y.ct.b.a"
= "e.e.vtree_y.ct.in[0]" "e.e.vtree_y.OR2_tf[0].y"
"e.e.vtree_y.OR2_tf[0].a"|"e.e.vtree_y.OR2_tf[0].b"->"e.e.vtree_y.OR2_tf[0]._y"-
~("e.e.vtree_y.OR2_tf[0].a"|"e.e.vtree_y.OR2_tf[0].b")->"e.e.vtree_y.OR2_tf[0]._y"+
"e.e.vtree_y.OR2_tf[0]._y"->"e.e.vtree_y.OR2_tf[0].y"-
~("e.e.vtree_y.OR2_tf[0]._y")->"e.e.vtree_y.OR2_tf[0].y"+
= "e.e.vtree_y.supply.vss" "e.e.vtree_y.ct.supply.vss"
= "e.e.vtree_y.supply.vdd" "e.e.vtree_y.ct.supply.vdd"
= "e.e.vtree_y.supply.vdd" "e.e.vtree_y.OR2_tf[0].vdd"
= "e.e.vtree_y.supply.vss" "e.e.vtree_y.OR2_tf[0].vss"
= "e.e.vtree_y.out" "e.e.vtree_y.ct.out"
= "e.e.vtree_y.in.d[0].d[0]" "e.e.vtree_y.in.d[0].f"
= "e.e.vtree_y.in.d[0].d[1]" "e.e.vtree_y.in.d[0].t"
= "e.e.vtree_y.in.d[0].d[0]" "e.e.vtree_y.in.d[0].f"
= "e.e.vtree_y.in.d[0].d[1]" "e.e.vtree_y.in.d[0].t"
= "e.e.vtree_y.in.d[0].d[0]" "e.e.vtree_y.OR2_tf[0].b"
= "e.e.vtree_y.in.d[0].d[0]" "e.e.vtree_y.in.d[0].f"
= "e.e.vtree_y.in.d[0].d[1]" "e.e.vtree_y.OR2_tf[0].a"
= "e.e.vtree_y.in.d[0].d[1]" "e.e.vtree_y.in.d[0].t"
= "e.e._in_y_v" "e.e._in_xy_v.b"
= "e.e._in_y_v" "e.e.vtree_y.out"
= "e.e._in_y_v" "e.e.x_ack.p2"
= "e.e._arb_out_x.d.d[0]" "e.e._arb_out_x.r"
= "e.e._arb_out_x.r" "e.e.Xarb.out.r"
= "e.e._arb_out_x.a" "e.e.Xarb.out.a"
= "e.e._arb_out_x.d.d[0]" "e.e.Xarb.out.d.d[0]"
= "e.e._arb_out_x.a" "e.e.X_ack_confirm.y"
"e.e.reset_buf.a"->"e.e.reset_buf._y"-
~("e.e.reset_buf.a")->"e.e.reset_buf._y"+
"e.e.reset_buf._y"->"e.e.reset_buf.y"-
~("e.e.reset_buf._y")->"e.e.reset_buf.y"+
"e.e.x_ack_arb[0].buf1.a"->"e.e.x_ack_arb[0].buf1._y"-
~("e.e.x_ack_arb[0].buf1.a")->"e.e.x_ack_arb[0].buf1._y"+
"e.e.x_ack_arb[0].buf1._y"->"e.e.x_ack_arb[0].buf1.y"-
~("e.e.x_ack_arb[0].buf1._y")->"e.e.x_ack_arb[0].buf1.y"+
= "e.e.x_ack_arb[0].supply.vdd" "e.e.x_ack_arb[0].buf1.vdd"
= "e.e.x_ack_arb[0].supply.vss" "e.e.x_ack_arb[0].buf1.vss"
= "e.e.x_ack_arb[0].out" "e.e.x_ack_arb[0].buf1.y"
= "e.e.x_ack_arb[0].in" "e.e.x_ack_arb[0].buf1.a"
"e.e.x_ack_arb[1].buf1.a"->"e.e.x_ack_arb[1].buf1._y"-
~("e.e.x_ack_arb[1].buf1.a")->"e.e.x_ack_arb[1].buf1._y"+
"e.e.x_ack_arb[1].buf1._y"->"e.e.x_ack_arb[1].buf1.y"-
~("e.e.x_ack_arb[1].buf1._y")->"e.e.x_ack_arb[1].buf1.y"+
= "e.e.x_ack_arb[1].supply.vdd" "e.e.x_ack_arb[1].buf1.vdd"
= "e.e.x_ack_arb[1].supply.vss" "e.e.x_ack_arb[1].buf1.vss"
= "e.e.x_ack_arb[1].out" "e.e.x_ack_arb[1].buf1.y"
= "e.e.x_ack_arb[1].in" "e.e.x_ack_arb[1].buf1.a"
= "e.e._x_v_B" "e.e.x_ack.p5"
= "e.e._x_v_B" "e.e.not_x_req_ortree.y"
"e.e.x_req_ortree.or2s[0].a"|"e.e.x_req_ortree.or2s[0].b"->"e.e.x_req_ortree.or2s[0]._y"-
~("e.e.x_req_ortree.or2s[0].a"|"e.e.x_req_ortree.or2s[0].b")->"e.e.x_req_ortree.or2s[0]._y"+
"e.e.x_req_ortree.or2s[0]._y"->"e.e.x_req_ortree.or2s[0].y"-
~("e.e.x_req_ortree.or2s[0]._y")->"e.e.x_req_ortree.or2s[0].y"+
= "e.e.x_req_ortree.supply.vdd" "e.e.x_req_ortree.or2s[0].vdd"
= "e.e.x_req_ortree.supply.vss" "e.e.x_req_ortree.or2s[0].vss"
= "e.e.x_req_ortree.in[0]" "e.e.x_req_ortree.or2s[0].a"
= "e.e.x_req_ortree.in[0]" "e.e.x_req_ortree.tmp[0]"
= "e.e.x_req_ortree.in[1]" "e.e.x_req_ortree.or2s[0].b"
= "e.e.x_req_ortree.in[1]" "e.e.x_req_ortree.tmp[1]"
= "e.e.x_req_ortree.out" "e.e.x_req_ortree.or2s[0].y"
= "e.e.x_req_ortree.out" "e.e.x_req_ortree.tmp[2]"
= "e.e._arb_out_y.d.d[0]" "e.e._arb_out_y.r"
= "e.e._arb_out_y.r" "e.e.Yarb.out.r"
= "e.e._arb_out_y.a" "e.e.Yarb.out.a"
= "e.e._arb_out_y.d.d[0]" "e.e.Yarb.out.d.d[0]"
= "e.e._arb_out_y.a" "e.e.Y_ack_confirm.y"
= "e.e._reset_BX" "e.e.x_ack.sr_B"
= "e.e._reset_BX" "e.e.x_ack.pr_B"
= "e.e._reset_BX" "e.e.X_ack_confirm.sr_B"
= "e.e._reset_BX" "e.e.X_ack_confirm.pr_B"
= "e.e._reset_BX" "e.e.Y_ack_confirm.reset_B"
= "e.e._reset_BX" "e.e.reset_bufarray.in"
= "e.e._reset_BX" "e.e.reset_buf.y"
= "e.e.reset_B" "e.e.buf_s_func.reset_B"
= "e.e.reset_B" "e.e.reset_buf.a"
"e.e.not_x_ack.a"->"e.e.not_x_ack.y"-
~("e.e.not_x_ack.a")->"e.e.not_x_ack.y"+
= "e.e._reset_BXX[0]" "e.e.reset_bufarray.out[0]"
= "e.e._reset_BXX[1]" "e.e.reset_bufarray.out[1]"
= "e.e._reset_BXX[2]" "e.e.reset_bufarray.out[2]"
= "e.e._reset_BXX[3]" "e.e.reset_bufarray.out[3]"
= "e.e._reset_BXX[0]" "e.e._reset_BXX[3]"
= "e.e._reset_BXX[0]" "e.e._reset_BXX[2]"
= "e.e._reset_BXX[0]" "e.e._reset_BXX[1]"
= "e.e._x_v" "e.e.x_ack.p3"
= "e.e._x_v" "e.e.not_x_req_ortree.a"
= "e.e._x_v" "e.e.x_req_ortree.out"
= "e.e._x_v" "e.e.Y_ack_confirm.p1"
"e.e.vtree_x.ct.b.a"->"e.e.vtree_x.ct.b._y"-
~("e.e.vtree_x.ct.b.a")->"e.e.vtree_x.ct.b._y"+
"e.e.vtree_x.ct.b._y"->"e.e.vtree_x.ct.b.y"-
~("e.e.vtree_x.ct.b._y")->"e.e.vtree_x.ct.b.y"+
= "e.e.vtree_x.ct.supply.vdd" "e.e.vtree_x.ct.b.vdd"
= "e.e.vtree_x.ct.supply.vss" "e.e.vtree_x.ct.b.vss"
= "e.e.vtree_x.ct.out" "e.e.vtree_x.ct.b.y"
= "e.e.vtree_x.ct.in[0]" "e.e.vtree_x.ct.b.a"
= "e.e.vtree_x.ct.in[0]" "e.e.vtree_x.OR2_tf[0].y"
"e.e.vtree_x.OR2_tf[0].a"|"e.e.vtree_x.OR2_tf[0].b"->"e.e.vtree_x.OR2_tf[0]._y"-
~("e.e.vtree_x.OR2_tf[0].a"|"e.e.vtree_x.OR2_tf[0].b")->"e.e.vtree_x.OR2_tf[0]._y"+
"e.e.vtree_x.OR2_tf[0]._y"->"e.e.vtree_x.OR2_tf[0].y"-
~("e.e.vtree_x.OR2_tf[0]._y")->"e.e.vtree_x.OR2_tf[0].y"+
= "e.e.vtree_x.supply.vss" "e.e.vtree_x.ct.supply.vss"
= "e.e.vtree_x.supply.vdd" "e.e.vtree_x.ct.supply.vdd"
= "e.e.vtree_x.supply.vdd" "e.e.vtree_x.OR2_tf[0].vdd"
= "e.e.vtree_x.supply.vss" "e.e.vtree_x.OR2_tf[0].vss"
= "e.e.vtree_x.out" "e.e.vtree_x.ct.out"
= "e.e.vtree_x.in.d[0].d[0]" "e.e.vtree_x.in.d[0].f"
= "e.e.vtree_x.in.d[0].d[1]" "e.e.vtree_x.in.d[0].t"
= "e.e.vtree_x.in.d[0].d[0]" "e.e.vtree_x.in.d[0].f"
= "e.e.vtree_x.in.d[0].d[1]" "e.e.vtree_x.in.d[0].t"
= "e.e.vtree_x.in.d[0].d[0]" "e.e.vtree_x.OR2_tf[0].b"
= "e.e.vtree_x.in.d[0].d[0]" "e.e.vtree_x.in.d[0].f"
= "e.e.vtree_x.in.d[0].d[1]" "e.e.vtree_x.OR2_tf[0].a"
= "e.e.vtree_x.in.d[0].d[1]" "e.e.vtree_x.in.d[0].t"
= "e.e.y_acks[0]" "e.e.y_encoder.in[0]"
= "e.e.y_acks[1]" "e.e.y_encoder.in[1]"
~"e.e.x_ack.p1"&~"e.e.x_ack.p2"&~"e.e.x_ack.p3"&~"e.e.x_ack.c1"|~"e.e.x_ack.p4"&~"e.e.x_ack.p5"&~"e.e.x_ack.c1"|~"e.e.x_ack.pr_B"->"e.e.x_ack.y"+
"e.e.x_ack.c1"&"e.e.x_ack.n1"&"e.e.x_ack.n2"&"e.e.x_ack.sr_B"->"e.e.x_ack.y"-
"e.e.buf_s_func.out_a_B_buf_t.buf1.a"->"e.e.buf_s_func.out_a_B_buf_t.buf1._y"-
~("e.e.buf_s_func.out_a_B_buf_t.buf1.a")->"e.e.buf_s_func.out_a_B_buf_t.buf1._y"+
"e.e.buf_s_func.out_a_B_buf_t.buf1._y"->"e.e.buf_s_func.out_a_B_buf_t.buf1.y"-
~("e.e.buf_s_func.out_a_B_buf_t.buf1._y")->"e.e.buf_s_func.out_a_B_buf_t.buf1.y"+
= "e.e.buf_s_func.out_a_B_buf_t.supply.vdd" "e.e.buf_s_func.out_a_B_buf_t.buf1.vdd"
= "e.e.buf_s_func.out_a_B_buf_t.supply.vss" "e.e.buf_s_func.out_a_B_buf_t.buf1.vss"
= "e.e.buf_s_func.out_a_B_buf_t.out[0]" "e.e.buf_s_func.out_a_B_buf_t.out[1]"
= "e.e.buf_s_func.out_a_B_buf_t.out[0]" "e.e.buf_s_func.out_a_B_buf_t.buf1.y"
= "e.e.buf_s_func.out_a_B_buf_t.in" "e.e.buf_s_func.out_a_B_buf_t.buf1.a"
"e.e.buf_s_func.reset_bufarray.buf1.a"->"e.e.buf_s_func.reset_bufarray.buf1._y"-
~("e.e.buf_s_func.reset_bufarray.buf1.a")->"e.e.buf_s_func.reset_bufarray.buf1._y"+
"e.e.buf_s_func.reset_bufarray.buf1._y"->"e.e.buf_s_func.reset_bufarray.buf1.y"-
~("e.e.buf_s_func.reset_bufarray.buf1._y")->"e.e.buf_s_func.reset_bufarray.buf1.y"+
= "e.e.buf_s_func.reset_bufarray.supply.vdd" "e.e.buf_s_func.reset_bufarray.buf1.vdd"
= "e.e.buf_s_func.reset_bufarray.supply.vss" "e.e.buf_s_func.reset_bufarray.buf1.vss"
= "e.e.buf_s_func.reset_bufarray.out[0]" "e.e.buf_s_func.reset_bufarray.out[1]"
= "e.e.buf_s_func.reset_bufarray.out[0]" "e.e.buf_s_func.reset_bufarray.buf1.y"
= "e.e.buf_s_func.reset_bufarray.in" "e.e.buf_s_func.reset_bufarray.buf1.a"
= "e.e.buf_s_func._en_X_f[0]" "e.e.buf_s_func.en_buf_f.out[0]"
= "e.e.buf_s_func._en_X_f[1]" "e.e.buf_s_func.en_buf_f.out[1]"
= "e.e.buf_s_func._en_X_f[0]" "e.e.buf_s_func.f_buf_func[1].c1"
= "e.e.buf_s_func._en_X_f[0]" "e.e.buf_s_func.f_buf_func[0].c1"
= "e.e.buf_s_func._en_X_f[0]" "e.e.buf_s_func._en_X_f[1]"
"e.e.buf_s_func.out_a_inv.a"->"e.e.buf_s_func.out_a_inv.y"-
~("e.e.buf_s_func.out_a_inv.a")->"e.e.buf_s_func.out_a_inv.y"+
= "e.e.buf_s_func._out_a_BX_f[0]" "e.e.buf_s_func.out_a_B_buf_t.out[0]"
= "e.e.buf_s_func._out_a_BX_f[1]" "e.e.buf_s_func.out_a_B_buf_t.out[1]"
= "e.e.buf_s_func._out_a_BX_f[0]" "e.e.buf_s_func.f_buf_func[1].c2"
= "e.e.buf_s_func._out_a_BX_f[0]" "e.e.buf_s_func.f_buf_func[0].c2"
= "e.e.buf_s_func._out_a_BX_f[0]" "e.e.buf_s_func._out_a_BX_f[1]"
= "e.e.buf_s_func.supply.vss" "e.e.buf_s_func.in_v_buf_f.supply.vss"
= "e.e.buf_s_func.supply.vdd" "e.e.buf_s_func.in_v_buf_f.supply.vdd"
= "e.e.buf_s_func.supply.vss" "e.e.buf_s_func.in_v_buf_t.supply.vss"
= "e.e.buf_s_func.supply.vdd" "e.e.buf_s_func.in_v_buf_t.supply.vdd"
= "e.e.buf_s_func.supply.vss" "e.e.buf_s_func.out_a_B_buf_t.supply.vss"
= "e.e.buf_s_func.supply.vdd" "e.e.buf_s_func.out_a_B_buf_t.supply.vdd"
= "e.e.buf_s_func.supply.vss" "e.e.buf_s_func.out_a_B_buf_f.supply.vss"
= "e.e.buf_s_func.supply.vdd" "e.e.buf_s_func.out_a_B_buf_f.supply.vdd"
= "e.e.buf_s_func.supply.vss" "e.e.buf_s_func.en_buf_f.supply.vss"
= "e.e.buf_s_func.supply.vdd" "e.e.buf_s_func.en_buf_f.supply.vdd"
= "e.e.buf_s_func.supply.vss" "e.e.buf_s_func.en_buf_t.supply.vss"
= "e.e.buf_s_func.supply.vdd" "e.e.buf_s_func.en_buf_t.supply.vdd"
= "e.e.buf_s_func.supply.vss" "e.e.buf_s_func.reset_bufarray.supply.vss"
= "e.e.buf_s_func.supply.vdd" "e.e.buf_s_func.reset_bufarray.supply.vdd"
= "e.e.buf_s_func.supply.vdd" "e.e.buf_s_func.t_buf_func[1].vdd"
= "e.e.buf_s_func.supply.vdd" "e.e.buf_s_func.f_buf_func[1].vdd"
= "e.e.buf_s_func.supply.vdd" "e.e.buf_s_func.t_buf_func[0].vdd"
= "e.e.buf_s_func.supply.vdd" "e.e.buf_s_func.f_buf_func[0].vdd"
= "e.e.buf_s_func.supply.vdd" "e.e.buf_s_func.in_v_prebuf.vdd"
= "e.e.buf_s_func.supply.vdd" "e.e.buf_s_func.out_a_inv.vdd"
= "e.e.buf_s_func.supply.vdd" "e.e.buf_s_func.reset_buf.vdd"
= "e.e.buf_s_func.supply.vss" "e.e.buf_s_func.t_buf_func[1].vss"
= "e.e.buf_s_func.supply.vss" "e.e.buf_s_func.f_buf_func[1].vss"
= "e.e.buf_s_func.supply.vss" "e.e.buf_s_func.t_buf_func[0].vss"
= "e.e.buf_s_func.supply.vss" "e.e.buf_s_func.f_buf_func[0].vss"
= "e.e.buf_s_func.supply.vss" "e.e.buf_s_func.in_v_prebuf.vss"
= "e.e.buf_s_func.supply.vss" "e.e.buf_s_func.out_a_inv.vss"
= "e.e.buf_s_func.supply.vss" "e.e.buf_s_func.reset_buf.vss"
"e.e.buf_s_func.in_v_prebuf.a"->"e.e.buf_s_func.in_v_prebuf._y"-
~("e.e.buf_s_func.in_v_prebuf.a")->"e.e.buf_s_func.in_v_prebuf._y"+
"e.e.buf_s_func.in_v_prebuf._y"->"e.e.buf_s_func.in_v_prebuf.y"-
~("e.e.buf_s_func.in_v_prebuf._y")->"e.e.buf_s_func.in_v_prebuf.y"+
"e.e.buf_s_func.out_a_B_buf_f.buf1.a"->"e.e.buf_s_func.out_a_B_buf_f.buf1._y"-
~("e.e.buf_s_func.out_a_B_buf_f.buf1.a")->"e.e.buf_s_func.out_a_B_buf_f.buf1._y"+
"e.e.buf_s_func.out_a_B_buf_f.buf1._y"->"e.e.buf_s_func.out_a_B_buf_f.buf1.y"-
~("e.e.buf_s_func.out_a_B_buf_f.buf1._y")->"e.e.buf_s_func.out_a_B_buf_f.buf1.y"+
= "e.e.buf_s_func.out_a_B_buf_f.supply.vdd" "e.e.buf_s_func.out_a_B_buf_f.buf1.vdd"
= "e.e.buf_s_func.out_a_B_buf_f.supply.vss" "e.e.buf_s_func.out_a_B_buf_f.buf1.vss"
= "e.e.buf_s_func.out_a_B_buf_f.out[0]" "e.e.buf_s_func.out_a_B_buf_f.out[1]"
= "e.e.buf_s_func.out_a_B_buf_f.out[0]" "e.e.buf_s_func.out_a_B_buf_f.buf1.y"
= "e.e.buf_s_func.out_a_B_buf_f.in" "e.e.buf_s_func.out_a_B_buf_f.buf1.a"
= "e.e.buf_s_func.in_v" "e.e.buf_s_func.in_v_prebuf.a"
= "e.e.buf_s_func.out.d.d[0].d[0]" "e.e.buf_s_func.out.d.d[0].f"
= "e.e.buf_s_func.out.d.d[0].d[1]" "e.e.buf_s_func.out.d.d[0].t"
= "e.e.buf_s_func.out.d.d[1].d[0]" "e.e.buf_s_func.out.d.d[1].f"
= "e.e.buf_s_func.out.d.d[1].d[1]" "e.e.buf_s_func.out.d.d[1].t"
= "e.e.buf_s_func.out.d.d[1].d[0]" "e.e.buf_s_func.out.d.d[1].f"
= "e.e.buf_s_func.out.d.d[1].d[1]" "e.e.buf_s_func.out.d.d[1].t"
= "e.e.buf_s_func.out.d.d[0].d[0]" "e.e.buf_s_func.out.d.d[0].f"
= "e.e.buf_s_func.out.d.d[0].d[1]" "e.e.buf_s_func.out.d.d[0].t"
= "e.e.buf_s_func.out.d.d[1].d[0]" "e.e.buf_s_func.out.d.d[1].f"
= "e.e.buf_s_func.out.d.d[1].d[1]" "e.e.buf_s_func.out.d.d[1].t"
= "e.e.buf_s_func.out.d.d[0].d[0]" "e.e.buf_s_func.out.d.d[0].f"
= "e.e.buf_s_func.out.d.d[0].d[1]" "e.e.buf_s_func.out.d.d[0].t"
= "e.e.buf_s_func.out.a" "e.e.buf_s_func.out_a_inv.a"
= "e.e.buf_s_func.out.d.d[1].d[0]" "e.e.buf_s_func.f_buf_func[1].y"
= "e.e.buf_s_func.out.d.d[1].d[0]" "e.e.buf_s_func.out.d.d[1].f"
= "e.e.buf_s_func.out.d.d[1].d[1]" "e.e.buf_s_func.t_buf_func[1].y"
= "e.e.buf_s_func.out.d.d[1].d[1]" "e.e.buf_s_func.out.d.d[1].t"
= "e.e.buf_s_func.out.d.d[0].d[0]" "e.e.buf_s_func.f_buf_func[0].y"
= "e.e.buf_s_func.out.d.d[0].d[0]" "e.e.buf_s_func.out.d.d[0].f"
= "e.e.buf_s_func.out.d.d[0].d[1]" "e.e.buf_s_func.t_buf_func[0].y"
= "e.e.buf_s_func.out.d.d[0].d[1]" "e.e.buf_s_func.out.d.d[0].t"
= "e.e.buf_s_func.in.d[0].d[0]" "e.e.buf_s_func.in.d[0].f"
= "e.e.buf_s_func.in.d[0].d[1]" "e.e.buf_s_func.in.d[0].t"
= "e.e.buf_s_func.in.d[1].d[0]" "e.e.buf_s_func.in.d[1].f"
= "e.e.buf_s_func.in.d[1].d[1]" "e.e.buf_s_func.in.d[1].t"
= "e.e.buf_s_func.in.d[1].d[0]" "e.e.buf_s_func.in.d[1].f"
= "e.e.buf_s_func.in.d[1].d[1]" "e.e.buf_s_func.in.d[1].t"
= "e.e.buf_s_func.in.d[0].d[0]" "e.e.buf_s_func.in.d[0].f"
= "e.e.buf_s_func.in.d[0].d[1]" "e.e.buf_s_func.in.d[0].t"
= "e.e.buf_s_func.in.d[1].d[0]" "e.e.buf_s_func.f_buf_func[1].n1"
= "e.e.buf_s_func.in.d[1].d[0]" "e.e.buf_s_func.in.d[1].f"
= "e.e.buf_s_func.in.d[1].d[1]" "e.e.buf_s_func.t_buf_func[1].n1"
= "e.e.buf_s_func.in.d[1].d[1]" "e.e.buf_s_func.in.d[1].t"
= "e.e.buf_s_func.in.d[0].d[0]" "e.e.buf_s_func.f_buf_func[0].n1"
= "e.e.buf_s_func.in.d[0].d[0]" "e.e.buf_s_func.in.d[0].f"
= "e.e.buf_s_func.in.d[0].d[1]" "e.e.buf_s_func.t_buf_func[0].n1"
= "e.e.buf_s_func.in.d[0].d[1]" "e.e.buf_s_func.in.d[0].t"
"e.e.buf_s_func.in_v_buf_f.buf1.a"->"e.e.buf_s_func.in_v_buf_f.buf1._y"-
~("e.e.buf_s_func.in_v_buf_f.buf1.a")->"e.e.buf_s_func.in_v_buf_f.buf1._y"+
"e.e.buf_s_func.in_v_buf_f.buf1._y"->"e.e.buf_s_func.in_v_buf_f.buf1.y"-
~("e.e.buf_s_func.in_v_buf_f.buf1._y")->"e.e.buf_s_func.in_v_buf_f.buf1.y"+
= "e.e.buf_s_func.in_v_buf_f.supply.vdd" "e.e.buf_s_func.in_v_buf_f.buf1.vdd"
= "e.e.buf_s_func.in_v_buf_f.supply.vss" "e.e.buf_s_func.in_v_buf_f.buf1.vss"
= "e.e.buf_s_func.in_v_buf_f.out[0]" "e.e.buf_s_func.in_v_buf_f.out[1]"
= "e.e.buf_s_func.in_v_buf_f.out[0]" "e.e.buf_s_func.in_v_buf_f.buf1.y"
= "e.e.buf_s_func.in_v_buf_f.in" "e.e.buf_s_func.in_v_buf_f.buf1.a"
"e.e.buf_s_func.reset_buf.a"->"e.e.buf_s_func.reset_buf._y"-
~("e.e.buf_s_func.reset_buf.a")->"e.e.buf_s_func.reset_buf._y"+
"e.e.buf_s_func.reset_buf._y"->"e.e.buf_s_func.reset_buf.y"-
~("e.e.buf_s_func.reset_buf._y")->"e.e.buf_s_func.reset_buf.y"+
= "e.e.buf_s_func.en" "e.e.buf_s_func.en_buf_f.in"
= "e.e.buf_s_func.en" "e.e.buf_s_func.en_buf_t.in"
"e.e.buf_s_func.in_v_buf_t.buf1.a"->"e.e.buf_s_func.in_v_buf_t.buf1._y"-
~("e.e.buf_s_func.in_v_buf_t.buf1.a")->"e.e.buf_s_func.in_v_buf_t.buf1._y"+
"e.e.buf_s_func.in_v_buf_t.buf1._y"->"e.e.buf_s_func.in_v_buf_t.buf1.y"-
~("e.e.buf_s_func.in_v_buf_t.buf1._y")->"e.e.buf_s_func.in_v_buf_t.buf1.y"+
= "e.e.buf_s_func.in_v_buf_t.supply.vdd" "e.e.buf_s_func.in_v_buf_t.buf1.vdd"
= "e.e.buf_s_func.in_v_buf_t.supply.vss" "e.e.buf_s_func.in_v_buf_t.buf1.vss"
= "e.e.buf_s_func.in_v_buf_t.out[0]" "e.e.buf_s_func.in_v_buf_t.out[1]"
= "e.e.buf_s_func.in_v_buf_t.out[0]" "e.e.buf_s_func.in_v_buf_t.buf1.y"
= "e.e.buf_s_func.in_v_buf_t.in" "e.e.buf_s_func.in_v_buf_t.buf1.a"
= "e.e.buf_s_func._reset_BX" "e.e.buf_s_func.reset_bufarray.in"
= "e.e.buf_s_func._reset_BX" "e.e.buf_s_func.reset_buf.y"
= "e.e.buf_s_func._out_a_BX_t[0]" "e.e.buf_s_func.out_a_B_buf_f.out[0]"
= "e.e.buf_s_func._out_a_BX_t[1]" "e.e.buf_s_func.out_a_B_buf_f.out[1]"
= "e.e.buf_s_func._out_a_BX_t[0]" "e.e.buf_s_func.t_buf_func[1].c2"
= "e.e.buf_s_func._out_a_BX_t[0]" "e.e.buf_s_func.t_buf_func[0].c2"
= "e.e.buf_s_func._out_a_BX_t[0]" "e.e.buf_s_func._out_a_BX_t[1]"
= "e.e.buf_s_func.reset_B" "e.e.buf_s_func.reset_buf.a"
"e.e.buf_s_func.en_buf_f.buf1.a"->"e.e.buf_s_func.en_buf_f.buf1._y"-
~("e.e.buf_s_func.en_buf_f.buf1.a")->"e.e.buf_s_func.en_buf_f.buf1._y"+
"e.e.buf_s_func.en_buf_f.buf1._y"->"e.e.buf_s_func.en_buf_f.buf1.y"-
~("e.e.buf_s_func.en_buf_f.buf1._y")->"e.e.buf_s_func.en_buf_f.buf1.y"+
= "e.e.buf_s_func.en_buf_f.supply.vdd" "e.e.buf_s_func.en_buf_f.buf1.vdd"
= "e.e.buf_s_func.en_buf_f.supply.vss" "e.e.buf_s_func.en_buf_f.buf1.vss"
= "e.e.buf_s_func.en_buf_f.out[0]" "e.e.buf_s_func.en_buf_f.out[1]"
= "e.e.buf_s_func.en_buf_f.out[0]" "e.e.buf_s_func.en_buf_f.buf1.y"
= "e.e.buf_s_func.en_buf_f.in" "e.e.buf_s_func.en_buf_f.buf1.a"
"e.e.buf_s_func.en_buf_t.buf1.a"->"e.e.buf_s_func.en_buf_t.buf1._y"-
~("e.e.buf_s_func.en_buf_t.buf1.a")->"e.e.buf_s_func.en_buf_t.buf1._y"+
"e.e.buf_s_func.en_buf_t.buf1._y"->"e.e.buf_s_func.en_buf_t.buf1.y"-
~("e.e.buf_s_func.en_buf_t.buf1._y")->"e.e.buf_s_func.en_buf_t.buf1.y"+
= "e.e.buf_s_func.en_buf_t.supply.vdd" "e.e.buf_s_func.en_buf_t.buf1.vdd"
= "e.e.buf_s_func.en_buf_t.supply.vss" "e.e.buf_s_func.en_buf_t.buf1.vss"
= "e.e.buf_s_func.en_buf_t.out[0]" "e.e.buf_s_func.en_buf_t.out[1]"
= "e.e.buf_s_func.en_buf_t.out[0]" "e.e.buf_s_func.en_buf_t.buf1.y"
= "e.e.buf_s_func.en_buf_t.in" "e.e.buf_s_func.en_buf_t.buf1.a"
= "e.e.buf_s_func._reset_BXX[0]" "e.e.buf_s_func.reset_bufarray.out[0]"
= "e.e.buf_s_func._reset_BXX[1]" "e.e.buf_s_func.reset_bufarray.out[1]"
= "e.e.buf_s_func._reset_BXX[0]" "e.e.buf_s_func.f_buf_func[1].sr_B"
= "e.e.buf_s_func._reset_BXX[0]" "e.e.buf_s_func.f_buf_func[1].pr_B"
= "e.e.buf_s_func._reset_BXX[0]" "e.e.buf_s_func.t_buf_func[1].sr_B"
= "e.e.buf_s_func._reset_BXX[0]" "e.e.buf_s_func.t_buf_func[1].pr_B"
= "e.e.buf_s_func._reset_BXX[0]" "e.e.buf_s_func.f_buf_func[0].sr_B"
= "e.e.buf_s_func._reset_BXX[0]" "e.e.buf_s_func.f_buf_func[0].pr_B"
= "e.e.buf_s_func._reset_BXX[0]" "e.e.buf_s_func.t_buf_func[0].sr_B"
= "e.e.buf_s_func._reset_BXX[0]" "e.e.buf_s_func.t_buf_func[0].pr_B"
= "e.e.buf_s_func._reset_BXX[0]" "e.e.buf_s_func._reset_BXX[1]"
= "e.e.buf_s_func._out_a_B" "e.e.buf_s_func.out_a_B_buf_t.in"
= "e.e.buf_s_func._out_a_B" "e.e.buf_s_func.out_a_B_buf_f.in"
= "e.e.buf_s_func._out_a_B" "e.e.buf_s_func.out_a_inv.y"
= "e.e.buf_s_func._in_vX" "e.e.buf_s_func.in_v_buf_f.in"
= "e.e.buf_s_func._in_vX" "e.e.buf_s_func.in_v_buf_t.in"
= "e.e.buf_s_func._in_vX" "e.e.buf_s_func.in_v_prebuf.y"
= "e.e.buf_s_func._in_vXX_t[0]" "e.e.buf_s_func.in_v_buf_t.out[0]"
= "e.e.buf_s_func._in_vXX_t[1]" "e.e.buf_s_func.in_v_buf_t.out[1]"
= "e.e.buf_s_func._in_vXX_t[0]" "e.e.buf_s_func.t_buf_func[1].n2"
= "e.e.buf_s_func._in_vXX_t[0]" "e.e.buf_s_func.t_buf_func[0].n2"
= "e.e.buf_s_func._in_vXX_t[0]" "e.e.buf_s_func._in_vXX_t[1]"
= "e.e.buf_s_func._in_vXX_f[0]" "e.e.buf_s_func.in_v_buf_f.out[0]"
= "e.e.buf_s_func._in_vXX_f[1]" "e.e.buf_s_func.in_v_buf_f.out[1]"
= "e.e.buf_s_func._in_vXX_f[0]" "e.e.buf_s_func.f_buf_func[1].n2"
= "e.e.buf_s_func._in_vXX_f[0]" "e.e.buf_s_func.f_buf_func[0].n2"
= "e.e.buf_s_func._in_vXX_f[0]" "e.e.buf_s_func._in_vXX_f[1]"
= "e.e.buf_s_func._en_X_t[0]" "e.e.buf_s_func.en_buf_t.out[0]"
= "e.e.buf_s_func._en_X_t[1]" "e.e.buf_s_func.en_buf_t.out[1]"
= "e.e.buf_s_func._en_X_t[0]" "e.e.buf_s_func.t_buf_func[1].c1"
= "e.e.buf_s_func._en_X_t[0]" "e.e.buf_s_func.t_buf_func[0].c1"
= "e.e.buf_s_func._en_X_t[0]" "e.e.buf_s_func._en_X_t[1]"
~"e.e.buf_s_func.f_buf_func[0].c1"&~"e.e.buf_s_func.f_buf_func[0].c2"|~"e.e.buf_s_func.f_buf_func[0].pr_B"->"e.e.buf_s_func.f_buf_func[0]._y"+
"e.e.buf_s_func.f_buf_func[0].c1"&"e.e.buf_s_func.f_buf_func[0].c2"&"e.e.buf_s_func.f_buf_func[0].n1"&"e.e.buf_s_func.f_buf_func[0].n2"&"e.e.buf_s_func.f_buf_func[0].sr_B"->"e.e.buf_s_func.f_buf_func[0]._y"-
"e.e.buf_s_func.f_buf_func[0]._y"->"e.e.buf_s_func.f_buf_func[0].y"-
~("e.e.buf_s_func.f_buf_func[0]._y")->"e.e.buf_s_func.f_buf_func[0].y"+
~"e.e.buf_s_func.f_buf_func[1].c1"&~"e.e.buf_s_func.f_buf_func[1].c2"|~"e.e.buf_s_func.f_buf_func[1].pr_B"->"e.e.buf_s_func.f_buf_func[1]._y"+
"e.e.buf_s_func.f_buf_func[1].c1"&"e.e.buf_s_func.f_buf_func[1].c2"&"e.e.buf_s_func.f_buf_func[1].n1"&"e.e.buf_s_func.f_buf_func[1].n2"&"e.e.buf_s_func.f_buf_func[1].sr_B"->"e.e.buf_s_func.f_buf_func[1]._y"-
"e.e.buf_s_func.f_buf_func[1]._y"->"e.e.buf_s_func.f_buf_func[1].y"-
~("e.e.buf_s_func.f_buf_func[1]._y")->"e.e.buf_s_func.f_buf_func[1].y"+
~"e.e.buf_s_func.t_buf_func[0].c1"&~"e.e.buf_s_func.t_buf_func[0].c2"|~"e.e.buf_s_func.t_buf_func[0].pr_B"->"e.e.buf_s_func.t_buf_func[0]._y"+
"e.e.buf_s_func.t_buf_func[0].c1"&"e.e.buf_s_func.t_buf_func[0].c2"&"e.e.buf_s_func.t_buf_func[0].n1"&"e.e.buf_s_func.t_buf_func[0].n2"&"e.e.buf_s_func.t_buf_func[0].sr_B"->"e.e.buf_s_func.t_buf_func[0]._y"-
"e.e.buf_s_func.t_buf_func[0]._y"->"e.e.buf_s_func.t_buf_func[0].y"-
~("e.e.buf_s_func.t_buf_func[0]._y")->"e.e.buf_s_func.t_buf_func[0].y"+
~"e.e.buf_s_func.t_buf_func[1].c1"&~"e.e.buf_s_func.t_buf_func[1].c2"|~"e.e.buf_s_func.t_buf_func[1].pr_B"->"e.e.buf_s_func.t_buf_func[1]._y"+
"e.e.buf_s_func.t_buf_func[1].c1"&"e.e.buf_s_func.t_buf_func[1].c2"&"e.e.buf_s_func.t_buf_func[1].n1"&"e.e.buf_s_func.t_buf_func[1].n2"&"e.e.buf_s_func.t_buf_func[1].sr_B"->"e.e.buf_s_func.t_buf_func[1]._y"-
"e.e.buf_s_func.t_buf_func[1]._y"->"e.e.buf_s_func.t_buf_func[1].y"-
~("e.e.buf_s_func.t_buf_func[1]._y")->"e.e.buf_s_func.t_buf_func[1].y"+
= "e.e._in_x.d.d[0].d[0]" "e.e._in_x.d.d[0].f"
= "e.e._in_x.d.d[0].d[1]" "e.e._in_x.d.d[0].t"
= "e.e._in_x.d.d[1].d[0]" "e.e._in_x.d.d[1].f"
= "e.e._in_x.d.d[1].d[1]" "e.e._in_x.d.d[1].t"
= "e.e._in_x.d.d[1].d[0]" "e.e._in_x.d.d[1].f"
= "e.e._in_x.d.d[1].d[1]" "e.e._in_x.d.d[1].t"
= "e.e._in_x.d.d[0].d[0]" "e.e._in_x.d.d[0].f"
= "e.e._in_x.d.d[0].d[1]" "e.e._in_x.d.d[0].t"
= "e.e._in_x.d.d[1].d[0]" "e.e._in_x.d.d[1].f"
= "e.e._in_x.d.d[1].d[1]" "e.e._in_x.d.d[1].t"
= "e.e._in_x.d.d[0].d[0]" "e.e._in_x.d.d[0].f"
= "e.e._in_x.d.d[0].d[1]" "e.e._in_x.d.d[0].t"
= "e.e.supply.vss" "e.e.buf_s_func.supply.vss"
= "e.e.supply.vdd" "e.e.buf_s_func.supply.vdd"
= "e.e.supply.vss" "e.e.vtree_y.supply.vss"
= "e.e.supply.vdd" "e.e.vtree_y.supply.vdd"
= "e.e.supply.vss" "e.e.vtree_x.supply.vss"
= "e.e.supply.vdd" "e.e.vtree_x.supply.vdd"
= "e.e.supply.vss" "e.e.y_encoder.supply.vss"
= "e.e.supply.vdd" "e.e.y_encoder.supply.vdd"
= "e.e.supply.vss" "e.e.x_encoder.supply.vss"
= "e.e.supply.vdd" "e.e.x_encoder.supply.vdd"
= "e.e.supply.vss" "e.e.x_req_ortree.supply.vss"
= "e.e.supply.vdd" "e.e.x_req_ortree.supply.vdd"
= "e.e.supply.vss" "e.e.y_ack_arb[1].supply.vss"
= "e.e.supply.vdd" "e.e.y_ack_arb[1].supply.vdd"
= "e.e.supply.vss" "e.e.y_ack_arb[0].supply.vss"
= "e.e.supply.vdd" "e.e.y_ack_arb[0].supply.vdd"
= "e.e.supply.vss" "e.e.x_ack_arb[1].supply.vss"
= "e.e.supply.vdd" "e.e.x_ack_arb[1].supply.vdd"
= "e.e.supply.vss" "e.e.x_ack_arb[0].supply.vss"
= "e.e.supply.vdd" "e.e.x_ack_arb[0].supply.vdd"
= "e.e.supply.vss" "e.e.Yarb.supply.vss"
= "e.e.supply.vdd" "e.e.Yarb.supply.vdd"
= "e.e.supply.vss" "e.e.Xarb.supply.vss"
= "e.e.supply.vdd" "e.e.Xarb.supply.vdd"
= "e.e.supply.vss" "e.e.reset_bufarray.supply.vss"
= "e.e.supply.vdd" "e.e.reset_bufarray.supply.vdd"
= "e.e.supply.vdd" "e.e._in_xy_v.vdd"
= "e.e.supply.vdd" "e.e.enabling.vdd"
= "e.e.supply.vdd" "e.e.not_x_ack.vdd"
= "e.e.supply.vdd" "e.e.x_ack.vdd"
= "e.e.supply.vdd" "e.e.X_ack_confirm.vdd"
= "e.e.supply.vdd" "e.e.Y_ack_confirm.vdd"
= "e.e.supply.vdd" "e.e.reset_buf.vdd"
= "e.e.supply.vss" "e.e._in_xy_v.vss"
= "e.e.supply.vss" "e.e.enabling.vss"
= "e.e.supply.vss" "e.e.not_x_ack.vss"
= "e.e.supply.vss" "e.e.x_ack.vss"
= "e.e.supply.vss" "e.e.X_ack_confirm.vss"
= "e.e.supply.vss" "e.e.Y_ack_confirm.vss"
= "e.e.supply.vss" "e.e.reset_buf.vss"
= "e.e._in_x_v" "e.e._in_xy_v.a"
= "e.e._in_x_v" "e.e.vtree_x.out"
= "e.e._in_x_v" "e.e.x_ack.n2"
= "e.e._in_x_v" "e.e.x_ack.p1"
= "e.e._in_x_v" "e.e.x_ack.p4"
= "e.e._in_x_v" "e.e.Y_ack_confirm.p2"
= "e.e.out.d.d[0].d[0]" "e.e.out.d.d[0].f"
= "e.e.out.d.d[0].d[1]" "e.e.out.d.d[0].t"
= "e.e.out.d.d[1].d[0]" "e.e.out.d.d[1].f"
= "e.e.out.d.d[1].d[1]" "e.e.out.d.d[1].t"
= "e.e.out.d.d[1].d[0]" "e.e.out.d.d[1].f"
= "e.e.out.d.d[1].d[1]" "e.e.out.d.d[1].t"
= "e.e.out.d.d[0].d[0]" "e.e.out.d.d[0].f"
= "e.e.out.d.d[0].d[1]" "e.e.out.d.d[0].t"
= "e.e.out.d.d[1].d[0]" "e.e.out.d.d[1].f"
= "e.e.out.d.d[1].d[1]" "e.e.out.d.d[1].t"
= "e.e.out.d.d[0].d[0]" "e.e.out.d.d[0].f"
= "e.e.out.d.d[0].d[1]" "e.e.out.d.d[0].t"
= "e.e.out.v" "e.e.buf_s_func.out.v"
= "e.e.out.a" "e.e.buf_s_func.out.a"
= "e.e.out.d.d[0].f" "e.e.buf_s_func.out.d.d[0].f"
= "e.e.out.d.d[0].t" "e.e.buf_s_func.out.d.d[0].t"
= "e.e.out.d.d[0].d[0]" "e.e.buf_s_func.out.d.d[0].d[0]"
= "e.e.out.d.d[0].d[1]" "e.e.buf_s_func.out.d.d[0].d[1]"
= "e.e.out.d.d[1].f" "e.e.buf_s_func.out.d.d[1].f"
= "e.e.out.d.d[1].t" "e.e.buf_s_func.out.d.d[1].t"
= "e.e.out.d.d[1].d[0]" "e.e.buf_s_func.out.d.d[1].d[0]"
= "e.e.out.d.d[1].d[1]" "e.e.buf_s_func.out.d.d[1].d[1]"
= "e.e.out.a" "e.e.enabling.p1"
= "e.e.out.v" "e.e.enabling.p2"
= "e.e.out.v" "e.e.x_ack.n1"
= "e.e.out.d.d[1].d[0]" "e.e.out.d.d[1].f"
= "e.e.out.d.d[1].d[1]" "e.e.out.d.d[1].t"
= "e.e.out.d.d[0].d[0]" "e.e.out.d.d[0].f"
= "e.e.out.d.d[0].d[1]" "e.e.out.d.d[0].t"
= "e.e.Yarb.arbs[0].in1.d.d[0]" "e.e.Yarb.arbs[0].in1.r"
= "e.e.Yarb.arbs[0].in1.a" "e.e.Yarb.arbs[0].arbiter.d"
= "e.e.Yarb.arbs[0].in1.a" "e.e.Yarb.arbs[0].ack_cell1.y"
= "e.e.Yarb.arbs[0].in1.d.d[0]" "e.e.Yarb.arbs[0].arbiter.a"
= "e.e.Yarb.arbs[0].in1.d.d[0]" "e.e.Yarb.arbs[0].in1.r"
~"e.e.Yarb.arbs[0].ack_cell1.c1"&~"e.e.Yarb.arbs[0].ack_cell1.c2"->"e.e.Yarb.arbs[0].ack_cell1._y"+
"e.e.Yarb.arbs[0].ack_cell1.c1"&"e.e.Yarb.arbs[0].ack_cell1.c2"->"e.e.Yarb.arbs[0].ack_cell1._y"-
"e.e.Yarb.arbs[0].ack_cell1._y"->"e.e.Yarb.arbs[0].ack_cell1.y"-
~("e.e.Yarb.arbs[0].ack_cell1._y")->"e.e.Yarb.arbs[0].ack_cell1.y"+
= "e.e.Yarb.arbs[0].in2.d.d[0]" "e.e.Yarb.arbs[0].in2.r"
= "e.e.Yarb.arbs[0].in2.a" "e.e.Yarb.arbs[0].arbiter.c"
= "e.e.Yarb.arbs[0].in2.a" "e.e.Yarb.arbs[0].ack_cell2.y"
= "e.e.Yarb.arbs[0].in2.d.d[0]" "e.e.Yarb.arbs[0].arbiter.b"
= "e.e.Yarb.arbs[0].in2.d.d[0]" "e.e.Yarb.arbs[0].in2.r"
= "e.e.Yarb.arbs[0].supply.vdd" "e.e.Yarb.arbs[0].arbiter.vdd"
= "e.e.Yarb.arbs[0].supply.vdd" "e.e.Yarb.arbs[0].or_cell.vdd"
= "e.e.Yarb.arbs[0].supply.vdd" "e.e.Yarb.arbs[0].ack_cell2.vdd"
= "e.e.Yarb.arbs[0].supply.vdd" "e.e.Yarb.arbs[0].ack_cell1.vdd"
= "e.e.Yarb.arbs[0].supply.vss" "e.e.Yarb.arbs[0].arbiter.vss"
= "e.e.Yarb.arbs[0].supply.vss" "e.e.Yarb.arbs[0].or_cell.vss"
= "e.e.Yarb.arbs[0].supply.vss" "e.e.Yarb.arbs[0].ack_cell2.vss"
= "e.e.Yarb.arbs[0].supply.vss" "e.e.Yarb.arbs[0].ack_cell1.vss"
"e.e.Yarb.arbs[0].arbiter.a"&"e.e.Yarb.arbs[0].arbiter._y2"->"e.e.Yarb.arbs[0].arbiter._y1"-
~"e.e.Yarb.arbs[0].arbiter.a"|~"e.e.Yarb.arbs[0].arbiter._y2"->"e.e.Yarb.arbs[0].arbiter._y1"+
"e.e.Yarb.arbs[0].arbiter.b"&"e.e.Yarb.arbs[0].arbiter._y1"->"e.e.Yarb.arbs[0].arbiter._y2"-
~"e.e.Yarb.arbs[0].arbiter.b"|~"e.e.Yarb.arbs[0].arbiter._y1"->"e.e.Yarb.arbs[0].arbiter._y2"+
"e.e.Yarb.arbs[0].arbiter._y1"|"e.e.Yarb.arbs[0].arbiter.c"->"e.e.Yarb.arbs[0].arbiter.y1"-
~("e.e.Yarb.arbs[0].arbiter._y1"|"e.e.Yarb.arbs[0].arbiter.c")->"e.e.Yarb.arbs[0].arbiter.y1"+
"e.e.Yarb.arbs[0].arbiter._y2"|"e.e.Yarb.arbs[0].arbiter.d"->"e.e.Yarb.arbs[0].arbiter.y2"-
~("e.e.Yarb.arbs[0].arbiter._y2"|"e.e.Yarb.arbs[0].arbiter.d")->"e.e.Yarb.arbs[0].arbiter.y2"+
mk_excllo("e.e.Yarb.arbs[0].arbiter._y1","e.e.Yarb.arbs[0].arbiter._y2")
= "e.e.Yarb.arbs[0]._y1_arb" "e.e.Yarb.arbs[0].arbiter.y1"
= "e.e.Yarb.arbs[0]._y1_arb" "e.e.Yarb.arbs[0].or_cell.a"
= "e.e.Yarb.arbs[0]._y1_arb" "e.e.Yarb.arbs[0].ack_cell1.c2"
~"e.e.Yarb.arbs[0].ack_cell2.c1"&~"e.e.Yarb.arbs[0].ack_cell2.c2"->"e.e.Yarb.arbs[0].ack_cell2._y"+
"e.e.Yarb.arbs[0].ack_cell2.c1"&"e.e.Yarb.arbs[0].ack_cell2.c2"->"e.e.Yarb.arbs[0].ack_cell2._y"-
"e.e.Yarb.arbs[0].ack_cell2._y"->"e.e.Yarb.arbs[0].ack_cell2.y"-
~("e.e.Yarb.arbs[0].ack_cell2._y")->"e.e.Yarb.arbs[0].ack_cell2.y"+
"e.e.Yarb.arbs[0].or_cell.a"|"e.e.Yarb.arbs[0].or_cell.b"->"e.e.Yarb.arbs[0].or_cell._y"-
~("e.e.Yarb.arbs[0].or_cell.a"|"e.e.Yarb.arbs[0].or_cell.b")->"e.e.Yarb.arbs[0].or_cell._y"+
"e.e.Yarb.arbs[0].or_cell._y"->"e.e.Yarb.arbs[0].or_cell.y"-
~("e.e.Yarb.arbs[0].or_cell._y")->"e.e.Yarb.arbs[0].or_cell.y"+
= "e.e.Yarb.arbs[0].out.d.d[0]" "e.e.Yarb.arbs[0].out.r"
= "e.e.Yarb.arbs[0].out.a" "e.e.Yarb.arbs[0].ack_cell2.c1"
= "e.e.Yarb.arbs[0].out.a" "e.e.Yarb.arbs[0].ack_cell1.c1"
= "e.e.Yarb.arbs[0].out.d.d[0]" "e.e.Yarb.arbs[0].or_cell.y"
= "e.e.Yarb.arbs[0].out.d.d[0]" "e.e.Yarb.arbs[0].out.r"
= "e.e.Yarb.arbs[0]._y2_arb" "e.e.Yarb.arbs[0].arbiter.y2"
= "e.e.Yarb.arbs[0]._y2_arb" "e.e.Yarb.arbs[0].or_cell.b"
= "e.e.Yarb.arbs[0]._y2_arb" "e.e.Yarb.arbs[0].ack_cell2.c2"
= "e.e.Yarb.supply.vss" "e.e.Yarb.arbs[0].supply.vss"
= "e.e.Yarb.supply.vdd" "e.e.Yarb.arbs[0].supply.vdd"
= "e.e.Yarb.in[0].d.d[0]" "e.e.Yarb.in[0].r"
= "e.e.Yarb.in[1].d.d[0]" "e.e.Yarb.in[1].r"
= "e.e.Yarb.in[0].r" "e.e.Yarb.arbs[0].in1.r"
= "e.e.Yarb.in[0].a" "e.e.Yarb.arbs[0].in1.a"
= "e.e.Yarb.in[0].d.d[0]" "e.e.Yarb.arbs[0].in1.d.d[0]"
= "e.e.Yarb.in[0].r" "e.e.Yarb.tmp[0].r"
= "e.e.Yarb.in[0].a" "e.e.Yarb.tmp[0].a"
= "e.e.Yarb.in[0].d.d[0]" "e.e.Yarb.tmp[0].d.d[0]"
= "e.e.Yarb.in[1].r" "e.e.Yarb.arbs[0].in2.r"
= "e.e.Yarb.in[1].a" "e.e.Yarb.arbs[0].in2.a"
= "e.e.Yarb.in[1].d.d[0]" "e.e.Yarb.arbs[0].in2.d.d[0]"
= "e.e.Yarb.in[1].r" "e.e.Yarb.tmp[1].r"
= "e.e.Yarb.in[1].a" "e.e.Yarb.tmp[1].a"
= "e.e.Yarb.in[1].d.d[0]" "e.e.Yarb.tmp[1].d.d[0]"
= "e.e.Yarb.in[1].d.d[0]" "e.e.Yarb.in[1].r"
= "e.e.Yarb.in[0].d.d[0]" "e.e.Yarb.in[0].r"
= "e.e.Yarb.out.d.d[0]" "e.e.Yarb.out.r"
= "e.e.Yarb.out.r" "e.e.Yarb.arbs[0].out.r"
= "e.e.Yarb.out.a" "e.e.Yarb.arbs[0].out.a"
= "e.e.Yarb.out.d.d[0]" "e.e.Yarb.arbs[0].out.d.d[0]"
= "e.e.Yarb.out.r" "e.e.Yarb.tmp[2].r"
= "e.e.Yarb.out.a" "e.e.Yarb.tmp[2].a"
= "e.e.Yarb.out.d.d[0]" "e.e.Yarb.tmp[2].d.d[0]"
= "e.e.Yarb.out.d.d[0]" "e.e.Yarb.out.r"
= "e.e._x_req_array[0]" "e.e.x_req_ortree.in[0]"
= "e.e._x_req_array[1]" "e.e.x_req_ortree.in[1]"
"e.e._in_xy_v.a"&"e.e._in_xy_v.b"->"e.e._in_xy_v._y"-
~("e.e._in_xy_v.a"&"e.e._in_xy_v.b")->"e.e._in_xy_v._y"+
"e.e._in_xy_v._y"->"e.e._in_xy_v.y"-
~("e.e._in_xy_v._y")->"e.e._in_xy_v.y"+
= "e.e._in_xy_v.y" "e.e.buf_s_func.in_v"
= "e.e._y_temp[0].d.d[0]" "e.e._y_temp[0].r"
= "e.e._y_temp[1].d.d[0]" "e.e._y_temp[1].r"
= "e.e._y_temp[0].r" "e.e.Yarb.in[0].r"
= "e.e._y_temp[1].r" "e.e.Yarb.in[1].r"
= "e.e._y_temp[0].a" "e.e.Yarb.in[0].a"
= "e.e._y_temp[1].a" "e.e.Yarb.in[1].a"
= "e.e._y_temp[0].d.d[0]" "e.e.Yarb.in[0].d.d[0]"
= "e.e._y_temp[1].d.d[0]" "e.e.Yarb.in[1].d.d[0]"
= "e.e._y_temp[1].a" "e.e.y_ack_arb[1].in"
= "e.e._y_temp[0].a" "e.e.y_ack_arb[0].in"
~"e.e.Y_ack_confirm.p1"&~"e.e.Y_ack_confirm.p2"&~"e.e.Y_ack_confirm.c1"&~"e.e.Y_ack_confirm.c2"|~"e.e.Y_ack_confirm.reset_B"->"e.e.Y_ack_confirm._y"+
"e.e.Y_ack_confirm.c1"&"e.e.Y_ack_confirm.c2"&"e.e.Y_ack_confirm.reset_B"->"e.e.Y_ack_confirm._y"-
"e.e.Y_ack_confirm._y"->"e.e.Y_ack_confirm.y"-
~("e.e.Y_ack_confirm._y")->"e.e.Y_ack_confirm.y"+
= "e.e.Y_ack_confirm.c1" "e.e._arb_out_y.r"
= "e.e.Y_ack_confirm.c1" "e.e._arb_out_y.d.d[0]"
= "e.e.y_enc_out.d[0].d[0]" "e.e.y_enc_out.d[0].f"
= "e.e.y_enc_out.d[0].d[1]" "e.e.y_enc_out.d[0].t"
= "e.e.y_enc_out.d[0].d[0]" "e.e.y_enc_out.d[0].f"
= "e.e.y_enc_out.d[0].d[1]" "e.e.y_enc_out.d[0].t"
= "e.e.y_enc_out.d[0].f" "e.e.vtree_y.in.d[0].f"
= "e.e.y_enc_out.d[0].t" "e.e.vtree_y.in.d[0].t"
= "e.e.y_enc_out.d[0].d[0]" "e.e.vtree_y.in.d[0].d[0]"
= "e.e.y_enc_out.d[0].d[1]" "e.e.vtree_y.in.d[0].d[1]"
= "e.e.y_enc_out.d[0].f" "e.e.y_encoder.out.d[0].f"
= "e.e.y_enc_out.d[0].t" "e.e.y_encoder.out.d[0].t"
= "e.e.y_enc_out.d[0].d[0]" "e.e.y_encoder.out.d[0].d[0]"
= "e.e.y_enc_out.d[0].d[1]" "e.e.y_encoder.out.d[0].d[1]"
= "e.e.y_enc_out.d[0].f" "e.e.into_buffer.d[1].f"
= "e.e.y_enc_out.d[0].t" "e.e.into_buffer.d[1].t"
= "e.e.y_enc_out.d[0].d[0]" "e.e.into_buffer.d[1].d[0]"
= "e.e.y_enc_out.d[0].d[1]" "e.e.into_buffer.d[1].d[1]"
= "e.e.y_enc_out.d[0].d[0]" "e.e.y_enc_out.d[0].f"
= "e.e.y_enc_out.d[0].d[1]" "e.e.y_enc_out.d[0].t"
= "e.e.x_acks[0]" "e.e.x_encoder.in[0]"
= "e.e.x_acks[1]" "e.e.x_encoder.in[1]"
"e.e.not_x_req_ortree.a"->"e.e.not_x_req_ortree.y"-
~("e.e.not_x_req_ortree.a")->"e.e.not_x_req_ortree.y"+
= "e.e.y[0].d.d[0]" "e.e.y[0].r"
= "e.e.y[1].d.d[0]" "e.e.y[1].r"
= "e.e.y[1].a" "e.e.y_acks[1]"
= "e.e.y[1].a" "e.e.y_ack_arb[1].out"
= "e.e.y[1].d.d[0]" "e.e._y_temp[1].r"
= "e.e.y[1].d.d[0]" "e.e._y_temp[1].d.d[0]"
= "e.e.y[1].d.d[0]" "e.e.y[1].r"
= "e.e.y[0].a" "e.e.y_acks[0]"
= "e.e.y[0].a" "e.e.y_ack_arb[0].out"
= "e.e.y[0].d.d[0]" "e.e._y_temp[0].r"
= "e.e.y[0].d.d[0]" "e.e._y_temp[0].d.d[0]"
= "e.e.y[0].d.d[0]" "e.e.y[0].r"
= "e.e._x_a_B" "e.e.not_x_ack.a"
= "e.e._x_a_B" "e.e.x_ack.y"
= "e.e._x_a_B" "e.e.X_ack_confirm.c2"
= "e.e._x_a_B" "e.e.Y_ack_confirm.c2"
= "e.e._x_a" "e.e.enabling.c1"
= "e.e._x_a" "e.e.not_x_ack.y"
= "e.e.x_enc_out.d[0].d[0]" "e.e.x_enc_out.d[0].f"
= "e.e.x_enc_out.d[0].d[1]" "e.e.x_enc_out.d[0].t"
= "e.e.x_enc_out.d[0].d[0]" "e.e.x_enc_out.d[0].f"
= "e.e.x_enc_out.d[0].d[1]" "e.e.x_enc_out.d[0].t"
= "e.e.x_enc_out.d[0].f" "e.e.vtree_x.in.d[0].f"
= "e.e.x_enc_out.d[0].t" "e.e.vtree_x.in.d[0].t"
= "e.e.x_enc_out.d[0].d[0]" "e.e.vtree_x.in.d[0].d[0]"
= "e.e.x_enc_out.d[0].d[1]" "e.e.vtree_x.in.d[0].d[1]"
= "e.e.x_enc_out.d[0].f" "e.e.x_encoder.out.d[0].f"
= "e.e.x_enc_out.d[0].t" "e.e.x_encoder.out.d[0].t"
= "e.e.x_enc_out.d[0].d[0]" "e.e.x_encoder.out.d[0].d[0]"
= "e.e.x_enc_out.d[0].d[1]" "e.e.x_encoder.out.d[0].d[1]"
= "e.e.x_enc_out.d[0].f" "e.e.into_buffer.d[0].f"
= "e.e.x_enc_out.d[0].t" "e.e.into_buffer.d[0].t"
= "e.e.x_enc_out.d[0].d[0]" "e.e.into_buffer.d[0].d[0]"
= "e.e.x_enc_out.d[0].d[1]" "e.e.into_buffer.d[0].d[1]"
= "e.e.x_enc_out.d[0].d[0]" "e.e.x_enc_out.d[0].f"
= "e.e.x_enc_out.d[0].d[1]" "e.e.x_enc_out.d[0].t"
= "e.e._x_temp[0].d.d[0]" "e.e._x_temp[0].r"
= "e.e._x_temp[1].d.d[0]" "e.e._x_temp[1].r"
= "e.e._x_temp[0].r" "e.e.Xarb.in[0].r"
= "e.e._x_temp[1].r" "e.e.Xarb.in[1].r"
= "e.e._x_temp[0].a" "e.e.Xarb.in[0].a"
= "e.e._x_temp[1].a" "e.e.Xarb.in[1].a"
= "e.e._x_temp[0].d.d[0]" "e.e.Xarb.in[0].d.d[0]"
= "e.e._x_temp[1].d.d[0]" "e.e.Xarb.in[1].d.d[0]"
= "e.e._x_temp[1].a" "e.e.x_ack_arb[1].in"
= "e.e._x_temp[0].a" "e.e.x_ack_arb[0].in"
~"e.e.X_ack_confirm.c1"&~"e.e.X_ack_confirm.c2"|~"e.e.X_ack_confirm.pr_B"->"e.e.X_ack_confirm._y"+
"e.e.X_ack_confirm.c1"&"e.e.X_ack_confirm.c2"&"e.e.X_ack_confirm.sr_B"->"e.e.X_ack_confirm._y"-
"e.e.X_ack_confirm._y"->"e.e.X_ack_confirm.y"-
~("e.e.X_ack_confirm._y")->"e.e.X_ack_confirm.y"+
= "e.e.X_ack_confirm.c1" "e.e._arb_out_x.r"
= "e.e.X_ack_confirm.c1" "e.e._arb_out_x.d.d[0]"
= "Vdd" "e.e.supply.vdd"
= "GND" "e.e.supply.vss"
= "e.y[0].d.d[0]" "e.y[0].r"
= "e.y[1].d.d[0]" "e.y[1].r"
= "e.y[0].r" "e.e.y[0].r"
= "e.y[1].r" "e.e.y[1].r"
= "e.y[0].a" "e.e.y[0].a"
= "e.y[1].a" "e.e.y[1].a"
= "e.y[0].d.d[0]" "e.e.y[0].d.d[0]"
= "e.y[1].d.d[0]" "e.e.y[1].d.d[0]"
= "e.y[1].d.d[0]" "e.y[1].r"
= "e.y[0].d.d[0]" "e.y[0].r"
= "e.x[0].d.d[0]" "e.x[0].r"
= "e.x[1].d.d[0]" "e.x[1].r"
= "e.x[0].r" "e.e.x[0].r"
= "e.x[1].r" "e.e.x[1].r"
= "e.x[0].a" "e.e.x[0].a"
= "e.x[1].a" "e.e.x[1].a"
= "e.x[0].d.d[0]" "e.e.x[0].d.d[0]"
= "e.x[1].d.d[0]" "e.e.x[1].d.d[0]"
= "e.x[1].d.d[0]" "e.x[1].r"
= "e.x[0].d.d[0]" "e.x[0].r"
= "e.out.d.d[0].d[0]" "e.out.d.d[0].f"
= "e.out.d.d[0].d[1]" "e.out.d.d[0].t"
= "e.out.d.d[1].d[0]" "e.out.d.d[1].f"
= "e.out.d.d[1].d[1]" "e.out.d.d[1].t"
= "e.out.d.d[1].d[0]" "e.out.d.d[1].f"
= "e.out.d.d[1].d[1]" "e.out.d.d[1].t"
= "e.out.d.d[0].d[0]" "e.out.d.d[0].f"
= "e.out.d.d[0].d[1]" "e.out.d.d[0].t"
= "e.out.d.d[1].d[0]" "e.out.d.d[1].f"
= "e.out.d.d[1].d[1]" "e.out.d.d[1].t"
= "e.out.d.d[0].d[0]" "e.out.d.d[0].f"
= "e.out.d.d[0].d[1]" "e.out.d.d[0].t"
= "e.out.v" "e.e.out.v"
= "e.out.a" "e.e.out.a"
= "e.out.d.d[0].f" "e.e.out.d.d[0].f"
= "e.out.d.d[0].t" "e.e.out.d.d[0].t"
= "e.out.d.d[0].d[0]" "e.e.out.d.d[0].d[0]"
= "e.out.d.d[0].d[1]" "e.e.out.d.d[0].d[1]"
= "e.out.d.d[1].f" "e.e.out.d.d[1].f"
= "e.out.d.d[1].t" "e.e.out.d.d[1].t"
= "e.out.d.d[1].d[0]" "e.e.out.d.d[1].d[0]"
= "e.out.d.d[1].d[1]" "e.e.out.d.d[1].d[1]"
= "e.out.d.d[1].d[0]" "e.out.d.d[1].f"
= "e.out.d.d[1].d[1]" "e.out.d.d[1].t"
= "e.out.d.d[0].d[0]" "e.out.d.d[0].f"
= "e.out.d.d[0].d[1]" "e.out.d.d[0].t"

49
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@@ -1,49 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/coders.act";
import globals;
import std::data;
open std::data;
open tmpl::dataflow_neuro;
defproc encoder2D_2x2 (a1of1 x[2]; a1of1 y[2]; avMx1of2<2> out){
encoder2D<1, 1, 2, 2, 1> e(.x=x, .y=y, .out=out);
bool _reset_B;
prs {
Reset => _reset_B-
}
e.supply.vss = GND;
e.supply.vdd = Vdd;
e.reset_B = _reset_B;
}
encoder2D_2x2 e;

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@@ -1,377 +0,0 @@
watchall
mode run
system "echo '[] Set Out Ack/Valid Low'"
set e.out.a 0
set e.out.v 0
cycle
system "echo '[] Setting Neuron Req Low'"
set e.y[0].r 0
set e.y[1].r 0
set e.x[0].r 0
set e.x[1].r 0
cycle
# # Slightly confused as to whether Reset should be set to 1 given A_2C_RB_X1 needs active high to change y
# # status X
# # set Reset 1
# # cycle
cycle
set Reset 0
cycle
system "echo '[] Single Neuron Spikes (0,0)'"
set e.y[0].r 1
set e.x[0].r 1
cycle
assert e.e.Yarb.out.r 1
assert e.e.Xarb.out.r 1
assert e.e._x_v 1
system "echo '[] Check Arbiter Acks'"
assert e.e._x_a_B 1
assert e.y[0].a 1
assert e.y[1].a 0
assert e.e.Yarb.out.a 1
assert e.x[0].a 1
assert e.x[1].a 0
assert e.e.Xarb.out.a 1
system "echo '[] Check Encoders'"
assert e.e.y_enc_out.d[0].t 0
assert e.e.y_enc_out.d[0].f 1
assert e.e.x_enc_out.d[0].t 0
assert e.e.x_enc_out.d[0].f 1
system "echo '[] Check Buffer'"
assert e.e._in_x_v 1
assert e.e._in_y_v 1
assert e.e._en 1
assert e.out.d.d[0].t 0
assert e.out.d.d[0].f 1
assert e.out.d.d[1].t 0
assert e.out.d.d[1].f 1
system "echo '[] Finish Neuron Handshake'"
set e.y[0].r 0
set e.x[0].r 0
cycle
assert e.e.Yarb.out.r 0
assert e.e.Xarb.out.r 0
set e.out.a 1
set e.out.v 1
cycle
assert e.e.Yarb.out.a 0
assert e.e.Xarb.out.a 0
assert e.y[0].a 0
assert e.x[0].a 0
set e.out.a 0
set e.out.v 0
cycle
system "echo '[] Neuron (0,0) Encoded'"
system "echo '[] Single Neuron Spikes (1,1)'"
set e.y[1].r 1
set e.x[1].r 1
cycle
assert e.e.Yarb.out.r 1
assert e.e.Xarb.out.r 1
system "echo '[] Check Arbiter Acks'"
assert e.e._x_a_B 1
assert e.y[0].a 0
assert e.y[1].a 1
assert e.e.Yarb.out.a 1
assert e.x[0].a 0
assert e.x[1].a 1
assert e.e.Xarb.out.a 1
system "echo '[] Check Encoders'"
assert e.e.y_enc_out.d[0].t 1
assert e.e.y_enc_out.d[0].f 0
assert e.e.x_enc_out.d[0].t 1
assert e.e.x_enc_out.d[0].f 0
system "echo '[] Check Buffer'"
assert e.e._in_x_v 1
assert e.e._in_y_v 1
assert e.e._en 1
assert e.out.d.d[0].t 1
assert e.out.d.d[0].f 0
assert e.out.d.d[1].t 1
assert e.out.d.d[1].f 0
system "echo '[] Finish Neuron Handshake'"
set e.y[1].r 0
set e.x[1].r 0
cycle
assert e.e.Yarb.out.r 0
assert e.e.Xarb.out.r 0
set e.out.a 1
set e.out.v 1
cycle
assert e.e.Yarb.out.a 0
assert e.e.Xarb.out.a 0
assert e.y[1].a 0
assert e.x[1].a 0
set e.out.a 0
set e.out.v 0
cycle
system "echo '[] Neuron (1,1) Encoded'"
system "echo '[] Neuron Spikes (0,0), (1,0)'"
set e.x[0].r 1
set e.y[0].r 1
set e.x[1].r 1
cycle
assert e.e.Yarb.out.r 1
assert e.e.Xarb.out.r 1
system "echo '[] Check Arbiter Acks (0,0)'"
assert e.e._x_a_B 1
assert e.y[0].a 1
assert e.y[1].a 0
assert e.e.Yarb.out.a 1
assert e.x[0].a 1
assert e.x[1].a 0
assert e.e.Xarb.out.a 1
system "echo '[] Check Encoders'"
assert e.e.y_enc_out.d[0].t 0
assert e.e.y_enc_out.d[0].f 1
assert e.e.x_enc_out.d[0].t 0
assert e.e.x_enc_out.d[0].f 1
system "echo '[] Check Buffer'"
assert e.e._in_x_v 1
assert e.e._in_y_v 1
assert e.e._en 1
assert e.out.d.d[0].t 0
assert e.out.d.d[0].f 1
assert e.out.d.d[1].t 0
assert e.out.d.d[1].f 1
system "echo '[] Finish Neuron Handshake (0,0)'"
set e.x[0].r 0
cycle
set e.out.a 1
set e.out.v 1
cycle
set e.out.a 0
set e.out.v 0
cycle
system "echo '[] Neuron (0,0) Encoded'"
system "echo '[] Check Neuron (1,0) Waiting'"
assert e.e.Yarb.out.r 1
assert e.e.Xarb.out.r 1
system "echo '[] Check Arbiter Acks (1,0)'"
assert e.e._x_a_B 1
assert e.y[0].a 1
assert e.y[1].a 0
assert e.e.Yarb.out.a 1
assert e.x[0].a 0
assert e.x[1].a 1
assert e.e.Xarb.out.a 1
system "echo '[] Check Encoders'"
assert e.e.y_enc_out.d[0].t 0
assert e.e.y_enc_out.d[0].f 1
assert e.e.x_enc_out.d[0].t 1
assert e.e.x_enc_out.d[0].f 0
system "echo '[] Check Buffer'"
assert e.e._in_x_v 1
assert e.e._in_y_v 1
assert e.e._en 1
assert e.out.d.d[0].t 1
assert e.out.d.d[0].f 0
assert e.out.d.d[1].t 0
assert e.out.d.d[1].f 1
system "echo '[] Finish Neuron Handshake (1,0)'"
set e.x[1].r 0
set e.y[0].r 0
cycle
set e.out.a 1
set e.out.v 1
cycle
set e.out.a 0
set e.out.v 0
cycle
system "echo '[] Neuron (1,0) Encoded'"
system "echo '[] Neuron Spikes (1,0), (0,1)'"
set e.x[1].r 1
set e.y[0].r 1
set e.x[0].r 1
set e.y[1].r 1
cycle
assert e.e.Yarb.out.r 1
assert e.e.Xarb.out.r 1
system "echo '[] Check Arbiter Acks (1,0)'"
assert e.e._x_a_B 1
assert e.y[0].a 0
assert e.y[1].a 1
assert e.e.Yarb.out.a 1
assert e.x[0].a 0
assert e.x[1].a 1
assert e.e.Xarb.out.a 1
system "echo '[] Check Encoders'"
assert e.e.y_enc_out.d[0].t 1
assert e.e.y_enc_out.d[0].f 0
assert e.e.x_enc_out.d[0].t 1
assert e.e.x_enc_out.d[0].f 0
system "echo '[] Check Buffer'"
assert e.e._in_x_v 1
assert e.e._in_y_v 1
assert e.e._en 1
assert e.out.d.d[0].t 1
assert e.out.d.d[0].f 0
assert e.out.d.d[1].t 1
assert e.out.d.d[1].f 0
system "echo '[] Finish Neuron Handshake (1,0)'"
set e.x[1].r 0
set e.y[0].r 0
cycle
set e.out.a 1
set e.out.v 1
cycle
set e.out.a 0
set e.out.v 0
cycle
system "echo '[] Neuron (1,0) Encoded'"
system "echo '[] Check Neuron (0,1) Waiting'"
assert e.e.Yarb.out.r 1
assert e.e.Xarb.out.r 1
system "echo '[] Check Arbiter Acks (0,1)'"
assert e.e._x_a_B 1
assert e.y[0].a 0
assert e.y[1].a 1
assert e.e.Yarb.out.a 1
assert e.x[0].a 1
assert e.x[1].a 0
assert e.e.Xarb.out.a 1
system "echo '[] Check Encoders'"
assert e.e.y_enc_out.d[0].t 1
assert e.e.y_enc_out.d[0].f 0
assert e.e.x_enc_out.d[0].t 0
assert e.e.x_enc_out.d[0].f 1
system "echo '[] Check Buffer'"
assert e.e._in_x_v 1
assert e.e._in_y_v 1
assert e.e._en 1
assert e.out.d.d[0].t 0
assert e.out.d.d[0].f 1
assert e.out.d.d[1].t 1
assert e.out.d.d[1].f 0
system "echo '[] Finish Neuron Handshake (1,0)'"
set e.x[0].r 0
set e.y[1].r 0
cycle
set e.out.a 1
set e.out.v 1
cycle
set e.out.a 0
set e.out.v 0
cycle
assert e.e._in_x_v 0
assert e.e._in_y_v 0
assert e.e._x_v 0
system "echo '[] Neuron (1,0) Encoded'"

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49
test/unit_tests/encoder2D_8x7/test.act
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@@ -1,49 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/coders.act";
import globals;
import std::data;
open std::data;
open tmpl::dataflow_neuro;
defproc encoder2D_2x2 (a1of1 x[8]; a1of1 y[7]; avMx1of2<6> out){
encoder2D<3, 3, 8, 7, 1> e(.x=x, .y=y, .out=out);
bool _reset_B;
prs {
Reset => _reset_B-
}
e.supply.vss = GND;
e.supply.vdd = Vdd;
e.reset_B = _reset_B;
}
encoder2D_2x2 e;

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watchall
mode run
system "echo '[] Set Out Ack/Valid Low'"
set e.out.a 0
set e.out.v 0
cycle
system "echo '[] Setting Neuron Req Low'"
set e.y[0].r 0
set e.y[1].r 0
set e.y[2].r 0
set e.y[3].r 0
set e.y[4].r 0
set e.y[5].r 0
set e.y[6].r 0
# set e.y[7].r 0
set e.x[0].r 0
set e.x[1].r 0
set e.x[2].r 0
set e.x[3].r 0
set e.x[4].r 0
set e.x[5].r 0
set e.x[6].r 0
set e.x[7].r 0
cycle
# # Slightly confused as to whether Reset should be set to 1 given A_2C_RB_X1 needs active high to change y
# # status X
# # set Reset 1
# # cycle
cycle
mode run
status X
status 0
set Reset 0
cycle
system "echo '[] Single Neuron Spikes (2,5), raise y[5].r'"
set e.y[5].r 1
# set e.x[2].r 1
cycle
assert e.e.Yarb.out.r 1
assert e.e.Xarb.out.r 0
assert e.e._x_v 0
system "echo '[] Raise x[2].r'"
# set e.y[5].r 1
set e.x[2].r 1
cycle
assert e.e.Yarb.out.r 1
assert e.e.Xarb.out.r 1
assert e.e._x_v 1
system "echo '[] Check Arbiter Acks'"
assert e.e._x_a_B 1
assert e.y[0].a 0
assert e.y[1].a 0
assert e.y[2].a 0
assert e.y[3].a 0
assert e.y[4].a 0
assert e.y[5].a 1
assert e.y[6].a 0
# assert e.y[7].a 0
assert e.e.Yarb.out.a 1
assert e.x[0].a 0
assert e.x[1].a 0
assert e.x[2].a 1
assert e.x[3].a 0
assert e.x[4].a 0
assert e.x[5].a 0
assert e.x[6].a 0
assert e.x[7].a 0
assert e.e.Xarb.out.a 1
system "echo '[] Check Encoders'"
assert e.e.x_enc_out.d[0].t 0
assert e.e.x_enc_out.d[0].f 1
assert e.e.x_enc_out.d[1].t 1
assert e.e.x_enc_out.d[1].f 0
assert e.e.x_enc_out.d[2].t 0
assert e.e.x_enc_out.d[2].f 1
assert e.e.y_enc_out.d[0].t 1
assert e.e.y_enc_out.d[0].f 0
assert e.e.y_enc_out.d[1].t 0
assert e.e.y_enc_out.d[1].f 1
assert e.e.y_enc_out.d[2].t 1
assert e.e.y_enc_out.d[2].f 0
system "echo '[] Check Buffer'"
assert e.e._in_x_v 1
assert e.e._in_y_v 1
assert e.e._en 1
assert e.out.d.d[0].t 0
assert e.out.d.d[0].f 1
assert e.out.d.d[1].t 1
assert e.out.d.d[1].f 0
assert e.out.d.d[2].t 0
assert e.out.d.d[2].f 1
assert e.out.d.d[3].t 1
assert e.out.d.d[3].f 0
assert e.out.d.d[4].t 0
assert e.out.d.d[4].f 1
assert e.out.d.d[5].t 1
assert e.out.d.d[5].f 0
system "echo '[] Finish Neuron Handshake'"
set e.y[5].r 0
set e.x[2].r 0
cycle
assert e.e.Yarb.out.r 0
assert e.e.Xarb.out.r 0
set e.out.a 1
set e.out.v 1
cycle
assert e.e.Yarb.out.a 0
assert e.e.Xarb.out.a 0
assert e.y[5].a 0
assert e.x[2].a 0
set e.out.a 0
set e.out.v 0
cycle
system "echo '[] Neuron (2,5) Encoded'"
system "echo '[] Single Neuron Spikes (0,0)'"
set e.y[0].r 1
set e.x[0].r 1
cycle
assert e.e.Yarb.out.r 1
assert e.e.Xarb.out.r 1
assert e.e._x_v 1
system "echo '[] Check Arbiter Acks'"
assert e.e._x_a_B 1
assert e.y[0].a 1
assert e.y[1].a 0
assert e.y[2].a 0
assert e.y[3].a 0
assert e.y[4].a 0
assert e.y[5].a 0
assert e.y[6].a 0
# assert e.y[7].a 0
assert e.e.Yarb.out.a 1
assert e.x[0].a 1
assert e.x[1].a 0
assert e.x[2].a 0
assert e.x[3].a 0
assert e.x[4].a 0
assert e.x[5].a 0
assert e.x[6].a 0
assert e.x[7].a 0
assert e.e.Xarb.out.a 1
system "echo '[] Check Encoders'"
assert e.e.y_enc_out.d[0].t 0
assert e.e.y_enc_out.d[0].f 1
assert e.e.y_enc_out.d[1].t 0
assert e.e.y_enc_out.d[1].f 1
assert e.e.y_enc_out.d[2].t 0
assert e.e.y_enc_out.d[2].f 1
assert e.e.x_enc_out.d[0].t 0
assert e.e.x_enc_out.d[0].f 1
assert e.e.x_enc_out.d[1].t 0
assert e.e.x_enc_out.d[1].f 1
assert e.e.x_enc_out.d[2].t 0
assert e.e.x_enc_out.d[2].f 1
system "echo '[] Check Buffer'"
assert e.e._in_x_v 1
assert e.e._in_y_v 1
assert e.e._en 1
assert e.out.d.d[0].t 0
assert e.out.d.d[0].f 1
assert e.out.d.d[1].t 0
assert e.out.d.d[1].f 1
assert e.out.d.d[2].t 0
assert e.out.d.d[2].f 1
assert e.out.d.d[3].t 0
assert e.out.d.d[3].f 1
assert e.out.d.d[4].t 0
assert e.out.d.d[4].f 1
assert e.out.d.d[5].t 0
assert e.out.d.d[5].f 1
system "echo '[] Finish Neuron Handshake'"
set e.y[0].r 0
set e.x[0].r 0
cycle
assert e.e.Yarb.out.r 0
assert e.e.Xarb.out.r 0
set e.out.a 1
set e.out.v 1
cycle
assert e.e.Yarb.out.a 0
assert e.e.Xarb.out.a 0
assert e.y[0].a 0
assert e.x[0].a 0
set e.out.a 0
set e.out.v 0
cycle
system "echo '[] Neuron (0,0) Encoded'"

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test/unit_tests/encoder2D_8x8/test.act
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@@ -1,49 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/coders.act";
import globals;
import std::data;
open std::data;
open tmpl::dataflow_neuro;
defproc encoder2D_2x2 (a1of1 x[8]; a1of1 y[8]; avMx1of2<6> out){
encoder2D<3, 3, 8, 8, 1> e(.x=x, .y=y, .out=out);
bool _reset_B;
prs {
Reset => _reset_B-
}
e.supply.vss = GND;
e.supply.vdd = Vdd;
e.reset_B = _reset_B;
}
encoder2D_2x2 e;

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watchall
mode run
system "echo '[] Set Out Ack/Valid Low'"
set e.out.a 0
set e.out.v 0
cycle
system "echo '[] Setting Neuron Req Low'"
set e.y[0].r 0
set e.y[1].r 0
set e.y[2].r 0
set e.y[3].r 0
set e.y[4].r 0
set e.y[5].r 0
set e.y[6].r 0
set e.y[7].r 0
set e.x[0].r 0
set e.x[1].r 0
set e.x[2].r 0
set e.x[3].r 0
set e.x[4].r 0
set e.x[5].r 0
set e.x[6].r 0
set e.x[7].r 0
cycle
# # Slightly confused as to whether Reset should be set to 1 given A_2C_RB_X1 needs active high to change y
# # status X
# # set Reset 1
# # cycle
cycle
mode run
status X
status 0
set Reset 0
cycle
system "echo '[] Single Neuron Spikes (2,5), raise y[5].r'"
set e.y[5].r 1
# set e.x[2].r 1
cycle
assert e.e.Yarb.out.r 1
assert e.e.Xarb.out.r 0
assert e.e._x_v 0
system "echo '[] Raise x[2].r'"
# set e.y[5].r 1
set e.x[2].r 1
cycle
assert e.e.Yarb.out.r 1
assert e.e.Xarb.out.r 1
assert e.e._x_v 1
system "echo '[] Check Arbiter Acks'"
assert e.e._x_a_B 1
assert e.y[0].a 0
assert e.y[1].a 0
assert e.y[2].a 0
assert e.y[3].a 0
assert e.y[4].a 0
assert e.y[5].a 1
assert e.y[6].a 0
assert e.y[7].a 0
assert e.e.Yarb.out.a 1
assert e.x[0].a 0
assert e.x[1].a 0
assert e.x[2].a 1
assert e.x[3].a 0
assert e.x[4].a 0
assert e.x[5].a 0
assert e.x[6].a 0
assert e.x[7].a 0
assert e.e.Xarb.out.a 1
system "echo '[] Check Encoders'"
assert e.e.x_enc_out.d[0].t 0
assert e.e.x_enc_out.d[0].f 1
assert e.e.x_enc_out.d[1].t 1
assert e.e.x_enc_out.d[1].f 0
assert e.e.x_enc_out.d[2].t 0
assert e.e.x_enc_out.d[2].f 1
assert e.e.y_enc_out.d[0].t 1
assert e.e.y_enc_out.d[0].f 0
assert e.e.y_enc_out.d[1].t 0
assert e.e.y_enc_out.d[1].f 1
assert e.e.y_enc_out.d[2].t 1
assert e.e.y_enc_out.d[2].f 0
system "echo '[] Check Buffer'"
assert e.e._in_x_v 1
assert e.e._in_y_v 1
assert e.e._en 1
assert e.out.d.d[0].t 0
assert e.out.d.d[0].f 1
assert e.out.d.d[1].t 1
assert e.out.d.d[1].f 0
assert e.out.d.d[2].t 0
assert e.out.d.d[2].f 1
assert e.out.d.d[3].t 1
assert e.out.d.d[3].f 0
assert e.out.d.d[4].t 0
assert e.out.d.d[4].f 1
assert e.out.d.d[5].t 1
assert e.out.d.d[5].f 0
system "echo '[] Finish Neuron Handshake'"
set e.y[5].r 0
set e.x[2].r 0
cycle
assert e.e.Yarb.out.r 0
assert e.e.Xarb.out.r 0
set e.out.a 1
set e.out.v 1
cycle
assert e.e.Yarb.out.a 0
assert e.e.Xarb.out.a 0
assert e.y[5].a 0
assert e.x[2].a 0
set e.out.a 0
set e.out.v 0
cycle
system "echo '[] Neuron (2,5) Encoded'"
system "echo '[] Single Neuron Spikes (0,0)'"
set e.y[0].r 1
set e.x[0].r 1
cycle
assert e.e.Yarb.out.r 1
assert e.e.Xarb.out.r 1
assert e.e._x_v 1
system "echo '[] Check Arbiter Acks'"
assert e.e._x_a_B 1
assert e.y[0].a 1
assert e.y[1].a 0
assert e.y[2].a 0
assert e.y[3].a 0
assert e.y[4].a 0
assert e.y[5].a 0
assert e.y[6].a 0
assert e.y[7].a 0
assert e.e.Yarb.out.a 1
assert e.x[0].a 1
assert e.x[1].a 0
assert e.x[2].a 0
assert e.x[3].a 0
assert e.x[4].a 0
assert e.x[5].a 0
assert e.x[6].a 0
assert e.x[7].a 0
assert e.e.Xarb.out.a 1
system "echo '[] Check Encoders'"
assert e.e.y_enc_out.d[0].t 0
assert e.e.y_enc_out.d[0].f 1
assert e.e.y_enc_out.d[1].t 0
assert e.e.y_enc_out.d[1].f 1
assert e.e.y_enc_out.d[2].t 0
assert e.e.y_enc_out.d[2].f 1
assert e.e.x_enc_out.d[0].t 0
assert e.e.x_enc_out.d[0].f 1
assert e.e.x_enc_out.d[1].t 0
assert e.e.x_enc_out.d[1].f 1
assert e.e.x_enc_out.d[2].t 0
assert e.e.x_enc_out.d[2].f 1
system "echo '[] Check Buffer'"
assert e.e._in_x_v 1
assert e.e._in_y_v 1
assert e.e._en 1
assert e.out.d.d[0].t 0
assert e.out.d.d[0].f 1
assert e.out.d.d[1].t 0
assert e.out.d.d[1].f 1
assert e.out.d.d[2].t 0
assert e.out.d.d[2].f 1
assert e.out.d.d[3].t 0
assert e.out.d.d[3].f 1
assert e.out.d.d[4].t 0
assert e.out.d.d[4].f 1
assert e.out.d.d[5].t 0
assert e.out.d.d[5].f 1
system "echo '[] Finish Neuron Handshake'"
set e.y[0].r 0
set e.x[0].r 0
cycle
assert e.e.Yarb.out.r 0
assert e.e.Xarb.out.r 0
set e.out.a 1
set e.out.v 1
cycle
assert e.e.Yarb.out.a 0
assert e.e.Xarb.out.a 0
assert e.y[0].a 0
assert e.x[0].a 0
set e.out.a 0
set e.out.v 0
cycle
system "echo '[] Neuron (0,0) Encoded'"

130
test/unit_tests/encoder_7/run/prsim.out
View File

@@ -1,130 +0,0 @@
e.out.d[1].t e.in[6] e.in[1] e.e.ors_f[2].or2s[1]._y e.in[2] e.e.ors_t[2].tmp[4] e.e.ors_f[1].tmp[5] e.e.ors_t[1].or2s[1]._y e.in[4] e.in[5] e.e.ors_f[0].tmp[4] e.in[3] e.e.ors_f[2].tmp[4] e.e.ors_f[1].tmp[4] e.e.ors_t[0].tmp[4] e.e.ors_t[2].or2s[1]._y e.e.ors_t[2].or2s[2]._y e.out.d[1].f e.out.d[2].f e.out.d[2].t e.e.ors_t[1].or2s[0]._y e.e.ors_t[1].tmp[4] e.in[0] e.out.d[0].t e.e.ors_t[0].tmp[5] e.e.ors_t[1].tmp[5] e.e.ors_f[0].tmp[5] e.e.ors_t[2].tmp[5] e.e.ors_f[2].or2s[2]._y e.e.ors_f[1].or2s[0]._y e.e.ors_t[0].or2s[2]._y e.out.d[0].f e.e.ors_f[2].or2s[0]._y e.e.ors_f[0].or2s[0]._y e.e.ors_t[2].or2s[0]._y e.e.ors_f[2].tmp[5] e.e.ors_t[0].or2s[0]._y e.e.ors_f[1].or2s[2]._y e.e.ors_f[0].or2s[2]._y e.e.ors_t[1].or2s[2]._y e.e.ors_f[1].or2s[1]._y e.e.ors_f[0].or2s[1]._y e.e.ors_t[0].or2s[1]._y
0
0 e.in[0] : 0
0 e.in[6] : 0
0 e.in[5] : 0
0 e.in[2] : 0
0 e.in[1] : 0
0 e.in[4] : 0
0 e.in[3] : 0
1 e.e.ors_t[2].or2s[1]._y : 1 [by e.in[6]:=0]
2 e.e.ors_f[0].or2s[0]._y : 1 [by e.in[2]:=0]
14 e.e.ors_t[2].tmp[5] : 0 [by e.e.ors_t[2].or2s[1]._y:=1]
15 e.e.ors_t[1].or2s[0]._y : 1 [by e.in[3]:=0]
39 e.e.ors_f[2].or2s[1]._y : 1 [by e.in[3]:=0]
42 e.e.ors_f[0].tmp[4] : 0 [by e.e.ors_f[0].or2s[0]._y:=1]
59 e.e.ors_f[2].tmp[5] : 0 [by e.e.ors_f[2].or2s[1]._y:=1]
114 e.e.ors_t[2].or2s[0]._y : 1 [by e.in[4]:=0]
430 e.e.ors_t[1].tmp[4] : 0 [by e.e.ors_t[1].or2s[0]._y:=1]
491 e.e.ors_t[0].or2s[0]._y : 1 [by e.in[3]:=0]
538 e.e.ors_t[0].tmp[4] : 0 [by e.e.ors_t[0].or2s[0]._y:=1]
1137 e.e.ors_f[1].or2s[0]._y : 1 [by e.in[1]:=0]
1153 e.e.ors_f[1].tmp[4] : 0 [by e.e.ors_f[1].or2s[0]._y:=1]
1726 e.e.ors_f[0].or2s[1]._y : 1 [by e.in[4]:=0]
4753 e.e.ors_f[2].or2s[0]._y : 1 [by e.in[1]:=0]
6175 e.e.ors_t[2].tmp[4] : 0 [by e.e.ors_t[2].or2s[0]._y:=1]
6179 e.e.ors_t[2].or2s[2]._y : 1 [by e.e.ors_t[2].tmp[4]:=0]
7092 e.e.ors_t[1].or2s[1]._y : 1 [by e.in[6]:=0]
7107 e.e.ors_t[1].tmp[5] : 0 [by e.e.ors_t[1].or2s[1]._y:=1]
10467 e.e.ors_t[0].or2s[1]._y : 1 [by e.in[5]:=0]
15308 e.out.d[2].t : 0 [by e.e.ors_t[2].or2s[2]._y:=1]
18477 e.e.ors_f[2].tmp[4] : 0 [by e.e.ors_f[2].or2s[0]._y:=1]
18532 e.e.ors_f[2].or2s[2]._y : 1 [by e.e.ors_f[2].tmp[4]:=0]
45824 e.e.ors_f[0].tmp[5] : 0 [by e.e.ors_f[0].or2s[1]._y:=1]
47398 e.e.ors_t[0].tmp[5] : 0 [by e.e.ors_t[0].or2s[1]._y:=1]
50355 e.e.ors_t[1].or2s[2]._y : 1 [by e.e.ors_t[1].tmp[5]:=0]
61247 e.e.ors_t[0].or2s[2]._y : 1 [by e.e.ors_t[0].tmp[5]:=0]
65366 e.e.ors_f[1].or2s[1]._y : 1 [by e.in[4]:=0]
65788 e.e.ors_f[1].tmp[5] : 0 [by e.e.ors_f[1].or2s[1]._y:=1]
70185 e.out.d[2].f : 0 [by e.e.ors_f[2].or2s[2]._y:=1]
75167 e.out.d[1].t : 0 [by e.e.ors_t[1].or2s[2]._y:=1]
75590 e.out.d[0].t : 0 [by e.e.ors_t[0].or2s[2]._y:=1]
75604 e.e.ors_f[0].or2s[2]._y : 1 [by e.e.ors_f[0].tmp[5]:=0]
75605 e.out.d[0].f : 0 [by e.e.ors_f[0].or2s[2]._y:=1]
114502 e.e.ors_f[1].or2s[2]._y : 1 [by e.e.ors_f[1].tmp[5]:=0]
114503 e.out.d[1].f : 0 [by e.e.ors_f[1].or2s[2]._y:=1]
[] setting input 0 high
114503 Reset : 0
114503 e.in[0] : 1
114785 e.e.ors_f[1].or2s[0]._y : 0 [by e.in[0]:=1]
114788 e.e.ors_f[1].tmp[4] : 1 [by e.e.ors_f[1].or2s[0]._y:=0]
115271 e.e.ors_f[0].or2s[0]._y : 0 [by e.in[0]:=1]
115822 e.e.ors_f[0].tmp[4] : 1 [by e.e.ors_f[0].or2s[0]._y:=0]
116893 e.e.ors_f[0].or2s[2]._y : 0 [by e.e.ors_f[0].tmp[4]:=1]
117847 e.out.d[0].f : 1 [by e.e.ors_f[0].or2s[2]._y:=0]
134708 e.e.ors_f[2].or2s[0]._y : 0 [by e.in[0]:=1]
135789 e.e.ors_f[2].tmp[4] : 1 [by e.e.ors_f[2].or2s[0]._y:=0]
137229 e.e.ors_f[1].or2s[2]._y : 0 [by e.e.ors_f[1].tmp[4]:=1]
138211 e.out.d[1].f : 1 [by e.e.ors_f[1].or2s[2]._y:=0]
190259 e.e.ors_f[2].or2s[2]._y : 0 [by e.e.ors_f[2].tmp[4]:=1]
190277 e.out.d[2].f : 1 [by e.e.ors_f[2].or2s[2]._y:=0]
[] removing inputs
190277 e.in[0] : 0
194280 e.e.ors_f[1].or2s[0]._y : 1 [by e.in[0]:=0]
194290 e.e.ors_f[2].or2s[0]._y : 1 [by e.in[0]:=0]
199050 e.e.ors_f[2].tmp[4] : 0 [by e.e.ors_f[2].or2s[0]._y:=1]
199552 e.e.ors_f[2].or2s[2]._y : 1 [by e.e.ors_f[2].tmp[4]:=0]
199755 e.out.d[2].f : 0 [by e.e.ors_f[2].or2s[2]._y:=1]
215864 e.e.ors_f[1].tmp[4] : 0 [by e.e.ors_f[1].or2s[0]._y:=1]
217718 e.e.ors_f[1].or2s[2]._y : 1 [by e.e.ors_f[1].tmp[4]:=0]
217857 e.out.d[1].f : 0 [by e.e.ors_f[1].or2s[2]._y:=1]
235178 e.e.ors_f[0].or2s[0]._y : 1 [by e.in[0]:=0]
271524 e.e.ors_f[0].tmp[4] : 0 [by e.e.ors_f[0].or2s[0]._y:=1]
271593 e.e.ors_f[0].or2s[2]._y : 1 [by e.e.ors_f[0].tmp[4]:=0]
271604 e.out.d[0].f : 0 [by e.e.ors_f[0].or2s[2]._y:=1]
[] setting input 4 high
271604 e.in[4] : 1
271619 e.e.ors_f[0].or2s[1]._y : 0 [by e.in[4]:=1]
271620 e.e.ors_f[0].tmp[5] : 1 [by e.e.ors_f[0].or2s[1]._y:=0]
271657 e.e.ors_f[0].or2s[2]._y : 0 [by e.e.ors_f[0].tmp[5]:=1]
271808 e.e.ors_f[1].or2s[1]._y : 0 [by e.in[4]:=1]
271920 e.e.ors_f[1].tmp[5] : 1 [by e.e.ors_f[1].or2s[1]._y:=0]
272396 e.out.d[0].f : 1 [by e.e.ors_f[0].or2s[2]._y:=0]
319432 e.e.ors_f[1].or2s[2]._y : 0 [by e.e.ors_f[1].tmp[5]:=1]
319472 e.out.d[1].f : 1 [by e.e.ors_f[1].or2s[2]._y:=0]
323390 e.e.ors_t[2].or2s[0]._y : 0 [by e.in[4]:=1]
323647 e.e.ors_t[2].tmp[4] : 1 [by e.e.ors_t[2].or2s[0]._y:=0]
323734 e.e.ors_t[2].or2s[2]._y : 0 [by e.e.ors_t[2].tmp[4]:=1]
324028 e.out.d[2].t : 1 [by e.e.ors_t[2].or2s[2]._y:=0]
[] removing inputs
324028 e.in[4] : 0
324029 e.e.ors_t[2].or2s[0]._y : 1 [by e.in[4]:=0]
325238 e.e.ors_t[2].tmp[4] : 0 [by e.e.ors_t[2].or2s[0]._y:=1]
325828 e.e.ors_t[2].or2s[2]._y : 1 [by e.e.ors_t[2].tmp[4]:=0]
325834 e.e.ors_f[1].or2s[1]._y : 1 [by e.in[4]:=0]
326006 e.out.d[2].t : 0 [by e.e.ors_t[2].or2s[2]._y:=1]
326035 e.e.ors_f[0].or2s[1]._y : 1 [by e.in[4]:=0]
326199 e.e.ors_f[0].tmp[5] : 0 [by e.e.ors_f[0].or2s[1]._y:=1]
326637 e.e.ors_f[1].tmp[5] : 0 [by e.e.ors_f[1].or2s[1]._y:=1]
326659 e.e.ors_f[1].or2s[2]._y : 1 [by e.e.ors_f[1].tmp[5]:=0]
327506 e.out.d[1].f : 0 [by e.e.ors_f[1].or2s[2]._y:=1]
328394 e.e.ors_f[0].or2s[2]._y : 1 [by e.e.ors_f[0].tmp[5]:=0]
358522 e.out.d[0].f : 0 [by e.e.ors_f[0].or2s[2]._y:=1]
[] setting input 6 high
358522 e.in[6] : 1
358655 e.e.ors_t[2].or2s[1]._y : 0 [by e.in[6]:=1]
358881 e.e.ors_f[0].or2s[1]._y : 0 [by e.in[6]:=1]
359102 e.e.ors_f[0].tmp[5] : 1 [by e.e.ors_f[0].or2s[1]._y:=0]
359109 e.e.ors_f[0].or2s[2]._y : 0 [by e.e.ors_f[0].tmp[5]:=1]
359139 e.out.d[0].f : 1 [by e.e.ors_f[0].or2s[2]._y:=0]
372771 e.e.ors_t[2].tmp[5] : 1 [by e.e.ors_t[2].or2s[1]._y:=0]
374184 e.e.ors_t[1].or2s[1]._y : 0 [by e.in[6]:=1]
379484 e.e.ors_t[2].or2s[2]._y : 0 [by e.e.ors_t[2].tmp[5]:=1]
379575 e.out.d[2].t : 1 [by e.e.ors_t[2].or2s[2]._y:=0]
431645 e.e.ors_t[1].tmp[5] : 1 [by e.e.ors_t[1].or2s[1]._y:=0]
433834 e.e.ors_t[1].or2s[2]._y : 0 [by e.e.ors_t[1].tmp[5]:=1]
433841 e.out.d[1].t : 1 [by e.e.ors_t[1].or2s[2]._y:=0]
[] removing inputs
433841 e.in[6] : 0
433919 e.e.ors_f[0].or2s[1]._y : 1 [by e.in[6]:=0]
433947 e.e.ors_t[1].or2s[1]._y : 1 [by e.in[6]:=0]
434194 e.e.ors_f[0].tmp[5] : 0 [by e.e.ors_f[0].or2s[1]._y:=1]
434649 e.e.ors_f[0].or2s[2]._y : 1 [by e.e.ors_f[0].tmp[5]:=0]
434661 e.out.d[0].f : 0 [by e.e.ors_f[0].or2s[2]._y:=1]
436628 e.e.ors_t[2].or2s[1]._y : 1 [by e.in[6]:=0]
437032 e.e.ors_t[2].tmp[5] : 0 [by e.e.ors_t[2].or2s[1]._y:=1]
437044 e.e.ors_t[2].or2s[2]._y : 1 [by e.e.ors_t[2].tmp[5]:=0]
442960 e.out.d[2].t : 0 [by e.e.ors_t[2].or2s[2]._y:=1]
452943 e.e.ors_t[1].tmp[5] : 0 [by e.e.ors_t[1].or2s[1]._y:=1]
457219 e.e.ors_t[1].or2s[2]._y : 1 [by e.e.ors_t[1].tmp[5]:=0]
460118 e.out.d[1].t : 0 [by e.e.ors_t[1].or2s[2]._y:=1]

298
test/unit_tests/encoder_7/run/test.prs
View File

@@ -1,298 +0,0 @@
= "GND" "GND"
= "Vdd" "Vdd"
= "Reset" "Reset"
= "e.e.tielo.y" "e.e.tielo.vss"
"e.e.ors_t[0].or2s[0].a"|"e.e.ors_t[0].or2s[0].b"->"e.e.ors_t[0].or2s[0]._y"-
~("e.e.ors_t[0].or2s[0].a"|"e.e.ors_t[0].or2s[0].b")->"e.e.ors_t[0].or2s[0]._y"+
"e.e.ors_t[0].or2s[0]._y"->"e.e.ors_t[0].or2s[0].y"-
~("e.e.ors_t[0].or2s[0]._y")->"e.e.ors_t[0].or2s[0].y"+
"e.e.ors_t[0].or2s[1].a"|"e.e.ors_t[0].or2s[1].b"->"e.e.ors_t[0].or2s[1]._y"-
~("e.e.ors_t[0].or2s[1].a"|"e.e.ors_t[0].or2s[1].b")->"e.e.ors_t[0].or2s[1]._y"+
"e.e.ors_t[0].or2s[1]._y"->"e.e.ors_t[0].or2s[1].y"-
~("e.e.ors_t[0].or2s[1]._y")->"e.e.ors_t[0].or2s[1].y"+
"e.e.ors_t[0].or2s[2].a"|"e.e.ors_t[0].or2s[2].b"->"e.e.ors_t[0].or2s[2]._y"-
~("e.e.ors_t[0].or2s[2].a"|"e.e.ors_t[0].or2s[2].b")->"e.e.ors_t[0].or2s[2]._y"+
"e.e.ors_t[0].or2s[2]._y"->"e.e.ors_t[0].or2s[2].y"-
~("e.e.ors_t[0].or2s[2]._y")->"e.e.ors_t[0].or2s[2].y"+
= "e.e.ors_t[0].tmp[4]" "e.e.ors_t[0].or2s[2].a"
= "e.e.ors_t[0].tmp[4]" "e.e.ors_t[0].or2s[0].y"
= "e.e.ors_t[0].tmp[5]" "e.e.ors_t[0].or2s[2].b"
= "e.e.ors_t[0].tmp[5]" "e.e.ors_t[0].or2s[1].y"
= "e.e.ors_t[0].supply.vdd" "e.e.ors_t[0].or2s[2].vdd"
= "e.e.ors_t[0].supply.vdd" "e.e.ors_t[0].or2s[1].vdd"
= "e.e.ors_t[0].supply.vdd" "e.e.ors_t[0].or2s[0].vdd"
= "e.e.ors_t[0].supply.vss" "e.e.ors_t[0].or2s[2].vss"
= "e.e.ors_t[0].supply.vss" "e.e.ors_t[0].or2s[1].vss"
= "e.e.ors_t[0].supply.vss" "e.e.ors_t[0].or2s[0].vss"
= "e.e.ors_t[0].in[0]" "e.e.ors_t[0].or2s[0].a"
= "e.e.ors_t[0].in[0]" "e.e.ors_t[0].tmp[0]"
= "e.e.ors_t[0].in[1]" "e.e.ors_t[0].or2s[0].b"
= "e.e.ors_t[0].in[1]" "e.e.ors_t[0].tmp[1]"
= "e.e.ors_t[0].in[2]" "e.e.ors_t[0].or2s[1].a"
= "e.e.ors_t[0].in[2]" "e.e.ors_t[0].tmp[2]"
= "e.e.ors_t[0].in[3]" "e.e.ors_t[0].or2s[1].b"
= "e.e.ors_t[0].in[3]" "e.e.ors_t[0].tmp[3]"
= "e.e.ors_t[0].out" "e.e.ors_t[0].or2s[2].y"
= "e.e.ors_t[0].out" "e.e.ors_t[0].tmp[6]"
"e.e.ors_t[1].or2s[0].a"|"e.e.ors_t[1].or2s[0].b"->"e.e.ors_t[1].or2s[0]._y"-
~("e.e.ors_t[1].or2s[0].a"|"e.e.ors_t[1].or2s[0].b")->"e.e.ors_t[1].or2s[0]._y"+
"e.e.ors_t[1].or2s[0]._y"->"e.e.ors_t[1].or2s[0].y"-
~("e.e.ors_t[1].or2s[0]._y")->"e.e.ors_t[1].or2s[0].y"+
"e.e.ors_t[1].or2s[1].a"|"e.e.ors_t[1].or2s[1].b"->"e.e.ors_t[1].or2s[1]._y"-
~("e.e.ors_t[1].or2s[1].a"|"e.e.ors_t[1].or2s[1].b")->"e.e.ors_t[1].or2s[1]._y"+
"e.e.ors_t[1].or2s[1]._y"->"e.e.ors_t[1].or2s[1].y"-
~("e.e.ors_t[1].or2s[1]._y")->"e.e.ors_t[1].or2s[1].y"+
"e.e.ors_t[1].or2s[2].a"|"e.e.ors_t[1].or2s[2].b"->"e.e.ors_t[1].or2s[2]._y"-
~("e.e.ors_t[1].or2s[2].a"|"e.e.ors_t[1].or2s[2].b")->"e.e.ors_t[1].or2s[2]._y"+
"e.e.ors_t[1].or2s[2]._y"->"e.e.ors_t[1].or2s[2].y"-
~("e.e.ors_t[1].or2s[2]._y")->"e.e.ors_t[1].or2s[2].y"+
= "e.e.ors_t[1].tmp[4]" "e.e.ors_t[1].or2s[2].a"
= "e.e.ors_t[1].tmp[4]" "e.e.ors_t[1].or2s[0].y"
= "e.e.ors_t[1].tmp[5]" "e.e.ors_t[1].or2s[2].b"
= "e.e.ors_t[1].tmp[5]" "e.e.ors_t[1].or2s[1].y"
= "e.e.ors_t[1].supply.vdd" "e.e.ors_t[1].or2s[2].vdd"
= "e.e.ors_t[1].supply.vdd" "e.e.ors_t[1].or2s[1].vdd"
= "e.e.ors_t[1].supply.vdd" "e.e.ors_t[1].or2s[0].vdd"
= "e.e.ors_t[1].supply.vss" "e.e.ors_t[1].or2s[2].vss"
= "e.e.ors_t[1].supply.vss" "e.e.ors_t[1].or2s[1].vss"
= "e.e.ors_t[1].supply.vss" "e.e.ors_t[1].or2s[0].vss"
= "e.e.ors_t[1].in[0]" "e.e.ors_t[1].or2s[0].a"
= "e.e.ors_t[1].in[0]" "e.e.ors_t[1].tmp[0]"
= "e.e.ors_t[1].in[1]" "e.e.ors_t[1].or2s[0].b"
= "e.e.ors_t[1].in[1]" "e.e.ors_t[1].tmp[1]"
= "e.e.ors_t[1].in[2]" "e.e.ors_t[1].or2s[1].a"
= "e.e.ors_t[1].in[2]" "e.e.ors_t[1].tmp[2]"
= "e.e.ors_t[1].in[3]" "e.e.ors_t[1].or2s[1].b"
= "e.e.ors_t[1].in[3]" "e.e.ors_t[1].tmp[3]"
= "e.e.ors_t[1].out" "e.e.ors_t[1].or2s[2].y"
= "e.e.ors_t[1].out" "e.e.ors_t[1].tmp[6]"
"e.e.ors_t[2].or2s[0].a"|"e.e.ors_t[2].or2s[0].b"->"e.e.ors_t[2].or2s[0]._y"-
~("e.e.ors_t[2].or2s[0].a"|"e.e.ors_t[2].or2s[0].b")->"e.e.ors_t[2].or2s[0]._y"+
"e.e.ors_t[2].or2s[0]._y"->"e.e.ors_t[2].or2s[0].y"-
~("e.e.ors_t[2].or2s[0]._y")->"e.e.ors_t[2].or2s[0].y"+
"e.e.ors_t[2].or2s[1].a"|"e.e.ors_t[2].or2s[1].b"->"e.e.ors_t[2].or2s[1]._y"-
~("e.e.ors_t[2].or2s[1].a"|"e.e.ors_t[2].or2s[1].b")->"e.e.ors_t[2].or2s[1]._y"+
"e.e.ors_t[2].or2s[1]._y"->"e.e.ors_t[2].or2s[1].y"-
~("e.e.ors_t[2].or2s[1]._y")->"e.e.ors_t[2].or2s[1].y"+
"e.e.ors_t[2].or2s[2].a"|"e.e.ors_t[2].or2s[2].b"->"e.e.ors_t[2].or2s[2]._y"-
~("e.e.ors_t[2].or2s[2].a"|"e.e.ors_t[2].or2s[2].b")->"e.e.ors_t[2].or2s[2]._y"+
"e.e.ors_t[2].or2s[2]._y"->"e.e.ors_t[2].or2s[2].y"-
~("e.e.ors_t[2].or2s[2]._y")->"e.e.ors_t[2].or2s[2].y"+
= "e.e.ors_t[2].tmp[4]" "e.e.ors_t[2].or2s[2].a"
= "e.e.ors_t[2].tmp[4]" "e.e.ors_t[2].or2s[0].y"
= "e.e.ors_t[2].tmp[5]" "e.e.ors_t[2].or2s[2].b"
= "e.e.ors_t[2].tmp[5]" "e.e.ors_t[2].or2s[1].y"
= "e.e.ors_t[2].supply.vdd" "e.e.ors_t[2].or2s[2].vdd"
= "e.e.ors_t[2].supply.vdd" "e.e.ors_t[2].or2s[1].vdd"
= "e.e.ors_t[2].supply.vdd" "e.e.ors_t[2].or2s[0].vdd"
= "e.e.ors_t[2].supply.vss" "e.e.ors_t[2].or2s[2].vss"
= "e.e.ors_t[2].supply.vss" "e.e.ors_t[2].or2s[1].vss"
= "e.e.ors_t[2].supply.vss" "e.e.ors_t[2].or2s[0].vss"
= "e.e.ors_t[2].in[0]" "e.e.ors_t[2].or2s[0].a"
= "e.e.ors_t[2].in[0]" "e.e.ors_t[2].tmp[0]"
= "e.e.ors_t[2].in[1]" "e.e.ors_t[2].or2s[0].b"
= "e.e.ors_t[2].in[1]" "e.e.ors_t[2].tmp[1]"
= "e.e.ors_t[2].in[2]" "e.e.ors_t[2].or2s[1].a"
= "e.e.ors_t[2].in[2]" "e.e.ors_t[2].tmp[2]"
= "e.e.ors_t[2].in[3]" "e.e.ors_t[2].or2s[1].b"
= "e.e.ors_t[2].in[3]" "e.e.ors_t[2].tmp[3]"
= "e.e.ors_t[2].out" "e.e.ors_t[2].or2s[2].y"
= "e.e.ors_t[2].out" "e.e.ors_t[2].tmp[6]"
"e.e.ors_f[0].or2s[0].a"|"e.e.ors_f[0].or2s[0].b"->"e.e.ors_f[0].or2s[0]._y"-
~("e.e.ors_f[0].or2s[0].a"|"e.e.ors_f[0].or2s[0].b")->"e.e.ors_f[0].or2s[0]._y"+
"e.e.ors_f[0].or2s[0]._y"->"e.e.ors_f[0].or2s[0].y"-
~("e.e.ors_f[0].or2s[0]._y")->"e.e.ors_f[0].or2s[0].y"+
"e.e.ors_f[0].or2s[1].a"|"e.e.ors_f[0].or2s[1].b"->"e.e.ors_f[0].or2s[1]._y"-
~("e.e.ors_f[0].or2s[1].a"|"e.e.ors_f[0].or2s[1].b")->"e.e.ors_f[0].or2s[1]._y"+
"e.e.ors_f[0].or2s[1]._y"->"e.e.ors_f[0].or2s[1].y"-
~("e.e.ors_f[0].or2s[1]._y")->"e.e.ors_f[0].or2s[1].y"+
"e.e.ors_f[0].or2s[2].a"|"e.e.ors_f[0].or2s[2].b"->"e.e.ors_f[0].or2s[2]._y"-
~("e.e.ors_f[0].or2s[2].a"|"e.e.ors_f[0].or2s[2].b")->"e.e.ors_f[0].or2s[2]._y"+
"e.e.ors_f[0].or2s[2]._y"->"e.e.ors_f[0].or2s[2].y"-
~("e.e.ors_f[0].or2s[2]._y")->"e.e.ors_f[0].or2s[2].y"+
= "e.e.ors_f[0].tmp[4]" "e.e.ors_f[0].or2s[2].a"
= "e.e.ors_f[0].tmp[4]" "e.e.ors_f[0].or2s[0].y"
= "e.e.ors_f[0].tmp[5]" "e.e.ors_f[0].or2s[2].b"
= "e.e.ors_f[0].tmp[5]" "e.e.ors_f[0].or2s[1].y"
= "e.e.ors_f[0].supply.vdd" "e.e.ors_f[0].or2s[2].vdd"
= "e.e.ors_f[0].supply.vdd" "e.e.ors_f[0].or2s[1].vdd"
= "e.e.ors_f[0].supply.vdd" "e.e.ors_f[0].or2s[0].vdd"
= "e.e.ors_f[0].supply.vss" "e.e.ors_f[0].or2s[2].vss"
= "e.e.ors_f[0].supply.vss" "e.e.ors_f[0].or2s[1].vss"
= "e.e.ors_f[0].supply.vss" "e.e.ors_f[0].or2s[0].vss"
= "e.e.ors_f[0].in[0]" "e.e.ors_f[0].or2s[0].a"
= "e.e.ors_f[0].in[0]" "e.e.ors_f[0].tmp[0]"
= "e.e.ors_f[0].in[1]" "e.e.ors_f[0].or2s[0].b"
= "e.e.ors_f[0].in[1]" "e.e.ors_f[0].tmp[1]"
= "e.e.ors_f[0].in[2]" "e.e.ors_f[0].or2s[1].a"
= "e.e.ors_f[0].in[2]" "e.e.ors_f[0].tmp[2]"
= "e.e.ors_f[0].in[3]" "e.e.ors_f[0].or2s[1].b"
= "e.e.ors_f[0].in[3]" "e.e.ors_f[0].tmp[3]"
= "e.e.ors_f[0].out" "e.e.ors_f[0].or2s[2].y"
= "e.e.ors_f[0].out" "e.e.ors_f[0].tmp[6]"
"e.e.ors_f[1].or2s[0].a"|"e.e.ors_f[1].or2s[0].b"->"e.e.ors_f[1].or2s[0]._y"-
~("e.e.ors_f[1].or2s[0].a"|"e.e.ors_f[1].or2s[0].b")->"e.e.ors_f[1].or2s[0]._y"+
"e.e.ors_f[1].or2s[0]._y"->"e.e.ors_f[1].or2s[0].y"-
~("e.e.ors_f[1].or2s[0]._y")->"e.e.ors_f[1].or2s[0].y"+
"e.e.ors_f[1].or2s[1].a"|"e.e.ors_f[1].or2s[1].b"->"e.e.ors_f[1].or2s[1]._y"-
~("e.e.ors_f[1].or2s[1].a"|"e.e.ors_f[1].or2s[1].b")->"e.e.ors_f[1].or2s[1]._y"+
"e.e.ors_f[1].or2s[1]._y"->"e.e.ors_f[1].or2s[1].y"-
~("e.e.ors_f[1].or2s[1]._y")->"e.e.ors_f[1].or2s[1].y"+
"e.e.ors_f[1].or2s[2].a"|"e.e.ors_f[1].or2s[2].b"->"e.e.ors_f[1].or2s[2]._y"-
~("e.e.ors_f[1].or2s[2].a"|"e.e.ors_f[1].or2s[2].b")->"e.e.ors_f[1].or2s[2]._y"+
"e.e.ors_f[1].or2s[2]._y"->"e.e.ors_f[1].or2s[2].y"-
~("e.e.ors_f[1].or2s[2]._y")->"e.e.ors_f[1].or2s[2].y"+
= "e.e.ors_f[1].tmp[4]" "e.e.ors_f[1].or2s[2].a"
= "e.e.ors_f[1].tmp[4]" "e.e.ors_f[1].or2s[0].y"
= "e.e.ors_f[1].tmp[5]" "e.e.ors_f[1].or2s[2].b"
= "e.e.ors_f[1].tmp[5]" "e.e.ors_f[1].or2s[1].y"
= "e.e.ors_f[1].supply.vdd" "e.e.ors_f[1].or2s[2].vdd"
= "e.e.ors_f[1].supply.vdd" "e.e.ors_f[1].or2s[1].vdd"
= "e.e.ors_f[1].supply.vdd" "e.e.ors_f[1].or2s[0].vdd"
= "e.e.ors_f[1].supply.vss" "e.e.ors_f[1].or2s[2].vss"
= "e.e.ors_f[1].supply.vss" "e.e.ors_f[1].or2s[1].vss"
= "e.e.ors_f[1].supply.vss" "e.e.ors_f[1].or2s[0].vss"
= "e.e.ors_f[1].in[0]" "e.e.ors_f[1].or2s[0].a"
= "e.e.ors_f[1].in[0]" "e.e.ors_f[1].tmp[0]"
= "e.e.ors_f[1].in[1]" "e.e.ors_f[1].or2s[0].b"
= "e.e.ors_f[1].in[1]" "e.e.ors_f[1].tmp[1]"
= "e.e.ors_f[1].in[2]" "e.e.ors_f[1].or2s[1].a"
= "e.e.ors_f[1].in[2]" "e.e.ors_f[1].tmp[2]"
= "e.e.ors_f[1].in[3]" "e.e.ors_f[1].or2s[1].b"
= "e.e.ors_f[1].in[3]" "e.e.ors_f[1].tmp[3]"
= "e.e.ors_f[1].out" "e.e.ors_f[1].or2s[2].y"
= "e.e.ors_f[1].out" "e.e.ors_f[1].tmp[6]"
"e.e.ors_f[2].or2s[0].a"|"e.e.ors_f[2].or2s[0].b"->"e.e.ors_f[2].or2s[0]._y"-
~("e.e.ors_f[2].or2s[0].a"|"e.e.ors_f[2].or2s[0].b")->"e.e.ors_f[2].or2s[0]._y"+
"e.e.ors_f[2].or2s[0]._y"->"e.e.ors_f[2].or2s[0].y"-
~("e.e.ors_f[2].or2s[0]._y")->"e.e.ors_f[2].or2s[0].y"+
"e.e.ors_f[2].or2s[1].a"|"e.e.ors_f[2].or2s[1].b"->"e.e.ors_f[2].or2s[1]._y"-
~("e.e.ors_f[2].or2s[1].a"|"e.e.ors_f[2].or2s[1].b")->"e.e.ors_f[2].or2s[1]._y"+
"e.e.ors_f[2].or2s[1]._y"->"e.e.ors_f[2].or2s[1].y"-
~("e.e.ors_f[2].or2s[1]._y")->"e.e.ors_f[2].or2s[1].y"+
"e.e.ors_f[2].or2s[2].a"|"e.e.ors_f[2].or2s[2].b"->"e.e.ors_f[2].or2s[2]._y"-
~("e.e.ors_f[2].or2s[2].a"|"e.e.ors_f[2].or2s[2].b")->"e.e.ors_f[2].or2s[2]._y"+
"e.e.ors_f[2].or2s[2]._y"->"e.e.ors_f[2].or2s[2].y"-
~("e.e.ors_f[2].or2s[2]._y")->"e.e.ors_f[2].or2s[2].y"+
= "e.e.ors_f[2].tmp[4]" "e.e.ors_f[2].or2s[2].a"
= "e.e.ors_f[2].tmp[4]" "e.e.ors_f[2].or2s[0].y"
= "e.e.ors_f[2].tmp[5]" "e.e.ors_f[2].or2s[2].b"
= "e.e.ors_f[2].tmp[5]" "e.e.ors_f[2].or2s[1].y"
= "e.e.ors_f[2].supply.vdd" "e.e.ors_f[2].or2s[2].vdd"
= "e.e.ors_f[2].supply.vdd" "e.e.ors_f[2].or2s[1].vdd"
= "e.e.ors_f[2].supply.vdd" "e.e.ors_f[2].or2s[0].vdd"
= "e.e.ors_f[2].supply.vss" "e.e.ors_f[2].or2s[2].vss"
= "e.e.ors_f[2].supply.vss" "e.e.ors_f[2].or2s[1].vss"
= "e.e.ors_f[2].supply.vss" "e.e.ors_f[2].or2s[0].vss"
= "e.e.ors_f[2].in[0]" "e.e.ors_f[2].or2s[0].a"
= "e.e.ors_f[2].in[0]" "e.e.ors_f[2].tmp[0]"
= "e.e.ors_f[2].in[1]" "e.e.ors_f[2].or2s[0].b"
= "e.e.ors_f[2].in[1]" "e.e.ors_f[2].tmp[1]"
= "e.e.ors_f[2].in[2]" "e.e.ors_f[2].or2s[1].a"
= "e.e.ors_f[2].in[2]" "e.e.ors_f[2].tmp[2]"
= "e.e.ors_f[2].in[3]" "e.e.ors_f[2].or2s[1].b"
= "e.e.ors_f[2].in[3]" "e.e.ors_f[2].tmp[3]"
= "e.e.ors_f[2].out" "e.e.ors_f[2].or2s[2].y"
= "e.e.ors_f[2].out" "e.e.ors_f[2].tmp[6]"
= "e.e.supply.vss" "e.e.ors_f[2].supply.vss"
= "e.e.supply.vdd" "e.e.ors_f[2].supply.vdd"
= "e.e.supply.vss" "e.e.ors_f[1].supply.vss"
= "e.e.supply.vdd" "e.e.ors_f[1].supply.vdd"
= "e.e.supply.vss" "e.e.ors_f[0].supply.vss"
= "e.e.supply.vdd" "e.e.ors_f[0].supply.vdd"
= "e.e.supply.vss" "e.e.ors_t[2].supply.vss"
= "e.e.supply.vdd" "e.e.ors_t[2].supply.vdd"
= "e.e.supply.vss" "e.e.ors_t[1].supply.vss"
= "e.e.supply.vdd" "e.e.ors_t[1].supply.vdd"
= "e.e.supply.vss" "e.e.ors_t[0].supply.vss"
= "e.e.supply.vdd" "e.e.ors_t[0].supply.vdd"
= "e.e.supply.vdd" "e.e.tielo.vdd"
= "e.e.supply.vss" "e.e.ors_t[2].in[3]"
= "e.e.supply.vss" "e.e.ors_t[1].in[3]"
= "e.e.supply.vss" "e.e.ors_t[0].in[3]"
= "e.e.supply.vss" "e.e.tielo.vss"
= "e.e.supply.vss" "e.e.tielo.y"
= "e.e.in[0]" "e.e.ors_f[2].in[0]"
= "e.e.in[0]" "e.e.ors_f[1].in[0]"
= "e.e.in[0]" "e.e.ors_f[0].in[0]"
= "e.e.in[1]" "e.e.ors_f[2].in[1]"
= "e.e.in[1]" "e.e.ors_f[1].in[1]"
= "e.e.in[1]" "e.e.ors_t[0].in[0]"
= "e.e.in[2]" "e.e.ors_f[2].in[2]"
= "e.e.in[2]" "e.e.ors_t[1].in[0]"
= "e.e.in[2]" "e.e.ors_f[0].in[1]"
= "e.e.in[3]" "e.e.ors_f[2].in[3]"
= "e.e.in[3]" "e.e.ors_t[1].in[1]"
= "e.e.in[3]" "e.e.ors_t[0].in[1]"
= "e.e.in[4]" "e.e.ors_t[2].in[0]"
= "e.e.in[4]" "e.e.ors_f[1].in[2]"
= "e.e.in[4]" "e.e.ors_f[0].in[2]"
= "e.e.in[5]" "e.e.ors_t[2].in[1]"
= "e.e.in[5]" "e.e.ors_f[1].in[3]"
= "e.e.in[5]" "e.e.ors_t[0].in[2]"
= "e.e.in[6]" "e.e.ors_t[2].in[2]"
= "e.e.in[6]" "e.e.ors_t[1].in[2]"
= "e.e.in[6]" "e.e.ors_f[0].in[3]"
= "e.e.out.d[0].d[0]" "e.e.out.d[0].f"
= "e.e.out.d[0].d[1]" "e.e.out.d[0].t"
= "e.e.out.d[1].d[0]" "e.e.out.d[1].f"
= "e.e.out.d[1].d[1]" "e.e.out.d[1].t"
= "e.e.out.d[2].d[0]" "e.e.out.d[2].f"
= "e.e.out.d[2].d[1]" "e.e.out.d[2].t"
= "e.e.out.d[2].d[0]" "e.e.out.d[2].f"
= "e.e.out.d[2].d[1]" "e.e.out.d[2].t"
= "e.e.out.d[1].d[0]" "e.e.out.d[1].f"
= "e.e.out.d[1].d[1]" "e.e.out.d[1].t"
= "e.e.out.d[0].d[0]" "e.e.out.d[0].f"
= "e.e.out.d[0].d[1]" "e.e.out.d[0].t"
= "e.e.out.d[2].d[0]" "e.e.ors_f[2].out"
= "e.e.out.d[2].d[0]" "e.e.out.d[2].f"
= "e.e.out.d[2].d[1]" "e.e.ors_t[2].out"
= "e.e.out.d[2].d[1]" "e.e.out.d[2].t"
= "e.e.out.d[1].d[0]" "e.e.ors_f[1].out"
= "e.e.out.d[1].d[0]" "e.e.out.d[1].f"
= "e.e.out.d[1].d[1]" "e.e.ors_t[1].out"
= "e.e.out.d[1].d[1]" "e.e.out.d[1].t"
= "e.e.out.d[0].d[0]" "e.e.ors_f[0].out"
= "e.e.out.d[0].d[0]" "e.e.out.d[0].f"
= "e.e.out.d[0].d[1]" "e.e.ors_t[0].out"
= "e.e.out.d[0].d[1]" "e.e.out.d[0].t"
= "Vdd" "e.e.supply.vdd"
= "GND" "e.e.supply.vss"
= "e.out.d[0].d[0]" "e.out.d[0].f"
= "e.out.d[0].d[1]" "e.out.d[0].t"
= "e.out.d[1].d[0]" "e.out.d[1].f"
= "e.out.d[1].d[1]" "e.out.d[1].t"
= "e.out.d[2].d[0]" "e.out.d[2].f"
= "e.out.d[2].d[1]" "e.out.d[2].t"
= "e.out.d[2].d[0]" "e.out.d[2].f"
= "e.out.d[2].d[1]" "e.out.d[2].t"
= "e.out.d[1].d[0]" "e.out.d[1].f"
= "e.out.d[1].d[1]" "e.out.d[1].t"
= "e.out.d[0].d[0]" "e.out.d[0].f"
= "e.out.d[0].d[1]" "e.out.d[0].t"
= "e.out.d[0].f" "e.e.out.d[0].f"
= "e.out.d[0].t" "e.e.out.d[0].t"
= "e.out.d[0].d[0]" "e.e.out.d[0].d[0]"
= "e.out.d[0].d[1]" "e.e.out.d[0].d[1]"
= "e.out.d[1].f" "e.e.out.d[1].f"
= "e.out.d[1].t" "e.e.out.d[1].t"
= "e.out.d[1].d[0]" "e.e.out.d[1].d[0]"
= "e.out.d[1].d[1]" "e.e.out.d[1].d[1]"
= "e.out.d[2].f" "e.e.out.d[2].f"
= "e.out.d[2].t" "e.e.out.d[2].t"
= "e.out.d[2].d[0]" "e.e.out.d[2].d[0]"
= "e.out.d[2].d[1]" "e.e.out.d[2].d[1]"
= "e.out.d[2].d[0]" "e.out.d[2].f"
= "e.out.d[2].d[1]" "e.out.d[2].t"
= "e.out.d[1].d[0]" "e.out.d[1].f"
= "e.out.d[1].d[1]" "e.out.d[1].t"
= "e.out.d[0].d[0]" "e.out.d[0].f"
= "e.out.d[0].d[1]" "e.out.d[0].t"
= "e.in[0]" "e.e.in[0]"
= "e.in[1]" "e.e.in[1]"
= "e.in[2]" "e.e.in[2]"
= "e.in[3]" "e.e.in[3]"
= "e.in[4]" "e.e.in[4]"
= "e.in[5]" "e.e.in[5]"
= "e.in[6]" "e.e.in[6]"

44
test/unit_tests/encoder_7/test.act
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@@ -1,44 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/coders.act";
import globals;
import std::data;
open std::data;
open tmpl::dataflow_neuro;
defproc encoder_7 (bool? in[7]; Mx1of2<3> out){
dualrail_encoder<3,7> e(.in=in, .out=out);
e.supply.vss = GND;
e.supply.vdd = Vdd;
}
encoder_7 e;

78
test/unit_tests/encoder_7/test.prsim
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@@ -1,78 +0,0 @@
watchall
system "echo '0'"
set e.in[0] 0
set e.in[1] 0
set e.in[2] 0
set e.in[3] 0
set e.in[4] 0
set e.in[5] 0
set e.in[6] 0
# set-bool-array "e.in" 7 0
cycle
mode run
# assert t.out 0
system "echo '[] setting input 0 high'"
set Reset 0
set e.in[0] 1
cycle
system "echo '[] removing inputs'"
set e.in[0] 0
cycle
system "echo '[] setting input 4 high'"
set e.in[4] 1
cycle
system "echo '[] removing inputs'"
set e.in[4] 0
cycle
system "echo '[] setting input 6 high'"
set e.in[6] 1
cycle
system "echo '[] removing inputs'"
set e.in[6] 0
cycle
# system "echo '[] setting input 6 high'"
# set e.in[4] 0
# set e.in[6] 1
# cycle
# assert t.out 0
# system "echo '[] setting all bits high'"
# set t.in[3] 1
# set t.in[4] 1
# cycle
# assert t.out 1
# system "echo '[] setting some low'"
# set t.in[0] 0
# set t.in[1] 0
# cycle
# assert t.out 0
# system "echo '[] setting all low'"
# set t.in[2] 0
# set t.in[3] 0
# set t.in[4] 0
# cycle
# assert t.out 0

5380
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test/unit_tests/fifo-decoder-neurons-encoder-fifo/run/test.prs
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98
test/unit_tests/fifo-decoder-neurons-encoder-fifo/test.act
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@@ -1,98 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/coders.act";
import "../../dataflow_neuro/primitives.act";
import globals;
import std::data;
open std::data;
open tmpl::dataflow_neuro;
defproc fifo_decoder_neurons_encoder_fifo (avMx1of2<7> in; avMx1of2<7> out; bool? dly_cfg[6]){
bool _reset_B;
prs {
Reset => _reset_B-
}
power supply;
supply.vdd = Vdd;
supply.vss = GND;
pint NxC,NyC,Nx,Ny;
NxC = 4;
NyC = 3;
Nx = 1<<NxC;
Ny = 1<<NyC;
fifo<NxC + NyC,5> fifo_pre(.in = in, .reset_B = _reset_B, .supply = supply);
decoder_2d_dly<NxC,NyC,Nx,Ny,6> decoder(.in = fifo_pre.out, .dly_cfg = dly_cfg,
.reset_B = _reset_B, .supply = supply);
and_grid<Nx, Ny> _and_grid(.inx = decoder.outx, .iny = decoder.outy, .supply = supply);
// Pretend that each "synapse" immediately makes its one neuron "spike".
// that is, connect the output of each encoder target to the decoder input.
nrn_hs_2D_array<Nx,Ny,10> neuron_grid(.reset_B = _reset_B, .supply = supply);
(i:Nx*Ny:
// Connect the output bool to the input req of each neuron handshaker
// Leave ack dangling.
neuron_grid.in[i].r = _and_grid.out[i];
)
encoder2D<NxC,NyC,Nx,Ny,4> encoder(.inx = neuron_grid.outx, .iny = neuron_grid.outy,
.reset_B = _reset_B, .supply = supply);
fifo<NxC + NyC,5> fifo_post(.in = encoder.out, .out = out, .reset_B = _reset_B, .supply = supply);
}
// defproc fifo_decoder_and (avMx1of2<7> in; bool! out[8*16]; bool? dly_cfg[6]){
// bool _reset_B;
// prs {
// Reset => _reset_B-
// }
// power supply;
// supply.vdd = Vdd;
// supply.vss = GND;
// pint NxC,NyC,Nx,Ny;
// NxC = 4;
// NyC = 3;
// Nx = 1<<NxC;
// Ny = 1<<NyC;
// fifo<NxC + NyC,5> fifo_pre(.in = in, .reset_B = _reset_B, .supply = supply);
// decoder_2d_dly<NxC,NyC,Nx,Ny,6> decoder(.in = fifo_pre.out, .dly_cfg = dly_cfg,
// .reset_B = _reset_B, .supply = supply);
// and_grid<Nx, Ny> _and_grid(.inx = decoder.outx, .iny = decoder.outy, .out = out, .supply = supply);
// nrn_hs_2D_array<Nx,Ny,16> nrn_array(.reset_B = _reset_B, .supply = supply);
// }
// fifo_decoder_neurons_encoder_fifo e;
fifo_decoder_neurons_encoder_fifo e;

81
test/unit_tests/fifo-decoder-neurons-encoder-fifo/test.prsim
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@@ -1,81 +0,0 @@
watchall
set e.out.a 0
set e.out.v 0
set-qdi-channel-neutral "e.in" 7
set Reset 1
set e.dly_cfg[0] 1
set e.dly_cfg[1] 1
set e.dly_cfg[2] 1
set e.dly_cfg[3] 1
set e.dly_cfg[4] 1
set e.dly_cfg[5] 1
cycle
mode run
system "echo '[] Set reset 0'"
status X
set Reset 0
cycle
system "echo '[] Sending in a packet'"
set-qdi-channel-valid "e.in" 7 75
cycle
assert-qdi-channel-valid "e.out" 7 75
assert e.in.a 1
assert e.in.v 1
system "echo '[] Removing input'"
set-qdi-channel-neutral "e.in" 7
cycle
assert e.in.a 0
assert e.in.v 0
system "echo '[] Sending in another packet'"
set-qdi-channel-valid "e.in" 7 22
cycle
# Output is still the first packet
assert-qdi-channel-valid "e.out" 7 75
assert e.in.a 1
assert e.in.v 1
system "echo '[] Removing input'"
set-qdi-channel-neutral "e.in" 7
cycle
assert e.in.a 0
assert e.in.v 0
system "echo '[] Giving out ack'"
set e.out.a 1
set e.out.v 1
cycle
assert-qdi-channel-neutral "e.out" 7
system "echo '[] Removing ack'"
set e.out.a 0
set e.out.v 0
cycle
assert-qdi-channel-valid "e.out" 7 22
system "echo '[] Giving out ack'"
set e.out.a 1
set e.out.v 1
cycle
assert-qdi-channel-neutral "e.out" 7
system "echo '[] Removing ack'"
set e.out.a 0
set e.out.v 0
cycle
assert-qdi-channel-neutral "e.out" 7

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test/unit_tests/fifo-decoder_hs-neurons-encoder-fifo/run/test.prs
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72
test/unit_tests/fifo-decoder_hs-neurons-encoder-fifo/test.act
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@@ -1,72 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/coders.act";
import "../../dataflow_neuro/primitives.act";
import globals;
import std::data;
open std::data;
open tmpl::dataflow_neuro;
defproc fifo_decoder_neurons_encoder_fifo (avMx1of2<7> in; avMx1of2<7> out){
bool _reset_B;
prs {
Reset => _reset_B-
}
power supply;
supply.vdd = Vdd;
supply.vss = GND;
pint NxC,NyC,Nx,Ny;
NxC = 4;
NyC = 3;
Nx = 1<<NxC;
Ny = 1<<NyC;
fifo<NxC + NyC,5> fifo_pre(.in = in, .reset_B = _reset_B, .supply = supply);
decoder_2d_hs<NxC,NyC,Nx,Ny> decoder(.in = fifo_pre.out, .reset_B = _reset_B, .supply = supply);
// Pretend that each "synapse" immediately makes its one neuron "spike".
// that is, connect the output of each encoder target to the decoder input.
nrn_hs_2D_array<Nx,Ny,10> neuron_grid(.reset_B = _reset_B, .supply = supply);
(i:Nx*Ny:
neuron_grid.in[i].r = decoder.out[i].r;
neuron_grid.in[i].a = decoder.out[i].a;
)
encoder2D<NxC,NyC,Nx,Ny,4> encoder(.inx = neuron_grid.outx, .iny = neuron_grid.outy,
.reset_B = _reset_B, .supply = supply);
fifo<NxC + NyC,5> fifo_post(.in = encoder.out, .out = out, .reset_B = _reset_B, .supply = supply);
}
// fifo_decoder_neurons_encoder_fifo e;
fifo_decoder_neurons_encoder_fifo e;

74
test/unit_tests/fifo-decoder_hs-neurons-encoder-fifo/test.prsim
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@@ -1,74 +0,0 @@
watchall
set e.out.a 0
set e.out.v 0
set-qdi-channel-neutral "e.in" 7
set Reset 1
cycle
mode run
system "echo '[] Set reset 0'"
status X
set Reset 0
cycle
system "echo '[] Sending in a packet'"
set-qdi-channel-valid "e.in" 7 75
cycle
assert-qdi-channel-valid "e.out" 7 75
assert e.in.a 1
assert e.in.v 1
system "echo '[] Removing input'"
set-qdi-channel-neutral "e.in" 7
cycle
assert e.in.a 0
assert e.in.v 0
system "echo '[] Sending in another packet'"
set-qdi-channel-valid "e.in" 7 22
cycle
# Output is still the first packet
assert-qdi-channel-valid "e.out" 7 75
assert e.in.a 1
assert e.in.v 1
system "echo '[] Removing input'"
set-qdi-channel-neutral "e.in" 7
cycle
assert e.in.a 0
assert e.in.v 0
system "echo '[] Giving out ack'"
set e.out.a 1
set e.out.v 1
cycle
assert-qdi-channel-neutral "e.out" 7
system "echo '[] Removing ack'"
set e.out.a 0
set e.out.v 0
cycle
assert-qdi-channel-valid "e.out" 7 22
system "echo '[] Giving out ack'"
set e.out.a 1
set e.out.v 1
cycle
assert-qdi-channel-neutral "e.out" 7
system "echo '[] Removing ack'"
set e.out.a 0
set e.out.v 0
cycle
assert-qdi-channel-neutral "e.out" 7

12868
test/unit_tests/fifo-decoder_hybrid-neurons-encoder-fifo/run/prsim.out
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54416
test/unit_tests/fifo-decoder_hybrid-neurons-encoder-fifo/run/test.prs
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73
test/unit_tests/fifo-decoder_hybrid-neurons-encoder-fifo/test.act
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@@ -1,73 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/coders.act";
import "../../dataflow_neuro/primitives.act";
import globals;
import std::data;
open std::data;
open tmpl::dataflow_neuro;
defproc fifo_decoder_neurons_encoder_fifo (avMx1of2<7> in; avMx1of2<7> out; bool? dly_cfg[4], hs_en){
bool _reset_B;
prs {
Reset => _reset_B-
}
power supply;
supply.vdd = Vdd;
supply.vss = GND;
pint NxC,NyC,Nx,Ny;
NxC = 4;
NyC = 3;
Nx = 1<<NxC;
Ny = 1<<NyC;
fifo<NxC + NyC,5> fifo_pre(.in = in, .reset_B = _reset_B, .supply = supply);
decoder_2d_hybrid<NxC,NyC,Nx,Ny,4> decoder(.in = fifo_pre.out, .dly_cfg =dly_cfg, .hs_en = hs_en,
.reset_B = _reset_B, .supply = supply);
// Pretend that each "synapse" immediately makes its one neuron "spike".
// that is, connect the output of each encoder target to the decoder input.
nrn_hs_2D_array<Nx,Ny,10> neuron_grid(.reset_B = _reset_B, .supply = supply);
(i:Nx*Ny:
neuron_grid.in[i].r = decoder.out[i].r;
neuron_grid.in[i].a = decoder.out[i].a;
)
encoder2D<NxC,NyC,Nx,Ny,4> encoder(.inx = neuron_grid.outx, .iny = neuron_grid.outy,
.reset_B = _reset_B, .supply = supply);
fifo<NxC + NyC,5> fifo_post(.in = encoder.out, .out = out, .reset_B = _reset_B, .supply = supply);
}
// fifo_decoder_neurons_encoder_fifo e;
fifo_decoder_neurons_encoder_fifo e;

149
test/unit_tests/fifo-decoder_hybrid-neurons-encoder-fifo/test.prsim
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@@ -1,149 +0,0 @@
watchall
# Use handshaking at first
set e.dly_cfg[0] 0
set e.dly_cfg[1] 0
set e.dly_cfg[2] 0
set e.dly_cfg[3] 0
set e.hs_en 1
set e.out.a 0
set e.out.v 0
set-qdi-channel-neutral "e.in" 7
set Reset 1
cycle
mode run
system "echo '[] Set reset 0'"
status X
set Reset 0
cycle
system "echo '[] Sending in a packet'"
set-qdi-channel-valid "e.in" 7 75
cycle
assert-qdi-channel-valid "e.out" 7 75
assert e.in.a 1
assert e.in.v 1
system "echo '[] Removing input'"
set-qdi-channel-neutral "e.in" 7
cycle
assert e.in.a 0
assert e.in.v 0
system "echo '[] Sending in another packet'"
set-qdi-channel-valid "e.in" 7 22
cycle
# Output is still the first packet
assert-qdi-channel-valid "e.out" 7 75
assert e.in.a 1
assert e.in.v 1
system "echo '[] Removing input'"
set-qdi-channel-neutral "e.in" 7
cycle
assert e.in.a 0
assert e.in.v 0
system "echo '[] Giving out ack'"
set e.out.a 1
set e.out.v 1
cycle
assert-qdi-channel-neutral "e.out" 7
system "echo '[] Removing ack'"
set e.out.a 0
set e.out.v 0
cycle
assert-qdi-channel-valid "e.out" 7 22
system "echo '[] Giving out ack'"
set e.out.a 1
set e.out.v 1
cycle
assert-qdi-channel-neutral "e.out" 7
system "echo '[] Removing ack'"
set e.out.a 0
set e.out.v 0
cycle
assert-qdi-channel-neutral "e.out" 7
# Enable delays
set e.dly_cfg[0] 1
set e.dly_cfg[1] 1
set e.dly_cfg[2] 1
set e.dly_cfg[3] 1
set e.hs_en 0
cycle
mode run
system "echo '[] Set reset 0'"
status X
set Reset 0
cycle
system "echo '[] Sending in a packet WITH DELAYS'"
set-qdi-channel-valid "e.in" 7 75
cycle
assert-qdi-channel-valid "e.out" 7 75
assert e.in.a 1
assert e.in.v 1
system "echo '[] Removing input'"
set-qdi-channel-neutral "e.in" 7
cycle
assert e.in.a 0
assert e.in.v 0
system "echo '[] Sending in another packet'"
set-qdi-channel-valid "e.in" 7 22
cycle
# Output is still the first packet
assert-qdi-channel-valid "e.out" 7 75
assert e.in.a 1
assert e.in.v 1
system "echo '[] Removing input'"
set-qdi-channel-neutral "e.in" 7
cycle
assert e.in.a 0
assert e.in.v 0
system "echo '[] Giving out ack'"
set e.out.a 1
set e.out.v 1
cycle
assert-qdi-channel-neutral "e.out" 7
system "echo '[] Removing ack'"
set e.out.a 0
set e.out.v 0
cycle
assert-qdi-channel-valid "e.out" 7 22
system "echo '[] Giving out ack'"
set e.out.a 1
set e.out.v 1
cycle
assert-qdi-channel-neutral "e.out" 7
system "echo '[] Removing ack'"
set e.out.a 0
set e.out.v 0
cycle
assert-qdi-channel-neutral "e.out" 7

55
test/unit_tests/flipflop/run/prsim.out
View File

@@ -1,55 +0,0 @@
t.ff.__clk_B t.ff._clk_B t.d t.clk t._clk_B
[0] start test
15221 Reset : 0
15221 t.clk : 0
15221 t.d : 0
16947 t._clk_B : 1 [by t.clk:=0]
16986 t.ff._clk_B : 0 [by t._clk_B:=1]
17001 t.ff.__clk_B : 1 [by t.ff._clk_B:=0]
80587 t._reset_B : 1 [by Reset:=0]
[1] reset completed
[2] tested d = 0, clk rise
80587 t.clk : 1
80587 t.d : 1
80600 t.ff._mqib : 0 [by t.d:=1]
80640 t.ff._mqi : 1 [by t.ff._mqib:=0]
81078 t._clk_B : 0 [by t.clk:=1]
81493 t.ff._clk_B : 1 [by t._clk_B:=0]
81513 t.ff.__clk_B : 0 [by t.ff._clk_B:=1]
87554 t.ff._sqib : 0 [by t.ff._clk_B:=1]
87570 t.q : 1 [by t.ff._sqib:=0]
87601 t.ff._sqi : 1 [by t.ff._sqib:=0]
131668 t.ff.q_B : 0 [by t.q:=1]
131668 t.clk : 0
145392 t._clk_B : 1 [by t.clk:=0]
145396 t.ff._clk_B : 0 [by t._clk_B:=1]
154525 t.ff.__clk_B : 1 [by t.ff._clk_B:=0]
154525 t.d : 0
154540 t.ff._mqib : 1 [by t.d:=0]
197788 t.ff._mqi : 0 [by t.ff._mqib:=1]
197788 t.clk : 1
234719 t._clk_B : 0 [by t.clk:=1]
234774 t.ff._clk_B : 1 [by t._clk_B:=0]
286427 t.ff.__clk_B : 0 [by t.ff._clk_B:=1]
316207 t.ff._sqib : 1 [by t.ff.__clk_B:=0]
330056 t.ff._sqi : 0 [by t.ff._sqib:=1]
341019 t.q : 0 [by t.ff._sqib:=1]
355362 t.ff.q_B : 1 [by t.q:=0]
355362 t.clk : 0
355784 t._clk_B : 1 [by t.clk:=0]
404498 t.ff._clk_B : 0 [by t._clk_B:=1]
404499 t.ff.__clk_B : 1 [by t.ff._clk_B:=0]
404499 t.d : 1
404500 t.ff._mqib : 0 [by t.d:=1]
424705 t.ff._mqi : 1 [by t.ff._mqib:=0]
[3] tested d = 1, clk rise and fall
424705 t.clk : 1
424987 t._clk_B : 0 [by t.clk:=1]
425755 t.ff._clk_B : 1 [by t._clk_B:=0]
425758 t.ff.__clk_B : 0 [by t.ff._clk_B:=1]
448196 t.ff._sqib : 0 [by t.ff._clk_B:=1]
448747 t.ff._sqi : 1 [by t.ff._sqib:=0]
449267 t.q : 1 [by t.ff._sqib:=0]
450221 t.ff.q_B : 0 [by t.q:=1]
450221 t.d : 0

29
test/unit_tests/flipflop/run/test.prs
View File

@@ -1,29 +0,0 @@
= "GND" "GND"
= "Vdd" "Vdd"
= "Reset" "Reset"
"Reset"->"t._reset_B"-
~("Reset")->"t._reset_B"+
"t.clk"->"t._clk_B"-
~("t.clk")->"t._clk_B"+
= "t._reset_B" "t.ff.reset_B"
"t.ff.clk_B"->"t.ff._clk_B"-
~("t.ff.clk_B")->"t.ff._clk_B"+
"t.ff._clk_B"->"t.ff.__clk_B"-
~("t.ff._clk_B")->"t.ff.__clk_B"+
~"t.ff.d"&~"t.ff._clk_B"|~"t.ff.reset_B"|~"t.ff.__clk_B"&~"t.ff._mqi"->"t.ff._mqib"+
("t.ff.d"&"t.ff.__clk_B"|"t.ff._mqi"&"t.ff._clk_B")&"t.ff.reset_B"->"t.ff._mqib"-
"t.ff._mqib"->"t.ff._mqi"-
~("t.ff._mqib")->"t.ff._mqi"+
~"t.ff._mqi"&~"t.ff.__clk_B"|~"t.ff.reset_B"|~"t.ff._sqi"&~"t.ff._clk_B"->"t.ff._sqib"+
("t.ff._mqi"&"t.ff._clk_B"|"t.ff._sqi"&"t.ff.__clk_B")&"t.ff.reset_B"->"t.ff._sqib"-
"t.ff._sqib"->"t.ff._sqi"-
~("t.ff._sqib")->"t.ff._sqi"+
"t.ff._sqib"->"t.ff.q"-
~("t.ff._sqib")->"t.ff.q"+
"t.ff.q"->"t.ff.q_B"-
~("t.ff.q")->"t.ff.q_B"+
= "Vdd" "t.ff.vdd"
= "GND" "t.ff.vss"
= "t.q" "t.ff.q"
= "t._clk_B" "t.ff.clk_B"
= "t.d" "t.ff.d"

50
test/unit_tests/flipflop/test.act
View File

@@ -1,50 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/primitives.act";
import globals;
open tmpl::dataflow_neuro;
defproc flipflop_test (bool! q; bool? d,clk){
bool _clk_B;
DFFQ_R_X1 ff(.d=d,.clk_B = _clk_B, .q = q);
//Low active Reset
bool _reset_B;
prs {
Reset => _reset_B-
clk => _clk_B-
}
ff.vss = GND;
ff.vdd = Vdd;
ff.reset_B = _reset_B;
}
flipflop_test t;

51
test/unit_tests/flipflop/test.prsim
View File

@@ -1,51 +0,0 @@
watchall
system "echo '[0] start test'"
set Reset 0
set t.d 0
set t.clk 0
cycle
status X
mode run
assert t.q 0
system "echo '[1] reset completed'"
system "echo '[2] tested d = 0, clk rise'"
set t.clk 1
set t.d 1
cycle
set t.clk 0
cycle
set t.d 0
cycle
assert t.q 1
set t.clk 1
cycle
assert t.q 0
set t.d 0
set t.clk 0
cycle
assert t.q 0
set t.d 1
cycle
set t.clk 0
cycle
assert t.q 0
system "echo '[3] tested d = 1, clk rise and fall'"
set t.d 1
cycle
set t.clk 1
cycle
set t.d 0
cycle
assert t.q 1

17
test/unit_tests/line_end_pull_up/run/prsim.out
View File

@@ -1,17 +0,0 @@
t.in.a t.lepu.nor_out t.lepu.__out t.lepu.buf1._y t.lepu._out t.out t.lepu.buf2._y
1 t.in.a : 0
7093 t.lepu.buf1._y : 1 [by t.in.a:=0]
17560 t.lepu._out : 0 [by t.lepu.buf1._y:=1]
17562 t.lepu.nor_out : 1 [by t.lepu._out:=0]
22313 t.lepu.buf2._y : 1 [by t.lepu._out:=0]
23450 t.lepu.__out : 0 [by t.lepu.buf2._y:=1]
yo man
23450 Reset : 0
23564 t._reset_B : 1 [by Reset:=0]
88930 t.lepu.nor_out : 0 [by t._reset_B:=1]
90656 t.out : 1 [by t.lepu.nor_out:=0]
90656 t.in.a : 1
90695 t.lepu.buf1._y : 0 [by t.in.a:=1]
90710 t.lepu._out : 1 [by t.lepu.buf1._y:=0]
91201 t.lepu.buf2._y : 0 [by t.lepu._out:=1]
91214 t.lepu.__out : 1 [by t.lepu.buf2._y:=0]

42
test/unit_tests/line_end_pull_up/run/test.prs
View File

@@ -1,42 +0,0 @@
= "GND" "GND"
= "Vdd" "Vdd"
= "Reset" "Reset"
"Reset"->"t._reset_B"-
~("Reset")->"t._reset_B"+
= "t._reset_B" "t.lepu.reset_B"
~"t.lepu.pull_up.a"->"t.lepu.pull_up.y"+
"t.lepu.aenor.a"|"t.lepu.aenor.b"->"t.lepu.aenor.y"-
~("t.lepu.aenor.a"|"t.lepu.aenor.b")->"t.lepu.aenor.y"+
= "t.lepu._out" "t.lepu.aenor.a"
= "t.lepu._out" "t.lepu.buf2.a"
= "t.lepu._out" "t.lepu.buf1.y"
= "t.lepu.nor_out" "t.lepu.pull_up.a"
= "t.lepu.nor_out" "t.lepu.aenor.y"
"t.lepu.buf1.a"->"t.lepu.buf1._y"-
~("t.lepu.buf1.a")->"t.lepu.buf1._y"+
"t.lepu.buf1._y"->"t.lepu.buf1.y"-
~("t.lepu.buf1._y")->"t.lepu.buf1.y"+
= "t.lepu.reset_B" "t.lepu.aenor.b"
= "t.lepu.supply.vdd" "t.lepu.aenor.vdd"
= "t.lepu.supply.vdd" "t.lepu.buf2.vdd"
= "t.lepu.supply.vdd" "t.lepu.buf1.vdd"
= "t.lepu.supply.vss" "t.lepu.aenor.vss"
= "t.lepu.supply.vss" "t.lepu.buf2.vss"
= "t.lepu.supply.vss" "t.lepu.buf1.vss"
= "t.lepu.__out" "t.lepu.buf2.y"
"t.lepu.buf2.a"->"t.lepu.buf2._y"-
~("t.lepu.buf2.a")->"t.lepu.buf2._y"+
"t.lepu.buf2._y"->"t.lepu.buf2.y"-
~("t.lepu.buf2._y")->"t.lepu.buf2.y"+
= "t.lepu.in.d.d[0]" "t.lepu.in.r"
= "t.lepu.in.a" "t.lepu.buf1.a"
= "t.lepu.in.d.d[0]" "t.lepu.in.r"
= "t.lepu.out" "t.lepu.pull_up.y"
= "Vdd" "t.lepu.supply.vdd"
= "GND" "t.lepu.supply.vss"
= "t.out" "t.lepu.out"
= "t.in.d.d[0]" "t.in.r"
= "t.in.r" "t.lepu.in.r"
= "t.in.a" "t.lepu.in.a"
= "t.in.d.d[0]" "t.lepu.in.d.d[0]"
= "t.in.d.d[0]" "t.in.r"

48
test/unit_tests/line_end_pull_up/test.act
View File

@@ -1,48 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/primitives.act";
import globals;
open tmpl::dataflow_neuro;
defproc lepu (a1of1 in; bool! out){
line_end_pull_up lepu(.in=in, .out=out);
//Low active Reset
bool _reset_B;
prs {
Reset => _reset_B-
}
lepu.supply.vss = GND;
lepu.supply.vdd = Vdd;
lepu.reset_B = _reset_B;
}
lepu t;

15
test/unit_tests/line_end_pull_up/test.prsim
View File

@@ -1,15 +0,0 @@
watchall
set t.in.a 0
cycle
system "echo 'yo man'"
set Reset 0
cycle
set t.in.a 1
cycle
assert t.out 1

746
test/unit_tests/nrn_hs_2D_array_3x5/run/prsim.out
View File

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BIN
test/unit_tests/nrn_hs_2D_array_3x5/run/prsim.pdf
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2508
test/unit_tests/nrn_hs_2D_array_3x5/run/test.prs
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46
test/unit_tests/nrn_hs_2D_array_3x5/test.act
View File

@@ -1,46 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/coders.act";
import globals;
open tmpl::dataflow_neuro;
defproc nrn_hs_2D_array_3x5(a1of1 in[15]; a1of1 outx[3], outy[5])
{
bool _reset_B;
prs {
Reset => _reset_B-
}
nrn_hs_2D_array<3,5,5> b(.in = in, .outx = outx, .outy = outy);
b.supply.vdd = Vdd;
b.supply.vss = GND;
b.reset_B = _reset_B;
}
nrn_hs_2D_array_3x5 b;

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