bics/actlib_dataflow_neuro
20
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

Compare commits

base: bics:82a955b035250b8e775c46a74b66e5d755515b29
Branches Tags
bics:dev
bics:main
bics:encoder_wip
bics:TexelTapeout
..
compare: bics:d3614580dd37357cd1193469a5e0033f1386d925
Branches Tags
bics:main
bics:dev
bics:encoder_wip
bics:TexelTapeout

11 Commits
82a955b035 ... d3614580dd

Author SHA1 Message Date
alexmadison
d3614580dd wqMerge branch 'dev' of ssh://git.web.rug.nl:222/bics/actlib_dataflow_neuro into dev 2022-04-10 19:43:18 +02:00
alexmadison
8481d67f26 added sigs 2022-04-10 19:42:55 +02:00
alexmadison
812095840e fixed instability in buffers lol 2022-04-10 19:42:09 +02:00
alexmadison
007859023f fixed timing bug in encoder 2022-04-10 19:23:28 +02:00
alexmadison
5647d4affe added TBUF_X4 2022-04-10 19:02:03 +02:00
alexmadison
1aab499474 added 3p pullup 2022-04-10 19:01:51 +02:00
alexmadison
8c8a2eb9a4 altered neuron handshake design to use pullups without timing delays 2022-04-10 18:27:44 +02:00
alexmadison
3bf7c21c48 adding sigbufs 2022-04-10 18:18:11 +02:00
alexmadison
067b2645ee fixed a possible issue in validation of demux 2022-04-10 17:09:37 +02:00
alexmadison
a33bec178f added TBUFs 2022-04-10 16:40:37 +02:00
alexmadison
eeddc15060 added bool sigbuf 2022-04-10 16:40:11 +02:00
8 changed files with 114037 additions and 118335 deletions
Show Stats Expand all files Collapse all files

8
dataflow_neuro/cell_lib_async.act
View File

@ -684,6 +684,14 @@ namespace tmpl {
}
}
export
defproc A_3P_U_X4(bool? a, b, c; bool! y; bool? vdd, vss)
{
prs{
[keeper=0] ~a & ~b & ~c-> y+
}
}
export
defproc PULLDOWN_X4(bool? a; bool! y; bool? vdd, vss) {
A_1N_U_X4 cell(.a = a, .y = y, .vdd = vdd, .vss = vss);

13
dataflow_neuro/cell_lib_std.act
View File

@ -383,6 +383,19 @@ namespace tmpl {
}
sizing { _en{-2}; y{-2,2} }
}
export defcell TBUF_X4 (bool! y; bool? a, en, vdd, vss)
{
bool _en;
prs {
en => _en-
~a & ~_en -> y+
a & en -> y-
}
sizing { _en{-4}; y{-4,4} }
}
export defproc DFFQ_R_X1 (bool? clk_B, reset_B, d; bool! q,q_B; bool? vdd,vss)
{
bool _clk_B, __clk_B, _mqi,_mqib,_sqi,_sqib;

42
dataflow_neuro/chips.act
View File

@ -47,6 +47,7 @@ N_NRN_X, N_NRN_Y, N_SYN_X, N_SYN_Y, // Number of neurons / synapses
NC_NRN_X, NC_NRN_Y, NC_SYN_X, NC_SYN_Y,
N_SYN_DLY_CFG,
N_NRN_MON_X, N_NRN_MON_Y, N_SYN_MON_X, N_SYN_MON_Y,
N_MON_AMZO_PER_SYN, // Number of signals that each synapse outputs to be monitored.
N_BUFFERS,
N_LINE_PD_DLY, // Number of dummy delays to add line pull down
N_BD_DLY_CFG, N_BD_DLY_CFG2,
@ -56,13 +57,17 @@ defproc chip_texel (bd<N_IN> in, out;
Mx1of2<REG_NCW> reg_data[REG_M];
a1of1 synapses[N_SYN_X * N_SYN_Y];
a1of1 neurons[N_NRN_X * N_NRN_Y];
bool? nrn_mon_x[N_NRN_MON_X], nrn_mon_y[N_NRN_MON_Y];
bool? syn_mon_x[N_SYN_MON_X], syn_mon_y[N_SYN_MON_Y];
bool! nrn_mon_x[N_NRN_MON_X], nrn_mon_y[N_NRN_MON_Y];
bool! syn_mon_x[N_SYN_MON_X], syn_mon_y[N_SYN_MON_Y];
bool? syn_mon_AMZI[N_SYN_X * N_MON_AMZO_PER_SYN]; // Synapse column monitor outputs
bool? syn_mon_AMO[N_MON_AMZO_PER_SYN];
bool? bd_dly_cfg[N_BD_DLY_CFG], bd_dly_cfg2[N_BD_DLY_CFG2];
bool? loopback_en;
power supply;
bool? reset_B){
pint index = 0; // Just useful
bd2qdi<N_IN, N_BD_DLY_CFG, N_BD_DLY_CFG2> _bd2qdi(.in = in, .dly_cfg = bd_dly_cfg, .dly_cfg2 = bd_dly_cfg2,
.reset_B = reset_B, .supply = supply);
fifo<N_IN,N_BUFFERS> fifo_in2fork(.in = _bd2qdi.out, .reset_B = reset_B, .supply = supply);
@ -133,19 +138,19 @@ defproc chip_texel (bd<N_IN> in, out;
pint NC_SYN_MON_X = std::ceil_log2(N_SYN_MON_X);
pint NC_SYN_MON_Y = std::ceil_log2(N_SYN_MON_Y);
decoder_dualrail_en<NC_NRN_MON_X, N_NRN_MON_X> nrn_mon_dec_x(.out = nrn_mon_x,
.supply = supply);
decoder_dualrail_en<NC_NRN_MON_X, N_NRN_MON_X> nrn_mon_dec_x(.supply = supply);
nrn_mon_dec_x.en = register.data[1].d[0].t;
(i:NC_NRN_MON_X:
nrn_mon_dec_x.in.d[i] = register.data[2].d[i];
)
sigbuf_boolarray<N_NRN_MON_X, 40> nrn_mon_x_buf(.in = nrn_mon_dec_x.out, .out = nrn_mon_x, .supply = supply);
decoder_dualrail_en<NC_NRN_MON_Y, N_NRN_MON_Y> nrn_mon_dec_y(.out = nrn_mon_y,
.supply = supply);
decoder_dualrail_en<NC_NRN_MON_Y, N_NRN_MON_Y> nrn_mon_dec_y(.supply = supply);
nrn_mon_dec_y.en = register.data[1].d[0].t;
(i:NC_NRN_MON_Y:
nrn_mon_dec_y.in.d[i] = register.data[2].d[i+NC_NRN_MON_X];
)
sigbuf_boolarray<N_NRN_MON_Y, 40> nrn_mon_y_buf(.in = nrn_mon_dec_y.out, .out = nrn_mon_y, .supply = supply);
decoder_dualrail_en<NC_SYN_MON_X, N_SYN_MON_X> syn_mon_dec_x(
.supply = supply);
@ -153,13 +158,14 @@ defproc chip_texel (bd<N_IN> in, out;
(i:NC_SYN_MON_X:
syn_mon_dec_x.in.d[i] = register.data[3].d[i];
)
sigbuf_boolarray<N_SYN_MON_X, 40> syn_mon_x_buf(.out = syn_mon_x, .supply = supply);
decoder_dualrail_en<NC_SYN_MON_Y, N_SYN_MON_Y> syn_mon_dec_y(.out = syn_mon_y,
.supply = supply);
decoder_dualrail_en<NC_SYN_MON_Y, N_SYN_MON_Y> syn_mon_dec_y(.supply = supply);
syn_mon_dec_y.en = register.data[1].d[1].t;
(i:NC_SYN_MON_Y:
syn_mon_dec_y.in.d[i] = register.data[3].d[i+NC_SYN_MON_X];
)
sigbuf_boolarray<N_SYN_MON_Y,40> syn_mon_y_buf(.out = syn_mon_y, .in = syn_mon_dec_y.out, .supply = supply);
// Device debug hard-wired safety (reg0, b05 = DEV_DEBUG)
// Stops the possibility of dev_mon being high while some other sig is high.
@ -174,18 +180,34 @@ defproc chip_texel (bd<N_IN> in, out;
(i:NSMX4:
ands_devmon[i].a = syn_mon_dec_x.out[1+i*4];
ands_devmon[i].b = DEV_DEBUG;
ands_devmon[i].y = syn_mon_x[1+i*4];
ands_devmon[i].y = syn_mon_x_buf.in[1+i*4];
ands_devmon[i].vdd = supply.vdd;
ands_devmon[i].vss = supply.vss;
)
// Wire up the non-ANDed lines.
(i:N_SYN_MON_X:
[~(i%4 = 1) ->
syn_mon_x[i] = syn_mon_dec_x.out[i];
syn_mon_x_buf.in[i] = syn_mon_dec_x.out[i];
]
)
]
// Create TBUFs for each synapse column,
// ctrl wired to mon line (0'th in each 4).
pint N_TBUF = N_SYN_X * N_MON_AMZO_PER_SYN;
TBUF_X4 syn_x_AMZI_tbuf[N_TBUF];
(i:N_SYN_X:
(j:N_MON_AMZO_PER_SYN:
index = i*N_MON_AMZO_PER_SYN + j;
syn_x_AMZI_tbuf[index].a = syn_mon_AMZI[index];
syn_x_AMZI_tbuf[index].en = syn_mon_x[i*4];
syn_x_AMZI_tbuf[index].y = syn_mon_AMO[j];
)
)
}

127
dataflow_neuro/coders.act
View File

@ -91,15 +91,16 @@ defproc decoder_dualrail (Mx1of2<Nc> in; bool? out[N]; power supply) {
* Be careful of out[] indexing.
*/
export template<pint Nc, N, OUT_STRENGTH>
defproc decoder_dualrail_x(Mx1of2<Nc> in; bool? out[N*OUT_STRENGTH]; power supply) {
defproc decoder_dualrail_x(Mx1of2<Nc> in; bool? out[N]; power supply) {
decoder_dualrail<Nc, N> decoder(.in = in, .supply = supply);
sigbuf<OUT_STRENGTH> sb[N];
(i:N:
sb[i].in = decoder.out[i];
sb[i].supply = supply;
(j:OUT_STRENGTH:
sb[i].out[j] = out[j + i*OUT_STRENGTH];
)
sb[i].out[0] = out[i];
// (j:OUT_STRENGTH:
// sb[i].out[j] = out[j + i*OUT_STRENGTH];
// )
)
}
@ -126,40 +127,6 @@ defproc decoder_dualrail_en(Mx1of2<Nc> in; bool? en, out[N]; power supply) {
}
/**
* Dualrail decoder with on/off switch.
* Outputs are buffered.
*/
// export template<pint Nc, N, OUT_STRENGTH>
// defproc decoder_dualrail_en_x(Mx1of2<Nc> in; bool? en, out[N]; power supply) {
// decoder_dualrail<Nc, N> decoder(.in = in, .supply = supply);
// sigbuf<N> sb_en(.in = en, .supply = supply);
// sigbuf<OUT_STRENGTH> sb[N];
// AND2_X1 en_ands[N];
// (i:N:
// en_ands[i].a = decoder.out[i];
// en_ands[i].b = sb_en.out[i];
// en_ands[i].vdd = supply.vdd;
// en_ands[i].vss = supply.vss;
// sb[i].in = en_ands[i].y;
// sb[i].supply = supply;
// // (j:OUT_STRENGTH:
// // sb[i].out[j] = out[j + i*OUT_STRENGTH];
// // )
// sb[i].out[0] = out[i];
// )
// }
/**
@ -242,6 +209,9 @@ defproc and_grid(bool! out[Nx*Ny]; bool? inx[Nx], iny[Ny]; power supply) {
export template<pint NxC, NyC, Nx, Ny>
defproc decoder_2d_hs (avMx1of2<NxC+NyC> in; a1of1 out[Nx*Ny]; bool? reset_B; power supply) {
bool _reset_BX[Nx];
sigbuf<Nx> reset_sb(.in = reset_B, .out = _reset_BX, .supply = supply);
// Buffer to recieve concat(x,y) address packet
buffer<NxC+NyC> addr_buf(.in = in, .reset_B = reset_B, .supply = supply);
@ -303,7 +273,7 @@ defproc decoder_2d_hs (avMx1of2<NxC+NyC> in; a1of1 out[Nx*Ny]; bool? reset_B; po
pu[i].vdd = supply.vdd;
pu[i].vss = supply.vss;
pu_reset[i].a = reset_B;
pu_reset[i].a = _reset_BX[i];
pu_reset[i].y = _out_acksB[i];
pu_reset[i].vdd = supply.vdd;
pu_reset[i].vss = supply.vss;
@ -345,6 +315,9 @@ export template<pint NxC, NyC, Nx, Ny, N_dly_cfg>
defproc decoder_2d_hybrid (avMx1of2<NxC+NyC> in; a1of1 out[Nx*Ny]; bool? dly_cfg[N_dly_cfg], hs_en,
reset_B; power supply) {
bool _reset_BX[Nx];
sigbuf<Nx> reset_sb(.in = reset_B, .out = _reset_BX, .supply = supply);
bool hs_enB;
INV_X4 hs_inv(.a = hs_en, .y = hs_enB, .vdd = supply.vdd, .vss = supply.vss);
@ -358,6 +331,7 @@ defproc decoder_2d_hybrid (avMx1of2<NxC+NyC> in; a1of1 out[Nx*Ny]; bool? dly_cfg
(i:0..NyC-1:d_dr_y.in.d[i] = addr_buf.out.d.d[i+NxC];)
// sig buf for reqx lines, since they go to synapse pull down gates.
// Signals to the and-grid are buffered therein.
sigbuf<Ny+1> d_dr_xX[Nx];
(i:Nx:
d_dr_xX[i].in = d_dr_x.out[i];
@ -410,7 +384,7 @@ defproc decoder_2d_hybrid (avMx1of2<NxC+NyC> in; a1of1 out[Nx*Ny]; bool? dly_cfg
pu[i].vdd = supply.vdd;
pu[i].vss = supply.vss;
pu_reset[i].a = reset_B;
pu_reset[i].a = _reset_BX[i];
pu_reset[i].y = _out_acksB[i];
pu_reset[i].vdd = supply.vdd;
pu_reset[i].vss = supply.vss;
@ -570,10 +544,15 @@ defproc decoder_2d_hybrid (avMx1of2<NxC+NyC> in; a1of1 out[Nx*Ny]; bool? dly_cfg
(i:Nc:ors_t[i].supply = supply; ors_t[i].out = out.d[i].t;)
(i:Nc:ors_f[i].supply = supply; ors_f[i].out = out.d[i].f;)
bool _inX[N];
sigbuf_boolarray<N, Nc> sb_in(.in = in, .out = _inX, .supply = supply);
pint num_connected_t; // Number of guys already connected to the current OR tree
pint num_connected_f;
TIELO_X1 tielo(.vdd = supply.vdd, .vss = supply.vss); // I'm sorry
TIELO_X1 tielo[Nc]; // I'm sorry
(i:Nc:tielo[i].vdd = supply.vdd; tielo[i].vss = supply.vss;)
pint bitval;
(i:0..Nc-1: // For each output line
num_connected_t = 0;
@ -581,16 +560,16 @@ defproc decoder_2d_hybrid (avMx1of2<NxC+NyC> in; a1of1 out[Nx*Ny]; bool? dly_cfg
(j:0.. _N-1:
bitval = (j & ( 1 << i )) >> i; // Get binary digit of integer j, column i
[bitval = 1 & j <= N-1->
ors_t[i].in[num_connected_t] = in[j];
ors_t[i].in[num_connected_t] = _inX[j];
num_connected_t = num_connected_t + 1;
[] bitval = 0 & j <= N-1->
ors_f[i].in[num_connected_f] = in[j];
ors_f[i].in[num_connected_f] = _inX[j];
num_connected_f = num_connected_f + 1;
[] bitval = 1 & j > N-1->
ors_t[i].in[num_connected_t] = tielo.y;
ors_t[i].in[num_connected_t] = tielo[i].y;
num_connected_t = num_connected_t + 1;
[] bitval = 0 & j > N-1->
ors_f[i].in[num_connected_f] = tielo.y;
ors_f[i].in[num_connected_f] = tielo[i].y;
num_connected_f = num_connected_f + 1;
]
@ -604,11 +583,11 @@ defproc decoder_2d_hybrid (avMx1of2<NxC+NyC> in; a1of1 out[Nx*Ny]; bool? dly_cfg
/**
* Buffer function code.
* Is the function block ripped from the buffer_s.
* Used in the encoder2d.
*/
/**
* Buffer function code.
* Is the function block ripped from the buffer_s.
* Used in the encoder2d.
*/
export template<pint N>
defproc buffer_s_func (Mx1of2<N> in; avMx1of2<N> out; bool? in_v, en, reset_B; power supply) {
//function
@ -619,9 +598,9 @@ defproc decoder_2d_hybrid (avMx1of2<NxC+NyC> in; a1of1 out[Nx*Ny]; bool? dly_cfg
A_2C2N_RB_X4 t_buf_func[N];
// reset buffers
bool _reset_BX,_reset_BXX[N];
bool _reset_BX,_reset_BXX[N*2];
BUF_X1 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
sigbuf<N> reset_bufarray(.in=_reset_BX, .out=_reset_BXX, .supply=supply);
sigbuf<N*2> reset_bufarray(.in=_reset_BX, .out=_reset_BXX, .supply=supply);
// Enable signal buffers
sigbuf<N> en_buf_t(.in=en, .out=_en_X_t, .supply=supply);
@ -654,8 +633,8 @@ defproc decoder_2d_hybrid (avMx1of2<NxC+NyC> in; a1of1 out[Nx*Ny]; bool? dly_cfg
t_buf_func[i].vss=supply.vss;
t_buf_func[i].pr_B = _reset_BXX[i];
t_buf_func[i].sr_B = _reset_BXX[i];
f_buf_func[i].pr_B = _reset_BXX[i];
f_buf_func[i].sr_B = _reset_BXX[i];
f_buf_func[i].pr_B = _reset_BXX[i+N];
f_buf_func[i].sr_B = _reset_BXX[i+N];
)
}
@ -665,9 +644,10 @@ defproc decoder_2d_hybrid (avMx1of2<NxC+NyC> in; a1of1 out[Nx*Ny]; bool? dly_cfg
defproc encoder2d(a1of1 inx[Nx]; a1of1 iny[Ny]; avMx1of2<(NxC + NyC)> out; power supply; bool reset_B) {
// Reset buffers
pint H = 2*(NxC + NyC); //Reset strength? to be investigated
bool _reset_BX,_reset_BXX[H];
BUF_X4 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
sigbuf<2*(NxC + NyC)> reset_bufarray(.in=_reset_BX, .out=_reset_BXX,.supply=supply);
BUF_X4 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
sigbuf<2*(NxC + NyC)> reset_bufarray(.in=_reset_BX, .out=_reset_BXX,.supply=supply);
// Arbiters
a1of1 _arb_out_x, _arb_out_y;
@ -723,8 +703,10 @@ defproc decoder_2d_hybrid (avMx1of2<NxC+NyC> in; a1of1 out[Nx*Ny]; bool? dly_cfg
// X_req ORtree
bool _x_req_array[Nx], _x_v_B;
(i:Nx:_x_req_array[i] = inx[i].r;)
ortree<Nx> x_req_ortree(.in = _x_req_array,.out = _x_v,.supply = supply); //todo BUFF
INV_X1 not_x_req_ortree(.a = _x_v,.y = _x_v_B);
ortree<Nx> x_req_ortree(.in = _x_req_array, .supply = supply); //todo BUFF
INV_X1 not_x_req_ortree(.a = x_req_ortree.out, .y = _x_v_B);
INV_X1 not_x_req_ortree2(.a = _x_v_B,.y = _x_v);
//X_REQ validation
// bool _x_req_array[Nx],_x_v_B, _en;
@ -735,7 +717,7 @@ defproc decoder_2d_hybrid (avMx1of2<NxC+NyC> in; a1of1 out[Nx*Ny]; bool? dly_cfg
bool _x_a_B2; // sorry
bool _en;
A_1C3P2P2N_R_X1 x_ack(); // NEEDS BUFFERING TO X4
A_1C3P2P2N_R_X1 x_ack();
//branch1
x_ack.p4 = _in_x_v;
x_ack.p5 = _x_v_B;
@ -823,18 +805,31 @@ defproc decoder_2d_hybrid (avMx1of2<NxC+NyC> in; a1of1 out[Nx*Ny]; bool? dly_cfg
A_2C1P1N_RB_X1 A_req(.p1 = _x_a_B, .c1 = _en, .c2 = _y_a_B, .n1 = in.r, .y = _req,
.pr_B = _reset_BX, .sr_B = _reset_BX, .vdd = supply.vdd, .vss = supply.vss);
// // y_req pull up
// NAND2_X1 nand_y(.a = _y_a_B, .b = _req, .vdd = supply.vdd, .vss = supply.vss);
// A_1P_U_X4 pu_y(.a = nand_y.y, .y = outy.r, .vdd = supply.vdd, .vss = supply.vss);
// // x_req pull up
// NAND3_X1 nand_x(.a = _x_a_B, .b = _req, .c = outy.a, .vdd = supply.vdd, .vss = supply.vss);
// A_1P_U_X4 pu_x(.a = nand_x.y, .y = outx.r, .vdd = supply.vdd, .vss = supply.vss);
// Better version with fewer timing assumptions
// Core change is that the out acks stop the pullups without any delay.
// y_req pull up
NAND2_X1 nand_y(.a = _y_a_B, .b = _req, .vdd = supply.vdd, .vss = supply.vss);
A_1P_U_X4 pu_y(.a = nand_y.y, .y = outy.r, .vdd = supply.vdd, .vss = supply.vss);
bool _reqB;
INV_X1 req_inv(.a = _req, .y = _reqB, .vdd= supply.vdd, .vss = supply.vss);
A_2P_U_X4 pu_y(.a = _reqB, .b = outy.a, .y = outy.r, .vdd = supply.vdd, .vss = supply.vss);
// x_req pull up
NAND3_X1 nand_x(.a = _x_a_B, .b = _req, .c = outy.a, .vdd = supply.vdd, .vss = supply.vss);
A_1P_U_X4 pu_x(.a = nand_x.y, .y = outx.r, .vdd = supply.vdd, .vss = supply.vss);
A_3P_U_X4 pu_x(.a = outx.a, .b = _reqB, .c = _y_a_B, .y = outx.r,
.vdd = supply.vdd, .vss = supply.vss);
}
export
export
defproc nrn_line_end_pull_down (bool? in; bool? reset_B; power supply; bool! out)
{
bool _out, __out, nand_out;
@ -889,14 +884,14 @@ defproc decoder_2d_hybrid (avMx1of2<NxC+NyC> in; a1of1 out[Nx*Ny]; bool? dly_cfg
// Note that this should be generalised.
// And probably won't even be done by ACT/innovus anwyay
// TODO: do it properly with sigbufs?
BUF_X4 out_ack_buf_x[Nx];
BUF_X12 out_ack_buf_x[Nx];
(i:Nx:
out_ack_buf_x[i].vss = supply.vss;
out_ack_buf_x[i].vdd = supply.vdd;
out_ack_buf_x[i].a = outx[i].a;
out_ack_buf_x[i].y = _outx[i].a;
)
BUF_X4 out_ack_buf_y[Ny];
BUF_X12 out_ack_buf_y[Ny];
(i:Ny:
out_ack_buf_y[i].vss = supply.vss;
out_ack_buf_y[i].vdd = supply.vdd;

86
dataflow_neuro/primitives.act
View File

@ -125,14 +125,13 @@ namespace tmpl {
BUF_X4 in_v_buf(.a=_in_v, .y=in.v,.vdd=supply.vdd,.vss=supply.vss);
//function
bool _out_a_BX_t[N],_out_a_BX_f[N],_out_a_B,_en_X_t[N],_en_X_f[N];
bool _out_a_BX[N*2],_out_a_B,_en_X_t[N],_en_X_f[N];
A_2C1N_RB_X4 f_buf_func[N];
A_2C1N_RB_X4 t_buf_func[N];
sigbuf<N> en_buf_t(.in=_en, .out=_en_X_t, .supply=supply);
sigbuf<N> en_buf_f(.in=_en, .out=_en_X_f, .supply=supply);
INV_X1 out_a_inv(.a=out.a,.y=_out_a_B, .vss = supply.vss, .vdd = supply.vdd);
sigbuf<N> out_a_B_buf_f(.in=_out_a_B,.out=_out_a_BX_t, .supply = supply);
sigbuf<N> out_a_B_buf_t(.in=_out_a_B,.out=_out_a_BX_f, .supply = supply);
sigbuf<N*2> out_a_B_buf(.in=_out_a_B,.out=_out_a_BX, .supply = supply);
// check if you can also do single var to array connect a=b[N]
// and remove them from the loop
(i:N:
@ -140,8 +139,8 @@ namespace tmpl {
t_buf_func[i].y=out.d.d[i].t;
f_buf_func[i].c1=_en_X_f[i];
t_buf_func[i].c1=_en_X_t[i];
f_buf_func[i].c2=_out_a_BX_f[i];
t_buf_func[i].c2=_out_a_BX_t[i];
f_buf_func[i].c2=_out_a_BX[i];
t_buf_func[i].c2=_out_a_BX[i+N];
f_buf_func[i].n1=in.d.d[i].f;
t_buf_func[i].n1=in.d.d[i].t;
f_buf_func[i].vdd=supply.vdd;
@ -241,7 +240,7 @@ namespace tmpl {
OR2_X1 out_or(.a=out1.v, .b=out2.v, .y=_out_v,.vdd=supply.vdd,.vss=supply.vss);
A_3C_RB_X4 inack_ctl(.c1=_en,.c2=_in_c_v_,.c3=_out_v,.y=in.a,.pr_B=_reset_BX,.sr_B=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
cond.a = in.a;
cond.a = in.a; // THIS SHOULD BE IMPROVED UPON IN FUTURE VERSIONS
cond.v = _in_c_v_;
A_1C1P_X1 en_ctl(.c1=in.a,.p1=_out_v,.y=_en,.vdd=supply.vdd,.vss=supply.vss);
BUF_X1 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
@ -266,7 +265,7 @@ namespace tmpl {
A_2C2N_RB_X4 out1_t_buf_func[N];
sigbuf<N> out1_en_buf_t(.in=_en, .out=_en1_X_t, .supply=supply);
sigbuf<N> out1_en_buf_f(.in=_en, .out=_en1_X_f, .supply=supply);
INV_X1 out1_a_inv(.a=out1.a,.y=_out1_a_B);
INV_X1 out1_a_inv(.a=out1.a,.y=_out1_a_B, .vdd = supply.vdd, .vss = supply.vss);
sigbuf<N> out1_a_B_buf_f(.in=_out1_a_B,.out=_out1_a_BX_t, .supply=supply);
sigbuf<N> out1_a_B_buf_t(.in=_out1_a_B,.out=_out1_a_BX_f, .supply=supply);
(i:N:
@ -296,7 +295,7 @@ namespace tmpl {
A_2C2N_RB_X4 out2_t_buf_func[N];
sigbuf<N> out2_en_buf_t(.in=_en, .out=_en2_X_t, .supply=supply);
sigbuf<N> out2_en_buf_f(.in=_en, .out=_en2_X_f, .supply=supply);
INV_X1 out2_a_inv(.a=out2.a,.y=_out2_a_B);
INV_X1 out2_a_inv(.a=out2.a,.y=_out2_a_B, .vdd = supply.vdd, .vss = supply.vss);
sigbuf<N> out2_a_B_buf_f(.in=_out2_a_B,.out=_out2_a_BX_t);
sigbuf<N> out2_a_B_buf_t(.in=_out2_a_B,.out=_out2_a_BX_f);
(i:N:
@ -312,10 +311,10 @@ namespace tmpl {
out2_t_buf_func[i].vdd=supply.vdd;
out2_f_buf_func[i].vss=supply.vss;
out2_t_buf_func[i].vss=supply.vss;
out2_t_buf_func[i].pr_B = _reset_BXX[i+N-1];
out2_t_buf_func[i].sr_B = _reset_BXX[i+N-1];
out2_f_buf_func[i].pr_B = _reset_BXX[i+N-1];
out2_f_buf_func[i].sr_B = _reset_BXX[i+N-1];
out2_t_buf_func[i].pr_B = _reset_BXX[i+N];
out2_t_buf_func[i].sr_B = _reset_BXX[i+N];
out2_f_buf_func[i].pr_B = _reset_BXX[i+N];
out2_f_buf_func[i].sr_B = _reset_BXX[i+N];
out2_f_buf_func[i].n2=_c_t_buf[i];
out2_t_buf_func[i].n2=_c_t_buf[i];
)
@ -390,10 +389,10 @@ namespace tmpl {
out2_t_buf_func[i].vdd=supply.vdd;
out2_f_buf_func[i].vss=supply.vss;
out2_t_buf_func[i].vss=supply.vss;
out2_t_buf_func[i].pr_B = _reset_BXX[i+N-1];
out2_t_buf_func[i].sr_B = _reset_BXX[i+N-1];
out2_f_buf_func[i].pr_B = _reset_BXX[i+N-1];
out2_f_buf_func[i].sr_B = _reset_BXX[i+N-1];
out2_t_buf_func[i].pr_B = _reset_BXX[i+N];
out2_t_buf_func[i].sr_B = _reset_BXX[i+N];
out2_f_buf_func[i].pr_B = _reset_BXX[i+N];
out2_f_buf_func[i].sr_B = _reset_BXX[i+N];
)
}
@ -557,23 +556,23 @@ namespace tmpl {
}
//The buffer_t_valid doesn't work
export
defproc buffer_t_valid(a1of1 in; a1of1 out; bool? reset_B; power supply)
{
//control
bool _en, _reset_BX;
A_3C_RB_X4 inack_ctl(.c1=_en,.c2=in.r,.c3=out.r,.y=in.a,.pr_B=_reset_BX,.sr_B=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
A_1C1P_X1 en_ctl(.c1=in.a,.p1=out.r,.y=_en,.vdd=supply.vdd,.vss=supply.vss);
// export
// defproc buffer_t_valid(a1of1 in; a1of1 out; bool? reset_B; power supply)
// {
// //control
// bool _en, _reset_BX;
// A_3C_RB_X4 inack_ctl(.c1=_en,.c2=in.r,.c3=out.r,.y=in.a,.pr_B=_reset_BX,.sr_B=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
// A_1C1P_X1 en_ctl(.c1=in.a,.p1=out.r,.y=_en,.vdd=supply.vdd,.vss=supply.vss);
//function
bool _out_a_B;
INV_X1 inv_outa(.a = out.a,.y=_out_a_B,.vdd = supply.vdd,.vss=supply.vss);
A_2C1N_RB_X4 buf_func(.c1 = _en,.c2 = _out_a_B, .n1 = in.r,.y = out.r, .pr_B = _reset_BX, .sr_B = _reset_BX,.vdd = supply.vdd,.vss=supply.vss);
// //function
// bool _out_a_B;
// INV_X1 inv_outa(.a = out.a,.y=_out_a_B,.vdd = supply.vdd,.vss=supply.vss);
// A_2C1N_RB_X4 buf_func(.c1 = _en,.c2 = _out_a_B, .n1 = in.r,.y = out.r, .pr_B = _reset_BX, .sr_B = _reset_BX,.vdd = supply.vdd,.vss=supply.vss);
//reset buffers
BUF_X1 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
}
// //reset buffers
// BUF_X1 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
// }
@ -873,9 +872,17 @@ defproc slice_data(avMx1of2<N> in; avMx1of2<std::min(N1,N)-std::max(N0,0)> out;
in.d.d[CONDITION_BIT].f = demux.cond.d.d[0].f;
in.d.d[CONDITION_BIT].t = demux.cond.d.d[0].t;
in.v = demux.in.v;
in.a = demux.in.a;
A_2C_B_X1 val_Cel(.c1 = demux.in.v, .c2 = demux.cond.v, .y = in.v,
.vdd = supply.vdd, .vss = supply.vss);
// Not actually needed bc the current version of demux
// Something like below should be added once the handshakes are properly decoupled.
// wires the data and cond ack lines together anyway.
// A_2C_B_X1 ack_Cel(.c1 = demux.in.a, .c2 = demux.cond.a, .y = in.a,
// .vdd = supply.vdd, .vss = supply.vss);
// in.v = demux.in.v;
in.a = demux.in.a;
(i:0..CONDITION_BIT-1:
in.d.d[i].f = demux.in.d.d[i].f;
@ -893,5 +900,20 @@ defproc slice_data(avMx1of2<N> in; avMx1of2<std::min(N1,N)-std::max(N0,0)> out;
demux_bit<N,N> demux(.in = in, .out1 = out1, .out2 = out2, .reset_B = reset_B, .out1=out1, .out2=out2);
}
/**
* Create M sigbufs to buffer an M bool array to N strength.
* Done lazily.
**/
export template<pint M, N>
defproc sigbuf_boolarray(bool? in[M]; bool! out[M]; power supply) {
sigbuf<N> sb[M];
(i:M:
sb[i].in = in[i];
sb[i].out[0] = out[i];
sb[i].supply = supply;
)
}
}}

221456
test/unit_tests/texel_small/run/prsim.out
View File

File diff suppressed because one or more lines are too long

10629
test/unit_tests/texel_small/run/test.prs
View File

File diff suppressed because it is too large Load Diff

11
test/unit_tests/texel_small/test.act
View File

@ -71,12 +71,16 @@ defproc chip_texel_test (bd<14> in; bd<14> out; Mx1of2<8> reg_data[16];
pint N_NRN_MON_X = 2;
pint N_NRN_MON_Y = 4;
pint N_SYN_MON_X = 2;
pint N_SYN_MON_Y = 4;
// pint N_SYN_MON_X = 2;
// pint N_SYN_MON_Y = 4;
pint N_SYN_MON_X = N_SYN_X*4;
pint N_SYN_MON_Y = N_SYN_Y;
pint N_MON_AMZO_PER_SYN = 5;
pint N_BUFFERS = 3;
pint N_LINE_PD_DLY = 3;
pint N_LINE_PD_DLY = 0;
pint REG_NCA = 4;
pint REG_M = 1<<REG_NCA;
@ -87,6 +91,7 @@ defproc chip_texel_test (bd<14> in; bd<14> out; Mx1of2<8> reg_data[16];
NC_NRN_X, NC_NRN_Y, NC_SYN_X, NC_SYN_Y,
N_SYN_DLY_CFG,
N_NRN_MON_X, N_NRN_MON_Y, N_SYN_MON_X, N_SYN_MON_Y,
N_MON_AMZO_PER_SYN,
N_BUFFERS,
N_LINE_PD_DLY,
N_BD_DLY_CFG, N_BD_DLY_CFG2,